LEGEND A3292256 32x72 PC133 SDRAM Performance Technology A3292256 32x72 PC133 SDRAM (Part formerly known as A2709256. Part has not changed, only reference name has changed) FEATURES * PC100 and PC133 compliant * JEDEC-standard 168-pin, dual in-line memory module (DIMM) * Unbuffered * 256MB ECC * Single +3.3V 0.3V power supply * Fully synchronous; all signals registered on positive edge of system clock * Internal pipelined operation; column address can be changed every clock cycle * Internal SDRAM banks for hiding row access/precharge * Programmable burst lengths: 1, 2, 4, 8 or full page * Auto and Self Refresh capability * 4,096 cycle refresh (64ms) * LVTTL-compatible inputs and outputs * Serial presence-detect (SPD) GENERAL DESCRIPTION The Legend A3292256 is a high-speed CMOS, dynamic random-access 256MB memory module. The module consists of 18 DRAMS in TSOP-II 400mil packages, surface mounted to a 168-pin FR-4 printed circuit board. Read and write accesses to the SDRAM modules are burst oriented; accesses start at a selected location and continue for a programmed number of locations in a programmed sequence. The address bits registered coincident with the READ or WRITE command are used to select the starting column location for the burst access. The modules provide for programmable READ or WRITE burst lengths of 1, 2, 4 or 8 locations, or the full page. The modules use an internal pipelined architecture to achieve highspeed operation. Precharging one bank while accessing one of the other three banks will hide the precharge cycles and provide high-speed, random- access operation. The modules are designed to operate in 3.3V, low-power memory systems. An auto refresh mode is provided, along with a powersaving, power-down mode. All inputs and outputs are LVTTL-compatible. SDRAM modules offer significant operating performance enhancement over asynchronous DRAM, including the ability to synchronously burst data at a high data rate with automatic column-address generation, the ability to interleave between internal banks in order to hide precharge time and the capability to randomly change column addresses on each clock cycle during a burst access. These dual inline memory modules are intended for mounting into 168-pin edge connector sockets and offer a range of operating frequencies suitable for a variety of high bandwidth, high performance memory system applications SERIAL PRESENCE-DETECT OPERATION The module incorporates serial presence-detect (SPD). The SPD function is implemented using a 2,048-bit EEPROM. This nonvolatile storage device contains 256 bytes. The first 128 bytes can be programmed by Legend to identify the module type and various SDRAM organizations and timing parameters. ABSOLUTE MAXIMUM RATINGS* Voltage on Inputs, NC or I/O Pins Relative to VSS Operating Temperature, T A (ambient) Storage Temperature (plastic) Power Dissipation -0.3V to +4.6V 0C to +70C -40C to +120C 16W *Stresses greater than those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. Page 1 of 3 Legend reserves the right to change products or specifications without notice. LEGEND A3292256 32x72 PC133 SDRAM Performance Technology DC ELECTRICAL CHARACTERISTICS AND OPERATING CONDITIONS PARAMETER/CONDITION INPUT HIGH VOLTAGE: Logic 1; All inputs INPUT LOW VOLTAGE: Logic 0; All inputs INPUT LEAKAGE CURRENT: Any input 0V<VIN <VDD (All other pins not under test = 0V) SYMBOL V IH V IL MIN 2 -0.3 MAX VDD +0.3 0.8 II (L) -40 40 IOZ -40 40 V OH 2.4 UNITS V uA OUTPUT LEAKAGE CURRENT: DQs are disabled; 0V<V OUT<V DD OUTPUT LEVELS: Output High Voltage (IOUT = -4mA) Output Low Voltage (IOUT = 4mA) V OL V 0.4 SPECIFICATIONS AND CONDITIONS PARAMETER/CONDITION OPERATING CURRENT: t CK = t CK(MIN.) All banks operated in random access, all banks operated in ping-pong manner. PRECHARGE STANDBY CURRENT: Power-Down Mode; CKE = LOW; All banks idle PRECHARGE STANDBY CURRENT: Active Mode; S0#-S3#=HIGH; CKE=HIGH; All banks active after tRCD met; No accesses in progress NO OPERATING CURRENT: t CK = min., CS = VIH (MIN.), CKE =VIH(MIN.) active state (max. 4 banks) CKE =VIL(MAX.) BURST OPERATING CURRENT: Read command cycling. AUTO REFRESH CURRENT: tRC=t RC(MIN) SELF REFRESH CURRENT: CKE<0.2V SYMBOL PC133 ICC 1 1360 ICC 2P 12 ICC 2N 360 ICC 3N ICC 3P ICC 4 ICC 5 ICC 6 400 80 880 2000 12 UNITS mA SDRAM COMPONENT AC ELECTRICAL CHARACTERISTICS PARAMETER Access time from CLK (pos. edge) CL = 3 CL = 2 Address hold time Address setup time CLK high-level width CLK low-level width Clock cycle time CKE hold time CKE setup time CS#, RAS#, CAS#, WE#, DQM hold time CS#, RAS#, CAS#, WE#, DQM setup time Data-in hold time Data-in setup time Data-out high-impedance time Data-out low-impedance time Data-out hold time ACTIVE to PRECHARGE command ACTIVE to ACTIVE command period ACTIVE to READ or WRITE delay Refresh period (4,096 cycles) PRECHARGE command period ACTIVE bank A to ACTIVE bank B command Transition time WRITE recovery time SELF REFRESH exit time CL = 3 CL = 2 SYMBOL tAC tAC tAH tAS tCH tCL tCK tCK tCKH tCKS tCMH tCMS tDH tDS tHZ tLZ tOH tRAS tRC tRCD tREF tRP tRRD tT tWR tXSR Page 2 of 3 MIN 0.8 1.5 2.5 2.5 7.5 10 0.8 1.5 0.8 1.5 0.8 1.5 3 1 3 45 67 20 MAX 5.4 6 UNITS ns 7 120,000 64 20 15 0.3 2 1 1.2 CLK CLK Legend reserves the right to change products or specifications without notice. LEGEND A3292256 32x72 PC133 SDRAM Performance Technology METROLOGY Page 3 of 3 Legend reserves the right to change products or specifications without notice.