LEGEND
Performance Technology
A3292256
32x72 PC133 SDRAM
Page 1
of 3 Legend reserves the right to change products
or specifications without notice.
A3292256 32x72 PC133 SDRAM
(Part formerly known as A2709256. Part has not changed, only reference name has
changed)
FEATURES
• PC100 and PC133 compliant
• JEDEC-standard 168-pin, dual in-line memory module (DIMM)
• Unbuffered
• 256MB ECC
• Single +3.3V ±0.3V power supply
• Fully synchronous; all signals registered on positive edge of system clock
• Internal pipelined operation; column address can be changed every clock cycle
• Internal SDRAM banks for hiding row access/precharge
• Programmable burst lengths: 1, 2, 4, 8 or full page
• Auto and Self Refresh capability
• 4,096 cycle refresh (64ms)
• LVTTL-compatible inputs and outputs
• Serial presence-detect (SPD)
GENERAL DESCRIPTION
The Legend A3292256 is a high-speed CMOS,
dynamic random-access 256MB memory module.
The module consists of 18 DRAMS in TSOP-II 400-
mil packages, surface mounted to a 168-pin FR-4
printed circuit board. Read and write accesses to
the SDRAM modules are burst oriented; accesses
start at a selected location and continue for a
programmed number of locations in a programmed
sequence. The address bits registered coincident
with the READ or WRITE command are used to
select the starting column location for the burst
access. The modules provide for programmable
READ or WRITE burst lengths of 1, 2, 4 or 8
locations, or the full page. The modules use an
internal pipelined architecture to achieve high-
speed operation. Precharging one bank while
accessing one of the other three banks will hide the
precharge cycles and provide high-speed, random-
access operation. The modules are designed to
operate in 3.3V, low-power memory systems. An
auto refresh mode is provided, along with a power-
saving, power-down mode. All inputs and outputs
are LVTTL-compatible. SDRAM modules offer
significant operating performance enhancement
over asynchronous DRAM, including the ability to
synchronously burst data at a high data rate with
automatic column-address generation, the ability to
interleave between internal banks in order to hide
precharge time and the capability to randomly
change column addresses on each clock cycle
during a burst access. These dual inline memory
modules are intended for mounting into 168-pin
edge connector sockets and offer a range of
operating frequencies suitable for a variety of high
bandwidth, high performance memory system
applications
SERIAL PRESENCE-DETECT OPERATION
The module incorporates serial presence-detect
(SPD). The SPD function is implemented using a
2,048-bit EEPROM. This nonvolatile storage
device contains 256 bytes. The first 128 bytes can
be programmed by Legend to identify the module
type and various SDRAM organizations and timing
parameters.
ABSOLUTE MAXIMUM RATINGS*
Voltage on Inputs, NC or I/O Pins Relative to VSS -0.3V to +4.6V
Operating Temperature, T A (ambient) 0°C to +70°C
Storage Temperature (plastic) -40°C to +120°C
Power Dissipation 16W
*Stresses greater than those listed under “Absolute Maximum Ratings” may cause permanent damage to
the device.
LEGEND
Performance Technology
A3292256
32x72 PC133 SDRAM
Page 2
of 3 Legend reserves the right to change products
or specifications without notice.
DC ELECTRICAL CHARACTERISTICS AND OPERATING CONDITIONS
PARAMETER/CONDITION SYMBOL MIN MAX UNITS
INPUT HIGH VOLTAGE: Logic 1; All inputs VIH 2VDD+0.3
INPUT LOW VOLTAGE: Logic 0; All inputs VIL -0.3 0.8 V
INPUT LEAKAGE CURRENT: Any input 0V<VIN<VDD
(All other pins not under test = 0V) II(L) -40 40
OUTPUT LEAKAGE CURRENT:
DQs are disabled; 0V<VOUT<VDD IOZ -40 40 uA
VOH 2.4
OUTPUT LEVELS:
Output High Voltage (IOUT = -4mA)
Output Low Voltage (IOUT = 4mA) VOL 0.4 V
SPECIFICATIONS AND CONDITIONS
PARAMETER/CONDITION SYMBOL PC133 UNITS
OPERATING CURRENT: t CK = t CK(MIN.)
All banks operated in random access, all banks operated in ping-pong manner. ICC1 1360
PRECHARGE STANDBY CURRENT: Power-Down Mode;
CKE = LOW; All banks idle ICC2P12
PRECHARGE STANDBY CURRENT: Active Mode; S0#-S3#=HIGH; CKE=HIGH; All
banks active after tRCD met; No accesses in progress ICC2N360
CKE =VIH(MIN.) ICC3N400NO OPERATING CURRENT: t CK = min., CS = VIH (MIN.),
active state (max. 4 banks) CKE =VIL(MAX.) ICC3P 80
BURST OPERATING CURRENT: Read command cycling. ICC4 880
AUTO REFRESH CURRENT: tRC=t RC(MIN) ICC5 2000
SELF REFRESH CURRENT: CKE<0.2V ICC6 12
mA
SDRAM COMPONENT AC ELECTRICAL CHARACTERISTICS
PARAMETER SYMBOL MIN MAX UNITS
CL = 3 tAC 5.4
Access time from CLK (pos. edge) CL = 2 tAC 6
Address hold time tAH 0.8
Address setup time tAS 1.5
CLK high-level width tCH 2.5
CLK low-level width tCL 2.5
CL = 3 tCK 7.5
Clock cycle time CL = 2 tCK 10
CKE hold time tCKH 0.8
CKE setup time tCKS 1.5
CS#, RAS#, CAS#, WE#, DQM hold time tCMH 0.8
CS#, RAS#, CAS#, WE#, DQM setup time tCMS 1.5
Data-in hold time tDH 0.8
Data-in setup time tDS 1.5
Data-out high-impedance time tHZ 3 7
Data-out low-impedance time tLZ 1
Data-out hold time tOH 3
ACTIVE to PRECHARGE command tRAS 45 120,000
ACTIVE to ACTIVE command period tRC 67
ACTIVE to READ or WRITE delay tRCD 20
Refresh period (4,096 cycles) tREF 64
PRECHARGE command period tRP 20
ACTIVE bank A to ACTIVE bank B command tRRD 15
Transition time tT 0.3 1.2
ns
WRITE recovery time tWR 2CLK
SELF REFRESH exit time tXSR 1CLK
LEGEND
Performance Technology
A3292256
32x72 PC133 SDRAM
Page 3
of 3 Legend reserves the right to change products
or specifications without notice.
METROLOGY
