STM6321TAWY6F - STMicroelectronics, Inc.

A ugust 2006 Rev 6 1/26

STM6321/6322

STM6821/6822/6823/6824/6825

5-Pin Supervisor with

Watchdog Timer and Pus h-button Reset

Features

■Precision VCC Mon itoring of 5, 3.3, 3, or 2.5V

Power Supplies

■RST Outputs (Active-low, Push-pull or Open

Drain)

■RST Outputs (Active-high, Push-pull)

■Reset Pulse Width of 1.4ms, 200ms and

240ms (typ) (a)

■Watchdog Timeout Period of 1.6s (typ) (a)

■Manua l Res et Input (M R)

■Low Supp ly Current - 3µA (typ)

■Guaranteed RST (RST) Assertion down to

VCC = 1.0V

■Operating Temperature: –40 to 85°C (Industrial

Grade)

■RoHS Compliance

Lead-free Components are Compliant with the

RoHS Directive.

Fi gure 1. P ackage

a. Other trec and watchdog timings are offered . Minimum order quantities may ap ply. Contact

loca l s ale s off ic e for availa bilit y.

SOT23-5 (WY)

Table 1. Device Options

Part Number Watchdog Input Manua l Reset

Input

Reset Output

Active-Low

(Push-pull) Active-High

(Push-pull) Active-Low

(Open Drain)

STM6321 ✔✔✔

STM6322 ✔✔✔

STM6821 ✔✔ ✔

STM6822 ✔✔ ✔

STM6823 ✔✔✔

STM6824 ✔✔✔

STM6825 ✔✔✔

www.st.com

Contents STM6321/6322 STM6821/6822/6823/6824/6825

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Contents

1 Summary Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5

1.1 Pin Descr iptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7

1.1.1 Ac tive-low, Push-pull Reset Output (RST)

- STM6822/ 6823/6824/68 25 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7

1.1.2 Active-low, Open Drain Reset Output (RST) - STM632 1/63 22/6822 . . . . 7

1.1.3 Pus h-button Reset Input (MR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7

1.1.4 Watchdog Input (WDI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7

1.1.5 Active-High Reset O utput (RST) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7

2 Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10

2.1 R e set Output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10

2.2 Open D rain R ST Output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10

2.3 Pus h-button R es et Input (ST M6322/6821/ 6822/6823/ 6825) . . . . . . . . . . 11

2.4 Watchdog Input (STM 6321/6821/6822/6823/6824) . . . . . . . . . . . . . . . . . 11

2.5 A pplications In fo r ma tion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11

2.5.1 Watchdog Input Current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11

2.5.2 Ens uring a Valid Reset Output Down to VCC = 0V . . . . . . . . . . . . . . . . 11

2.6 Interfacing to Microprocessors with Bi-directional Reset Pins . . . . . . . . . 12

3 Typical Operating Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13

4 Maximum Rating . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

5 DC and AC Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

6 Package Mechanical . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22

7 Part Numbering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23

8 Revision Histor y . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25

STM6321/6 322 STM6 821/ 6822/6823/682 4/6825 List of Tables

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List of Tables

Table 1. Device Options . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1

Table 2. Signal Names . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5

Table 3. Pin Functi ons . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7

Table 4. Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

Table 5. Operating and AC Measurem ent Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

Table 6. DC and AC Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20

Table 7. SOT23-5 – 5-lead Small Outline Transisto r P ack age Mecha nical Data. . . . . . . . . . . . . . . 22

Table 8. Ordering Information Scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23

Table 9. Marking Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24

Table 10. Docume nt Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25

List of Figures STM6321/632 2 STM68 21/6 822/6823/ 6824/ 6825

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List of Figures

Figure 1. Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1

Figure 2. Logic Diagram (STM68 21/6822/ 6823) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5

Figure 3. Logic Diagram (STM63 21/6322/ 6824/ 6825 ). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5

Figure 4. STM6822/ 6823 SOT2 3-5 Connecti ons. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6

Figure 5. STM6821 SO T23 -5 Con nec tions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6

Figure 6. STM6322/ 6825 SOT2 3-5 Connecti ons. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6

Figure 7. STM6321/ 6824 SOT2 3-5 Connecti ons. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6

Figure 8. Block Diagram (ST M 6821/6822/ 6823 ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8

Figure 9. Block Diagram (STM 6321/ 6824) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8

Figure 10. Block Diagram (STM6322/6825) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8

Figure 11. Hardware Hookup. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9

Figure 12. STM6321/ 6322/6822 Open D rain RST Output with Multiple Supplies . . . . . . . . . . . . . . . . 10

Figure 13. Ensuring RST Valid to VCC = 0, (Active-Low Push-pull Outputs) . . . . . . . . . . . . . . . . . . . . 12

Figure 14. Ensuring RST Valid to VCC = 0, (A ctive - H i g h , Pu s h -p u ll Out p u ts) . . . . . . . . . . . . . . . . . . . 12

F ig u re 1 5 . In te r facin g to Mi c ropro c e ssors w i th Bi-directional Re s e t I/O . . . . . . . . . . . . . . . . . . . . . . . 12

Figure 16. VCC-to-Reset O utput Delay vs. Temperature. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13

Figure 17. Supply Cu rrent vs. Temperature. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13

Figure 18. MR-to-Reset Outpu t Delay vs. Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

Figure 19. Normalized Power-up trec vs. Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

Figure 20. Normalized Reset Thresh old Volta ge vs. Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

Figure 21. Normalized Power-up Watchdog Time-Out Period. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

Figure 22. Voltage Output Low vs. ISINK . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

Figure 23. Voltage Output High vs. ISOURCE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

Figure 24. Maximum Transient Duration vs. Reset Threshold Overdrive . . . . . . . . . . . . . . . . . . . . . . 17

Figure 25. AC Testing Input/Output Waveform s . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

Figure 26. MR Timing Wavefo rm. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

Figure 27. Watchdog Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 9

Figure 28. SOT23-5 – 5-lead Small Outline Transisto r P ack age Mecha nical Drawing . . . . . . . . . . . . 22

STM6321/6 322 STM6 821/ 6822/6823/682 4/6825 Summary Description

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1 Summary Description

The STM6xxx Supervisors are self-contained devices which provide microprocess or

supervisory functions. A precision voltage reference and comparator monitors the VCC input

for an out-of-tolerance condition. When an invalid VCC condition occurs, the reset output

(RST) is forced low (or high in the case of R ST). These devices also offer a watch dog timer

(except for STM6322/6825) and/or a push-button (MR) reset input.

These devices are available in a sta ndard 5-pin SOT23 package.

Figure 2. Logic Diagram (STM6821/6822/6823)

1. For STM6821 only.

Figure 3. Logic Diagram (STM6321/6322/6824/6825)

1. For STM6321/6824.

Table 2. Signal Names

MR Push-button Reset Input

WDI Watchdog Input

RST Active-Low Reset Outpu t

RST Active-High Reset Output

VCC Supply Voltage

VSS Ground

AI09128

VCC

STM6XXX

VSS

RST (RST)(1)

WDI

AI09129

VCC

STM6XXX

VSS

RST

(WDI)(1) MR

Summary Description STM6321/6322 STM6821/6822/6823/6824/6825

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Figure 4. STM6822/ 6823 SOT23-5 Connections

1. Open drain for STM6822.

Figure 5. STM6821 SOT 23-5 Con nections

1. Pus h- pu ll only .

Figure 6. STM6322/ 6825 SOT23-5 Connections

1. Open drain for STM6322.

2. Pus h- pu ll only .

Figure 7. STM6321/6824 SOT 23-5 Connections

1. Open drain for STM6321.

2. Pus h- pu ll only .

WDI

RST(1) VCC

VSS

AI09130a

SOT23-5

WDI

RST(1) VCC

VSS

AI12285

SOT23-5

1VCC

VSS

AI09131a

SOT23-5

RST(1)

RST(2)

1VCC

VSS

AI12286

SOT23-5

WDI

RST(1)

RST(2)

STM6321/6 322 STM6 821/ 6822/6823/682 4/6825 Summary Description

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1.1 Pin Descriptions

1.1.1 Active-low, Push-pull Reset Output (RST) - STM6822/6823/6824/6825

Pulses low when tr iggered , and stays low whenever VCC is below t he reset threshold or

when MR is a logic low. It remains low for trec after either VCC rises abov e the reset

threshold, the watch dog tr iggers a reset, or MR goe s from low to high.

1.1.2 Active-low, Open Drain Reset Output (RST) - STM6321/6 322/6 822

Pulses low when tr iggered , and stays low whenever VCC is below t he reset threshold or

when MR is a logic low. It remains low for trec after either VCC rises abov e the reset

threshold, the watch dog tr iggers a reset, or MR goe s from low to high. Connect a pull-up

resistor to supply voltage.

1.1.3 Push-button Reset Input (MR)

A logic low on MR ass er t s the reset output. Reset remains asser t ed as long as MR is low

and for trec after MR returns high. This active-l ow input has an internal 52kΩ pull-up. It can

be driven fro m a TTL or CMOS logic line, or s ho rt ed to ground with a switch. Leave open if

unused.

1.1.4 Watc hd og Inp ut (W DI)

If WDI remains high or low for at least 1.6s, the internal watchdog timer expires and reset is

asser t ed. The internal watchdog timer clears while reset is asser ted or when WDI sees a

rising or fal ling edge. The watchdog function CAN be disabled if WDI i s left unconnected or

is connected to a tr i-s tate buffer output.

1.1.5 Active-High Reset Output (RST)

Active -high, push-pull reset output; inverse of RST.

Table 3. Pin Functions

Name Function

STM6822

STM6823 STM6821 STM6321

STM6824 STM6322

STM6825

1—1 1RST

Acti ve -L ow R ese t Ou tpu t

33—4MR

Push-button Reset Input

4 4 4 — WDI Watchdog Input

— 1 3 3 RST Active-High Reset Output

5555V

CC Supply Voltage

2222V

SS Ground

Summary Description STM6321/6322 STM6821/6822/6823/6824/6825

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Figure 8. Block Diagram (ST M6 821/6822/ 6823)

1. Push-pull for STM6823, open drain for STM6822.

2. Active-high (push-pull) f or STM6 821.

Figure 9. Block Diagram (STM6 321/ 6824)

3. Acive-low ( open drain) for STM6321, ac tive -low (pus h-pull) for STM6824.

4. Pus h- pu ll only .

Figure 10. Block Diagram (ST M6322/ 6825)

1. Act iv e-low (open dr ai n) for S TM 63 2 2, ac t iv e -low (pus h- p ul l) for S TM 6 82 5.

2. Pus h- pu ll only .

AI09132a

VRST RST (RST)(1,2)

WATCHDOG

TIMER

WDI

Transitional

Detector

COMPARE trec

Generator

VCC

WDI

VCC

A12287

VRST

RST(1)

WATCHDOG

TIMER

WDI

Transitional

Detector

COMPARE trec

Generator

VCC

WDI

RST(2)

AI12288

VRST

RST(1)

COMPARE trec

Generator

VCC

RST(2)

VCC

STM6321/6 322 STM6 821/ 6822/6823/682 4/6825 Summary Description

9/26

Figure 11. Hardware Hookup

1. For STM6321/6821/6822/6823/6824

2. For STM6322/6821/6822/6823/6825

3. For STM 6 82 1/ ( RS T ou tp ut on ly )

4. For STM 6 32 1/6 322 / 68 24 /682 5 ( bo th R ST an d RS T outp uts)

AI09133

VCC

MR(2)

0.1µFSTM6XXX

WDI(1)

RST (RST)(3)

RST(4) To Microprocessor Reset

From Microprocessor

Push-button

To Microprocessor Reset

Operation STM6321/6322 STM6821/6822/6823/6824/6825

10/26

2 Operation

2.1 Reset Output

The STM6xxx Super v isor assert s a reset signal to th e MCU whenever VCC goes below the

re set thre sh old (VRST), a watc hdog time-out occurs, or when the Push-button Re set Input

(MR) is taken low. Reset is guaranteed valid for VCC < VRST down to VCC =1V for TA = 0°C

to 85°C.

During power-up , once VCC exceeds the reset threshold an internal timer k eeps reset low f or

the reset time-out period, trec. After this interval rese t is de-asserted.

Each time RST is assert ed, it stays low for at least the reset time-out period (trec). Any time

VCC goes below the reset thres hold the internal timer clears. The res et timer star t s when

VCC retur ns above the reset threshold.

2.2 Open Drain RST Output

The STM6321/6322/6822 ha v e an activ e-l ow, open drain reset output. This output structure

will sink curre nt when RS T is asserte d. Connect a pull-up resistor from RST to any supply

v oltage up to 6V (see Figure 12). Select a resistor val ue large enough to register a logic lo w ,

and small enough to register a logic high while supplying all input current and leakage paths

connected to the reset output line. A 10kΩ pull -up resistor is suffici ent in most applications.

Figure 12. STM6321/6322/6822 Open Drain RST Output with Multiple Supplies

1. STM6322/6822

2. STM6321/6822

3. STM6321/6322

AI09137

STM6XXX

RST

MR(1)

WDI(2)

RST(3)

GND

10k

VCC

5V System

5.0V3.3V

STM6321/6 322 STM6 821/ 6822/6823/682 4/68 25 Op erati on

11/26

2.3 Push-button Reset Input (STM6322/6821/6822/6823/6825)

A logic low on MR asserts reset. Reset remains asser ted while MR is low, and for trec (see

Figure 26 on page 19 ) after it returns high. The MR inpu t has an intern al 52kΩ pull-up

resistor , allo wing it to be left open if not used. This input can be driven with TTL/CMOS-logic

le v els or with open-drain/collector outputs. Connect a normally open momentary switc h from

MR to GND to create a manual reset function; external debounce circuitry is not required. If

MR is driven from long cables or the device is used in a noi sy en vironment, connect a 0. 1µF

capacitor from MR to GND to provide additional noise immunity. MR m ay float , or be tied to

VCC when not used.

2.4 Watchdog Input (STM6321/6821/6822/6823/6824)

The watc hdog tim er can be used to detect an out-of-control MCU. If th e MCU does not

toggle the Watchdog Input (WDI) within tWD (1.6 se c ), th e reset i s ass e rted. The in terna l

watchdog timer is cleared by either :

1. a reset pulse, or

2. by to ggling WD I (high-to-low or low-to-high), which can dete ct pulses as short as 50ns.

The timer remains cleared and does not count for as long as reset is as sert ed. As soon as

reset is rel eased, the tim er starts count ing.

Note: The watchdog function ma y be disabled by floating WDI or tri-stating the driver connected to

WDI. When tri-stated or disconnected, the maximum allowable leakage current is 10µA and

the maximum allowable load capacitance is 200pF.

2.5 Applications Information

2.5.1 Watc hd og Inp ut Curr en t

The WDI input is internally driven through a buffer and series resistor from the watchdog

counter. For minimum watchdog input current (minimum overall power consumption), leave

WDI low for the majority of the watchdog time-out period. When high, WDI can draw as

much as 160µA. Pulsing WDI high at a low duty cycle will reduce the effect of the large input

current. When WDI is left unconnected, the watchdog timer is serviced within the watchdog

time-out period by a low-high-low pulse from the counter chain.

2.5.2 Ensuring a Valid Reset Output Down to VCC =0V

The STM6xxx Supervisors are guaranteed to opera te proper ly down to VCC = 1V. In

applications that require valid reset le v els down to VCC = 0, a pull-down resistor to active-l ow

outputs (push/pull only, see Figure 13 on page 12) and a pull-up resistor to active-high

outputs (push/pull only, see Figure 14 on page 12) will ensure that the reset line is valid

while the r eset output can no longer sink or s ource current. This scheme does not work wi th

the open drain outputs of the STM6321/6322/6822.

The resistor value used is not critical, but it must be large enough not to l oad th e reset

output when VCC is above the reset threshold. For most applications, 100kΩ is adequate.

Operation STM6321/6322 STM6821/6822/6823/6824/6825

12/26

Figure 13. Ensuring RST Valid to V CC = 0, (Activ e-Low Push-pull Outputs)

Figure 14. Ensuring RST Valid to VCC = 0, (Active-High, Push-pull Outputs)

1. This configuration does not work on open drain outputs of the STM6321/6322/6822.

2.6 In te rf ac i ng to Micropr o ce ss or s wit h B i- dir e cti on al Res et Pin s

Microprocessors with bi-directional reset pins can contend with the ST M63 21

6322

6821

6822

6823

6824

6825 reset output. For example, if the reset output is driven high and the

microprocessor wants to pull it low, signal contention will result. To prevent this from

occurring, connect a 4.7kΩ resistor between the reset output and the microprocessor’ s reset

I/O a s in Figure 15.

Figure 15. Interfacing to Micr o pr ocessors with Bi-directional Reset I/O

AI09138

STM6XXX

RSTGND

VCC

AI09139

STM6XXX

RST

GND

VCC

AI09135

STM6XXX

RST

GND

4.7k

VCC

Microprocessor

RST

Buffered Reset to other

System Components

GND

VCC

STM6321/6322 ST M6 821/6822/ 6823/6824/68 25 Typical Operatin g Characteri stics

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3 Typi cal Operating Characteristics

Figure 16. VCC-to-Reset Output Delay vs. Tem p eratur e

Figure 17. Supply Current vs. Temperature

Temperature (˚C)

Reset Output Delay (µs)

AI09627a

–40 –20 0 20 40 60 80

Temperature (˚C)

Supply Current (µA)

VCC = 3V

VCC = 5V

AI09628a

–40 –20 0 20 40 60 80

Typical Operating Characteristics STM6321/6322 STM6821/6822/6823/6824/6825

14/26

Figure 18. MR-to -Reset Outp ut Delay v s. Tempe rature

Figure 19. Normalized P ower-up trec vs. Tem p eratu re

Temperature (˚C)

Reset Output Delay (ns)

AI09669

100

200

300

400

500

600

–40 –20 0 20 40 60 80

Temperature (˚C)

Normalized Power-up trec

AI09670

0.99

1.00

1.01

1.02

1.03

1.04

1.05

–40 –20 0 20 40 60 80

STM6321/6322 ST M6 821/6822/ 6823/6824/68 25 Typical Operatin g Characteri stics

15/26

Figure 20. Normalized Reset Threshold Voltage vs. Temperature

Figure 21. Normalized P ower-up Watchdog Time-Out Period

Temperature (˚C)

Normalized Reset Threshold Voltage

AI09631a

0.95

0.96

0.97

0.98

0.99

1.00

1.01

1.02

1.03

1.04

1.05

–40 –20 0 20 40 60 80

Temperature (˚C)

Normalized Watchdog Time-out P eriod

AI09671

0.99

1.00

1.01

1.02

1.03

1.04

1.05

–40 –20 0 20 40 60 80

Typical Operating Characteristics STM6321/6322 STM6821/6822/6823/6824/6825

16/26

Figure 2 2. Volt age Out pu t Low vs . ISINK

Figure 2 3. Volt age Out pu t Hi gh vs. I SOURCE

ISINK (mA)

VOUT (V)

VCC = 2.9V

AI09634a

0.00

0.05

0.10

0.15

0.20

0.25

0.30

0.35

0123456

ISOURCE (mA)

VOUT (V)

AI09635a

2.74

2.76

2.78

2.80

2.82

2.84

2.86

2.88

2.90

2.92

0.0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0

VCC = 2.9V

STM6321/6322 ST M6 821/6822/ 6823/6824/68 25 Typical Operatin g Characteri stics

17/26

Figure 24. Maximum Transient Duration vs. Reset Threshold Over drive

Reset Threshold Overdrive (mV)

Transient Duration (µs)

AI09637a

0 20 40 60 80 100 120 140 160 180 200

Maxim um Rati ng STM6321/632 2 STM68 21/6822/ 6823/ 6824/6825

18/26

4 Maximum Rating

Stressing the device above the rating listed in the Table 4 ma y cause perm anent damage to

the device. These are stress ratings only and operatio n of the device at these or any other

conditions above thos e indicated in the Operating sections of this specification is not

implied. Exposure to Absolute Maximum Rating con ditions for extended period s may affect

device reliability. Refer also to the STMicroelectronics SURE Program and other relevant

quality documents.

Table 4. Absolute Maximum Ratings

Symbol Parameter Value Unit

TSTG Storage Temperature (VCC Off) –55 to 150 °C

TSLD(1)

1. Reflo

w at peak temperature of 260°C (total thermal budget not to exceed 245°C for greater than 30 seco

nds).

Lead Solder Temperature for 10 seconds 260 °C

VIO Input or Output Volta ge –0.3 to VCC +0.3 V

VCC Supply Vo l tag e –0.3 to 7.0 V

IOOutput Current 20 mA

PDPower Dissipation 320 mW

STM6321/6322 ST M6 821/6822/ 6823/6824/68 25 DC and AC Parameters

19/26

5 DC and AC Parameters

This section summari zes the operati ng mea suremen t conditions, and the DC and AC

characteristics of the device. The parameters in the DC and AC characteristics Tables that

follow, are derived from tests performed under the Measurement Conditions summarized in

Table 5. Des igners should check that the operating conditions in th eir circuit match the

operating conditions when relying on the quoted parameters.

Table 5. Operating an d AC Me asure ment Con dit ions

Figure 25. AC Testing Input/Output Waveforms

Figure 26. MR Timing Waveform

1. RST for STM6322/6821/6825.

Figure 27. Watchdog Timing

Parameter STM6xxx Unit

VCC Supply Voltage 1.0 to 5.5 V

Am bient Operating Temperature (TA) –40 to 85 °C

Input Rise and Fall Ti mes ≤ 5ns

Input Pulse Voltages 0.2 to 0.8VCC V

Input and Output Tim ing Ref. Volt ages 0.3 to 0.7V CC V

AI02568

0.8VCC

0.2VCC

0.7VCC

0.3VCC

AI07837a

RST (1)

tMLRL

trec

tMLMH

AI09136

RST

WDI

VCC

trec

tWD

DC and AC Param eters S TM 6321 /632 2 STM68 21/6 822/6823/ 6824/ 6825

20/26

Ta ble 6. DC and AC Cha racteristics

Sym Alter-

native Description Test Condition (1) Min Typ Max Unit

VCC Operating Voltage 1.2 (2) 5.5 V

ICC

VCC Supply Current

(MR and WDI unconnected) T/S/R/Z (VCC < 3.6V) 4 12 µA

L/M (VCC < 5.5V) 6 17 µA

VCC Supply Current

(MR unconnected;

STM6322/6825)

T/S/R/Z (VCC < 3.6V) 3 8 µA

L/M (VCC < 5.5V) 3 12 µA

ILI

Input Leak age Current 0V = VIN = VCC –1 +1 µA

Input Leakage Current

(WDI)(3) WDI = VCC, time a verage 120 160 µA

WDI = GND, time a verage –20 –15 µA

ILO Open Dra in Reset Output

Leakage Cur rent VCC > VRST,

Reset not asserted –1 +1 µA

VIH Input High Voltage (MR )VRST > 4.0V 2.0 V

VRST < 4.0V 0.7VCC V

VIH Input High Volt age (WDI) (4) VRST (max) < VCC < 5.5V 0.7VCC V

VIL Input Low Volt age (MR)VRST > 4.0V 0.8 V

VRST < 4.0V 0.3VCC V

VIL Input Lo w Voltage (WDI) (4) VRST (m a x) < VCC < 5.5V 0.3VCC V

VOL

Output Lo w Voltage (R ST;

Push-pull or Open Drain)

VCC ≥ 1.0V, ISINK = 50µA,

Reset asserted 0.3 V

VCC ≥ 1.2V, ISINK = 100µA,

Reset asserted 0.3 V

VCC ≥ 2.7V, ISINK = 1.2mA,

Reset asserted 0.3 V

VCC ≥ 4.5V, ISINK = 3.2mA,

Reset asserted 0.4 V

Output Lo w Voltage (RST ;

Push-pull Only)

VCC ≥ 2.7V, ISINK = 1.2mA,

Reset not asserted 0.3 V

VCC ≥ 4.5V, ISINK = 3.2mA,

Reset not asserted 0.4 V

VOH

Output Hi gh Voltage (RST)

VCC ≥ 2.7V, ISOURCE = 500µA,

Reset not asserted 0.8VCC V

VCC ≥ 4.5V, ISOURCE = 800µA

, Reset not asserted 0.8VCC V

Output Hi gh Voltage (RST)

VCC ≥ 1.0V, ISOURCE = 1µA,

Reset asserted (0°C to 85°C) 0.8VCC V

VCC ≥ 1.5V, ISOURCE = 100µA,

Reset asserted 0.8VCC V

VCC ≥ 2.55V, ISOURCE = 500µA,

Reset asserted 0.8VCC V

VCC ≥ 4.25V, ISOURCE = 800µA,

Reset asserted 0.8VCC V

STM6321/6322 ST M6 821/6822/ 6823/6824/68 25 DC and AC Parameters

21/26

Reset Thresholds

VRST(5) Reset Thre shold

STM6xxxL 25°C 4.561 4.630 4.699 V

–40 to 85°C 4.514 4.746 V

STM6xxxM 25°C 4.314 4.390 4.446 V

–40 to 85°C 4.270 4.490 V

STM6xxxT 25°C 3.040 3.080 3.110 V

–40 to 85°C 3.000 3.150 V

STM6xxxS 25°C 2.890 2.930 2.960 V

–40 to 85°C 2.857 3.000 V

STM6xxxR 25°C 2.590 2.630 2.660 V

–40 to 85°C 2.564 2.696 V

STM6xxxZ (6) 25°C 2.280 2.320 2.350 V

–40 to 85°C 2.250 2.380 V

Reset Threshold Hysteresis L/M versions 10 mV

T/S/ R/Z versions 5 mV

VCC to RST Dela y

(VRST – VCC = 100mV, VCC

falling at 1mV/µs) 20 µs

trec (7) Reset Pulse Width A11.42ms

Blank 140 200 280 ms

J 240 280 480 ms

Reset Threshold

Temperature Coeffici ent 40 ppm

/°C

Push-button Rese t Input

tMLMH tMR MR Pulse Wid th 1 µs

tMLRL tMRD MR to RST Output Delay 500 ns

MR Glitch Immunity 100 ns

MR Pull-up Resistor 35 52 75 kΩ

W atchdog Timer

tWD (7) Watchdog Timeout Period 1.12 1.60 2.24 s

WDI Pulse Width 50 ns

1. Valid for Ambient Operating Temperature: TA = –40 to 85°C; VCC = 4.5 to 5.5V for “L/M” versions; VCC = 2.7 to 3.6V for

“T/S/R” versions; and VCC = 2.1 to 2.75V for “Z” ver s ion (except wher e noted).

2. VCC (min) = 1.0V for TA = 0 to +85°C.

3. WDI input is designed to be driven by a three-state output device. To float WD I, the “high-impedanc e mode” of the output

device must have a maximu m leak age curre nt of 10µA and a maximum output capacitance of 200pF. The output devi ce

mus t als o be able to sou rce an d sink at least 20 0µA wh en active.

4. WDI is internally serviced within the watchdog period if WDI is left unconnected.

5. The leak age current measured on the RS T pin is tested with the reset asserted (o utput hi gh imp edance).

6. Contact local sales office for availability.

7. Other trec and watc hdog timings are offer ed. M inimum order quantities may a pply. Contact local sale s office for availability.

Sym Alter-

native Description Test Condition (1) Min Typ Max Unit

Package Mechanical STM6321/6322 STM6821/6822/6823/6824/6825

22/26

6 Package Mechanical

Figure 28. SOT23-5 – 5-lead Smal l Outline Tran si stor Pa ckage Mechanical Drawin g

1. Dr awing is not to scale.

Table 7. S OT 23-5 – 5-lead Small Outline Tran si stor Pa ckage Mechanical Data

Symb mm inches

Typ Min Max Typ Min Max

A 1.200 0.900 1.450 0.0472 0.0354 0.0571

A1 0.150 0.0059

A2 1.050 0.900 1.300 0.0413 0.0354 0.0512

B 0.400 0.350 0.500 0.0157 0.0138 0.0197

C 0.150 0.090 0.200 0.0059 0.0035 0.0079

D 2.900 2.800 3.000 0.1142 0.1102 0.1181

D1 1.900 0.0748

E 2.800 2.600 3.000 0.1102 0.1024 0.1181

e 0.950 0.0374

F 1.600 1.500 1.750 0.0630 0.0591 0.0689

K010010

L 0.350 0.100 0.600 0.0138 0.0039 0.0236

SOT23-5

D1D

STM6321/6 322 STM6 821/ 6822/6823/682 4/6825 Part Numbering

23/26

7 Part Numbering

Table 8. Ordering Information Scheme

For other options, or for more inform ation on any aspect of this device, p lease conta ct the

ST Sales Office nearest you.

Example: STM6xxx LWY6E

Device Type

STM6xxx

Reset Threshold Voltage

L: VRST = 4.514 to 4.746V

M: VRST = 4.270 to 4.490V

T: VRST = 3.000 to 3.150V

S: VRST = 2.850 to 3.000V

R: VRST = 2.564 to 2.696V

Z: VRST = 2.250 to 2.380V (1)

1. Contact local sales office for availability.

Reset Pulse Width (2)

2. Contact local sales office for availability. Other trec and w atc h do g t im in gs are of f ered.

Minimum order quantities may apply. Contact local sales office for availability.

A: trec = 1 to 2ms

Blank: trec = 140 to 280ms

J: trec = 240 to 480ms

Package

WY = SOT23-5

Temperature Range

6 = –40 t o 85 °C

S hippi ng M ethod

E = ECOPA CK Package, Tubes

F = ECOPACK Package, Tape & Reel

Part Numbering STM6321/6322 STM6821/6822/6823/6824/6825

24/26

Table 9. Marking Description

Note: Where “x” = Assembly Work Week (A to Z), such that “A” = WW01-02, “B” = WW03-04, and

so fo rth .

Part Number Reset Thresho ld (V) Reset Pulse Width (ms) Topside Marki ng

STM6321MAWY6F 4.390 1.4 5CRx

STM6321LWY6F 4.630 200 5AUx

STM6321MWY6F 4.390 200 5AVx

STM6321TWY6F 3.080 200 5AWx

STM6321SWY6F 2.930 200 5AXx

STM6321RWY6F 2.630 200 5AYx

STM6322LWY6F 4.630 200 5BAx

STM6322MWY6F 4.390 200 5BBx

STM6322TWY6F 3.080 200 5BCx

STM6322SWY6F 2.930 200 5BDx

STM6322RWY6F 2.630 200 5BEx

STM6821LWY6F 4.630 200 5BGx

STM6821MWY6F 4.390 200 5BHx

STM6821TWY6F 3.080 200 5BJx

STM6821SWY6F 2.930 200 5BKx

STM6821RWY6F 2.630 200 5BLx

STM6822LWY6F 4.630 200 5BNx

STM6822MWY6F 4.390 200 5BPx

STM6822TWY6F 3.080 200 5BQx

STM6822SWY6F 2.930 200 5BRx

STM6822RWY6F 2.630 200 5BSx

STM6823LWY6F 4.630 200 5BUx

STM6823MWY6F 4.390 200 5BVx

STM6823TWY6F 3.080 200 5BWx

STM6823SWY6F 2.930 200 5BXx

STM6823RWY6F 2.630 200 5BYx

STM6824LWY6F 4.630 200 5CAx

STM6824MWY6F 4.390 200 5CBx

STM6824TWY6F 3.080 200 5CCx

STM6824SWY6F 2.930 200 5CDx

STM6824RWY6F 2.630 200 5CEx

STM6825LWY6F 4.630 200 5CGx

STM6825MWY6F 4.390 200 5CHx

STM6825TWY6F 3.080 200 5CJx

STM6825SWY6F 2.930 200 5CKx

STM6825RWY6F 2.630 200 5CLx

STM6823TJWY6F 3.080 280 5CQx

STM6823SJWY6F 2.930 280 5CRx

STM6823RJWY6F 2.630 280 5CSx

STM6321/6322 ST M6 821/6822/ 6823/6824/68 25 Revision History

25/26

8 Revision History

Table 10. Document Revision History

Date Revision Changes

August 25,

2004 1.0 First Draft

15-Dec- 04 2.0 Update characteristics (Figure 16, 17, 18; Table 6, and 8)

10-Mar-05 3.0 Document promoted to Datasheet status

17-Jun-05 4.0 Package marking update (Table 9)

11-Apr-06 5 Update characteristics, Lead- free text, a vailabili ty (Figure 4, 5, 6, 7,

8, 9, and 10; Table 1, 6, 8, and 9)

11-Aug-2006 6 Update Summary Description, Table 8, and 9.

STM6321/6322 STM6821/6822/6823/6824/6825

26/26

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