KA3842B/3B/4B/5B LINEAR INTEGRATED CIRCUIT CURRENT-MODE PWM CONTROLLERS The KA3842B/3B/4B/5B are fixe frequency current-mode PWM controller. They are specially designed for Off-Line and DC-to-DC converter applications with minimal external components. These integrated circuits feature a trimmed oscillator for precise duty cycle control, a temperature compensated reference, high gain error amplifier, current sensing comparator, and a high current totempole output Ideally suited for driving a power MOSFET. Protection circuity Includes built in under-voltage lockout and current limiting. The KA3842B and KA3844B have UVLO thresholds of 16V (on) and 10V (off). The KA3843B and KA3845B are 8.5V (on) and 7.9V (off). The KA3842B and KA38438B can operate within 100% duty cycle. The KA3844B and KA3845B can operate withi 50% duty cycle. FEATURES * Low Start Up Current Maximum Duty Clamp U/V Lockout With Hysteresis ORDERING INFORMATION Operating Frequency Up To 500 KHz Device | Package Operating Te re KA384XB | 8 DIP O~ +70C KA384XBD| 14 SOP O~ +70C BLOCK DIAGRAM Veg (12) 7 Vaer(t4) VND 8 5V SETI VreF RESET U.V.L.O, INTERNAL BIAS LOGLG PWR VC (11) V2 Veer Ves (3) R OUTPUT (10) PWM COMP (1) LATCH $s CURRENT SENSE (5) 3 RrlCy (7) OSCILLATOR *( 1S 14S0IC PIN NO *TOGGLE FLIP FLOP USED ONLY IN KA3844B, KA3845B PWR GND (8) a ELECTRONICS 603KA3842B/3B/4B/5B LINEAR INTEGRATED CIRCUIT ABSOLUTE MAXIMUM RATINGS em ELECTRONICS Characteristic Symbol Value Unit Supply Voltage Voc 3 Vv Output Current lo +1 A Analog Inputs Viana) 0.3 to Voc v Error Amp Output Sink Current Isak (.4) 10 mA Power Dissipation (T, = 25C) Pp 1 Ww ELECTRICAL CHARACTERISTICS ("Veo = 15V, Rr= 10KQ, Cr=3.3nF, T, =0C to + 70C, unless otherwise specified) Characteristic Symboi Test Conditions Min Typ Max | Unit REFERENCE SECTION Reference Output Voltage Veer Ty= 25C, Incr = 1MA 4,90 5.00 5.10 Vv Line Regulation AVace | 12VsVccs25V 6 20 mV Load Regulation AVrce | imAslner<20MA 6 25 mV Short Circit Output Current Isc Ty = 25C -100 | -180 | mA OSCILLATOR SECTION Oscillation Frequency f Ty = 25C 47 52 57 KHz Frequency Change with Voltage | Aff/AVec | 12V<Vocs25V 0.05 1 % Oscillator Amplitude Viosc) 1.6 Vop ERROR AMPLIFIER SECTION Input Bias Current laws -0.1 -2 uA Input Voltage Vues) Vi #2.5V 2.42 2.50 2.58 Vv Open Loop Voltage Gain Gvo 2V.<Vo<4V 65 90 dB Power Supply Rejection Ratio | PSRR 12V <Vecs 25V 60 70 dB Output Sink Current Isink Vo=2.7V, Vie t.1V 2 7 mA Output Source Current Isource Vo=2.3V, Vi = 5V -05 -1.0 mA High Output Vottage Vor V2= 2.3V, R. = 15K2 to GND 5 6 Vv | Low Output Voltage Vor V2=2.7V, R, = 15KO to Pin 8 0.8 1.1 v CURRENT SENSE SECTION Gain Gy (Note 1 & 2) 2.85 3 3.15 | VV Maximum Input Signal Via | Vi = 5V (Note 1) 0.9 1 1 v Power Supply Rejection Ratio | PSRR, 12V $Vcc<25V (Note 1) 70 dB Input Bias Current las ~3 -10 pA 604KA3842B/3B/4B/5B LINEAR INTEGRATED CIRCUIT ELECTRICAL CHARACTERISTICS (continued) (*Veo = 15V, Ry = 10K0, Cy =3.3nF, T,=0C to + 70C unless otherwise specified) Characteristic | symbot | Test Conditions | Min | Typ | Max | Unit OUTPUT SECTION isink = 20MA 0.08 0.4 v Low Output Voltage Vor len = 200mA 14 22 Vv lsounce = 2ZOMA 13 13.5 Vv High Output Voltage Vou Isounce = 200mA 12 130 Vv Rise Time ta Ty) =25C, C_= 1nF (Note 3) 45 150 ns Fait Time te T, = 25C, C,= InF (Note 3) 35 150 | ns | UNDER-VOLTAGE LOCKOUT SECTION KA3842B/44B 14.5 16.0 17.5 Vv Start Threshold Vrs Ka3843B/458 78 | 84 | 90 | Vv Min. Operating Voltage KA3842B/44B 8.5 10.0 11.5 Vv (After Turn On) Vorreny 1 n38496/458 7.0 7.6 8.2 Vv PWM SECTION KA3842B/43B 95 97 100 % Max. Duty Cycle Pon | KA3844B/458 47 48 50 % Min. Duty Cycle Dany 0 % TOTAL STANDBY CURRENT Start-Up Current Ist 0.45 1 mA Operating Supply Current locorry V3 = V2=OV 14 17 mA Zener Voltage Vz loc = 25mMA 30 38 Vv * Adjust Vcc above the start thresheld before setting at 15V Note 1. Parameter measured at trip point of lath with V.=0 2. Gain defined as: AV; A=, 0<V3<0.8V 3. These parameters, although guaranteed, are not 100% tested in production. 605 i ELECTRONICSADJUST KA3842B/3B/4B/5B LINEAR INTEGRATED CIRCUIT Fig. 1 Open Loop Test Circuit 2 2 Vase Ar 4.7K 2222 7 v4 1K aa tKIW 0.1 SENSE ADJUST OUTPUT 4.7K High peak currents associated with capacitive oads necessitate careful grounding techniques Timing and bypass capacitors should be connected close to pin 5 in a single point ground. The transistor and 5KQ potentiometer are used to sample the oscillator waveform and apply an adjustable ramp to pin 3. Fig. 2 Under Voltage Lockout ON/OFF COMMAND lec TO REST OF IC KA3842B/48/KA3843B/58 jc 15mA Von 16V 8.4V 10V 7.8V <tmaA fre Veo Vorr Von During Under-Voltage Lock-Out, the output driver is biased to a high impedance state. Pin 6 should be shunted to ground with a bleeder resistor to prevent activating the power switch with output leakage current. Fig. 3 Error Amp Configuration Error amp can source or sink up to 0.5mMA ELECTRONICSKA3842B/3B/4B/5B LINEAR INTEGRATED CIRCUIT Fig. 4 Current Sense Circuit ERROR aR R W CURRENT SENSE CURRENT COMPARATOR SENSE Peak current (ls) is determined by the formula: I 1.0V | SIMAX) ze Rs A small RC filter may be required to suppress switch transients. Fig. 5 Oscillator Waveforms and Maximum Duty Cycle LARGE Rr SMALL Cy vy j | | | INTERNAL CLOCK SMALL Rr LARGE Rr VAN AN, " LDL wternat croc Oscitiator timing capacitor, Cr, is charged by-Vper through Rr, and discharged by an internal current source. During the discharge time, the internal clock signal blanks the output to the low state. Selection of Rr and C; therefore determines both oscillator frequency and maximum duty cycle. Charge and discharge times are deter- mined by the formulas: t. * 0.55 Rr Cr te= Ps Cr int opes Ra) Frequency, then, is: f=(t.+td)-' 1.8 F 5KQ, f= or Rr> ,f RC; ELECTRONICSKA3842B/3B/4B/5B LINEAR INTEGRATED CIRCUIT Fig. 6 Oscillator Dead Time & Frequency DEADTIME vs Cy (Ar>5K) Fig. 7 Timing Resistance vs Frequency 100 30 | I g | % : | 10 4 \\ NN 1 22 4a? af] 22 a7 100 100 1K 10K 100K IM Fig. 8 Shutdown Techniques FREQUENCY (Hz) 1K VREF COMP = \ > 3300 SENSE SHUTDOWN TO CURRENT SHUTDOWN ot / SENSE-RESIST OR Shutdown of the KA3842B can be accomplished by two methods; either raise pin 3 above 1V or pull pin 1 below a voltage two diode drops above ground. Either method causes the output of the PWM comparator to be high (refer to block diagram). The PWM latch is reset dominant so that the output will remain low until the next clock cycle after the shutdown condition at pins 1 and/or 3 is removed. In one example, an externaily latched shutdown may be accomplished by adding an SCR which will be reset by cycling Vcc below the lower UVLO threshold. At this point the reference turns off, allowing the SCR to reset. Fig. 9 Slope Compensation Vaer ( 8 A fraction of the oscillator ramp can be resistively summed with the current sense signal to provide slope compen- sation for converters requiring duty cycles over 50%. Note that capacitor, C, forms a filter with R2 to suppress the leading edge switch spikes. ELECTRONICSKA3842B/3B/4B/5B LINEAR INTEGRATED CIRCUIT Fig. 10 TEMPERATURE DRIFT (Vref) Fig. 11 TEMPERATURE DRIFT (1st) KA3842B KA38428 5.02 T 550 T ' | rm | | Voom 15 () I : Voo=9 (V) 5.01} + Pt font (mA) | ___J soo | ~~ me pe 5.00 : ; an | | ; ON | \ \ | \ 498 350 |}- - - N fe | Ho \ | So \ 300 i RS N 4.96 | i | | 260 50 -2 0 2 50 75 100 125 150 -50 -25 0 2 80 75 100 125 150 TEMPERATURE (C) TEMPERATURE (C) Fig. 12 TEMPERATURE DRIFT (icc) KA3842B 15 T Vec# 18 (M), fo=1 (mA) , 14 NX t , NL _ 1 : : i : i 10 -50 ~25 0 25 50 7S 100 125 150 TEMPERATURE (C) ELECTRONICS