Integrated Device Technology, Inc. CMOS PARALLEL FIFO 64 x 4-BIT AND 64 x 5-BIT 1DT72401 IDT72402 1DT72403 IDT72404 FEATURES: First-In/First-Out Dual-Port memory 64x 4 organization (IDT72401/03) * 64x 5 organization (IDT72402/04) * 1DT72401/02 pin and functionally compatible with MMI67401/02 RAM-based FIFO with low fall-through time Low-power consumption Active: 175mW (typ.) Maximum shift rate 45MHz High data output drive capability Asynchronous and simultaneous read and write Fully expandable by bit width Fully expandable by word depth 1DT72403/04 have Output Enable pin to enable output data High-speed data communications applications High-performance CMOS technology Available in CERDIP, plastic DIP and SOIC Military product compliant to MIL-STD-883, Class B Standard Military Drawing #5962-86846 and 5962-89523 is listed on this function. DESCRIPTION: The 1DT72401 and IDT72403 are asynchronous high- performance First-In/First-Out memories organized 64 words by 4 bits. The IDT72402 and IDT72404 are asynchronous high-performance First-In/First-Out memories organized as 64 words by 5 bits. The IDT72403 and IDT72404 also have an Output Enable (QE) pin. The FIFOs accept 4-bit or 5-bit data at the data input (Do-D3, 4). The stored data stack up on a first- inftirst-out basis. A Shift Out (SO) signal causes the data at the next to last word to be shifted to the output while all other data shifts down one location in the stack. The Input Ready (IR) signal acts like a flag to indicate when the input is ready for new data (IR = HIGH) or to signal when the FIFO is full (IR = LOW). The Input Ready signal can also be used to cascade multiple devices together. The Output Ready (OR) signal is a flag to indicate that the output remains valid data (OR = HIGH) or to indicate that the FIFO is empty (OR = LOW). The Output Ready can also be used to cagcade multiple devices together. Width expansion is accomplished by logically ANDing the Input Ready (IR) and Output Ready (OR) signals to form composite signals. Depth expansion is accomplished by tying the data inputs of one device to the data outputs of the previous device. The Input Ready pin of the receiving device is connected to the Shift Out pin of the sending device and the Output Ready pin of the sending device is connected to the Shift In pin of the receiving device. Reading and writing operations are completely asynchro- nous allowing the FIFO to be used as a buffer between two digital machines of widely varying operating frequencies. The 45MHz speed makes these FIFOs ideal for high-speed communication and controller applications. Military grade product is manufactured in compliance with the latest revision of MIL-STD-883, Class B. FUNCTIONAL BLOCK DIAGRAM INPUT rT OUTPUT |, __ GE (1D 72403 and S| CONTROL WRITE POINTER ENABLE ror 2404) IR ,_LOGIC WRITE MULTIPLEXER T Dos Cc MEMORY S Qos DATAIN AR DATAout D4 __-+] RAY (IDT72402 I Qs (IDT72402 and and IDT72404) F IDT72404) _- MASTER AEAD MULTIPLEXER MR | RESET OUTPUT [* SO READ POINTER . CONTROL LOGIC H*orR The JOT logo is a registered trademark of integrated Device Technology, Inc. FAST is a trademark of National Samiconductar, Inc, MILITARY AND COMMERCIAL TEMPERATURE RANGES "21996 Integrated Device Technology. Inc 2747 dw 01 DECEMBER 1995 DSC-2747/4 5.22 11DT72401, IDT72402, IDT72403, 1DT72404 CMOS PARALLEL FIFO 64 x 4-BIT AND 64 x -BIT MILITARY AND COMMERCIAL TEMPERATURE RANGES PIN CONFIGURATIONS 1DT72401ADT72403 IDT724021DT72404 (IDT72404 Only) YY NC/OE V1 16 Vee NC/OE@? 1 Mv 1819 Vec OE C1 VY 20D Vee IR [2 1817 so IR G2 171] so NC [J 2 19] NC SIC) 3 P16-1, 14[5 OR si G3 16] OR in Cs wf] so Do 4 16-1 30 Qo Do C4 P18-1, 1f] Qo S| Oh 1777 OR 0105 S016-1 270 Qi Dt Os 018-1 14 I] Qi Dos 16 Qo De Oe 1 Qe Dz C6 5068-1 131 Qe Di Oe sO ai D3 7 101 Qa Ds 7 120 Qa D2 O17 41 Qe GND (]8 91] MR Ds C8 1) Qa Daa 1310 Qs DIP/SOIC arrawog | OND 8 of MR Da Co 121 Qa TOP VIEW DIP/SOIC 2747 dew 03 GND 10 117 MR TOP VIEW 2747 drw 04 CERPACK NOTES: TOP VIEW 1. Pin 1: NC - No Connection IDT72401, QE - 1IDT72403 2. Pin t: NC - No Connection IDT72402,0E - 1DT72404 ABSOLUTE MAXIMUM RATINGS") RECOMMENDED OPERATING CONDITIONS Symbo! Rating Commercial} Military | Unit Symbol Parameter Min. | Typ. | Max. | Unit VTERM | Terminal Voltage | -0.5 to +7.0 | -0.5to+7.0] Vv Vcc Mil. Supply Voltage 4.5 5.0 5.5 Vv wn aspect Vcc | Com't Supply Voltage| 45 | 50] 55] V fo GND GND _| Supply Voltage o |o |] o1Vv TA Operating Temp. Oto +70 55 to +125] C Vin Input High Voltage 20 _ V TBIAS Temperature 55 to +125 | -65 to +135] C Ty - Under Bias Vi Input High Voltage _ _- 0.8 Vv NOTE: 2747 toi 02 Ista Storage Temp. =55 to +125 | ~65 to +150 1. 1.5V undershoots are allowed for 10ns once per cycle. lout DC Output 50 50 mA Current CAPACITANCE (Ta = +25C, f = 1.0MHz) NOTE: 2747 tl 04 1. Stresses greater than those listed under ABSOLUTE MAXIMUM Symbol Parameter) Conditions | Max. | Unit RATINGS may cause permanent damage to the device. This is a stress F ~ rating only and functional operation of the device at these or any other CIN Input Capacitance VIN = OV 5 pF conditions above those indicated in the operational sections of this Cout Output Capacitance] Vout = 0V 7 pF specification is not implied. Exposure to absolute maximum rating NOTE: 3747 wio3 conditions for extended periods may affect reliabitity. 1. This parameter is sampled and not 100% tested. DC ELECTRICAL CHARACTERISTICS (Commercial: Vcc = 5.0V + 10%, TA = 0C to +70C; Military: Vcc = 5.0V + 10%, TA = -55C to +125C) Symbol Parameter Test Conditions Min. Max. Unit {iL Low-Level Input Current Vcc = Max., GND < Vis Vcc -10 - pA Nit High-Level Input Current Vcc = Max., GND < Vis Voc _ 10 LA VoL Low-Level Output Voltage Vcc = Min., lo. = 8MA _ 0.4 Vv VOH High-Level Output Voltage Vcc = Min., loH = -4mA 2.4 = Vv tos!) Output Short-Circuit Current Vcc = Max., Vo = GND ~20 =110 mA THz Off-State Output Current Vcc = Max., Vo = 2.4V 20 pA Itz (IDT72403 and iDT72404) Vcc = Max., Vo = 0.4V -20 = pA icc) Supply Current Vcc = Max., f = 10MHz | Com'l. _ 35 mA Military _ 45 mA NOTES: . 2747 tbl 04 1. Not more than one output should be shorted at a time and duration of the short-circuit should not exceed one second. Guaranteed but not tested. 2. Icc measurements are made with outputs open. OE is HIGH for IDT72403/72404. 3 For frequencies greater than 10MHZ, Icc = 35mA + (1.5mA x [f - 10MHz}) commercial, and Icc = 45mA + (1.5mA x [f - 10MHz)} military.1DT72401, IDT72402, IDT72403, 1DT72404 CMOS PARALLEL FIFO 64 x 4-BIT AND 64 x 5-BIT OPERATING CONDITIONS (Commercial: Voc = 5.0V + 10%, TA = 0C to +70C; Military: MILITARY AND COMMERCIAL TEMPERATURE RANGES Vcc = .0V + 10%, TA = ~55C to +125C) Commercial Mliltary and Commercial IDT72401L45 | IDT72401L35 | IDT72401L25 | IDT72401L15 | IOT72401L10 IDT72402L45 | IDT72402L35 | IDT72402L25 | IDT72402L15 | IDT724021,10 IDT72403L45 | IDT72403L35 | 10T72403L25 | IDT72403L15 | 1DT72403L10 IDT72404L45 | IDT72404L35 | IDT72404L25 | IDT72404L15 | IDT72404L10 Symbol Parameters Figure | Min. | Max. | Min. | Max. | Min. | Max. | Min. | Max. | Min. | Max. | Unit tsnH!) Shift in HIGH Time 2 9 = 9 = 1 = 1 11 - ns tsIL Shift in LOW Time 2 1 = 17 _ 24 _ 25 _ 30 _ ns tiDs Input Data Set-up 2 0 =- 0 _ 0 _ 0 _ 0 - ns ttDH Input Data Hold Time 2 13 15 _ 20 _ 30 _ 40 _ ns tsoH) | Shift Out HIGH Time 5 9 = 9 = 41 = 4 - 1 | os tsoL Shift Out LOW Time 5 11 _ 17 _ 24 _ 25 _ 25 _ ns tMRW Master Reset Pulse 8 20 = 25 = 25 = 25 = 30 _ ns tMRs Master Reset Pulse to SI 8 10 = 10 _ 10 _ 25 =~ 35 = ns tsIR Oata Set-up to IR 4 3 _ 3 _ 5 _ 5 _ 5 _ ns tHIA Data Hold from IR 4 13 _ 15 _ 20 _ 30 _ 30 = ns tson) | Data Set-up to OR HIGH 7 0 =~ 0 - 0 - 0 _ 0 _ ns 2747 tbl 05 AC ELECTRICAL CHARACTERISTICS (Commercial: Vcc = 5.0V + 10%, Ta = 0C to +70C; Military: Voc = 5.0V + 10%, TA = -55C to +125C) Commercial Military and Commercial 1OT72401L45 ] IDT72401L35 | IDT72401L25 | IDT72401L15 | IDT72401L10 10T72402L45 | IDT72402L35 | IOT72402L25 | IDT72402L15 | IDT72402L10 1DT72403L45 | IDT72403L35 | 1DT72403L25 | IDT72403L15 | 10T72403L10 IDT72404L45 | IDT72404L35 | IDT72404L25 | 1DT72404L15 | IDT72404L10 Symbol Parameters Figure | Min. | Max. | Min. | Max. | Min. | Max. | Min. | Max. | Min. | Max. | Unit tin Shift In Rate 2 _ 45 _ 35 = 25 = 15 _ 10 MHz tac Shift In to Input Ready LOW 2 _ 18 = 18 = 21 _ 35 = 40 ns tay!) Shift In to Input Ready HIGH 2 - 18 - 20 - 28 _ 40 _ 45 ns tout Shift Out Rate 5 _ 45 _- 35 _ 25 _ 15 _ 410 MHz ton) | Shift Out to Qutput Ready LOW 5 = 18 = 18 = 19 _ 35 = 40_| ns tory | Shift Out to Output Ready HIGH 5 _ 19 _ 20 _ 34 40 _ 55 ns 100H Output Data Hold (Pravious Word) 5 5 5 _ 5 _ _ _ ns toos Output Data Shift (Next Word} 5 _ 19 _ 20 _ 34 _ 40 _ 55 ns teT Data Throughput or "Fall-Through 4,7 _ 30 _ 34 _ 40 _ 65 = 65 ns tMRORL Master Reset to OR LOW 8 _ 25 _ 28 _ 35 _ 35 _ 40 ns tMAIRH Master Reset to [R HIGH 8 _- 25 _- 28 - 35 _- 35 _ 40 ns iMRQ Master Reset to Data Output LOW 8 _ 20 _ 20 _ 25 _ 35 = 40 ns tooe') | Output Valid from OF LOW 9 _ 12 15 _ 20 _ 30 _ 35 ns tuzoe] Output High-Z from QE HIGH 9 = 12 = 12 = 15 _ 25 = 30_]| ns tieH!2) | Input Ready Pulse HIGH 4 9 = 9 = 1 = u = 1 = ns torH!2) | Quput Ready Pulse HIGH 7 9 9 = 11 = 14 _ 11 _ ns j NOTES: 2747 tht 0: 1, Since the FIFO is a very high-speed device, care must be excercised in the dasign of the hardware and timing utilized within the design, Device grounding and decoupling are crucial to corract operation as the FIFO will respond to very small glitches dua to long reflective lines, high capacitances and/or poor supply decoupling and grounding. A monolithic ceramic capacitor of 0.11F directly between Vcc and GND with very short lead length is recommendec 2. This parameter applies to FIFOs communicating with each other in a cascaded mode. IDT FIFOs are guaranteed to cascade with other IDT FIFOs cf like speed grades. wo . 10772403 and IDT72404 only. 4. Guaranteed by design but not currently tested.1DT72401, IDT72402, IDT72403, 1DT72404 CMOS PARALLEL FIFO 64 x 4-BIT AND 64 x 5-BIT AC TEST CONDITIONS Input Pulse Levels GND to 3.0V Input Rise/Falt Times 3ns Input Timing Reference Levels 1.5V Output Reference Levels 1.5V Output Load See Figure 1 2747 tbl 07 ALL INPUT PULSES: 3.0V GND <3ns 2747 drw 05 SIGNAL DESCRIPTIONS INPUTS: DATA INPUT (D0-3, 4) Data input lines. The 1IDT72401 and IDT72403 have a 4-bit data input. The 1IDT72402 and IDT72404 have a 5-bit data input. CONTROLS: SHIFT IN (SI) Shift In controls the input of the data into the FIFO. When Stis HIGH, data can be written to the FIFO via the Do-3, 4 lines. SHIFT OUT (SO) Shift Out controls the output of data of the FIFO. When SO is HIGH, data can be read from the FIFO via the Data Output (Qo-3, 4) lines. MASTER RESET (MR) Master Reset clears the FIFO of any data stored within. Upon power up, the FIFO should be cleared with a Master Reset. Master Reset is active LOW. INPUT READY (IR) When Input Ready is HIGH, the FIFO is ready for new input data to be written to it. When IR is LOW the FIFO is unavailable for new input data. Input Ready is also used to cascade many FIFOs together, as shown in Figures 10 and 11 in the Applica- tions section. OUTPUT READY (OR) When Output Ready is HIGH, the output (Qo-3, 4) contains valid data. When OR is LOW, the FIFO is unavailable for new output data. Output Ready is also used to cascade many FIFOs together, as shown in Figures 10 and 11. OUTPUT ENABLE (QE) (IDT72403 AND IDT72404 ONLY) Output enable is used to read FIFO data onto a bus. Output Enable is active LOW. MILITARY AND COMMERCIAL TEMPERATURE RANGES 5V 5600 OUTPUT 1.1K 30pF* o P' = 2747 drw 06 of equivalent circuit Figure 1. AC Test Load including scope and jig OUTPUTS: DATA OUTPUT (Qo-3, 4) Data Output lines. The 1DT72401 and IDT72403 have a 4- bit data output. The |DT72402 andIDT72404 havea 5-bit data output. FUNCTIONAL DESCRIPTION These 64 x 4 and 64 x 5 FIFOs are designed using a dual port RAM architecture as opposed to the traditional shift register approach. This FIFO architecture has a write pointer, a read pointer and control logic, which allow simultaneous read and write operations. The write pointer is incremented by the falling edge of the Shift In (SI) control; the read pointer is incremented by the falling edge of the Shift Out (SO). The Input Ready (IR) signals when the FIFO has an available memory location; Output Ready (OR) signals when there is valid data on the output. Output Enable (QE) provides the capability of three-stating the FIFO outputs. FIFO Reset The FIFO must be reset upon power up using the Master Reset (MR) signal. This causes the FIFO to enter an empty state, signified by Output Ready (OR) being LOW and Input Ready (IR) being HIGH. In this state, the data outputs (Qo-3, 4) will be LOW. Data Input Data is shifted in on the LOW-to-HIGH transition of Shift In (SI). This loads input data into the first word location of the FIFO and causes Input Ready to go LOW. On the HIGH-to- LOW transition of Shift In, the write pointer is moved to the next word position and Input Ready (IR) goes HIGH, indicating the readiness to accept new data. Ifthe FIFO is full, Input Ready will remain LOW until a word of data is shifted out.1DT72401, IDT72402, IDT72403, iDT72404 CMOS PARALLEL FIFO 64 x 4-BIT AND 64 x 5-BIT MILITARY AND COMMERCIAL TEMPERATURE RANGES Data Output Data is shifted out on the HIGH-to-LOW transition of Shift Out (SO). This causes the internal read pointer to be advanced to the next word location. If data is present, valid data will appear on the outputs and Output Ready (OR) will go HIGH. If data is not present, Output Ready will stay LOW indicating the FIFO is empty. The last valid word read from the FIFO will remain at the FIFOs output when itis empty. When the FIFO is not empty, Output Ready (OR) goes LOW on the LOW-to-HIGH transition of Shift Out. Previous data remains on the output until the HIGH-to-LOW transition of Shift Out (SO). TIMING DIAGRAMS SHIFT IN INPUT READY INPUT DATA tios Fall-Through Mode The FIFO operates in a fall-through mode when data gets shifted into an empty FIFO. After a fall-through delay the data propagates to the output. When the data reaches the output, the Output Ready (OR) goes HIGH, Fall-through made also occurs when the FIFO is completely full. When data is shifted out of the full FIFO, a location is available for new data. After a fall-through delay, the Input Ready goes HIGH. if Shift In is HIGH, the new data can be written to the FIFO. Since these FIFOs are based on an internal dual-port RAM architecture with separate read and write pointers, the fall- through time (tPT) is one cycle long. A word may be written into the FIFO on aclock cycle and can be accessed on the next clack cycle. 2747 drw 07 Figure 2. Input Timing (7 SHIFT IN" @) (1) INPUT READY (3) STABLE DATA eX INPUT DATA NOTES: . Input Data is loaded into the first word. . Input Ready goes LOW indicating the first word is full. . The write pointer is incremented. . The FIFO is ready for the next word. . If the FIFO is full then the Input Ready remains LOW. NOOB WON RRRKRKKKRKKK RRR KKKKKKKKKKKRN 2747 drw 0B . Input Ready HIGH indicates space is available and a Shift |n pulse may be applied. . Shift In pulses applied while Input Ready is LOW will be ignored (sea Figure 4). Figure 3. The Mechanism of Shifting Data Into the FIFO10772401, IDT72402, IDT72403, IDT72404 CMOS PARALLEL FIFO 64 x 4-BIT AND 64 x 5-BIT MILITARY AND COMMERCIAL TEMPERATURE RANGES TIMING DIAGRAMS (Continued) (2) SHIFT OUT j (3) SHIFT IN / (5) (4) INPUTREADY 1) > teT tiPH tsin t HIR wor ons RRRRERRXXKKKREEERRKKRRERERKKIE | SAB ra 2747 drw 09 NOTES: 1. FIFO is initially full. 2, Shift Out pulse is applied. 3. Shift In is held HIGH. 4. As soon as Input Ready becomes HIGH the input Data is loaded into the FIFO. 5. The write pointer is incremented. Shift In should not go LOW until (tet + tieH). Figure 4. Data is Shifted In Whenever Shift In and input Ready are Both HIGH tout V/fouT SHIFT OUT OUTPUT READY tODH OUTPUT DATA A-DATA C-DATA (1) 2747 drw 10 NOTES: 1. This data is loaded consecutively A, B, C. 2. Data is shifted out when Shift Out makes a HIGH to LOW transition. Figure 5. Output Timing SHIFT OUT (2) OUTPUT READY (3) OUTPUT DATA A-DATA 2747 drw 14 NOTES: . Output Ready HIGH indicates that data is available and a Shift Out pulse may be applied. . Shift Out goes HIGH causing the next step. . Output Ready goes LOW. The read pointer is incremented. . Output Ready goes HIGH indicating that new data (B) is now available at the FIFO outputs. . If the FIFO has only one word loaded (A DATA) then Output Ready stays LOW and the A DATA remains unchanged at the outputs. . Shift Out pulses applied when Output Ready is LOW will be ignored. NOMWERONS Figure 6. The Mechanism of Shifting Data Out of the FIFO 5.22 6(DT72401, IDT72402, IDT72403, IDT72404 CMOS PARALLEL FIFO 64 x 4-BIT AND 64 x 5-BIT MILITARY AND COMMERCIAL TEMPERATURE RANGES TIMING DIAGRAMS (Continued) SHIFT IN A \ SHIFT OUT / {PT OUTPUT READY 41) A tsor he tory DATA OUTPUT DATA VALID 2747 dew 12 NOTE: +. FIFO intial empty. Figure 7. tet and topx Specification ~_ 1 MAW >| MASTER RESET \ ft a tMRIRH > INPUT READY 13) A \ (1) ot tMRORL OUTPUT READY \ t {MAS | SHIFT IN ft {MRO cal para ouTuT \\A AAA, NOTE: 2747 dew 13 1. Worst case, FIFO initially full... Figure 8, Master Reset Timing OUTPUT ENABLE THZOE {ooe DATA OUT 4 2747 drw 14 NOTE: 1. High-Z transitions are referenced to the steady-state Vou -SOOmV and Vot +500mV levels on the output. tHz0E is tested with 5pF load capacitance instead of 30pF as shown in Figure 1. Figure 9. Output Enable Timing, IDT72403 and IDT72404 Only 5.22 7IDT72401, 1IDT72402, IDT72403, IDT72404 CMOS PARALLEL FIFO 64 x 4-BIT AND 64 x 5-BIT MILITARY AND COMMERCIAL TEMPERATURE RANGES APPLICATIONS SHIFT IN -*} SI OR SI OR / OUTPUT READY INPUT READY 7 IR so ;* IR SO /#* SHIFT OUT *] Do Qo | Do Qo ->_ *| D Q D +_ DATAIN4 41 p, az} +] pe Qz[ > PDATAOUT | D3 WR Qs Ds MR Q3;- R Tt | 2747 drw 15 MR & NOTE: 1. FIFOs can be easily cascaded to any desired path. The handshaking and associated timing between the FIFOs are handied by the inherent timing of the devices. Figure 10. 128 x 4 Depth Expansion IR so IR so IR so SHIFT OUT SI OR Si OR Sl OR Do Qo Do Qo Do Qo Di Qi Di Qi Di Qi LLL D2 Qe2 D2 Qz2 D2 Qa2 = D3 MR 3 D3 MR 3 D3 MR Q3f- +CE IR so IR sO IR so Sl OR Sl OR Si OR COMPOSITE INPUT Do Qo Do Qo Do Qo f- COMPOSITE READY Di Qi Di Qi Di Qi READY. D2 Q2 D2 Q2 D2 Q2;- 703 MR a3 D3 MR 3 D3 MA Q3aP IR so IR so IR so SHIFT IN Sl OR Sl OR sl OR Do Qo Do Qo Do Qo - Di Qi Di Qi Di Qi-- -] Da Q2 D2 Qa D2 Q2[- 7103 MA Qs D3 MR Q3 D3 MR 3 T T T 2747 dew 16 NOTES: 1. When the memory is empty, the last word will remain on the outputs until tha Master Reset is strobed or a new data word falls through to the output. However, OR will remain LOW, indicating data at the output is not valid. 2. When the output data changes as a result of a pulse on SO, the OR signal always goes LOW before there is any change in output data and stays LOW until the new data has appeared on the outputs. Anytime OR is HIGH, there is valid stable data on the outputs. 3. If SO is held HIGH while the memory is empty and a word is written into the input, that word will appear at the output after a fall-through time. OR will go HIGH for one internal cycle {at least toAL) and then go back LOW again. The stored word will remain on the outputs. if more words are written into the FIFO, they will line up behind the first word and will not appear on the outputs until SO has been brought LOW. 4. When the Master Reset is brought Low, the outputs ara cleared to LOW, IR goes HIGH and OR goes LOW. If Sl is HIGH when the Master Reset goes HIGH, the data on the inputs will be written into the memory and IR will retum to the LOW state until SI is brought LOW. if SI is LOW when the Master Reset is ended, IR will go HIGH, but the data in the inputs will not enter the memory until SI goes HIGH. 5. FIFOs are expandable on depth and width. However, in forming wider words, two extemal gates are required to generate composite tnput and Output Ready flags. This is due to the variation of delays of the FIFOs. Figure 11. 192 x 12 Depth and Width Expansion .22 810772401, IDT72402, IDT72403, IDT72404 CMOS PARALLEL FIFO 64 x 4-BIT AND 64 x 5-BIT ORDERING INFORMATION IDT XXXXX xX Xx x x Device Type Power Speed Package Process/ Temperature Range Blank 72401 72402 72403 72404 MILITARY AND COMMERCIAL TEMPERATURE RANGES Commercial (0C to+70C) Military (-55C to+125C) Compliant to MIL-STD-883, Class B Plastic DIP (600 mils wide) Plastic DIP (600 mils wide) Small Outline IC Com'l, Only co and MU shift Frequency (ts) Com't. and Mit Speed in MHz Com'l. and Mil Low Power 64 x 4 FIFO 64 x5 FIFO 64 x 4 FIFO 64 x 5 FIFO 2747 dew 17 5.22