Am26L02/96L02 Low Power Dual Retriggerable Resettable Monostable Multivibrators Distinctive Characteristics: One-fourth the power of the equivalent Am2602/9602 . dual single shots. 50ns typical propagation delay. | Fan-out of 3 with standard TTL circuits. | Guaranteed pulse width variation versus temperature. 100% reliability assurance testing in compliance with MIL STD 883 Electrically tested and optically inspected die far the assemblers of hybrid products Mixing privileges for obtaining price discounts. Refer to price list Available in highiy reliable molded epoxy, hermetic dual-in-line or Hermetic flat package. FUNCTIONAL DESCRIPTION tive The Am 26L02 and 96L02 are low-power dual DC-level sensi- ators which provide an output puise whose duration and accuracy depend on external timing components. Provision Is made for triggering on the rising or falling edge of an input signal. AN inputs are DC coupled making trigger- Ing independent of input rise and fall times. Each time the output from the OR trigger gate goes from a FALSE (LOW) to TRUE (HIGH) condition triggering occurs independent of the state of the monostable. The direct clear facility allows a tuning cycle to be terminated at any time during the cycle. A LOW signal on the t, input tesets the monostable independent of other canditions. The Am26L02 has a guaranteed pulse width variation versus temperature of only1% over the temperature range 0 to +75C LOGIC DIAGRAM Dp 7 v = Pin 16 i 3 Gad = Ping INTERNAL TIMING CIRCUITRY &x CxPx 1,18 214 Ban. 9 2 aS S.2b2 V32Ka . a Ver P sans co oc 343 a6io 2ean 0 GND ORDERING INFORMATION Pan Package Temperature .* Order Number Type Range - Number Am26L02 Molded DIP 0C to 425C Am26L0259A Am26L02 Hermetic DIP OG +75C Am26L0259E Am26L02 Hermetic DIP 68C ta 4125C Am26L0251E Am26L02 Hermetic Flat Pak, - 65Gte +125C Am26L0251N Am26L02 Olea s- . Note Am26LO02XXD AmS6L02 Moided oe ed C to +75C U6M96L0259X Am96L02 Herm@ic DIRZ ~ O0C to +75C U7B96L0259X Am96L02 Hermetic pr 55C ta +125C 1 U7B96L0251X Ama6L02.<,termelic FlatPak 55C to +125C U4L96L0251X Am96L02 Dice Note UXX96L02XXD Note: The dice supptied will contain units which meet both OG to +75C 55C to +125C temperatura range. CONNECTION DIAGRAM Top View cleat LO TOUT RowesTaBht # TTI: 4 ake SMEAR MAXIMUM NGS (Above which the useful life may be impaired) Storage Tempe... i.e 65C to +159 Temperature (Ambient) Under Bias 55C to +125 Supply Voltage to Ground Potential (Pin 16 to Pin 8) Continuous O.5Vto +4) OC Voltage Applied to Outputs for High Output State 0.5 Vito +Vcom DC Input Voltage ~0.5 Vio 455 Output Current Into Outputs When Output is LOW 307 DC input Current ~30 MA to 455, ELECTRICAL CHARACTERISTICS OVER OPERATING TEMPERATURE RANGE {Unless Otherwise Noted) AMOGLOZ5OX/ 26L0260X T, = 0C to + 78C Voc 4.75 V to 5.25 Am@CLOZSIX/2OLONSIX T, = 88C 10 +125C Voc = 4.50 V 105.50 Parameters Description Test Conditions (Note 1) Min. Typ. (Note 1) Max, Unis Vou Output HIGH Voltage Voc = MIN. log, = 0.38 mA 24 36 Volts Min = Mig Or My Voc =MIN., lo, = 4.92 mA Vv, Output LOW Voltage ce 7 OL 0.15 Og Volts o : Vin = Min Orv | | Guaranteed input logical HIGH GH rf A Vin Input HIGH Level voltage for ali Inputa 20 Volts Vi input LOW Level Gvaranteed input logical LOW 07 Volts voltage for all inputs 93L Unit Load | = MAX, V,, = 0.3V 0.25 0. (hota 2 Input LOW Curent Voc = MAX. Vy = 0.3 02 04 ma 93L Unit Load Vv MAX, Vi = 24V 2. lig Input HIGH Current co = MAK Viy = 2.4 20 uA (Note 2) input HIGH Current MAX..V,, = 5.5 V 1.0 mA ise Output Short Circuit Current | Voc = MAX. Va, = 1.00 | Lae 13 mA hoc Power Supply Current Voc = MAX. 10 16 mA Notes: 1: Typicat limite are at Veo @ 5.0 , 25C ambient and maximum Wading. 2: Actual input currents are obtained by multiplying unit load currant by the 931 Input load factor. (See loeding ruleu) Switching Characteristics (7, = 25c) Parameters Test Conditions Min =Typ Max Units tay Turn Off Delay Negative Trigger input | Am26/96L0251X 55 75 | ou to True Output Am26/96L0258X 55 80 ! toy Turn On Delay Negative Trigger Input Nec = 5.0V, C, = 15 pF : Z to False Output Ry == 20 kt, Cy = 0 pF 42 a2 | ons th. (min) Minimum True Output Pulse Width 110 ns Voc = 5.0 V, CG a= 15 pF : T Pulse Width at True Output Fy = 39 KO, Cy 1000 pF 124 #138 15.2 Fe Am26/96L0251X 20 200 Timing Resistor te 2) po | Li Pa s (Note 2) Am26/96L0258X 16 220 _ (8) Delay from > to Q output LOW 27 4 | ns: AmB6L0259X 0 60348 i 4T Maximum Change in Pulse Width True Output | Am@6L0251X Voc = 6.0 V, C, = 15 pF oD 1.3 % Over operating temperature range Am2610259X Ry = 39 kf, Cy = 1000 pF 0O 0.3 1.0 | [ Am26L0251xX 0 i040 | i Notes: 1. Tents are conducted with a 30 k0 resistor pl 2. Maximum permissibie R, when used below 4-28 laced between Pin 2 (14} and Veg unless otherwise noted. OC is 100 ka. 3 iza!l@l<eidlcl 1S13! ee OPERATION RULES 0C to +75C operation and 20 Ki to 1 if a fixed vatue of A, ls used, the following values operation. |. The output pulse width T Is defined as follows: 3.0 T= 099R,C, 11 + RoI n e 4 a A < 0.6 FR, (Max) . R~ R,(O7hih,.O) 2 This circuit also aliows larger value of A, (min). A, - A, (mex) ; D,:; any wiicon oa . R to be used for fonges output pulse widin Q Any NPN suscon device with aye vee diode, euch suiticient h,, al (ow Currents, im yee) iN 1141 es FOTO part mimes such as 2N2511 Both circuits prevent reverse voltage across C,. The pulse width F for the circuits 18 defined as follows = 0.90 AC, {1 + $y Where: Risin k@, GC, nin pF, T Is in oe. 5. To obtain variabie pulse width, by remote iimming, the following circuit is recommended im 2081 We x ny tm My ASCLORE AS POSSINLE TD DE VICE mono ee 6. Under any operating condition, C, and FR, (min) must be kept as close la the circuit as possible to minimize stiay Capacitance end reduce noise pickup 7. Input Trigger Pulse Rules. t,t, ty, t, > GOn8 2 wn sos we input to Pin 5 (14) nt WF oe Nf Input to Pin 4 (12) . : XS, Pin 4 (12) = LOW ov . ae Pin 5 (11) = HIGH Ste Sent Pin 3 (13) HIGH wourvr foi fi Pin 3 (13) = HIGH Law ve firs 8. The relriggerable pulse width Is calculated as shown below: 3.0 The retrigper pulse width 18 aqua to the pulse width (,_ alus a delay time For pulse widins gresier than S00ns. 1 Can be approximated as t,_ Tete thee BOBIAC TH GD + tye NOTE: Aetriggering will not occur It the retrigger pulse comes within 0.33 RC, { * 9. Reset Operation - The Am26L02/06L02 have an sclive LOW reset facility. By applying a low to the reset input, any timing cycla can be terminated or any new cycle inhibited until the iow reset input ia ramoved. Trigge: inpute will not produce spikes in the ouiput when the | An external resisior A, and an external capactior C, are required as shown 00 kQ for 5SC to +125C operation. C, may vary trom 0 to any value necessary and obtamable recommended: R, # 120 kL for 0G to + 75C operation, A, = 38 KL for S54C to + 125C (For C, greater than 10! pF) Where: A, is in ki, Cy is in pF, Tis inns For C,- 10: pF see Fig. 3 Kf electrolytic type capacitors are to be used, the following two arrangements are recommended in the dogic diagram The valuva of A, may vary trom 20 kt: to 200 ki! for O ns atter the initial tngger pulse at is held tow. DEFINITION OF TERMS SUBSCRIPT TERMS: H HIGH, applying to a HIGH logic level or when used with Voc to indicate high Vcc value. 1 Input. L_ LOW, applying to LOW logic level or when used with Voc to indicate low V_- value. 0 Output. OPERATIONAL TERMS: 1, Forward input load current. tg, Output HIGH current, forced out of output in Vo,, test. ly, Output LOW current, forced into the output in V_, test. I, Reverse input load current. Negative Current Current flowing out of the device. Positive Current Current flowing into the device. Vy Minimum logic HIGH input voltage. Refer to tigure 2. , Maximum togic LOW input voltage. Refer to figure 2. You Minimum togic HIGH output voltage with output HiGH current I,,, flowing out of output. Yo, Maximum logic LOW output voltage with output LOW current to, into output. FUNCTIONAL TERMS: cf The asynchronous direct clear input. A LOW on this input resets the monostable independent of other conditions. Fan-Out The logic HIGH or LOW output drive capability in terms ot input Unit Loads. , The active LOW input of the monostables. With input |, LOW @ HIGH to LOW transition on 1, will cause triggering. 1, The active HIGH input of the monostables. With T; HIGH a LOW to HIGH transition on I, will cause triggering. Input Unit Load One T?L gate input joad. Q@ The TRUE output of the monastables. @ = The FALSE output of the monostabies. Triggering The switching of the monoslable from the stable state to the unstable state and start of the timing cycle. SWITCHING TERMS: hae The propagation delay trom a HIGH lo LOW transition on % to the true (Q) output LOW to HIGH transition. Spa The propagation delay from a HIGH to LOW transition on to to the false (Q) outpul HIGH ta LOW transition. t, {min} The minimum true (Q)} output pulse width with Ry = 20 ka, C, = 0 pF. T The pulse width obtained with R, = 39 k2, C, = 1000 pF. AT The maximum percentage change in puise width of the true (Q) autput over the lemperature range from the pulse width at 25C. VEi | 4 4 ome net ma Ne Raa ES Toe ee rapeanat cet pronto ecg: 4-30) Switcia,. IME TEST CIRCUIT AND WAVEFORMS TRUTH TABLE Am26L02/96L.02 For Each Monostabie c, Operation HL L H Trigger H Lo-H H Trigger x x L Reset H= HIGH Voltage Level L=Low Vollage Levet % = Don't Care . HL = HIGH to LOW Voltage Level transition LH = LOW to HIGH Voltage Lavel transition INPUT PULSE i= 25 kHz Amp ~ Jovy Width = 100 ns Let Wag Figure 1 INPUT/OUTPUT INTERFACE CONDITIONS Voltage interlace Conditions Low & HIGH Current Interface Conditions Low OUTPUT OFIVING Low INPUT LOAD ORIVEN "Low" MINIMUM Logic HIGH OUTPUT VOLTAGE MAUMUM LOGIC LOW OUTPUT VOLTAGE a: ais Current intertace Conditions HiGH & OUTPUT DRIVING INPUT LOAD HIGH DRIVEN HIGH ORIVEN DE vice DAIVEN: Device DEVICE Figure 2 us i vereAm26L02/96L02 LOADING RULES 93100 SERIES 9300 SERIES UNIT LOADS UNIT LOADS Input Fanout Unit Load Fanoul Input Output Output Input input Output Output Input/Output Pin No.'s Unit Load HIGH tow HIGH LOW HIGH Low Monostable 1 C, 1 =_ -_ _ _ Te CA, 2 ~ ~ - | = _ _ a G 3 1 _ 05 0.25 ee 1, 4 1 | os 0.25 _ To 5 1 _ 05 0.25 _ a a 6 12 12 6. ~ a 7 12 12 or GND 8 = = _ ~ Monostabie 2Q 9 _ 12 12 = - Q 10 _ 2 12 Oe Ib " 1 [os 0.28 _ 1 12 1 - O50.25 a G 13 1 = _ 05 0.25 - 2 CR, 14 a _ ~ ~ Cy 15 _ - _ _ - Veco 18 = = a a Tabie | NEGATIVE TRIGGER DELAYns MIN OUTPUT PULSE WIDTH na Typical Pulse Characteristics Negative Trigger Delay Time Versus Ambient Temperature 100, Yec CL + 159F oO 16 -% 6 126 Ty, - AMBIENT TEMPERATURE Cc Min. Output Pulse Width Versus Ambient Temperat Veos x = 2OkiL ey #0 50 75 28 2 76 126 Ty AMBIENT TEMPERATURE *C NORMALIZED O/F PULSE WIDTH Tow us Normalized Output Pulse Width Versus Operating Duty Cycle 14 08 a8 20 Yoo * Ry = 39k: Cy 1000pF Tao C 40 60 BO OPERATING DUTY CYCLE -*. Gulput Pulse Width T Using Low Values Of Cx 10 100 19! x07 Cy ~ PF Figura 3 10 NORMALIZED OUTPUT PULSE WIDTH VEASUS SUPPLY VOLTAGE NORMALIZED OUTPUT PULSE WIDTH Normalized Output Pulse Width Versus Supply Voltage 6 40 4s 50 55 6.0 SUPPLY VOLTAGE - VOLTS Normalized Output Pulse Width Versus Ambient Temperature 1.02 Veg 2 80V Hy = 30a: eye O00 pF 98 bu 24 G25 SO 75 100 128 Tq AMBENT TEMPERATURE = C a 431Am96L02 APPLICATIONS Voc Yee . R 4 ! at x2 Cxy Cx - Lb ws] hia . 6 19 OuTPuT : 4 Arn26L02 Iz Am26L02 T=} an + oaLoz u jt aBLa2 - AAMT AMM2 a Q 2 on out hL | t te Delayed Pulse Generation Tha first monostable datermines the time T, before the initiation of the output puise. The second monostable determines T,, the output pulse width. Figure 5 - 1 2 15 14 - 5 " Q| 10 OuTeuT Am26L02 Am26L02 + oft af ' z to ENABLE i , i i Pulse Generator : The output frequency produced with the above contiguration is determined by C,, and A,,, while the pulse width is determined by C,, and Ay; Monostabte 1 forms an astable multivibrator with an output pulse width 3 Of approximately 110.ns, while manostable 2 extends the pulse width to the required value. z Figure 6 hh PHYSICAL DIMENSIONS : -in-Line ? 4 TYT TTT . tke ro ' soo = ray i = fh aft {U. Le a seer ea be Fiet Package ee uo te nas RAEN GM Rac it ig era Pt ADVANCE MICA - DEVICES IN. - 9017 Thompson Plat Suanyva California 9408 ~ (408) 792-24 TWX: 910-339-926 - TELEX: 34-636 Advanced Micro Devices can not assume responsibility far use of any cleultry described other than circuitry entirely embodied In an Advanced Micro Devices produc 4-32Preliminary Information AMD<ad\ 21850E/0November 1998 AMD-K6-2 Processor Data Sheet Stop Clock Stop Grant State STPCLK# Sampled Negated Normal (Re-entered after PLL stabilization) CLK AVAVAVAUAVAUAUAUA\\GAUAUAUAVAVAVAUB WAUAUAVAY AI313] BE[7:0|# S f ADS# S$ TL M/\O# % v_/ D/C# S S W/R# 5 s\ CACHE# $5 mr STPCLK+# SS $ D[63:0] 5 KEN# 5) BRDV# Figure 75. Stop Grant and Stop Clock Modes, Part 2 Chapter 5 Bus Cycles 169AMD@ Preliminary Information AMD-K6-2 Processor Data Sheet 21850E/0November 1998 INIT-Initiated Transition from Protected Mode to Real Mode INIT is typically asserted in response to a BIOS interrupt that writes to an I/O port. This interrupt is often in response to a Ctrl-Alt-Del keyboard input. The BIOS writes to a port (similar to port 64h in the keyboard controller) that asserts INIT. INIT is also used to support 80286 software that must return to Real mode after accessing extended memory in Protected mode. The assertion of INIT causes the processor to empty its pipelines, initialize most of its internal state, and branch to address FFFF_FFFOhthe same instruction execution starting point used after RESET. Unlike RESET, the processor preserves the contents of its caches, the floating-point state, the MMxX state, Model-Specific Registers (MSRs), the CD and NW bits of the CRO register, the time stamp counter, and other specific internal resources. Figure 76 shows an example in which the operating system writes to an I/O port, causing the system logic to assert INIT. The sampling of INIT asserted starts an extended microcode sequence that terminates with a code fetch from FFFF_FFF0h, the reset location. INIT is sampled on every clock edge but is not recognized until the next instruction boundary. During an I/O write cycle, it must be sampled asserted a minimum of three clock edges before BRDY# is sampled asserted if it is to be recognized on the boundary between the I/O write instruction and the following instruction. If INIT is asserted synchronously, it can be asserted for a minimum of one clock. If it is asserted asynchronously, it must have been negated for a minimum of two clocks, followed by an assertion of a minimum of two clocks. 170 Bus Cycles Chapter 5Preliminary Information AMD<ad\ 21850E/0November 1998 AMD-K6-2 Processor Data Sheet INIT Sampled Asserted Code Fetch CLK ADP DPD PPD PPS MN A133] CX % X BE[7:0]4 X S X ADSH LS SL MO# \ DICH __ \ wRe / 5 D[63:0] }+{ s (XXX }- KEN# V/ BRDY# / \ a INIT / \ Figure 76. INIT-Initiated Transition from Protected Mode to Real Mode Chapter 5 Bus Cycles 171AMDd@ Preliminary Information AMD-K6-2 Processor Data Sheet 21850E/0November 1998 172 Bus Cycles Chapter 5Preliminary Information AMDZI 21850E/0November 1998 AMD-K6-2 Processor Data Sheet Power-on Configuration and Initialization On power-on the system logic must reset the AMD-K6-2 processor by asserting the RESET signal. When the processor samples RESET asserted, it immediately flushes and initializes all internal resources and its internal state, including its pipelines and caches, the floating-point state, the MMX and 3DNow! states, and all registers. Then the processor jumps to address FFFF_FFFOh to start instruction execution. Signals Sampled During the Falling Transition of RESET FLUSH# BF[2:0] BRDYC# FLUSH# is sampled on the falling transition of RESET to determine if the processor begins normal instruction execution or enters Tri-State Test mode. If FLUSH# is High during the falling transition of RESET, the processor unconditionally runs its Built-In Self Test (BIST), performs the normal reset functions, then jumps to address FFFF_FFFOh to start instruction execution. (See Built-In Self-Test (BIST) on page 217 for more details.) If FLUSH# is Low during the falling transition of RESET, the processor enters Tri-State Test mode. (See Tri-State Test Mode on page 218 and FLUSH# (Cache Flush) on page 103 for more details.) The internal operating frequency of the processor is determined by the state of the bus frequency signals BF[2:0] when they are sampled during the falling transition of RESET. The frequency of the CLK input signal is multiplied internally by a ratio defined by BF[2:0]. (See BF[2:0] (Bus Frequency) on page 92 for the processor-clock to bus-clock ratios.) BRDYC# is sampled on the falling transition of RESET to configure the drive strength of A[20:3], ADS#, HITM#, and W/R#. If BRDYC# is Low during the fall of RESET, these outputs are configured using higher drive strengths than the standard strength. If BRDYC# is High during the fall of RESET, the standard strength is selected. (See BRDYC# (Burst Ready Copy) on page 95 for more details.) Chapter 6 Power-on Configuration and Initialization 173AMD@ Preliminary Information AMD-K6-2 Processor Data Sheet 21850E/0November 1998 6.2 RESET Requirements During the initial power-on reset of the processor, RESET must remain asserted for a minimum of 1.0 ms after CLK and Vcc reach specification. (See CLK Switching Characteristics on page 255 for clock specifications. See Electrical Data on page 247 for Vcc specifications.) During a warm reset while CLK and Vcc are within specification, RESET must remain asserted for a minimum of 15 clocks prior to its negation. 6.3 State of Processor After RESET Output Signals Table 31 shows the state of all processor outputs and bidirectional signals immediately after RESET is sampled asserted. Table 31. Output Signal State After RESET Signal State Signal State A[31:3], AP Floating || LOCK# High ADS#, ADSC# High M/lO# Low APCHK# High PCD Low BE[7:0]# Floating || PCHK# High BREQ Low PWT Low CACHE# High SCYC Low D/C# Low SMIACT# High D[63:0], DP[7:0] Floating TDO Floating FERR# High VCC2DET Low HIT# High VCC2H/L# Low HITM# High W/R# Low HLDA Low - - Registers Table 32 on page 175 shows the state of all architecture registers and Model-Specific Registers (MSRs) after the processor has completed its initialization due to the recognition of the assertion of RESET. 174 Power-on Configuration and Initialization Chapter 6