preliminary Data Sheet Rev.0.9 15.11.2011 8192MB DDR3 - SDRAM SO-DIMM 204 Pin SO-DIMM Features: SGN08G64B3BB2SA-xxRT 8GByte in FBGA Technology RoHS compliant Options: Data Rate / Latency DDR3 1333 MT/s CL9 DDR3 1600 MT/s CL11 Module density 8192MB with 16 dies and 2 ranks Standard Grade Grade E Grade W Grade W Marking -CC -DC (TA) (TC) (TA) (TC) (TA) (TC) 0C to 70C 0C to 85C *) 0C to 85C 0C to 95C *) -40C to 85C -40C to 95C *) (T ) (Tc) -40C to 85C -40C to 95C A *) The refresh rate has to be doubled when 85C<TC<95C Environmental Requirements: Operating temperature (ambient) Standard Grade 0C to 70C Grade E 0C to 85C Grade W -40C to 85C Operating Humidity 10% to 90% relative humidity, noncondensing Operating Pressure 105 to 69 kPa (up to 10000 ft.) Storage Temperature -55C to 100C Storage Humidity 5% to 95% relative humidity, noncondensing Storage Pressure 1682 PSI (up to 5000 ft.) at 50C 204-pin 64-bit DDR3 Small Outline Dual-In-Line Double Data Rate Synchronous DRAM module Module organization: dual rank 1G x 64 VDD = 1.5V 0.075V, VDDQ 1.5V 0.075V 1.5V I/O ( SSTL_15 compatible) On-board I2C temperature sensor with integrated serial presence-detect (SPD) EEPROM Gold-contact pads This module is fully pin and functional compatible to the JEDEC PC3-12800 spec. and JEDEC- Standard MO-268. (see www.jedec.org) The pcb and all components are manufactured according to the RoHS compliance specification [EU Directive 2002/95/EC Restriction of Hazardous Substances (RoHS)] DDR3 - SDRAM component Samsung K4B4G0846B-HCH9 512Mx8 DDR3 SDRAM in PG-TFBGA-78 package 8-bit pre-fetch architecture Programmable CAS Latency, CAS Write Latency, Additive Latency, Burst Length and Burst Type. On-Die-Termination (ODT) and Dynamic ODT for improved signal integrity. Refresh. Self Refresh and Power Down Modes. ZQ Calibration for output driver and ODT. System Level Timing Calibration Support via Write Leveling and Multi Purpose Register (MPR) Read Pattern. Figure: mechanical dimensions 1 1 if no tolerances specified 0.15mm Swissbit AG Industriestrasse 4 CH - 9552 Bronschhofen Fon: +41 (0) 71 913 03 03 Fax: +41 (0) 71 913 03 15 www.swissbit.com eMail: info@swissbit.com Page 1 of 15 preliminary Data Sheet Rev.0.9 15.11.2011 This Swissbit module is an industry standard 204-pin 8-byte DDR3 SDRAM Small Outline Dual-In-line Memory Module (SO-DIMM) which is organized as x64 high speed CMOS memory arrays. The module uses internally configured octal-bank DDR3 SDRAM devices. The module uses double data rate architecture to achieve highspeed operation. DDR3 SDRAM modules operate from a differential clock (CK and CK#). READ and WRITE accesses to a DDR3 SDRAM module is burst-oriented; accesses start at a selected location and continue for a programmed number of locations in a programmed sequence. The burst length is either four or eight locations. An auto precharge function can be enabled to provide a self-timed row precharge that is initiated at the end of a burst access. The DDR3 SDRAM devices have a multibank architecture which allows a concurrent operation that is providing a high effective bandwidth. A self refresh mode is provided and a power-saving "power-down" mode. All inputs and all full drive-strength outputs are SSTL_15 compatible. The DDR3 SDRAM module uses the serial presence detect (SPD) function implemented via serial EEPROM 2 using the standard I C protocol. This nonvolatile storage device contains 256 bytes. The first 128 bytes are utilized by the SO-DIMM manufacturer (Swissbit) to identify the module type, the module's organization and several timing parameters. The second 128 bytes are available to the end user. Module Configuration Organization DDR3 SDRAMs used Row Addr. Device Bank Addr. 1G x 64bit 16 x 512M x 8bit (4096Mbit) 16 BA0, BA1, BA2 Column Module Refresh Addr. Bank Select 10 8k S0#, S1# Module Dimensions in mm 67.60 (long) x 30(high) x 3.80 [max] (thickness) Timing Parameters Part Number Module Density Data Rate Clock Cycle/Data bit rate Latency SGN08G64B3BB2SA-CCRT 8192MB 10.6 GB/s 1.50ns / 1333MT/s 9-9-9 SGN08G64B3BB2SA-DCRT 8192MB 12.8 GB/s 1.25ns / 1600MT/s 11-11-11 Pin Name A0-9, A11 - A15 Address Inputs A10/AP Address Input / Autoprecharge Bit A12/BC# BC switch on the fly BA0 - BA2 Bank Address Inputs DQ0 - DQ63 Data Input / Output DM0-DM7 Input Data Mask DQS0 - DQS7 Data Strobe, positive line DQS0# - DQS7# Data Strobe, negative line (only used when differential data strobe mode is enabled) S0#, S1# Chip Select RAS# Row Address Strobe CAS# Column Address Strobe WE# Write Enable CKE0, CKE1 Clock Enable ODT0, ODT1 On-Die Termination CK0, CK1 Clock Inputs, positive line Swissbit AG Industriestrasse 4 CH - 9552 Bronschhofen Fon: +41 (0) 71 913 03 03 Fax: +41 (0) 71 913 03 15 www.swissbit.com eMail: info@swissbit.com Page 2 of 15 preliminary Data Sheet Rev.0.9 15.11.2011 CK0#, CK1# Clock Inputs, negative line VDD Supply Voltage (1.5V 0.075V) VREFDQ Reference voltage: DQ, DM (VDD/2) VREFCA Reference voltage: Control, command, and address (VDD/2) VSS Ground VTT Termination voltage: Used for control, command, and address (VDD/2). VDDSPD Serial EEPROM Positive Power Supply SCL Serial Clock for Presence Detect SDA Serial Data Out for Presence Detect SA0 - SA1 Presence Detect Address Inputs Event# Temperature event: The EVENT# pin is asserted by the temperature sensor when critical NC No Connection Pin Configuration Frontside PIN Symbol PIN Symbol PIN Symbol PIN Symbol 1 VREFDQ 53 DQ19 105 VDD 155 VSS 3 VSS 55 VSS 107 A10/AP 157 DQ42 5 DQ0 57 DQ24 109 BA0 159 DQ43 7 DQ1 59 DQ25 111 VDD 161 VSS 9 VSS 61 VSS 113 WE# 163 DQ48 11 DM0 63 DM3 115 CAS# 165 DQ49 13 VSS 65 VSS 117 VDD 167 VSS 15 DQ2 67 DQ26 119 A13 169 DQS6# 17 DQ3 69 DQ27 121 S1# 171 DQS6 19 VSS 71 VSS 123 VDD 173 VSS 21 DQ8 73 CKE0 125 NC(TEST) 175 DQ50 23 DQ9 75 VDD 127 VSS 177 DQ51 25 VSS 77 NC 129 DQ32 179 VSS 27 DQS1# 79 BA2 131 DQ33 181 DQ56 29 DQS1 81 VDD 133 VSS 183 DQ57 31 VSS 83 A12/BC# 135 DQS4# 185 VSS 33 DQ10 85 A9 137 DQS4 187 DM7 35 DQ11 87 VDD 139 VSS 189 VSS 37 VSS 89 A8 141 DQ34 191 DQ58 39 DQ16 91 A5 143 DQ35 193 DQ59 41 DQ17 93 VDD 145 VSS 195 VSS 43 VSS 95 A3 147 DQ40 197 SA0 45 DQS2# 97 A1 149 DQ41 199 VDDSPD 47 DQS2 99 VDD 151 VSS 201 SA1 49 VSS 101 CK0 153 DM5 203 VTT 51 DQ18 103 CK0# Swissbit AG Industriestrasse 4 CH - 9552 Bronschhofen Fon: +41 (0) 71 913 03 03 Fax: +41 (0) 71 913 03 15 www.swissbit.com eMail: info@swissbit.com Page 3 of 15 preliminary Data Sheet Rev.0.9 15.11.2011 Backside Pin Symbol Pin Symbol Pin Symbol Pin Symbol 2 VSS 54 VSS 106 VDD 156 VSS 4 DQ4 56 DQ28 108 BA1 158 DQ46 6 DQ5 58 DQ29 110 RAS# 160 DQ47 8 VSS 60 VSS 112 VDD 162 VSS 10 DQS0# 62 DQS3# 114 S0# 164 DQ52 12 DQS0 64 DQS3 116 ODT0 166 DQ53 14 VSS 66 VSS 118 VDD 168 VSS 16 DQ6 68 DQ30 120 ODT1 170 DM6 18 DQ7 70 DQ31 122 NC 172 VSS 20 VSS 72 VSS 124 VDD 174 DQ54 22 DQ12 74 CKE1 126 VREFCA 176 DQ55 24 DQ13 76 VDD 128 VSS 178 VSS 26 VSS 78 NC(A15) 130 DQ36 180 DQ60 28 DM1 80 A14 132 DQ37 182 DQ61 30 Reset# 82 VDD 134 VSS 184 VSS 32 VSS 84 A11 136 DM4 186 DQS7# 34 DQ14 86 A7 138 VSS 188 DQS7 36 DQ15 88 VDD 140 DQ38 190 VSS 38 VSS 90 A6 142 DQ39 192 DQ62 40 DQ20 92 A4 144 VSS 194 DQ63 42 DQ21 94 VDD 146 DQ44 196 VSS 44 VSS 96 A2 148 DQ45 198 EVENT# 46 DM2 98 A0 150 VSS 200 SDA 48 VSS 100 VDD 152 DQS5# 202 SCL 50 DQ22 102 CK1 154 DQS5 204 VTT 52 DQ23 104 CK1# Signal in brackets may be routed to the socket connector, but is not used on the module Swissbit AG Industriestrasse 4 CH - 9552 Bronschhofen Fon: +41 (0) 71 913 03 03 Fax: +41 (0) 71 913 03 15 www.swissbit.com eMail: info@swissbit.com Page 4 of 15 preliminary Data Sheet Rev.0.9 15.11.2011 FUNCTIONAL BLOCK DIAGRAMM 8192MB DDR3 SDRAM SODIMM, 2 RANKS AND 16 COMPONENTS S1 S0 DQS4 DQS4 DM4 DQS0 DQS0 DM0 DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 CS I/O 0 I/O 1 I/O 2 I/O 3 I/O 4 I/O 5 I/O 6 I/O 7 DM DQS DQS D0 ZQ CS I/O 0 I/O 1 I/O 2 I/O 3 I/O 4 I/O 5 I/O 6 I/O 7 D8 ZQ CS I/O 0 I/O 1 I/O 2 I/O 3 I/O 4 I/O 5 I/O 6 I/O 7 DM DQS DQS DQ40 DQ41 DQ42 DQ43 DQ44 DQ45 DQ46 DQ47 CS I/O 0 I/O 1 I/O 2 I/O 3 I/O 4 I/O 5 I/O 6 I/O 7 DM DQS DQS DQ48 DQ49 DQ50 DQ51 DQ52 DQ53 DQ54 DQ55 CS I/O 0 I/O 1 I/O 2 I/O 3 I/O 4 I/O 5 I/O 6 I/O 7 DM DQS DQS DQ56 DQ57 DQ58 DQ59 DQ60 DQ61 DQ62 DQ63 D4 ZQ CS I/O 0 I/O 1 I/O 2 I/O 3 I/O 4 I/O 5 I/O 6 I/O 7 DM DQS DQS CS I/O 0 I/O 1 I/O 2 I/O 3 I/O 4 I/O 5 I/O 6 I/O 7 DM DQS DQS CS I/O 0 I/O 1 I/O 2 I/O 3 I/O 4 I/O 5 I/O 6 I/O 7 DM DQS DQS CS I/O 0 I/O 1 I/O 2 I/O 3 I/O 4 I/O 5 I/O 6 I/O 7 DM DQS DQS D12 ZQ DQS1 DQS1 DM1 DQS1 DQS1 DM1 DQ8 DQ9 DQ10 DQ11 DQ12 DQ13 DQ14 DQ15 CS I/O 0 I/O 1 I/O 2 I/O 3 I/O 4 I/O 5 I/O 6 I/O 7 DM DQS DQS D1 ZQ CS I/O 0 I/O 1 I/O 2 I/O 3 I/O 4 I/O 5 I/O 6 I/O 7 DM DQS DQS D9 ZQ D5 ZQ D13 ZQ DQS2 DQS2 DM2 DQS2 DQS2 DM2 DQ16 DQ17 DQ18 DQ19 DQ20 DQ21 DQ22 DQ23 CS I/O 0 I/O 1 I/O 2 I/O 3 I/O 4 I/O 5 I/O 6 I/O 7 DM DQS DQS D2 ZQ CS I/O 0 I/O 1 I/O 2 I/O 3 I/O 4 I/O 5 I/O 6 I/O 7 DM DQS DQS D10 ZQ D6 ZQ D14 ZQ DQS3 DQS3 DM3 DQS3 DQS3 DM3 DQ24 DQ25 DQ26 DQ27 DQ28 DQ29 DQ30 DQ31 BA0-BA2 A0-A15 RAS CAS WE ODT0 ODT1 CKE0 CKE1 CK0,CK1 CK0,CK1 RESET CS I/O 0 I/O 1 I/O 2 I/O 3 I/O 4 I/O 5 I/O 6 I/O 7 DM DQS DQS DQ32 DQ33 DQ34 DQ35 DQ36 DQ37 DQ38 DQ39 DM DQS DQS CS I/O 0 I/O 1 I/O 2 I/O 3 I/O 4 I/O 5 I/O 6 I/O 7 DM DQS DQS D3 ZQ CS I/O 0 I/O 1 I/O 2 I/O 3 I/O 4 I/O 5 I/O 6 I/O 7 BA0-BA2: SDRAM D0-D15 A0-A15: SDRAM D0-D15 RAS: SDRAM D0-D15 CAS: SDRAM D0-D15 WE: SDRAM D0-D15 ODT: SDRAM D0-D7 ODT: SDRAM D8-D15 CKE: SDRAM D0-D7 CKE: SDRAM D8-D15 CK: SDRAM D0-D15 CK: SDRAM D0-D15 RESET: SDRAM D0-D15 Swissbit AG Industriestrasse 4 CH - 9552 Bronschhofen DM DQS DQS D11 ZQ VDDSPD VDD/VDDQ SPD D0-D15 VREFDQ D0-D15 VREFCA D0-D15 VSS D0-D15 Fon: +41 (0) 71 913 03 03 Fax: +41 (0) 71 913 03 15 D7 ZQ D15 ZQ Notes: 1. DQ-to-I/O wiring is shown as recommended but may be changed. 2. DQ/DQS/DQS/ODT/DM/CKE/S relationship must be maintained as shown. 3. DQ, DM, DQS/DQS resistors: Refer to associated topology diagram. 4. Refer to the appropriate clock wiring topology under the DIMM wiring details section of the JEDED document. 5. For each DRAM, a unique ZQ resistor is connected to GND. The ZQ resistor is 240O1%. 6. Refer to associated figure for SPD details. www.swissbit.com eMail: info@swissbit.com Page 5 of 15 preliminary Data Sheet Rev.0.9 15.11.2011 MAXIMUM ELECTRICAL DC CHARACTERISTICS PARAMETER/ CONDITION Supply Voltage I/O Supply Voltage Voltage on any pin relative to VSS INPUT LEAKAGE CURRENT SYMBOL VDD VDDQ VIN, VOUT Any input 0V VIN VDD, VREF pin 0V VIN 0.95V (All other pins not under test = 0V) MIN -0.4 -0.4 -0.4 MAX 1.975 1.975 1.975 II UNITS V V V A Command/Address -16 16 IOZ -16 -2 -5 16 2 5 A IVREF -8 8 A RAS#, CAS#, WE#, S#, CKE CK, CK# DM OUTPUT LEAKAGE CURRENT (DQ's and ODT are disabled; 0V VOUT VDDQ) DQ, DQS, DQS# VREF LEAKAGE CURRENT ; VREF is on a valid level DC OPERATING CONDITIONS PARAMETER/ CONDITION Supply Voltage I/O Supply Voltage I/O Reference Voltage I/O Termination Voltage (system) Input High (Logic 1) Voltage Input Low (Logic 0) Voltage SYMBOL MIN VDD 1.425 VDDQ 1.425 VREF 0.49 x VDDQ VTT 0.49 x VDDQ-20mV VIH (DC) VREF + 0.1 VIL (DC) -0.3 NOM 1.5 1.5 0.50 x VDDQ 0.50 x VDDQ MAX 1.575 1.575 0.51x VDDQ 0.51x VDDQ+20mV VDDQ + 0.3 VREF - 0.1 UNITS V V V V V V AC INPUT OPERATING CONDITIONS PARAMETER/ CONDITION Input High (Logic 1) Voltage Input Low (Logic 0) Voltage SYMBOL VIH (AC) VIL (AC) MIN VREF + 0.175 - MAX VREF - 0.175 UNITS V V CAPACITANCE At DDR3 data rates, it is recommended to simulate the performance of the module to achieve optimum values. When inductance and delay parameters associated with trace lengths are used in simulations, they are significantly more accurate and realistic than a gross estimation of module capacitance. Simulations can then render a considerably more accurate result. JEDEC modules are now designed by using simulations to close timing budgets. Swissbit AG Industriestrasse 4 CH - 9552 Bronschhofen Fon: +41 (0) 71 913 03 03 Fax: +41 (0) 71 913 03 15 www.swissbit.com eMail: info@swissbit.com Page 6 of 15 preliminary Data Sheet Rev.0.9 15.11.2011 IDD Specifications and Conditions (0C TCASE + 85C; VDDQ = +1.5V 0.075V, VDD = +1.5V 0.075V) Parameter & Test Condition OPERATING CURRENT *) : One device bank Active-Precharge; tRC= tRC (IDD); tCK = tCK (IDD); CKE is HIGH, CS# is HIGH between valid commands; DQ inputs changing once per clock cycle; Address and control inputs changing once every two clock cycles OPERATING CURRENT *) : One device bank; Active-Read-Precharge; IOUT = 0mA; BL = 4, CL = CL (IDD), AL = 0; tCK = tCK (IDD), tRC= tRC (IDD), tRAS = tRAS MIN (IDD), tRCD = tRCD (IDD); CKE is HIGH, CS# is HIGH between valid commands; Address inputs changing once every two clock cycles; Data Pattern is same as IDD4W Slow Exit PRECHARGE POWER-DOWN CURRENT: All device banks idle; Power-down mode; tCK = tCK (IDD); CKE is LOW; All Control and Fast Exit Address bus inputs are not changing; DQ's are floating at VREF PRECHARGE QUIET STANDBY CURRENT: All device banks idle; tCK = tCK (IDD); CKE is HIGH, CS# is HIGH; All Control and Address bus inputs are not changing; DQ's are floating at VREF PRECHARGE STANDBY CURRENT: All device banks idle; tCK = tCK (IDD); CKE is HIGH, CS# is HIGH; All other Control and Address bus inputs are changing once every two clock cycles; DQ inputs changing once per clock cycle ACTIVE POWER-DOWN CURRENT: All device banks open; tCK = tCK (IDD); CKE is LOW; All Control and Address bus inputs are not changing; DQ's are floating at VREF (always fast exit) ACTIVE STANDBY CURRENT: All device banks open; tCK = tCK (IDD), tRAS = tRAS MAX (IDD), tRP = tRP (IDD); CKE is HIGH, CS# is HIGH between valid commands; All other Control and Address bus inputs are changing once every two clock cycles; DQ inputs changing once per clock cycle OPERATING READ CURRENT: All device banks open, Continuous burst reads; One module rank active; IOUT = 0mA; BL = 4, CL = CL (IDD), AL = 0; tCK = tCK (IDD), tRAS = tRAS MAX (IDD), tRP = tRP (IDD); CKE is HIGH, CS# is HIGH between valid commands; Address bus inputs are changing once every two clock cycles; DQ inputs changing once per clock cycle Swissbit AG Industriestrasse 4 CH - 9552 Bronschhofen Fon: +41 (0) 71 913 03 03 Fax: +41 (0) 71 913 03 15 Symbol max. Unit 12800-11-11-11 10600-9-9-9 IDD0 480 440 mA IDD1 560 520 mA IDD2P 240 240 mA 240 240 IDD2Q 320 320 mA IDD2N 400 400 mA IDD3P 320 320 mA IDD3N 480 480 mA IDD4R 920 800 mA www.swissbit.com eMail: info@swissbit.com Page 7 of 15 preliminary Data Sheet Parameter & Test Condition OPERATING WRITE CURRENT: All device banks open, Continuous burst writes; One module rank active; BL = 4, CL = CL (IDD), AL = 0; tCK = tCK (IDD), tRAS = tRAS MAX (IDD), tRP = tRP (IDD); CKE is HIGH, CS# is HIGH between valid commands; Address bus inputs are changing once every two clock cycles; DQ inputs changing once per clock cycle BURST REFRESH CURRENT: tCK = tCK (IDD); refresh command at every tRFC (IDD) interval, CKE is HIGH, CS# is HIGH between valid commands; All other Control and Address bus inputs are changing once every two clock cycles; DQ inputs changing once per clock cycle SELF REFRESH CURRENT: CK and CK# at 0V; CKE 0.2V; All other Control and Address bus inputs are floating at VREF; DQ's are floating at VREF OPERATING CURRENT*) : Four device bank interleaving READs, IOUT = 0mA; BL = 4, CL = CL (IDD), AL = tRCD (IDD) - 1 x tCK (IDD); tCK = tCK (IDD), tRC = tRC (IDD), tRRD = tRRD (IDD), tRCD = tRCD (IDD); CKE is HIGH, CS# is HIGH between valid commands; Address bus inputs are not changing during DESELECT; DQ inputs changing once per clock cycle Symbol Rev.0.9 15.11.2011 max. Unit 12800-11-11-11 10600-9-9-9 IDD4W 1000 840 mA IDD5 2320 2320 mA IDD6 240 240 mA IDD7 1560 1480 mA *) Value calculated as one module rank in this operating condition, and all other module ranks in IDD2P (CKE LOW) mode. TIMING VALUES USED FOR IDD MEASUREMENT IDD MEASUREMENT CONDITIONS SYMBOL 12800-11-11-11 11 CL (IDD) 13.75 tRCD (IDD) 48.75 tRC (IDD) 6 tRRD (IDD) 1.25 tCK (IDD) 35 tRAS MIN (IDD) 70'200 tRAS MAX (IDD) 13.75 tRP (IDD) 260 tRFC (IDD) Swissbit AG Industriestrasse 4 CH - 9552 Bronschhofen 10600-9-9-9 9 13.5 49.5 6 1.5 36 70'200 13.5 260 Unit tCK ns ns ns ns ns ns ns ns Fon: +41 (0) 71 913 03 03 Fax: +41 (0) 71 913 03 15 www.swissbit.com eMail: info@swissbit.com Page 8 of 15 preliminary Data Sheet Rev.0.9 15.11.2011 DDR3 SDRAM COMPONENT ELECTRICAL CHARACTERISTICS AND RECOMMENDED AC OPERATING CONDITIONS (0C TCASE + 85C; VDDQ = +1.5V 0.075V, VDD = +1.5V 0.075V) AC CHARACTERISTICS PARAMETER Clock cycle time CL = 11 CL = 10 CL = 9 CL = 8 CL = 7 CL = 6 CL = 5 Internal read command to first data CK high-level width CK low-level width Data-out high-impedance window from CK/CK# Data-out low-impedance window from CK/CK# DQ and DM input setup time relative to DQS VREF=1V/ns DQ and DM input hold time relative to DQS VREF=1V/ns DQ and DM input pulse width ( for each input ) DQS, DQS# to DQ skew, per access DQ-DQS hold, DQS to first DQ to go non-valid, per access DQS input high pulse width DQS input low pulse width DQS, DQS# rising to/from CK, CK# DQS, DQS# rising to/from CK, CK# when DLL disabled DQS falling edge to CK rising - setup time DQS falling edge from CK rising - hold time DQS read preamble DQS read postamble DQS write preamble DQS write postamble Positive DQS latching edge to associated clock edge Address and control input pulse width ( for each input ) CTRL, CMD, Addr setup to CK, CK# CTRL, CMD, Addr setup to CK, CK# VREF @ 1V/ns 1 2 SYMBOL tCK (11) tCK (10) tCK (9) tCK (8) tCK (7) tCK (6) tCK (5) tAA 12800-11-11-11 MIN MAX 1.25 <1.5 1.5 <1.875 1.5 <1.875 1.875 <2.5 1.875 <2.5 2.5 3.3 3.0 3.3 10600-9-9-9 MIN MAX 1.5 <1.875 1.5 <1.875 1.875 <2.5 1.875 <2.5 2.5 3.3 3.0 3.3 Unit ns 13.75 20 13.5 20 0.47 0.47 0.53 0.53 0.47 0.47 0.53 0.53 tCK tCK - 225 - 250 ps -450 225 -500 250 ps 160 - 180 - ps tDH1V 145 - 165 - ps tDIPW 360 - 400 - ps 100 - 125 ps 0.38 - 0.38 - tCH (avg) tCL (avg) tHZ tLZ tDS1V tDQSQ tQH tCK (AVG) tDQSH tDQSL tDQSCK 0.45 0.45 0.55 0.55 0.45 0.45 0.55 0.55 tCK tCK -225 225 -255 255 ps tDQSCK 1 10 1 10 ns tDSS 0.18 - 0.2 - tCK tDSH 0.18 - 0.2 - tCK 0.9 0.3 0.9 0.3 Note1 Note2 - 0.9 0.3 0.9 0.3 Note1 Note2 - tCK tCK tCK tCK - 0.27 + 0.27 - 0.25 + 0.25 tCK tIPW 560 - 620 - ps tIS(Base) 45 - 65 - ps tIS(1V) 220 - 240 - ps DLL_DIS tRPRE tRPST tWPRE tWPST tDQSS The maximum preamble is bound by tLZDQS (MAX) The maximum postamble is bound by tHZDQS (MAX) Swissbit AG Industriestrasse 4 CH - 9552 Bronschhofen Fon: +41 (0) 71 913 03 03 Fax: +41 (0) 71 913 03 15 www.swissbit.com eMail: info@swissbit.com Page 9 of 15 preliminary Data Sheet Rev.0.9 15.11.2011 DDR3 SDRAM COMPONENT ELECTRICAL CHARACTERISTICS AND RECOMMENDED AC OPERATING CONDITIONS (Continued) (0C TCASE + 85C; VDDQ = +1.5V 0.075V, VDD = +1.5V 0.075V) AC CHARACTERISTICS PARAMETER SYMBOL CTRL, CMD, Addr hold to CK, tIH(Base) CK# CTRL, CMD, Addr hold to CK, tIH(1V) CK# VREF @ 1V/ns CAS# to CAS# command delay tCCD ACTIVE to ACTIVE (same bank) tRC command period ACTIVE bank a to ACTIVE bank tRRD b command ACTIVE to READ or WRITE tRCD delay Four bank 1K Page size tFAW Activate period 2K Page size ACTIVE to PRECHARGE tRAS command Internal READ to precharge tRTP command delay Write recovery time tWR Auto precharge write recovery + tDAL precharge time Internal WRITE to READ tWTR command delay PRECHARGE command period tRP LOAD MODE command cycle tMRD time REFRESH to ACTIVE or REFRESH to REFRESH tRFC command interval Average periodic refresh interval 0 C TCASE 85C 85 C < TCASE 95C RTT turn-on from ODTL on reference RTT turn-on from ODTL off reference Asynchronous RTT turn-on delay (power Down with DLL off) Asynchronous RTT turn-off delay (power Down with DLL off) RTT dynamic change skew Exit self refresh to commands not requiring a locked DLL Write levelling setup from rising CK, CK# crossing to rising DQS, DQS# crossing Write levelling setup from rising DQS, DQS# crossing to rising CK, CK# crossing First DQS, DQS# rising edge DQS, DQS# delay Swissbit AG Industriestrasse 4 CH - 9552 Bronschhofen 12800-11-11-11 MIN MAX 10600-9-9-9 MIN MAX Unit 120 - 140 - ps 220 - 240 - ps 4 - 4 - tCK 48.75 - 49.5 - ns max - max - ns 4nCK,6ns 4nCK,6ns 13.75 - 13.5 - ns 30 40 - 30 45 - ns 35 70'200 36 70'200 ns max - max - ns 4nCK,7.5ns 4nCK,7.5ns 15 - 15 - ns tWR + tRP/tCK - tWR + tRP/tCK - ns max - max - ns 4nCK,7.5ns 4nCK,7.5ns 13.75 - 13.5 - ns 4 - 4 - tCK 260 70'200 260 70'200 ns tREFI - 7.8 - 7.8 tREFI (IT) - 3.9 - 3.9 tAON -225 225 -250 250 ps tAOF 0.3 0.7 0.3 0.7 tCK tAONPD 2 8.5 2 8.5 ns tAOFPD 2 8.5 2 8.5 ns tADC 0.3 max 0.7 0.3 max 0.7 tCK s tXS 5nCK,tR FC + 10ns - 5nCK,tR FC + 10ns - ns tWLS 165 - 195 - ps tWLH 165 - 195 - ps tWLMRD tWLDQSEN 40 25 - 40 25 - tCK tCK Fon: +41 (0) 71 913 03 03 Fax: +41 (0) 71 913 03 15 www.swissbit.com eMail: info@swissbit.com Page 10 of 15 preliminary Data Sheet Rev.0.9 15.11.2011 DDR3 SDRAM COMPONENT ELECTRICAL CHARACTERISTICS AND RECOMMENDED AC OPERATING CONDITIONS (Continued) (0C TCASE + 85C; VDDQ = +1.5V 0.075V, VDD = +1.5V 0.075V) AC CHARACTERISTICS PARAMETER Exit reset from CKE HIGH to a valid command Begin power supply ramp to power supplies stable RESET# LOW to power supplies stable RESET# LOW to I/O and RTT High-Z Exit precharge power-down to any non-READ command CKE minimum high/low time 12800-11-11-11 MIN MAX max 5nCK, SYMBOL tXPR 10600-9-9-9 MIN MAX max 5nCK, tRFC + 10ns Unit tCK tRFC + 10ns ms tVDDPR - 200 - 200 tRPS 0 200 0 200 tIOz - 20 - 20 max - max - tCK - tCK tXP 3nCK,6ns max tCKE 3nCK,6ns max - 3nCK, 5ns 3nCK, 5.625ns ms ns Temperature Sensor with Serial Presence-Detect EEPROM SCL SDA WP/ EVENT EVENT R1 0 SA0 SA1 SA0 SA1 SA2 Temperature Sensor with Serial Presence-Detect EEPROM Operating Conditions Parameter / Condition Supply voltage Supply current: VDD= 3.3V Input high voltage: Logic 1; SCL, SDA Input low voltage: Logic 0; SCL, SDA Output low voltage: IOUT = 2.1mA Input current Temperature sensing range Temperature sensor accuracy Swissbit AG Industriestrasse 4 CH - 9552 Bronschhofen Symbol VDDSPD IDD VIH VIL VOL IIN Fon: +41 (0) 71 913 03 03 Fax: +41 (0) 71 913 03 15 MIN +3 MAX +3.6 +2.0 +1.45 -5.0 TBD TBD VDDSPD +1 550 400 5.0 TBD TBD www.swissbit.com eMail: info@swissbit.com Unit V mA V mV mV A C C Page 11 of 15 preliminary Data Sheet Rev.0.9 15.11.2011 A.C. Characteristics of Temperature Sensor VCC = 3.3 V 10%, TA = -40C to +125C Symbol fSCL tBUF tF tR tHD:DAT tH:STA tHIGH tLOW tSU:DAT tSU:STA tSU:STO tTIMEOUT tI tWR tPU Parameter / Condition SCL clock frequency Bus Free Time Between STOP and START SDA fall time SDA rise time Data hold time (accepted for Input Data) Data Hold Time (guaranteed for Output Data) Start condition hold time High Period of SCL Low Period of SCL Data setup time Start condition setup time Stop condition setup time SMBus SCL Clock Low Timeout Noise Pulse Filtered at SCL and SDA Inputs Write Cycle Time Power-up Delay to Valid Temperature Recording MIN 10 1300 MAX 400 300 300 0 300 600 600 1300 100 600 600 25 900 35 100 5 100 Unit kHz ns ns ns ns ns ns ns ns ns ns ns ms ns ms ms Temperature Characteristics of Temperature Sensor VCC = 3.3 V 10%, TA = -40C to +125C Parameter Test Conditions/Comments +75C TA +95C, active range +40C TA +125C, monitor range -40C TA +125C, sensing range Temperature Reading Error Class B, JC42.4 compliant ADC Resolution Temperature Resolution Conversion Time 1 Thermal Resistance JA Junction-to-Ambient (Still Air) MAX 1.0 2.0 3.0 12 0.0625 100 92 Unit C C C Bits C Ms C/W 1 Power Dissipation is defined as PJ = (TJ - TA)/JA, where TJ is the junction temperature and TA is the ambient temperature. The thermal resistance value refers to the case of a package being used on a standard 2-layer PCB. Slave Address Bits of Temperature Sensor Device EEPROM Temp. Sensor 1 Device Type Identifier 1 b7 b6 b5 b4 1 0 1 0 0 0 1 1 Select Address Signals b3 b2 b1 A2 A1 A0 A2 A1 A0 R/W# b0 R/W# R/W# The most significant bit, b7, is sent first. Swissbit AG Industriestrasse 4 CH - 9552 Bronschhofen Fon: +41 (0) 71 913 03 03 Fax: +41 (0) 71 913 03 15 www.swissbit.com eMail: info@swissbit.com Page 12 of 15 preliminary Data Sheet Rev.0.9 15.11.2011 SERIAL PRESENCE-DETECT MATRIX Byte Byte Description 12800-11-11-11 10600-9-9-9 0 CRC RANGE, EEPROM BYTES, BYTES USED 0x92 1 SPD REVISON 0x11 2 DRAM DEVICE TYPE 0x0B 3 MODULE TYPE (FORM FACTOR) 0x03 4 SDRAM DEVICE DENSITY & BANKS 0x04 5 SDRAM DEVICE ROW & COLUMN COUNT 0x21 6 BYTE 6 RESERVED 0x00 7 MODULE RANKS & DEVICE DQ COUNT 0x09 8 ECC TAG & MODULE MEMORY BUS WIDTH 0x03 9 FINE TIMEBASE DIVIDEND/DIVISOR 0x52 10 MEDIUM TIMEBASE DIVIDEND 0x01 11 MEDIUM TIMEBASE DIVISOR 0x08 12 MIN SDRAM CYCLE TIME (tCK MIN) 13 BYTE 13 RESERVED 14 CAS LATENCIES SUPPORTED (CL4 => CL11) 15 CAS LATENCIES SUPPORTED (CL12 => CL18) 0x00 16 MIN CAS LATENCY TIME (tAA MIN) 0x69 17 MIN WRITE RECOVERY TIME (tWR MIN) 0x78 18 MIN RAS# TO CAS# DELAY (tRCD MIN) 0x69 19 MIN ROW ACTIVE TO ROW ACTIVE DELAY (TRRD MIN) 20 MIN ROW PRECHARGE DELAY (tRP MIN) 0x69 21 UPPER NIBBLE FOR tRAS & tRC 0x11 22 MIN ACTIVE TO PRECHARGE DELAY (tRAS MIN) 0x18 0x2C 23 MIN ACTIVE TO ACTIVE/REFRESH DELAY (tRC MIN) 0x81 0x95 24 MIN REFRESH RECOVERY DELAY (tRFC MIN) LSB 0x20 25 MIN REFRESH RECOVERY DELAY (tRFC MIN) MSB 0x08 26 MIN INTERNAL WRITE TO READ CMD DELAY (tWTR MIN) 0x3C 27 MIN INTERNAL READ TO PRECHARGE CMD DELAY (tRTP MIN) 0x3C 28 MIN FOUR ACTIVE WINDOW DELAY (tFAW MIN) MSB 0x00 29 MIN FOUR ACTIVE WINDOW DELAY (tFAW MIN) LSB 0xF0 30 SDRAM DEVICE OUTPUT DRIVERS SUPPORTED 0x83 31 SDRAM DEVICE THERMAL & REFRESH OPTIONS 0x01 Swissbit AG Industriestrasse 4 CH - 9552 Bronschhofen 0x0A 0x0F 0x00 Fon: +41 (0) 71 913 03 03 Fax: +41 (0) 71 913 03 15 0xFE 0x1C 0x30 www.swissbit.com eMail: info@swissbit.com 0x3C Page 13 of 15 preliminary Data Sheet Byte 32 Byte Description Rev.0.9 12800-11-11-11 10600-9-9-9 DDR3-MODULE THERMAL SENSOR 0x80 BYTES 32-59 RESERVED 0x00 60 MODULE HEIGHT (NOMINAL) 0x0F 61 MODULE THICKNESS (MAX) 0x11 62 REFERENCE RAW CARD ID 0x65 63 ADDRESS MAPPING EDGE CONECTOR TO DRAM 0x00 BYTES 64-116 RESEVED 0x00 117 MODULE MFR ID (LSB) 0x83 118 MODULE MFR ID (MSB) 0xDA 119 MODULE MFR LOCATION ID 0x01 0x02 0x03 120 MODULE MFR YEAR X 121 MODULE MFR WEEK X 122-125 MODULE SERIAL NUMBER X 126-127 CRC 128-145 MODULE PART NUMBER 33-59 64-116 15.11.2011 (Switzerland) (Germany) (USA) 0x67EA 0x5335 "SGN08G64B3BB2SA-xx" 146 MODULE DIE REV X 147 MODULE PCB REV X 148 DRAM DEVICE MFR ID (LSB) 0x80 149 DRAM DEVICE MFR (MSB) 0xCE 150-175 MFR RESERVED BYTES 150-175 0x00 176-255 CUSTOMER RESERVED BYTES 176-255 0xFF Part Number Code S G N 08G 64 B3 B B 2 SA 1 2 3 4 5 6 7 8 9 10 - DC * R T 11 12 13 14 *RoHs compl. DDR3-1600MT/s Swissbit AG SDRAM DDR3 204 Pin unbuffered 1.5V Depth (8GB) Width PCB-Type (B83SRCF 1.10 ) Chip Vendor (Samsung) 2 Module Ranks Chip Rev. B Chip organisation x8 * optional / additional information T=Thermal Sensor Swissbit AG Industriestrasse 4 CH - 9552 Bronschhofen Fon: +41 (0) 71 913 03 03 Fax: +41 (0) 71 913 03 15 www.swissbit.com eMail: info@swissbit.com Page 14 of 15 preliminary Data Sheet Rev.0.9 15.11.2011 Locations Swissbit AG Industriestrasse 4 CH - 9552 Bronschhofen Switzerland Phone: +41 (0)71 913 03 03 Fax: +41 (0)71 913 03 15 _____________________________ Swissbit Germany GmbH Wolfener Strasse 36 D - 12681 Berlin Germany Phone: +49 (0)30 93 69 54 - 0 Fax: +49 (0)30 93 69 54 - 55 _____________________________ Swissbit NA, Inc. 14 Willett Avenue, Suite 301A Port Chester, NY 10573 USA Phone: +1 914 935 1400 Fax: +1 914 935 9865 _____________________________ Swissbit NA, Inc. 3913 Todd Lane, Suite - 307 Austin, TX 78744 USA Phone: +1 512 302 9001 Fax: +1 512 302 4808 _____________________________ Swissbit Japan, Inc. 3F Core Koenji, 2-1-24 Koenji-Kita, Suginami-Ku, Tokyo 166-0002 Japan Phone: +81 3 5356 3511 Fax: +81 3 5356 3512 Swissbit AG Industriestrasse 4 CH - 9552 Bronschhofen Fon: +41 (0) 71 913 03 03 Fax: +41 (0) 71 913 03 15 www.swissbit.com eMail: info@swissbit.com Page 15 of 15 Mouser Electronics Authorized Distributor Click to View Pricing, Inventory, Delivery & Lifecycle Information: Swissbit: SGN08G64B3BB2SA-DCRT