PROLINX TM GS7032 Digital Video Serializer DATA SHEET DESCRIPTION * SMPTE 259M-C compliant (270Mb/s) The GS7032 is designed to encode and serialize SMPTE 125M bit parallel digital video signals as well as other 8-bit or 10-bit parallel formats. This device performs the following functions: * serializes 8-bit or 10-bit data * minimal external components (no loop filter components required) * isolated, dual-output, adjustable cable driver * sync detection * 3.3V and 5.0V CMOS/TTL compatible inputs * parallel to serial conversion * 9 4 data scrambling (using the X + X + 1 algorithm) * EDH support with GS9001, GS9021 * 10x parallel clock multiplication * Pb-Free and RoHS Compliant * conversion of NRZ to NRZI serial data APPLICATION The GS7032 features 270M/bs data rate with a single VCO resistor. Other features include a lock detect output, NRZI encoding and SMPTE scrambler bypass, a sync detect disable, and an isolated dual output cable driver suitable for driving 75 loads. * lock detect indication * SMPTE scramble and NRZI coding bypass option SMPTE 259M-C parallel to serial interfaces for video cameras, VTRs, signal generators; Generic parallel to serial conversion. ORDERING INFORMATION PART NUMBER PACKAGE TEMPERATURE Pb-FREE AND RoHS COMPLIANT GS7032 - CVM 44 pin TQFP 0C to 70C No GS7032 - CVME3 44 pin TQFP 0C to 70C Yes SYNC DETECT DISABLE (SYNC DIS) 10 SYNC DETECT RESET BYPASS SDO 2 10 DATA IN (PD0-PD9) 10 INPUT LATCH 8 SMPTE SCRAMBLER RESET BYPASS SCLK/10 PARALLEL to SERIAL CONVERTER & NRZ to NRZI SCLK SDO SERIAL DIGITAL OUTPUTS PLOAD PARALLEL CLOCK INPUT (PCLKIN) PLL MUTE LOOP BANDWIDTH CONTROL (LBWC) LOCK DETECT (LOCK DET) RVCO+ RVCO- BLOCK DIAGRAM Revision Date: May 2005 Document No. 14583 - 04 GENNUM CORPORATION P.O. Box 489, Stn. A, Burlington, Ontario, Canada L7R 3Y3 Tel. +1 (905) 632-2996 Fax. +1 (905) 632-5946 E-mail: info@gennum.com www.gennum.com GS7032 FEATURES ABSOLUTE MAXIMUM RATINGS PARAMETER VALUE Supply Voltage (VS = VCC-VEE) 5.5V Input Voltage Range (any input) VEE<VIN<VCC 5mA Power Dissipation (VCC = 5.25V) 1200mW j-a 42.5C/W j-c 6.4C/W Maximum Die Temperature GS7032 DC Input Current (any one input) 125C 0C TA 70C Operating Temperature Range -65C TS 150C Storage Temperature Range Lead Temperature (soldering, 10 sec) 260C DC ELECTRICAL CHARACTERISTICS VCC = 5V, VEE = 0V, TA = 0 - 70C unless otherwise specified. PARAMETER SYMBOL Positive Supply Voltage VCC Power (System Power) P Supply Current Data & Clock Inputs (PD[9:0] PCLKIN) SYNC DIS Logic Input Levels (Bypass, RESET) Lock Detect Output CC CONDITIONS TYP MAX UNITS 4.75 5.00 5.25 V 3 VCC = 5.0V, T = 25C (2 outputs) - 550 - mW 5 VCC = 5.25V (2 outputs) - - 160 mA 1 VCC = 5.0V, T = 25C (2 outputs) - 110 - mA 3 3 Operating Range VIH Logic Input High (wrt VEE) 2.4 - - V VIL Logic Input Low (wrt VEE) - - 0.8 V L Input Current - - 8.0 A VIH Logic Input High (wrt to VEE) 2.4 - - V VIL Logic Input Low (wrt to VEE) - - 0.8 V L Input Current - - 5.0 A VOL Sinking 500A - - 0.4 V NOTES TEST LEVEL MIN 3 1 TEST LEVELS 1. Production test at room temperature and nominal supply voltage with guardbands for supply and temperature ranges. 2. Production test at room temperature and nominal supply voltage with guardbands for supply and temperature ranges using correlated test. 3. Production test at room temperature and nominal supply voltage. 4. QA sample test. 5. Calculated result based on Level 1,2, or 3. 6. Not tested. Guaranteed by design simulations. 7. Not tested. Based on characterization of nominal parts. 8. Not tested. Based on existing design/characterization data of similar product. 2 of 9 14583 - 04 AC ELECTRICAL CHARACTERISTICS VCC = 5V, VEE = 0V, TA = 0 - 70C unless otherwise specified. PARAMETER Serial Data Bit Rate SYMBOL BRSDO CONDITIONS RVCO = 374 MIN TYP MAX UNITS NOTES - 270Mb/s - Mb/s SMPTE 259M-C TEST LEVEL 3 VSDO RLOAD = 37.5, RSET = 54.9 740 800 860 mVp-p 1 SD Rise/Fall Times tr, tf 20% - 80% 400 - 700 ps 7 - - 7 % 1 7 1 7 SD Overshoot/Undershoot Output Return Loss ORL at 270MHz 15 - - dB Lock Time tLOCK Worst case - - 5 ms 6 Min Loop Bandwidth BWMIN LBWC = Grounded : BWMIN - 220 - kHz 7 Typical Loop Bandwidth BWTYP LBWC = Floating : - 500 - kHz 7 LBWC = VCC : 10 BWMIN - 1.7 - MHz 7 LBWC = VCC (270Mb/s) - 0.08 - UI 3 10 BWMIN Max Loop Bandwidth BWMAX Intrinsic Jitter (6 ) Data & Clock Inputs (PD[9:0] PCLKIN) tSU Setup Time at 25C 2.5 - - ns 3 tH Hold Time at 25C 2.0 - - ns 3 TEST LEVELS NOTES 1. Production test at room temperature and nominal supply voltage with guardbands for supply and temperature ranges. 1. Depends on PCB layout. 2. Production test at room temperature and nominal supply voltage with guardbands for supply and temperature ranges using correlated test. 3. Production test at room temperature and nominal supply voltage. 4. QA sample test. 5. Calculated result based on Level 1,2, or 3. 6. Not tested. Guaranteed by design simulations. 7. Not tested. Based on characterization of nominal parts. 8. Not tested. Based on existing design/characterization data of similar product. 3 of 9 14583 - 04 GS7032 Serial Data Outputs Signal Swing 44 43 42 41 40 39 38 37 36 35 VCC1 VEE1 RVCO+ NC VEE RVCO- LF+ LBWC VEE LF- SYNC DIS PIN CONNECTIONS 34 1 33 PD8 2 32 NC PD7 3 31 BYPASS PD6 4 30 NC PD5 5 29 VEE PD4 6 PD3 GS7032 TOP VIEW 28 NC 7 27 NC PD2 8 26 VEE PD1 9 25 SDO PD0 10 24 SDO PCLKIN 11 23 VEE GS7032 RESET PD9 NC RSET LOCK NC VEE2 VCC2 NC RSV1 RSV2 VEE3 VCC3 12 13 14 15 16 17 18 19 20 21 22 PIN DESCRIPTIONS NUMBER SYMBOL TYPE DESCRIPTION 1-10 PD9 - PD0 I CMOS or TTL compatible parallel data inputs. PD0 is the LSB and PD9 is the MSB. 11 PCLKIN I CMOS or TTL compatible parallel clock input. 12 VEE3 - Most negative power supply connection for parallel data and clock inputs. 13 VCC3 - Most positive power supply connection for parallel data and clock inputs. 14 RSV2 I Reserved pin. Do not connect. 15, 19, 21, 27, 28, 30, 32, 37 NC I No connect. 16 RSV1 I Reserved pin. Always connect to VCC. 17 VCC2 - Most positive power supply connection for internal logic and digital circuits. 18 VEE2 - Most negative power supply connection for internal logic and digital circuits. 20 LOCK O TTL level which is high when the internal PLL is locked. 22 RSET I External resistor used to set the data output amplitude for SDO and SDO. 23, 26, 29 VEE - Most negative power supply connection for shielding (not connected). 24, 25 SDO, SDO O Primary, current mode, 75 cable driving output (inverse and true) 31 BYPASS I When high, the SMPTE Scrambler and NRZ encoder are bypassed. 4 of 9 14583 - 04 PIN DESCRIPTIONS SYMBOL TYPE DESCRIPTION 33 RESET I Resets the scrambler when asserted. 34 VCC1 - Most positive power supply connection for analog circuits. 35 VEE1 - Most negative power supply connection for analog circuits. 36, 38 RVCO+, RVCO- I Differential VCO current setting resistor that sets the VCO frequency. 39, 43 VEE - Most negative power supply connection (substrate). 40 LBWC I TTL level loop bandwidth control that adjusts the PLL bandwidth to optimize for lowest jitter. If the pin is set to ground the loop bandwidth is BWMIN. If the pin is left floating, the loop bandwidth is approximately 3 BWMIN, if the pin is tied to VCC the loop bandwidth is approximately10 BWMIN 41, 42 LF+, LF- I Differential loop filter pins to optimize loop transfer performance at low loop bandwidths (NC if not used). 44 SYNC DIS I Sync detect disable. Logic high disables sync detection. Logic low allows 8 bit operation by mapping 000-003 to 000 and 3FC-3FF to 3FF. GS7032 NUMBER 5 of 9 14583 - 04 TYPICAL PERFORMANCE CURVES (VS = 5V, TA = 25C unless otherwise shown. Guard band tested to 70C only.) 500 0.8075 OUTPUT SWING (V) 0.805 480 4.75 RISE 470 5.0 RISE 460 5.0 FALL 5.25 RISE 450 4.75 FALL 5.25 0.8025 5.0 GS7032 RISE / FALL TIME (ps) 490 0.800 4.75 0.7975 5.25 FALL 440 0.795 430 0.7925 420 0 20 40 60 0 80 20 TEMPERATURE (C) 40 60 80 TEMPERATURE (C) Fig. 1 Rise/Fall Times vs. Temperature Fig. 3b Output Swing vs. Temperature (800mV) 155 tCLKL = tCLKH CURRENT (mA) 150 145 50% PARALLEL CLOCK PLCK 5.25 140 5.0 135 4.75 130 125 0 20 40 60 PARALLEL DATA PDn 80 TEMPERATURE (C) tHOLD tSU Fig. 2 Supply Current vs. Temperature (SDO ON) Fig. 4 Waveforms OUTPUT SWING (V) 1.01 4:2:2 DATA STREAM 1.005 E A V S H BLNK A V E A V ACTIVE VIDEO H BLNK S A V 5.25 SYNC DETECT 1.000 5.0 0.995 4.75 PCLK IN PDN XXX 3FF 000 000 XXX *** 0.99 0 20 40 60 80 *** XXX 3FF 000 000 XXX *** SYNC DETECT TEMPERATURE (C) Fig. 3a Output Swing vs. Temperature (1000mV) Fig. 5 Timing Diagram 6 of 9 14583 - 04 The parallel data (PD0-PD9) and parallel clock (PCLKIN) are applied via pins 1 through 11 respectively. 600 500 The Sync Detector looks for the reserved words used in the TRS-ID sync word. The reserved words are 000-003 and 3FC-3FF in 10-bit hexadecimal, or 00 and FF in 8-bit hexadecimal. When the occurrence of either all zeros or all ones at inputs PD2-PD9 are detected, the lower two bits PD0 and PD1 are forced to zeros or ones, respectively. This makes the system compatible with 8-bit or 10-bit data. 400 300 200 100 (270Mb/s) 0 GROUNDED FLOATING For non-SMPTE standard parallel data, the Sync Detector can be disabled with a logic input, Sync Detect Disable (pin 44). VCC LOOP BANDWIDTH CONTROL (LBWC) Fig. 6 Output Jitter vs. LBWC 2. SCRAMBLER The Scrambler is a linear feedback shift register used to pseudo-randomize the incoming serial data according to the fixed polynomial (X9+X4+1). This minimizes the DC component in the output serial data stream. The NRZ to NRZI converter uses another polynomial (X+1) to convert a long sequence of ones to a series of transitions, minimizing polarity effects. These functions can be disabled by setting BYPASS high (pin 31). 3. PHASE LOCKED LOOP The PLL performs parallel clock multiplication and provides the timing signal for the serializer. It is composed of a phase/frequency detector (with no dead zone), charge pump, VCO, a divide-by-ten counter, and a divide by two counter. Fig. 7 Output Eye Diagram (270Mb/s) DETAILED DESCRIPTION The GS7032 Serializer is a bipolar integrated circuit used to convert parallel data into a serial format according to the SMPTE 259M-C standard. The device encodes both 8-bit and 10-bit TTL-compatible parallel signals producing serial data rates at 270Mb/s. It operates from a single 5V supply and is packaged in a 44 pin TQFP. Functional blocks within the device include the following: * input latches * sync detector * parallel to serial converter * SMPTE scrambler * NRZ to NRZI converter * internal cable driver * PLL for 10x parallel clock multiplication * lock detect The phase/frequency detector allows a wider capture range and faster lock time than can be achieved with a phase discriminator alone. The discrimination of frequency also eliminates harmonic locking. With this type of discriminator, the PLL can be over-damped for good stability without sacrificing lock time. The charge pump delivers a 'charge packet' to the loop filter which is proportional to the system phase error. Internal voltage clamps are used to constrain the loop filter voltage between approximately 1.8 and 3.4 volts. The VCO is a differential low phase noise, factory trimmed design that provides increased immunity to PCB noise and precise control of the VCO centre frequency. The VCO has a pull range of 15% about the centre frequency. The single external resistor, RVCO, sets the VCO frequency. 7 of 9 14583 - 04 GS7032 JITTER p-p (ps) 1. SYNC DETECTOR 4. VCO CENTRE FREQUENCY SELECTION 6. SERIAL OUTPUTS The recommended RVCO value for auto rate SMPTE 259M-C applications (270Mb/s) is 374 (see the Typical Application Circuit). The true and complement serial data, SDO and SDO, are available from pins 24 and 25. These outputs will drive two 75 co-axial cables with SMPTE level serial digital video signals. The VCO and an internal divider generate the PLL clock. RSET calculation: The Lock Detect output is available from pin 20 and is HIGH when the loop is locked. When the loop is not locked, the lock detect circuit mutes the serial data outputs. GS7032 1.154 x R LOAD R SET = -------------------------------------V SDO 5. LOCK DETECT OUTPUT where RLOAD = RPULL-UP || ZO TYPICAL APPLICATION CIRCUIT VCC VCC J1 100n LBWC 374 1 PD9 2 PD8 PARALLEL DATA INPUTS VEE1 VCC1 NC RVCO+ VEE RVCO LBWC LF- LF+ VEE SYNC_DIS 44 43 42 41 40 39 38 37 36 35 34 RESET NC 3 PD7 BYPASS 4 PD6 NC 5 PD5 VEE GS7032 6 PD4 NC 7 PD3 NC 8 PD2 RSET NC LOCK NC VEE2 VCC2 RSV1 NC RSV2 SDO 11 PCLKIN VCC3 SDO 10 PD0 VEE3 PARALLEL CLOCK INPUT VEE 9 PD1 VEE 33 RESET 32 31 30 29 28 27 26 25 L 24 J3 R 75 12 13 14 15 16 17 18 19 20 21 22 100n VCC 75 VCC 54.9 VCC 1 23 L 1 J4 100n R 10k VCC VCC 220 100n L = 8.2nH R = 75 All resistors on ohms, all capacitors in farads, unless otherwise stated. LOCK 8 of 9 14583 - 04 PACKAGE DIMENSIONS 12.00 10.00 12 TYP 0.20 MIN 7 MAX 0 MIN 12.00 10.00 0.20 MAX RADIUS GS7032 0 MIN 12 TYP 0.60 0.15 0.08 MIN. RADIUS PIN 1 0.20 MIN 0.80 0.30 1.00 44 pin TQFP 1.10 0.10 All dimensions in millimetres 0.127 REVISION HISTORY VERSION ECR DATE 4 136659 May 2005 CHANGES AND/OR MODIFICATIONS Removed reference to EDH FPGA core. Updated Pb-Free and RoHS Compliant part ordering information. DOCUMENT IDENTIFICATION CAUTION DATA SHEET The product is in production. Gennum reserves the right to make changes at any time to improve reliability, function or design, in order to provide the best product possible. ELECTROSTATIC SENSITIVE DEVICES DO NOT OPEN PACKAGES OR HANDLE EXCEPT AT A STATIC-FREE WORKSTATION GENNUM CORPORATION Mailing Address: P.O. Box 489, Stn. A, Burlington, Ontario, Canada L7R 3Y3 Shipping Address: 970 Fraser Drive, Burlington, Ontario, Canada L7L 5P5 Tel. +1 (905) 632-2996 Fax. +1 (905) 632-5946 GENNUM JAPAN CORPORATION Shinjuku Green Tower Building 27F, 6-14-1, Nishi Shinjuku, Shinjuku-ku, Tokyo, 160-0023 Japan Tel. +81 (03) 3349-5501, Fax. +81 (03) 3349-5505 GENNUM UK lIMITED 25 Long Garden Walk, Farnham, Surrey, England GU9 7HX Tel. +44 (0)1252 747 000 Fax +44 (0)1252 726 523 Gennum Corporation assumes no liability for any errors or omissions in this document, or for the use of the circuits or devices described herein. The sale of the circuit or device described herein does not imply any patent license, and Gennum makes no representation that the circuit or device is free from patent infringement. GENNUM and the G logo are registered trademarks of Gennum Corporation. (c) Copyright 2001 Gennum Corporation. All rights reserved. Printed in Canada. www.gennum.com 9 of 9 14583 - 04