GS7032-CVME3 - Gennum Corp.

GENNUM CORPORATION P.O. Box 489, Stn. A, Burlington, Ontario, Canada L7R 3Y3

Tel. +1 (905) 632-2996 Fax. +1 (905) 632-5946 E-mail: info@gennum.com

www.gennum.com

Revision Date: May 2005 Document No. 14583 - 04

DATA SHEET

GS7032

FEATURES

• SMPTE 259M-C compliant (270Mb/s)

• serializes 8-bit or 10-bit data

• minimal external components (no loop filter

components required)

• isolate d, du al-output, adju s t able cab le driver

• 3.3V and 5.0V CMOS/TTL compatible inputs

• loc k detect indi cation

• SMPTE scramble and NRZI coding bypass option

• EDH support with GS9001 , GS9021

• Pb-Free and RoHS Compliant

APPLICATION

SMPTE 259M-C parallel to serial interfaces for video

cameras, VTRs, signal generators; Generic parallel to serial

conversion.

DESCRIPTION

The GS7032 is designed to encode and serialize SMPTE

125M bit parallel digital video signals as well as other 8-bit

or 10-bit parallel formats. This device performs the following

functions:

• sync detection

• parallel to serial conversion

• data scrambling (using the X9 + X4 + 1 algorithm)

• 10x parallel clock multiplication

• conversion of NRZ to NRZI serial data

The GS7032 features 270M/bs data rate with a single VCO

resistor. Other features include a lock detect output, NRZI

encoding and SMPTE scrambler bypass, a sync detect

disable, and an isolated dual output cable driver suitable

for driving 75Ω loads.

BLOCK DIAGRAM

ORDERING INFORMATION

PART NUMBER PACKA GE TEMPERATURE Pb-FREE AND RoHS COMPLIANT

GS7032 - CVM 44 pin TQFP 0°C to 70°C No

GS7032 - CVME3 44 pin TQFP 0°C to 70°C Yes

LOCK

DETECT

(LOCK DET)

SERIAL

DIGITAL

OUTPUTS

PARALLEL CLOCK

INPUT (PCLKIN)

PLOAD

SCLK

SCLK/10

LOOP BANDWIDTH

CONTROL (LBWC)

RVCO+ RVCO-

MUTE

RESET

SYNC DETECT DISABLE (SYNC DIS)

BYPASS

PARALLEL

to SERIAL

CONVERTER

NRZ to NRZI

DATA

(PD0-PD9)

INPUT

LATCH

SYNC

DETECT

SMPTE

SCRAMBLER

PLL

SDO

PROLINX ™ GS7032

Digital Video Serializer

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GS7032

ABSOLUTE MAXIMUM RATINGS

PARAMETER VALUE

Supply Voltage (VS = VCC-VEE)5.5V

Input Voltage Range (any input) VEE<VIN<VCC

DC Input Current (any one input) 5mA

Power Dissipation (VCC = 5.25V) 1200mW

θj-a 42.5°C/W

θj-c 6.4°C/W

Maximum Die Temperature 125°C

Operating Temperature Range 0°C ≤ TA ≤ 70°C

Storage Temperature Range -65°C ≤ TS ≤ 150°C

Lead Temperature (soldering, 10 sec) 260°C

DC ELECTRICAL CHARACTERISTICS

VCC = 5V, VEE = 0V, TA = 0° – 70°C unless otherwise specified.

PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS NOTES TEST

LEVEL

Positive Supply Voltage VCC Operating Range 4.75 5.00 5.25 V 3

Power (System Power) P VCC = 5.0V, T = 25°C (2 outputs) - 550 - mW 5

Supply Current ΙCC VCC = 5.25V (2 outputs) - - 160 mA 1

VCC = 5.0V, T = 25°C (2 outputs) - 110 - mA 3

Data & Clock Inputs

(PD[9:0] PCLKIN)

SYNC DIS

VIH Logic Input High (wrt VEE)2.4--V 3

VIL Logic Input Low (wrt VEE)--0.8V

ΙLInput Current - - 8.0 µA

Logic Input Levels

(Bypass, RESET)

VIH Logic Input High (wrt to VEE)2.4--V 3

VIL Logic Input Low (wrt to VEE)--0.8V

ΙLInput Current - - 5.0 µA

Lock Detect Output VOL Sinking 500µA - - 0.4 V 1

TEST LEVELS

1. Production test at room temperature and nominal supply voltage with guardbands for supply and temperature ranges.

2. Production test at room temperature and nominal supply voltage with guardbands for supply and temperature ranges using correlated

test.

3. Production test at room temperature and nominal supply voltage.

4. QA sample test.

5. Calculated result based on Level 1,2, or 3.

6. Not tested. Guaranteed by design simulations.

7. Not tested. Based on characterization of nominal parts.

8. Not tested. Based on existing design/characterization data of similar product.

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GS7032

AC ELECTRICAL CHARACTERISTICS

VCC = 5V, VEE = 0V, TA = 0° – 70°C unless otherwise specified.

PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS NOTES TEST

LEVEL

Serial Data Bit Rate BRSDO RVCO = 374Ω- 270Mb/s - Mb/s SMPTE

259M-C

Serial Data Outputs Signal

Swing

VSDO RLOAD = 37.5Ω, RSET = 54.9Ω740 800 860 mVp-p 1

SD Rise/Fall Times tr, tf20% - 80% 400 - 700 ps 7

SD Overshoot/Undershoot - - 7 % 1 7

Output Return Loss ORL at 270MHz 15 - - dB 1 7

Lock Time tLOCK Worst case - - 5 ms 6

Min Loop Bandwidth BWMIN LBWC = Grounded : BWMIN - 220 - kHz 7

Typical Loop Bandwidth BWTYP LBWC = Floating :

BWMIN

- 500 - kHz 7

Max Loop Bandwidth BWMAX LBWC = VCC : 10 BWMIN -1.7-MHz 7

Intrinsic Jitter (6 σ)LBWC = V

CC (270Mb/s) - 0.08 - UI 3

Data & Clock Inputs

(PD[9:0] PCLKIN)

tSU Setup Time at 25°C 2.5 - - ns 3

tHHold Time at 25°C 2.0 - - ns 3

TEST LEVELS

1. Production test at room temperature and nominal supply voltage with guardbands for

supply and temperature ranges.

2. Production test at room temperature and nominal supply voltage with guardbands for

supply and temperature ranges using correlated test.

3. Production test at room temperature and nominal supply voltage.

4. QA sample test.

5. Calculated result based on Level 1,2, or 3.

6. Not tested. Guaranteed by design simulations.

7. Not tested. Based on characterization of nominal parts.

8. Not tested. Based on existing design/characterization data of similar product.

NOTES

1. Depends on PCB layout.

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GS7032

PIN CONNECTIONS

GS7032

TOP VIEW

44 43 42 41 40 39 38 37 36 35 34

VCO+

LF+

VEE

VCO-

LF-

VCC1

LBWC

SYNC DIS

VEE

VEE1

BYPASS

VEE

SDO

VEE

PD9

PD8

PD7

PD6

PD5

PD4

PD3

PD2

PD1

PD0

PCLKIN

12 13 14 15 16 17 18 19 20 21 22

VCC2

RSV2

RSET

RSV1

LOCK

VEE3

VCC3

RESET

PIN DESCRIPTIONS

NUMBER SYMBOL TYPE DESCRIPTION

1-10 PD9 - PD0 I CMOS or TTL compatible parallel data inputs. PD0 is the LSB and PD9 is the MSB.

11 PCLKIN I CMOS or TTL compatible parallel clock input.

12 VEE3 - Most negative power supply connection for parallel data and clock inputs.

13 VCC3 - Most positive power supply connection for parallel data and clock inputs.

14 RSV2 I Reserved pin. Do not connect.

15, 19, 21, 27,

28, 30, 32, 37

NC I No connect.

16 RSV1 I Reserved pin. Always connect to VCC.

17 VCC2 - Most positive power supply connection for internal logic and digital circuits.

18 VEE2 - Most negative power supply connection for internal logic and digital circuits.

20 LOCK O TTL level which is high when the internal PLL is locked.

22 RSET I External resistor used to set the data output amplitude for SDO and SDO.

23, 26, 29 VEE - Most negative power supply connection for shielding (not connected).

24, 25 SDO, SDO O Primary, current mode, 75Ω cable driving output (inverse and true)

31 BYPASS I When high, the SMPTE Scrambler and NRZ encoder are bypassed.

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GS7032

33 RESET I Resets the scrambler when asserted.

34 VCC1 - Most positive power supply connection for analog circuits.

35 VEE1 - Most negative power supply connection for analog circuits.

36, 38 RVCO+, RVCO- I Differential VCO current setting resistor that sets the VCO frequency.

39, 43 VEE - Most negative power supply connection (substrate).

40 LBWC I TTL level loop bandwidth control that adjusts the PLL bandwidth to optimize for lowest

jitter. If the pin is set to ground the loop bandwidth is BWMIN. If the pin is left floating, the

loop bandwidth is approximately 3 BWMIN, if the pin is tied to VCC the loop bandwidth is

approximately10 BWMIN

41, 42 LF+, LF- I Differential loop filter pins to optimize loop transfer performance at low loop bandwidths

(NC if not used).

44 SYNC DIS I Sync detect disable. Logic high disables sync detection. Logic low allows 8 bit operation

by mapping 000-003 to 000 and 3FC-3FF to 3FF.

PIN DESCRIPTIONS

NUMBER SYMBOL TYPE DESCRIPTION

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GS7032

TYPICAL PERFORMANCE CURVES

(VS = 5V, TA = 25°C unless otherwise shown. Guard band tested to 70°C only.)

Fig. 1 Rise/Fall Times vs. Temperature

Fig. 2 Supply Current vs. Tempe rature (SDO ON)

Fig. 3a Output Swing vs. Temperature (1000mV)

Fig. 3b Output Swing vs. Temperature (800mV)

Fig. 4 Waveforms

Fig. 5 Timing Diagram

5.25 FALL

4.75 RISE

5.0 RISE

5.0 FALL

5.25 RISE

4.75 FALL

020406080

500

490

480

470

460

450

440

430

420

RISE / FALL TIME (ps)

TEMPERATURE (˚C)

4.75

5.0

5.25

020406080

155

150

145

140

135

130

125

CURRENT (mA)

TEMPERATURE (˚C)

4.75

5.0

5.25

020406080

1.01

1.005

1.000

0.995

0.99

OUTPUT SWING (V)

TEMPERATURE (˚C)

4.75

5.0

5.25

020406080

0.8075

0.805

0.8025

0.800

0.7975

0.795

0.7925

OUTPUT SWING (V)

TEMPERATURE (˚C)

tSU tHOLD

tCLKL = tCLKH

PARALLEL

CLOCK

PLCK

50%

PARALLEL

DATA

PDn

ACTIVE

VIDEO

4:2:2

DATA

STREAM

BLNK H

BLNK

SYNC

DETECT

SYNC

DETECT

XXX 3FF 000 000 XXX ••• ••• XXX 3FF 000 000 XXX •••

PCLK IN

PDN

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GS7032

Fig. 6 Output Jitter vs. LBWC

Fig. 7 Output Eye Diagram (270Mb/s)

DETAILED DESCRIPTION

The GS7032 Serializer is a bipolar integrated circuit used to

convert parallel data into a serial format according to the

SMPTE 259M-C standard. The device encodes both 8-bit

and 10-bit TTL-compatible parallel signals producing serial

data rates at 270Mb/s. It operates from a single 5V supply

and is packaged in a 44 pin TQFP.

Functional blocks within the device include the following:

• input latches

• sync detector

• parallel to serial converter

• SMPTE scrambler

• NRZ to NRZI converter

• internal cable driver

• PLL for 10x parallel clock multiplication

• lock detect

The parallel data (PD0-PD9) and parallel clock (PCLKIN)

are applied via pins 1 through 11 respectively.

1. SYNC DETECTOR

The Sync Detector looks for the reserved words used in the

TRS-ID sync word. The reserved words are 000-003 and

3FC-3FF in 10-bit hexadecimal, or 00 and FF in 8-bit

hexadecimal. When the occurrence of either all zeros or all

ones at inputs PD2-PD9 are detected, the lower two bits

PD0 and PD1 are forced to zeros or ones, respectively. This

makes the system compatible with 8-bit or 10-bit data.

For non-SMPTE standard parallel data, the Sync Detector

can be disabled with a logic input, Sync Detect Disable (pin

44).

2. SCRAMBLER

The Scrambler is a linear feedback shift register used to

pseudo-randomize the incoming serial data according to

the fixed polynomial (X9+X4+1). This minimizes the DC

component in the output serial data stream. The NRZ to

NRZI converter uses another polynomial (X+1) to convert a

long sequence of ones to a series of transitions, minimizing

polarity effects. These functions can be disabled by setting

BYPASS high (pin 31).

3. PHASE LOCKED LOOP

The PLL performs parallel clock multiplication and provides

the timing signal for the serializer. It is composed of a

phase/frequency detector (with no dead zone), charge

pump, VCO, a divide-by-ten counter, and a divide by two

counter.

The phase/frequency detector allows a wider capture range

and faster lock time than can be achieved with a phase

discriminator alone. The discrimination of frequency also

eliminates harmonic locking. With this type of discriminator,

the PLL can be over-damped for good stability without

sacrificing lock time.

The charge pump delivers a 'charge packet' to the loop

filter which is proportional to the system phase error.

Internal voltage clamps are used to constrain the loop filter

voltage between approximately 1.8 and 3.4 volts.

The VCO is a differential low phase noise, factory trimmed

design that provides increased immunity to PCB noise and

precise control of the VCO centre frequency. The VCO has

a pull range of ±15% about the centre frequency. The single

external resistor, RVCO, sets the VCO frequency.

GROUNDED FLOATING V

600

500

400

300

200

100

JITTER p-p (ps)

LOOP BANDWIDTH CONTROL (LBWC)

(270Mb/s)

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GS7032

4. VCO CENTRE FREQUENCY SELECTION

The recommended RVCO value for auto rate SMPTE 259M-C

applications (270Mb/s) is 374Ω (see the Typical Application

Circuit).

The VCO and an internal divider generate the PLL clock.

5. LOCK DETECT OUTPUT

The Lock Detect output is available from pin 20 and is HIGH

when the loop is locked. When the loop is not locked, the

lock detect circuit mutes the serial data outputs.

6. SERIAL OUTPUTS

The true and complement serial data, SDO and SDO, are

available from pins 24 and 25. These outputs will drive two

75Ω co-axial cables with SMPTE level serial digital video

signals.

RSET calculation:

where RLOAD = RPULL-UP || ZO

TYPICAL APPLICATION CIRCUIT

RSET

1.154 RLOAD

VSDO

---------------------------------------=

GS7032

VEE3

VCC3

RSV2

RSV1

VCC2

VEE2

LOCK

RSET

SYNC_DIS

VEE

LF-

LF+

LBWC

VEE

RVCO

RVCO+

VEE1

VCC1

RESET

BYPASS

VEE

SDO

VEE

PD9

PD8

PD7

PD6

PD5

PD4

PD3

PD2

PD1

PD0

PCLKIN

VCC

374

100n

1µ

100n

54.9

220

LBWC

100n

10k

PARALLEL

CLOCK

INPUT

PARALLEL

DATA

INPUTS

L = 8.2nH

R = 75Ω

LOCK

All resistors on ohms,

all capacitors in farads,

unless otherwise stated.

12 13 14 15 16 17 18 19 20 21 22

44 43 42 41 40 39 38 37 36 35 34

RESET

VCC

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GENNUM CORPORATION

Mailing Address: P.O. Box 489, Stn. A, Burlington, Ontario, Canada L7R 3Y3

Shipping Address: 970 Fraser Drive, Burlington, Ontario, Canada L7L 5P5

Tel. +1 (905) 632-2996 Fax. +1 (905) 632-5946

GENNUM JAPAN CORPORATION

Shinjuku Green Tower Building 27F, 6-14-1, Nishi Shinjuku, Shinjuku-ku, Tokyo,

160-0023 Japan

Tel. +81 (03) 3349-5501, Fax. +81 (03) 3349-5505

GENNUM UK lIMITED

25 Long Garden Walk, Farnham, Surrey, England GU9 7HX

Tel. +44 (0)1252 747 000 Fax +44 (0)1252 726 523

Gennum Corporation assumes no liability for any errors or omissions in this

document, or for the use of the circuits or devices described herein. The sale

of the circuit or device described herein does not imply any patent license,

and Gennum makes no representation that the circuit or device is free from

patent infringement.

GENNUM and the G logo are registered trademarks of Gennum Corporation.

Printed in Canada.

www.gennum.com

GS7032

PACKAGE DIMENSIONS

REVISION HISTORY

VERSION ECR DATE CHANGES AND/OR MODIFICATIONS

4 136659 May 2005 Removed reference to EDH FPGA core. Updated Pb-Free and RoHS Compliant

part ordering information.

10.00

12.00

10.00

0.80 0.30

12.00

0.20 MAX

RADIUS

0.08 MIN.

RADIUS

0.60

±0.15

0.20 MIN

12˚ TYP

1.00

0.10

1.10

0.127

7˚ MAX

0˚ MIN

0 MIN

PIN 1

0.20 MIN

All dimensions in millimetres

44 pin TQFP

CAUTION

ELECTROSTATIC

SENSITIVE DEVICES

DO NOT OPEN PACKAGES OR HANDLE

EXCEPT AT A STAT IC-FREE WORKSTATION

DOCUMENT IDENTIFICATION

DATA SHEET

The product is in production. Gennum reserves the right to make

changes at any time to improve reliability, function or design, in order to

provide the best product possible.