AM27C1024-200PC5 - AMD - Datasheet.Live

FINAL

Publication# 06780 Rev: IAmendment/+2

Issue Date: July 1997

Am27C1024

1 Megabit (65,536 x 16-Bit) CMOS EPROM

DISTINCTIVE CHARACTERISTICS

■

Fast access time

— 55 ns maximum access time

■

Low power consumption

— 100

A typical CMOS standby current

■

JEDEC-approved pinouts

— 40-Pin DIP/PDIP

— 44-Pin PLCC

■

Single +5 V power supply

■

10% power supply tolerance available

■

100% Flashrite programming

— Typical programming time of 8 seconds

■

Latch-up protected to 100 mA from –1 V to V

+ 1 V

■

High noise immunity

■

Versatile features for simple interfacing

— Both CMOS and TTL input/output compatibility

— Two line control functions

GENERAL DESCRIPTION

The Am27C1024 is a 1 Mbit ultraviolet erasable program-

mable read-only memory . It is organized as 64K words by

16 bits per word, operates from a single +5 V supply, has

a static standby mode, and features fast single address

location programming. Products are available in win-

dowed cer amic DIP packages as well as plastic one time

programmab le (OTP) PDIP and PLCC packages.

Typically, any byte can be accessed in less than 70 ns ,

allowing operation with high-perf ormance microproces-

sors without any WAIT states. The Am27C1024 offers

separate Output Enable (OE) and Chip Enable (CE)

controls, thus eliminating bus contention in a multiple

bus microprocessor system.

AMD’s CMOS process technology provides high speed, low

power , and high noise immunity . T ypical power consumption is

only 125 mW in active mode , and 100

W in standby mode .

All signals are TTL levels, including programming sig-

nals. Bit locations may be programmed singly, in

bloc ks, or at random. The Am27C1024 supports AMD’ s

Flashrite programming algorithm (100

s pulses) re-

sulting in a typical programming time of 8 seconds.

BLOCK DIAGRAM

VSS

Output Enable

Chip Enable

and

Prog Logic

Decoder

OE Output

Buffers

Gating

1,048,576-Bit

Cell Matrix

A0–A15

Address

Inputs

Data Outputs

DQ0–DQ15

06780I-1

VCC

VPP

PGM

2 Am27C1024

PRODUCT SELECTOR GUIDE

CONNECTION DIAGRAMS

T op View

DIP PLCC

Note:

1. JEDEC nomenclature is in parenthesis.

PIN DESIGNATIONS

A0–A15 = Address Inputs

CE (E) = Chip Enable

DQ0–DQ15 = Data Inputs/Outputs

OE (G) = Output Enable Input

PGM (P) = Program Enable Input

Supply Voltage

= Program Voltage Input

= Ground

NC = No Internal Connection

DU = No External Connection (Do Not Use)

LOGIC SYMBOL

Family Part No: Am27C1024

Ordering Part No: V

= 5.0 V

10%

-55 -255

-55 -70 -90 -120 -150 -200

Max Access Time (ns) 55 70 90 120 150 200 250

CE (E) Access (ns) 55 70 90 120 150 200 250

OE (G) Access (ns) 40 40 40 50 65 75 75

VCC

PMG (P)

A16

A15

A14

A13

A12

A11

A10

VSS

VPP

CE (E)

DQ15

DQ14

DQ13

DQ12

DQ11

DQ10

DQ9

DQ8

VSS

DQ7

DQ6

DQ5

DQ4

DQ3

DQ2

DQ1

DQ0

OE (G) 06780I-2

144 43 42

5432

641

17 23 24 25 26

19 20 21 22

18 27 28

DQ12

DQ11

DQ10

DQ9

DQ8

VSS

DQ7

DQ6

DQ5

DQ4

A13

A12

A11

A10

VSS

DQ13

DQ14

DQ15

CE (E)

VPP

VCC

PGM (P)

A15

A14

DQ3

DQ2

DQ1

DQ0

OE (G)

06780I-3

DQ0–DQ15

A0–A15

CE (E)

PMG (P)

OE (G)/VPP

06780I-4

Am27C1024 3

ORDERING INFORMATION

UV EPROM Products

AMD standard products are av ailable in se v eral pac kages and operating ranges. The order number (Valid Combination) is formed

by a combination of:

Valid Combinations

Valid Combinations list conﬁgurations planned to be sup-

ported in volume for this device. Consult the local AMD sales

ofﬁce to conﬁrm availability of speciﬁc v alid combinations and

to check on newly released combinations.

TEMPERATURE RANGE

C = Commercial (0°C to +70°C)

I = Industrial (–40°C to +85°C)

E = Extended (–55°C to +125°C)

P ACKAGE TYPE

D = 40-Pin Ceramic DIP (CDV040)

DEVICE NUMBER/DESCRIPTION

Am27C1024

1 Megabit (65,536 x 16-Bit) CMOS UV EPROM

AM27C1024 -55 D C

OPTIONAL PROCESSING

Blank = Standard Processing

B = Burn-In

SPEED OPTION

See Product Selector Guide and

Valid Combinations

VOL T AGE TOLERANCE

5=V

CC ± 5%, 55 ns only

See Product Selector Guide and

Valid Combinations

AM27C1024-55

= 5.0 V

5% DC5, DC5B, DI5, DI5B

AM27C1024-55

= 5.0 V

10% DC, DCB, DI, DIB

AM27C1024-70

AM27C1024-90

AM27C1024-120

DC, DCB, DE, DEB, DI, DIBAM27C1024-150

AM27C1024-200

AM27C1024-255

= 5.0 V

5% DC, DCB, DI, DIB

4 Am27C1024

ORDERING INFORMATION

OTP EPROM Products

AMD standard products are av ailable in se v eral pac kages and operating ranges. The order number (Valid Combination) is formed

by a combination of:

Valid Combinations

Valid Combinations list conﬁgurations planned to be sup-

ported in volume for this device. Consult the local AMD sales

ofﬁce to conﬁrm availability of speciﬁc v alid combinations and

to check on newly released combinations.

TEMPERATURE RANGE

C = Commercial (0°C to +70°C)

I = Industrial (–40°C to +85°C)

P ACKAGE TYPE

P = 40-Pin Plastic DIP (PD 040)

J = 44-Pin Square Plastic Leaded Chip

Carrier (PL 044)

DEVICE NUMBER/DESCRIPTION

Am27C1024

2 Megabit (131,072 x 16-Bit) CMOS OTP EPROM

AM27C1024 -55 J C

OPTIONAL PROCESSING

Blank = Standard Processing

SPEED OPTION

See Product Selector Guide and

Valid Combinations

VOL T AGE TOLERANCE

5=V

CC ± 5%, -55 ns only

See Product Selector Guide and

Valid Combinations

AM27C1024-55

= 5.0 V

5% PC5, PI5, JC5, JI5

AM27C1024-55

= 5.0 V

10%

PC, PI, JC, JI

AM27C1024-70

AM27C1024-90

AM27C1024-120

AM27C1024-150

AM27C1024-200

AM27C1024-255

= 5.0 V

Am27C1024 5

FUNCTIONAL DESCRIPTION

Erasing the Am27C1024

In order to clear all locations of their programmed con-

tents, it is necessary to expose the Am27C1024 to an

ultra violet light source . A dosage of 15 W seconds/cm

is required to completely erase an Am27C1024. This

dosage can be obtained by exposure to an ultraviolet

lamp—wavelength of 2537 (Å)—with intensity of

12,000

W/cm

for 15 to 20 minutes. The Am27C1024

should be directly under and about one inch from the

source and all ﬁlters should be removed from the UV

light source prior to erasure.

It is impor tant to note that the Am27C1024 and similar

de vices will erase with light sources having w av elengths

shorter than 4000 Å. Although erasure times will be

much longer than with UV sources at 2537 Å, exposure

to ﬂuorescent light and sunlight will e v entually er ase the

Am27C1024 and e xposure to them should be prev ented

to realize maximum system reliability. If used in such an

environment, the pac kage window should be cov ered by

an opaque label or substance.

Programming the Am27C1024

Upon delivery or after each erasure the Am27C1024

has all 1,048,576 bits in the “ONE” or HIGH

state. “ZEROs” are loaded into the Am27C1024

through the procedure of programming.

The programming mode is entered when 12.75 V

0.25V is applied to the V

pin and CE and PGM are

atV

F or programming, the data to be progr ammed is applied

16 bits in parallel to the data output pins.

The Flashrite algorithm reduces programming time by

using 100

s programming pulses and by giving each

address only as many pulses as is necessary in order to

reliably program the data. After each pulse is applied to

a given address, the data in that address is veriﬁed. If the

data does not verify, additional pulses are given until it

veriﬁes or the maximum is reached. This process is re-

peated while sequencing through each address of the

Am27C1024. This part of the algorithm is done at V

6.25 V to assure that each EPROM bit is prog rammed to

a sufﬁciently high threshold voltage. After the ﬁnal ad-

dress is completed, the entire EPROM memory is veri-

ﬁed at V

= V

= 5.25 V.

Please refer to Section 6 for programming ﬂow chart

and characteristics.

Program Inhibit

Programming of multiple Am27C1024 in parallel with

different data is also easily accomplished. Except for

CE, all like inputs of the parallel Am27C1024 may be

common. A TTL low-level program pulse applied to an

Am27C1024 CE input with V

= 12.75 V

0.25 V, and

PGM Low will program that Am27C1024. A high-level

CE input inhibits the other Am27C1024 devices from

being programmed.

Program V erify

A verify should be performed on the programmed bits

to determine that they were correctly programmed. The

verify should be performed with OE and CE at V

PGM at V

and V

between 12.75 V

0.25 V.

Auto Select Mode

The auto select mode allows the reading out of a binary

code from an EPROM that will identify its manufacturer

and type. This mode is intended f or use by progr amming

equipment for the purpose of automatically matching the

device to be programmed with its corresponding pro-

gramming algorithm. This mode is functional in the 25

C ambient temperature range that is required when

programming the Am27C1024.

To activate this mode, the programming equipment

must force 12.0 V

0.5 V open address the A9 of the

Am27C1024. Two identiﬁer bytes may then be se-

quenced from the device outputs by toggling address

line A0 from V

to V

. All other address lines must be

held at V

during auto select mode.

Byte 0 (A0 = V

) represents the manufacturer code,

and byte 1 (A0 = VIH), the device code. For the

Am27C1024, these two identiﬁer b ytes are giv en in the

Mode Select Table. All identiﬁers for manufacturer and

device codes will possess odd parity, with the MSB

(DQ7) deﬁned as the parity bit.

Read Mode

The Am27C1024 has two control functions, both of

which must be logically satisﬁed in order to obtain data

at the outputs. Chip Enable (CE) is the power control

and should be used for device selection. Output Enable

(OE) is the output control and should be used to gate

data to the output pins, independent of de vice selection.

Assuming that addresses are stable, address access

time (tACC) is equal to the delay from CE to output (tCE).

Data is available at the outputs t OE after the falling edge

of OE, assuming that CE has been LO W and addresses

have been stable for at least tACC–tOE.

Standby Mode

The Am27C1024 has a CMOS standby mode which re-

duces the maximum VCC current to 100 µA. It is placed

in CMOS-standby when CE is at VCC ± 0.3 V. The

Am27C1024 also has a TTL-standby mode which re-

duces the maximum VCC current to 1.0 mA. It is placed

in TTL-standby when CE is at VIH. When in standby

mode, the outputs are in a high-impedance state, inde-

pendent of the OE input.

6 Am27C1024

Output OR-Tieing

To accommodate multiple memory connections, a

two-line control function is provided to allow for:

■Low memory power dissipation

■Assurance that output bus contention will not occur

It is recommended that CE be decoded and used as

the primary device-selecting function, while OE be

made a common connection to all devices in the array

and connected to the READ line from the system con-

trol bus. This assures that all deselected memory de-

vices are in low-power standby mode and that the

output pins are only active when data is desired from a

particular memory device.

System Applications

During the switch between active and standby condi-

tions, transient current peaks are produced on the ris-

ing and f alling edges of Chip Enab le. The magnitude of

these transient current peaks is dependent on the out-

put capacitance loading of the de vice . At a minimum, a

0.1 µF ceramic capacitor (high frequency, low inherent

inductance) should be used on each device between

VCC and VSS to minimize transient effects. In addition,

to overcome the voltage drop caused by the inductive

effects of the printed circuit board traces on EPROM ar-

ra ys, a 4.7 µF bulk electrolytic capacitor should be used

between VCC and VSS for each eight de vices. The loca-

tion of the capacitor should be close to where the

power supply is connected to the array.

MODE SELECT TABLE

Notes:

1. V

= 12.0 V ± 0.5 V

2. X = Either V

or V

3. A1–A8 = A10–A15 = V

4. See DC Programming Characteristics for V

voltage during programming.

CE OE PGM A0 A9 VPP Outputs

Read VIL VIL XXXXD

OUT

Output Disable X VIH XXXXHi-Z

Standby (TTL) VIH XXXXXHi-Z

Standby (CMOS) VCC ± 0.3 V XXXXXHi-Z

Program VIL XV

IL XXV

PP DIN

Program Verify V IL VIL VIH XXV

PP DOUT

Program Inhibit VIH XXXXV

PP Hi-Z

Autoselect

(Note 3) Manufacturer Code VIL VIL VIH VIL VHX 01H

Device Code VIL VIL VIH VIH VHX 8CH

Mode Pins

Am27C1024 7

ABSOLUTE MAXIMUM RATINGS

Storage Temperature

OTP Products. . . . . . . . . . . . . . . . . . –65°C to +125°C

All Other Products . . . . . . . . . . . . . . –65°C to +150°C

Ambient Temperature

with Power Applied. . . . . . . . . . . . . . –55°C to +125°C

Voltage with Respect to VSS

All pins except A9,VPP

,VCC . . . .–0.6 V to VCC + 0.6 V

A9 and VPP (Note 2). . . . . . . . . . . . . –0.6 V to +13.5 V

VCC (Note 1). . . . . . . . . . . . . . . . . . . .–0.6 V to +7.0 V

Notes:

1. Minimum DC v oltage on input or I/O pins is –0.5 V. During

voltage transitions, the inputs may overshoot V

to –2.0

V f or periods of up to 20 ns. Maximum DC v oltage on input

and I/O pins is V

+ 0.5 V. During voltage transitions,

input and I/O pins may overshoot to V

+ 2.0 V for

periods up to 20ns.

2. Minimum DC input v oltage on A9 pin is –0.5 V. During volt-

age transitions, A9 and V

ma y ov ershoot V

to –2.0 V

for periods of up to 20 ns. A9 and V

must not exceed

+13.5 V for any period of time.

Stresses above those listed under “Absolute Maximum Rat-

ings” may cause permanent damage to the device. This is a

stress rating only; functional operation of the device at these

or any other conditions above those indicated in the opera-

tional sections of this speciﬁcation is not implied. Exposure of

the device to absolute maximum rating conditions for ex-

tended periods may affect device reliability.

OPERATING RANGES

Commercial (C) Devices

Ambient Temperature (TA). . . . . . . . . . . .0°C to +70°C

Industrial (I) Devices

Ambient Temperature (TA). . . . . . . . . .–40°C to +85°C

Extended (E) Devices

Ambient Temperature (TA). . . . . . . . .–55°C to +125°C

Supply Read Voltages

VCC for Am27C1024-55, 255 . . . . +4.75 V to +5.25 V

VCC for Am27C1024 (All Others) . +4.50 V to +5.50 V

Operating ranges define those limits between which the func-

tionality of the device is guaranteed.

8 Am27C1024

DC CHARACTERISTICS over operating range unless otherwise speciﬁed

(Notes 1, 2, and 4)

Notes:

1. V

must be applied simultaneously or before V

, and removed simultaneously or after V

2. Caution: The Am27C1024 must not be removed from (or inserted into) a socket when V

or V

is applied.

3. I

CC1

is tested with OE = V

to simulate open outputs.

4. Minimum DC Input Voltage is –0.5 V. During transitions, the inputs may overshoot to –2.0 V for periods less than 20 ns.

Maximum DC Voltage on output pins is V

+ 0.5 V, which may overshoot to V

+ 2.0 V for periods less than 20 ns.

Figure 1. Typical Supply Current vs. Frequency

VCC = 5.5 V, T = 25°CFigure 2. Typical Supply Current vs. Frequency

VCC = 5.5 V, T = 25°C

Parameter

Symbol Parameter Description Test Conditions Min Max Unit

VOH Output HIGH Voltage IOH = –400 mA 2.4 V

VOL Output LOW Voltage IOL = 2.1 mA 0.45 V

VIH Input HIGH Voltage 2.0 VCC + 0.5 V

VIL Input LOW Voltage –0.5 +0.8 V

ILI Input Load Current VIN = 0 V to +VCC C/I Devices 1.0 µA

E Devices 5.0

ILO Output Leakage Current VOUT = 0 V to +VCC 5.0 µA

ICC1 VCC Active Current (Note 3) CE = VIL, f = 10 MHz

IOUT = 0 mA C/I Devices 50 mA

E Devices 60

ICC2 VCC TTL Standby Current CE = VIH 1.0 mA

ICC3 VCC CMOS Standby Current CE = VCC ± 0.3 V 100 µA

IPP1 VPP Current During (Read) CE = OE = VIL, VPP = VCC 100 µA

–75 –50 –25 0 25 50 75 100 125 150

Frequency in MHz

06780I-5

12345678910

Temperature in °C

Supply Current

in mA

Supply Current

in mA

Am27C1024 9

CAPACITANCE

Notes:

1. This parameter is only sampled and not 100% tested.

2. T

= +25

C, f = 1 MHz.

AC CHARACTERISTICS

Notes:

1. Caution: Do not remove the Am27C1024 from (or insert it into) a socket or board that has V

or V

applied.

2. V

must be applied simultaneously or before V

, and removed simultaneously or after V

3. This parameter is sampled and not 100% tested.

4. Switching characteristics are over operating range, unless otherwise speciﬁed.

5. Test Conditions for Am27C1024-55:

Output Load: 1 TTL gate and C

= 30 pF

Input rise and fall times: 20 ns

Input pulse levels: 0.0 V to 3.0 V

Timing measurement reference level Inputs and Outputs: 1.5 V

Test Conditions for all others:

Output Load: 1 TTL gate and C

= 100 pF

Input rise and fall times: 20 ns

Input pulse le vels: 0.45 V to 2.4 V

Timing measurement reference level Inputs and Outputs: 0.8 and 2.0 V

Parameter

Symbol Parameter Description Test

Conditions

CDV040 PD 040 PL 044

UnitTyp Max Typ Max Typ Max

CIN Input Capacitance VIN = 0 912712810pF

OUT Output Capacitance VOUT = 0 121411141114pF

Parameter

Symbols

Description Test Setup

Am27C1024

UnitJEDEC Standard -55 -70 -90 -120 -150 -200 -255

tAVQV tACC Address to Output Delay CE,

OE = VIL Max 55 70 90 120 150 200 250 ns

tELQV tCE Chip Enable to Output Delay OE = VIL Max 55 70 90 120 150 200 250 ns

tGLQV tOE Output Enable to Output Delay CE = VIL Max 40 40 45 50 65 75 75 ns

tEHQZ

tGHQZ

tDF

(Note 3)

Chip Enable to Output High Z or

Output Enable to Output High Z

to Output Float, whichever occurs

ﬁrst

Max 30 30 40 50 50 50 50 ns

tAXQX tOH

Output Hold Time from

Addresses, CE or OE, whiche ver

occurs ﬁrst Min0000000ns

10 Am27C1024

SWITCHING TEST CIRCUIT

Test Conditions

SWITCHING TEST WA VEFORM

2.7 kΩ

Diodes = IN3064

or Equivalent

CL6.2 kΩ

5.0 V

IN3064

or Equivalent

Notes:

For -55: C

= 30 pF including jig capacitance

For all others: C

= 100 pF including jig capacitance

Device

Under

Test

06780I-8

2.4 V

0.45 V Input Output

Test Points

2.0 V 2.0 V

0.8 V

06780I-9

3 V

0 V Input Output

1.5 V 1.5 V

Test Points

A C Testing (except f or -55 de vices): Inputs are driven at 2.4

for a logic “1” and 0.45 V for a logic “0”. Input pulse rise and

fall times are

≤

20 ns.

AC Testing for -55 devices: Inputs are driven at 3.0 V for a

logic “1” and 0 V for a logic “0”. Input pulse rise and fall times

are

≤

20 ns.

Am27C1024 11

KEY TO SWITCHING WAVEFORMS

SWITCHING W A VEFORMS

Notes:

1. OE may be delayed up to t

ACC

– t

after the falling edge of the addresses without impact on t

ACC.

2. DF is speciﬁed from OE or CE, whichever occurs ﬁrst.

Must be

Steady

May

Change

from H to L

May

Change

from L to H

Does Not

Apply

Don’t Care,

Any Change

Permitted

Will be

Steady

Will be

Changing

from H to L

Will be

Changing

from L to H

Changing,

State

Unknown

Center

Line is High-

Impedance

“Off” State

WAVEFORM INPUTS OUTPUTS

KS000010

Addresses

Output

06780I-10

Addresses V alid

High Z High Z

tCE

Valid Output

2.4

0.45

2.0

0.8 2.0

0.8

tACC

(Note 1)

tOE tDF

(Note 2)

tOH

12 Am27C1024

REVISION SUMMARY FOR AM27C1024

Distinctive Characteristics:

The fastest speed grade available is now 55 ns.

Product Selector Guide:

Added 55 ns column.

Ordering Information, UV EPROM Products:

The 55 ns part number is now listed in the example.

The nomenclature now has a method of clearly desig-

nating the voltage operating range and speed grade.

Ordering Information, OTP EPROM Products:

Changed the part number e xample from -70 to -55. The

nomenclature now has a method of clearly designating

the voltage operating range and speed grade.

Operating Ranges:

Changed Supply Read Voltages listings to match those

in the Product Selector Guide.

AC Characteristics:

Added column for 55 ns speed grade, rearranged

notes, moved text from table title to Note 4, renamed

table.

Switching Test Circuit:

Added 55 ns to the CL note on 30 pF test condition.

Switching Test Waveform:

Added the 3 V test waveform.