DC to 204 kHz, Dynamic Signal Analysis, Precision 24-Bit ADC with Power Scaling AD7768-1 Data Sheet FEATURES Power supply AVDD1 - AVSS = 5.0 V typical AVDD2 - AVSS = 2.0 V to 5.0 V typical Analog supplies can run from split supply (true bipolar) IOVDD - DGND = 1.8 V to 3.3 V typical Low power mode can run from single 3.3 V supply Pin control or SPI interface configurable Suite of diagnostic check mechanisms Temperature, interface CRC, and memory map CRC Package: 28-lead, 4 mm x 5 mm, LFCSP Temperature range: -40C to +125C ADC for single-channel low power, platform DAQ designs Wide BW Sinc filter BW range: DC to 204 kHz Low ripple FIR BW range: DC to 110.8 kHz Precision ac and dc performance 108.5 dB dynamic range -120 dB THD 1.1 ppm of FSR INL, 30 V offset error, 30 ppm of FSR gain error Programmable ODR, filter type, and latency ODR values up to 1024 kSPS Linear phase digital filter options Low ripple FIR filter: 0.005 dB maximum pass-band ripple, dc to 102.4 kHz Low latency sinc5 filter Low latency sinc3 filter enabling 50 Hz/60 Hz rejection Programmable power consumption and bandwidth Fast, highest speed 52.224 kHz BW, 26.4 mW (sinc5 filter) 110.8 kHz BW, 36.8 mW (FIR filter) Median, half speed: 55.4 kHz BW, 19.7 mW (FIR filter) Low power, low speed: 13.9 kHz BW, 6.75 mW (FIR filter) APPLICATIONS Platform ADC to serve a superset of measurements and sensor types Sound and vibration, acoustic, and material science research and development Control and hardware in loop verification Condition monitoring for predictive maintenance Electrical test and measurement Audio testing and current and voltage measurement Clinical EEG, EMG, and ECG vital signs monitoring USB-, PXI-, and Ethernet-based modular DAQ Channel to channel isolated modular DAQ designs FUNCTIONAL BLOCK DIAGRAM AVDD1 REF+ REF- AVDD2 REGCAPA REGCAPD IOVDD DGND AD7768-1 SYNC_IN 1.8V LDO 1.8V LDO REFERENCE BUFFERS WIDEBAND LOW RIPPLE FILTER AIN+ POWER SCALABLE - ADC AIN- AVSS SINC5 LOW LATENCY FILTER SINC3 FILTER ENABLING 50Hz/60Hz REJECTION PRECHARGE BUFFERS MCLK/XTAL2 XTAL1 SYNC_OUT RESET CLKSEL ADC DATA SERIAL INTERFACE DRDY CS DOUT/RDY SDI SCLK CONTROL BLOCK MODE3 TO MODE0 (GPIO3 TO GPIO0) PIN/SPI 16481-001 /2 VCM Figure 1. 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Technical Support www.analog.com AD7768-1 Data Sheet TABLE OF CONTENTS Features .............................................................................................. 1 Register Summary .......................................................................... 63 Applications ....................................................................................... 1 Register Details ............................................................................... 65 Functional Block Diagram .............................................................. 1 Component Type Register ........................................................ 65 Revision History ............................................................................... 3 Unique Product ID Registers .................................................... 65 General Description ......................................................................... 4 Device Grade and Revision Register ....................................... 65 Specifications..................................................................................... 5 User Scratchpad Register........................................................... 65 3 V Operation ............................................................................. 10 Device Vendor ID Registers ...................................................... 65 Timing Specifications ................................................................ 11 Interface Format Control Register ........................................... 66 1.8 V Timing Specifications ...................................................... 12 Power and Clock Control Register........................................... 66 Absolute Maximum Ratings .......................................................... 16 Analog Buffer Control Register ................................................ 67 Thermal Resistance .................................................................... 16 VCM Control Register ............................................................... 68 ESD Caution ................................................................................ 16 Conversion Source Select and Mode Control Register ......... 68 Pin Configuration and Function Descriptions ........................... 17 Digital Filter and Decimation Control Register ..................... 69 Typical Performance Characteristics ........................................... 19 Sinc3 Decimation Rate (MSB Register) .................................. 70 Terminology .................................................................................... 27 Sinc3 Decimation Rate (LSB Register) .................................... 70 Theory of Operation ...................................................................... 28 Periodic Conversion Rate Control Register ............................ 70 Clocking, Sampling Tree, and Power Scaling ......................... 28 Synchronization Modes and Reset Triggering Register ........ 70 Noise Performance and Resolution.......................................... 29 GPIO Port Control Register...................................................... 71 Core Converter ........................................................................... 31 GPIO Output Control Register ................................................ 71 Clocking and Clock Selection ................................................... 34 GPIO Input Read Register ........................................................ 71 Digital Filtering ........................................................................... 34 Offset Calibration MSB Register .............................................. 71 Decimation Rate Control .......................................................... 38 Offset Calibration MID Register .............................................. 72 Antialiasing Filtering ................................................................. 38 Offset Calibration LSB Register................................................ 72 Getting Started ............................................................................ 39 Gain Calibration MSB Register ................................................ 72 Power Supplies ............................................................................ 41 Gain Calibration MID Register ................................................ 72 Device Configuration Method ................................................. 41 Gain Calibration LSB Register .................................................. 73 Pin Control Mode Overview..................................................... 42 SPI Interface Diagnostic Control Register .............................. 73 SPI Control Overview ................................................................ 44 ADC Diagnostic Feature Control Register ............................. 73 SPI Control Mode ....................................................................... 45 Digital Diagnostic Feature Control Register .......................... 73 Digital Interface .............................................................................. 48 Conversion Result Register ....................................................... 74 Data Conversion Modes ............................................................ 52 Device Error Flags Master Register ......................................... 74 Synchronization of Multiple AD7768-1 Devices ................... 53 SPI Interface Error Register ...................................................... 74 Additional Functionality of the AD7768-1 ............................. 55 ADC Diagnostics Output Register........................................... 74 Applications Information .............................................................. 56 Digital Diagnostics Output Register ........................................ 75 Analog Input Recommendations ............................................. 56 MCLK Diagnostic Output Register ......................................... 75 Antialiasing Filter Design Considerations .............................. 57 Coefficient Control Register ..................................................... 75 Recommended Interface ........................................................... 58 Coefficient Data Register .......................................................... 75 Programmable Digital Filter ..................................................... 59 Access Key Register .................................................................... 75 Electromagnetic Compatibility (EMC) Testing ..................... 61 Outline Dimensions ....................................................................... 76 AD7768-1 Subsystem Layout .................................................... 62 Ordering Guide .......................................................................... 76 Rev. 0 | Page 2 of 76 Data Sheet AD7768-1 REVISION HISTORY 5/2018--Revision 0: Initial Version Rev. 0 | Page 3 of 76 AD7768-1 Data Sheet GENERAL DESCRIPTION The AD7768-1 is a low power, high performance, - analogto-digital converter (ADC), with a - modulator and digital filter for precision conversion of both ac and dc signals. The AD7768-1 is a single-channel version of the AD7768, an 8-channel, simultaneously sampling, - ADC. The AD7768-1 provides a single configurable and reusable data acquisition (DAQ) footprint, which establishes a new industry standard in combined ac and dc performance and enables instrumentation and industrial system designers to design across multiple measurement variants for both isolated and nonisolated applications. The AD7768-1 achieves a 108.5 dB dynamic range when using the low ripple, finite impulse response (FIR) digital filter at 256 kSPS, giving 110.8 kHz input bandwidth (BW), combined with 1.1 ppm integral nonlinearity (INL), 30 V offset error, and 30 ppm gain error. A wider bandwidth, up to 500 kHz Nyquist (filter -3 dB point of 204 kHz), is available using the sinc5 filter, enabling a view of signals over an extended range. The AD7768-1 offers the user the flexibility to configure and optimize for input bandwidth vs. output data rate (ODR) and vs. power dissipation. The flexibility of the AD7768-1 allows dynamic analysis of a changing input signal, making the device particularly useful in general-purpose DAQ systems. The selection of one of three available power modes allows the designer to achieve required noise targets while minimizing power consumption. The design of the AD7768-1 is unique in that it becomes a reusable and flexible platform for low power dc and high performance ac measurement modules. The AD7768-1 achieves the optimum balance of dc and ac performance with excellent power efficiency. The following three operating modes allow the user to trade off the input bandwidth vs. power budgets: * * * Fast mode offers both a sinc filter with up to 256 kSPS and 52.2 kHz of bandwidth, and 26.4 mW of power consumption, or a FIR filter with up to 256 kSPS, 110.8 kHz of bandwidth and 36.8 mW of power consumption. Median mode offers a FIR filter with up to 128 kSPS, 55.4 kHz of bandwidth and 19.7 mW of power consumption. Low power mode offers a FIR filter with up to 32 kSPS, 13.85 kHz of bandwidth and 6.75 mW of power consumption. The AD7768-1 offers extensive digital filtering capabilities that meet a wide range of system requirements. The filter options allow configuration for frequency domain measurements with tight gain error over frequency, linear phase response requirements (brick wall filter), a low latency path (sinc5 or sinc3) for use in control loop applications, and measuring dc inputs with the ability to configure the sinc3 filter to reject the line frequency of either 50 Hz or 60 Hz. All filters offer programmable decimation. A 1.024 MHz sinc5 filter path exists for users seeking an even higher ODR than is achievable using the low ripple FIR filter. This path is quantization noise limited. Therefore, it is best suited for customers requiring minimum latency for control loops or implementing custom digital filtering on an external field programmable gate array (FPGA) or digital signal processor (DSP). The filter options include the following: * * * A low ripple FIR filter with a 0.005 dB pass-band ripple to 102.4 kHz. A low latency sinc5 filter with up to a 1.024 MHz data rate to maximize control loop responsiveness. A low latency sinc3 filter that is fully programmable, with 50 Hz/60 Hz rejection capabilities. When using the AD7768-1, embedded analog functionality within the AD7768-1 greatly reduces the design burden over the entire application range. The precharge buffer on each analog input decreases the analog input current compared to competing products, simplifying the task of an external amplifier to drive the analog input. A full buffer input on the reference reduces the input current, providing a high impedance input for the external reference device or in buffering any reference sense resistor scenarios used in ratiometric measurements. The device operates with a 5.0 V AVDD1 - AVSS supply, a 2.0 V to 5.0 V AVDD2 - AVSS supply, and a 1.8 V to 3.3 V IOVDD - DGND supply. In low power mode, the AVDD1, AVDD2, and IOVDD supplies can run from a single 3.3 V rail. The device requires an external reference. The absolute input reference (REFIN) voltage range is 1 V to AVDD1 - AVSS. The specified operating temperature range is -40C to +125C. The device is housed in a 4 mm x 5 mm, 28-lead LFCSP. Note that, throughout this data sheet, multifunction pins, such as XTAL2/MCLK, are referred to either by the entire pin name or by a single function of the pin, for example, MCLK, when only that function is relevant. Rev. 0 | Page 4 of 76 Data Sheet AD7768-1 SPECIFICATIONS AVDD1 = 4.5 V to 5.5 V, AVDD2 = 2.0 V to 5.5 V, IOVDD = 1.7 V to 3.6 V, DGND = 0 V, AVSS = 0 V, REF+ = 4.096 V, REF- = 0 V, MCLK = 16.384 MHz, 50:50 duty cycle, analog input precharge buffers on, reference precharge on, the filter type is a low ripple FIR filter, and TA = TMIN to TMAX, unless otherwise noted. Table 1. Parameter ADC SPEED AND CODING ODR 1 Test Conditions/Comments Min Fast sinc5 Fast low ripple FIR Fast sinc3 Median sinc5 Median low ripple FIR Median sinc3 Low power sinc5 Low power low ripple FIR Low power sinc3 8 1024 8 256 0.05 256 4 512 4 128 0.025 128 1 128 1 32 0.0125 32 24-bit twos complement data, followed by eight status bits (if enabled), followed by eight cyclic redundancy check (CRC) bits (if enabled) kSPS kSPS kSPS kSPS kSPS kSPS kSPS kSPS kSPS 110 106.5 111.5 108.5 115 dB dB dB 110.5 107.5 107.3 dB dB dB Data Output Coding DYNAMIC PERFORMANCE Fast Mode Dynamic Range Signal to Noise Ratio (SNR) Signal-to-Noise-andDistortion (SINAD) Total Harmonic Distortion (THD) Spurious-Free Dynamic Range (SFDR) Median Mode Dynamic Range SNR SINAD THD SFDR Low Power Mode Dynamic Range SNR SINAD THD SFDR Decimation by 32, 256 kHz ODR Shorted inputs, sinc5 filter Shorted inputs, low ripple FIR A-weighted, 1 kHz input, -60 dBFS, decimation by 128, low ripple FIR 1 kHz, -0.25 dBFS, sine input Sinc5 filter Low ripple FIR 1 kHz, -0.25 dBFS, sine input 106 105 1 kHz, -0.25 dBFS, sine input Typ -120 Decimation by 32, 128 kHz ODR Shorted inputs, sinc5 filter Shorted inputs, low ripple FIR 1 kHz, -0.25 dBFS, sine input Sinc5 filter Low ripple FIR 1 kHz, -0.25 dBFS, sine input 1 kHz, -0.25 dBFS, sine input Decimation by 32, 32 kHz ODR Shorted inputs, sinc5 filter Shorted inputs, low ripple FIR 1 kHz, -0.25 dBFS, sine input Sinc filter Low ripple FIR 1 kHz, -0.25 dBFS, sine input 1 kHz, -0.25 dBFS, sine input 110 106.5 106 105 110 106.5 106 105 Rev. 0 | Page 5 of 76 Max -112 Unit dB 125 dBc 111.5 108.5 dB dB 110.5 107.5 107.3 -120 125 dB dB dB dB dBc -112 111.5 108.5 dB dB 111 107.8 107.5 -120 125 dB dB dB dB dBc -112 AD7768-1 Parameter Intermodulation Distortion (IMD) ACCURACY No Missing Codes 2 INL Offset Error Offset Error Drift2 Gain Error Gain Drift vs. Temperature2 ANALOG INPUTS Differential Input Voltage Absolute AINx Voltage2 Analog Input Current Unbuffered Precharge Buffers On 3 Input Current Drift2 Unbuffered Precharge Buffer On EXTERNAL REFERENCE REFIN Voltage Absolute REFIN Voltage Limits Average REFIN Current Average REFIN Current Drift2 Common-Mode Rejection DIGITAL FILTER RESPONSE Low Ripple FIR Filter Decimation Rate ODR Group Delay Settling Time Pass-Band Ripple 4 Data Sheet Test Conditions/Comments Frequency Input A (fa) = 9.7 kHz, Frequency Input B (fb) = 10.3 kHz Second order Third order Min Low ripple FIR, sinc5 decimation > 32 Endpoint method 24 Typ Max -125 -125 Unit dB dB 1.1 7 Fast mode Median mode Low power mode Fast mode Median mode Low power mode TA = 25C, reference buffer on 30 30 20 300 225 100 30 170 170 80 TA = 25C, reference buffer off 30 70 Reference buffer off 0.25 0.6 Bits ppm of FSR V V V nV/C nV/C nV/C ppm of FSR ppm of FSR ppm/C VREF+ AVDD1 + 0.05 V V Reference voltage (VREF) = REF+ - REF- Precharge buffers off, absolute voltage on AIN+ or AIN- Fast mode Differential component Common-mode component VREF- AVSS - 0.05 53 17 -20 A/V A/V A 12.5 3 nA/V/C nA/C Fast mode REFIN = (REF+) - (REF-) Reference unbuffered 1 AVSS - 0.05 AVDD1 - AVSS AVDD1 + 0.05 V V Reference precharge buffer on Reference buffer on Reference unbuffered Reference precharge buffer on Reference buffer on Reference unbuffered AVSS AVSS AVDD1 AVDD1 80 20 300 1.7 V V A/V A nA nA/V/C 125 4 100 nA/C nA/C dB Reference precharge buffer on Reference buffer on Up to 10 MHz Six selectable decimation rates 32 Latency Complete settling 1024 256 34/ODR 68/ODR 0.005 Rev. 0 | Page 6 of 76 kSPS Sec Sec dB Data Sheet Parameter Pass Band Stop-Band Frequency Stop-Band Attenuation 5 Sinc5 Filter Decimation Rate ODR Group Delay Settling Time Pass Band Sinc3 Filter Decimation Rate4 ODR Group Delay Settling Time Pass Band REJECTION AC Power Supply Rejection Ratio (PSRR) AVDD1 AVDD2 IOVDD DC PSRR AVDD1 AVDD2 IOVDD Analog Input CommonMode Rejection Ratio (CMRR) DC AC Normal Mode Rejection CLOCK MCLK External Clock Internal Clock Duty Cycle2 Crystal Frequency Start-Up Time ADC RESET ADC Start-Up Time After Reset Reset Low Pulse Width AD7768-1 Test Conditions/Comments -0.005 dB -0.1 dB pass band -3 dB bandwidth Attenuation > 105 dB Min Eight selectable decimation rates 8 Latency Complete settling -0.1 dB bandwidth -3 dB bandwidth Typ 0.4 x ODR 0.409 x ODR 0.433 x ODR 0.499 x ODR 105 Max 1024 1024 <3/ODR <6/ODR 0.0376 x ODR 0.204 x ODR Decimation from decimation by 32 to decimation by 185,280 is possible in steps of 32 32 kSPS Sec Sec Hz Hz 185,280 256 Latency Complete settling to reject 50 Hz -0.1 dB bandwidth -3 dB bandwidth Unit Hz Hz Hz Hz dB 2/ODR 60 0.0483 x ODR 0.2617 x ODR kSPS Sec ms Hz Hz 100 85 100 100 dB dB dB dB 105 118 95 dB dB dB 95 80 65 dB dB dB dB Input voltage (VIN) = 0.1 V, dc to 16 MHz Full, median mode Low power mode VIN = 0.1 V VIN = 0.1 V Up to 10 kHz, see Figure 54 50 Hz 1 Hz, sinc3 filter, 60 Hz rejection on 60 Hz 1 Hz, sinc3 filter, 60 Hz rejection on 90 0.6 16.384 MHz MCLK 25:75 8 Clock output valid Reset rising edge to first DRDY, PIN mode, decimate by 8 16.384 16.384 50:50 16 2 17 75:25 17 100 0.0001 Rev. 0 | Page 7 of 76 MHz MHz % MHz ms s 100 ms AD7768-1 Parameter LOGIC INPUTS Input Voltage High, VINH Low, VINL Hysteresis2 Leakage Current LOGIC OUTPUTS Output Voltage2 High, VOH Low, VOL Leakage Current Output Capacitance VCM OUTPUT VCM Noise4 Short-Circuit Current 6 Load Regulation POWER REQUIREMENTS AVDD1 - AVSS AVDD1 - AVSS AVDD2 - AVSS AVSS - DGND IOVDD - DGND POWER SUPPLY CURRENT Fast Mode AVDD1 Current AVDD2 Current IOVDD Current Data Sheet Test Conditions/Comments Min 1.7 V IOVDD 1.9 V 2.2 V IOVDD 3.6 V 1.7 V IOVDD 1.9 V 2.2 V IOVDD 3.6 V 2.2 V IOVDD 3.6 V 1.7 V IOVDD 1.9 V Excluding RESET pin RESET pin pull-up resistor 0.65 x IOVDD 0.65 x IOVDD 0.08 0.04 -10 2.2 V IOVDD < 3.6 V, source current (ISOURCE) = 500 A, LV_BOOST off 1.7 V IOVDD 1.9 V, ISOURCE = 200 A, LV_BOOST on 2.2 V IOVDD < 3.6 V, sink current (ISINK) = 1 mA, LV_BOOST off 1.7 V IOVDD 1.9 V, ISINK = 400 A, LV_BOOST on Floating state Floating state Default setting +0.05 1 Max 0.35 x IOVDD 0.7 0.25 0.2 +10 Unit V V V V V V A k 0.8 x IOVDD V 0.8 x IOVDD V -10 0.4 V 0.4 V +10 A pF V 10 AVDD1 - AVSS/2 10 VCM = (AVDD1 - AVSS)/2, from simulation, 1 kHz bandwidth limited VCM = 2.5 V, from simulation, 1 kHz bandwidth limited Power supply voltages All power modes Low power mode only Typ 4.5 3 2 -2.75 1.7 All buffers off, VCM off Analog input precharge on (defaults on in PIN mode) Precharge reference buffer (per precharge buffer, defaults on in PIN mode ) Full reference buffer (per buffer) VCM output on Sinc5 filter||low ripple FIR filter Rev. 0 | Page 8 of 76 V rms 65 V rms 10 1 mA mV/mA 5.0 1.8 to 3.3 5.5 5.5 5.5 0 3.6 V V V V V 2.2 4.1 2.65 5.1 mA mA 1.2 1.5 mA 3.2 0.21 4.7 3.35||9.2 4.15 mA mA mA mA 2.0 to 5.0 5.65 4.4||11.5 Data Sheet Parameter Median Mode AVDD1 Current AVDD2 Current IOVDD Current Low Power Mode AVDD1 Current AVDD2 Current IOVDD Current Power Saving States Standby Mode Power-Down Mode POWER DISSIPATION Sinc5 Filter Fast Mode Median Mode Low Power Mode Low Ripple FIR Filter Fast Mode Median Mode Low Power Mode Standby Mode Power-Down Mode AD7768-1 Test Conditions/Comments Min All buffers off Analog input precharge on (PIN mode default) Precharge reference buffer (per precharge buffer) Full reference buffer (per buffer) Sinc5 filter||low ripple FIR filter All buffers off Analog input precharge on (PIN mode default) Precharge reference buffer (per precharge buffer) Full reference buffer (per buffer) Sinc5 filter||low ripple FIR filter, 16.384 MHz MCLK, MCLK_DIV = 16 Serial peripheral interface (SPI) active, MCLK active, VCM off SPI active, MCLK inactive, VCM off Full power-down; SPI control mode only AVDD1 = 5 V, MCLK = 16.384 MHz, external complementary metal oxide semiconductor (CMOS) MCLK AVDD2 = 2 V, IOVDD = 1.8 V All buffers off Analog input (AIN) precharge only All buffers off AIN precharge only All buffers off AIN precharge only AVDD2 = 2 V, IOVDD = 1.8 V All buffers off AIN precharge only All buffers off AIN precharge only All buffers off AIN precharge only SPI active, MCLK active, VCM off SPI active, MCLK inactive, VCM off Full power down, SPI control mode only Typ Max Unit 1.2 2.45 1.35 2.6 mA mA 0.65 0.77 mA 1.6 2.7 1.97||5 2.1 3.2 2.8||6.4 mA mA mA 0.3 0.6 0.35 0.71 mA mA 0.16 0.22 mA 0.4 1.15 0.95||1.7 0.56 1.37 1.6||2.45 mA mA mA 400 A 50 5 A A 26.4 35.6 14.4 19.1 5.4 6.8 32.5 44.75 18.2 24.45 7.4 9.2 mW mW mW mW mW mW 36.8 46.1 19.7 24.4 6.75 8.1 780 125 14 45.25 57.5 24.7 30.95 8.9 10.7 mW mW mW mW mW mW W W W The ODR ranges refer to the programmable decimation rates available on the AD7768-1 for a fixed MCLK rate of 16.384 MHz. Varying the MCLK rate allows the user a wider variation of ODR. 2 This specification is not production tested, but is supported by characterization data at initial product release. 3 The typical value (-20 A) is measured when the analog input is close to either the AVDD1 or AVSS rail. The input current reduces as the common mode approaches the midpoint of the power supply rails: (AVDD1 - AVSS)/2. The analog input current scales with the MCLK frequency and the power mode (fast, median, and low power). 4 This specification is not production tested. It is supported by a combination of design simulation and test coverage on a limited number of units. 5 Alias rejection around frequencies related to the chop frequency may result in compound attenuation, which exceeds 105 dB. See the Antialiasing Filtering section describing front-end antialias protection for further detail. 6 VCM can typically source 10 mA, but it is recommended to source no more than 6 mA in normal operation. 1 Rev. 0 | Page 9 of 76 AD7768-1 Data Sheet 3 V OPERATION For low power mode only. AVDD1, AVDD2, and IOVDD = 3 V, DGND = 0 V, AVSS = 0 V, REF+ = 2.5V, and REF- = 0 V, MCLK = 16.384 MHz, analog input precharge buffers on, reference precharge on, the filter type is a low ripple FIR filter, chop frequency (fCHOP) = modulator frequency (fMOD)/32, and TA = TMIN to TMAX, unless otherwise noted. Table 2. Parameter ADC SPEED AND PERFORMANCE ODR 1 No Missing Codes 2 DYNAMIC PERFORMANCE Low Power Mode Dynamic Range SNR SINAD THD SFDR ACCURACY INL Offset Error Offset Error Drift2 Gain Error ANALOG INPUTS Differential Input Voltage Absolute AINx Voltage Analog Input Current Input Current Unbuffered Input Current 3 EXTERNAL REFERENCE REFIN Voltage Absolute REFIN Voltage Limits Average REFIN Current Common-Mode Rejection Ratio (CMRR) Test Conditions/Comments Min Low power mode Low ripple FIR filter and sinc5 filter Sinc3 Low ripple FIR, sinc5 decimation > 32 1 0.0125 24 Decimation by 32, 32 kHz ODR Shorted inputs, sinc5 filter Shorted inputs, low ripple FIR 1 kHz, -0.25 dBFS, sine input Low ripple FIR 100.9 Endpoint method Low power mode Low power mode TA = 25C Typ REFIN = (REF+) - (REF-) Reference buffer off Reference buffer on Reference buffer off Reference buffer on kSPS kSPS Bits 102.5 102.3 -125 120 dB dB dB dBc -112 175 VREF+ AVDD1 + 0.05 53 17 -20 1 AVSS - 0.05 AVSS ppm of FSR V nV/C ppm/FSR V V A/V A/V A AVDD1 - AVSS AVDD1 + 0.05 AVDD1 80 20 300 100 Up to 10 MHz 32 32 dB dB VREF- AVSS - 0.05 Differential component Common-mode component Precharge buffers on, external CMOS MCLK Unit 106.9 104 3 40 100 30 VREF = REF+ - REF- Analog input precharge buffers off, absolute voltage on AIN+ or AIN- Max V V V A/V nA nA/V/C dB The ODR ranges refer to the programmable decimation rates available on the AD7768-1 for a fixed MCLK rate of 16.384 MHz. Varying the MCLK rate allows the user a wider variation of ODR. 2 This specification is not production tested, but is supported by characterization data at initial product release. 3 The typical value (-20 A) is measured when the analog input is close to either the AVDD1 or AVSS rail. The input current reduces as the common mode approaches the midpoint of the power supply rails: (AVDD1 - AVSS)/2. Analog input current scales with the MCLK frequency and the power mode (fast, median, and low power). 1 Rev. 0 | Page 10 of 76 Data Sheet AD7768-1 TIMING SPECIFICATIONS AVDD1 = 4.5 V to 5.5 V, AVDD2 = 2.0 V to 5.5 V, IOVDD = 2.2 V to 3.6 V, AVSS = DGND = 0 V, Input Logic 0 = 0 V, Input Logic 1 = IOVDD, and load capacitance (CLOAD) = 20 pF, LV_BOOST bit (Bit 7, INTERFACE_FORMAT register, Address 0x14) disabled, unless otherwise noted. These specifications were sample tested during the initial release to ensure compliance. All input signals are specified with tR = tF = 5 ns (10% to 90% of IOVDD and timed from a voltage level of IOVDD/2). See Figure 2 to Figure 8 for the timing diagrams. These specifications are not production tested, but are supported by characterization data at initial product release. Table 3. Parameter MCLK tMCLK_HIGH tMCLK_LOW fMOD Description Frequency MCLK high time MCLK low time Modulator frequency tDRDY Conversion period tDRDY_HIGH Test Conditions/Comments MCLK/2 MCLK/4 MCLK/16 fMOD/DEC_RATE Unit MHz ns ns Hz Hz Hz Hz tMCLK - 5 1 x tMCLK ns Rising MCLK edge to DRDY rising edge 10 13 18 ns Rising MCLK edge to RDY falling edge 10 13 18 ns DRDY high time tMCLK_DRDY MCLK to DRDY tMCLK_RDY tUPDATE MCLK to RDY indicator on the DOUT/RDY pin ADC data update tSTART START pulse width tMCLK_SYNC_OUT MCLK to SYNC_OUT tSCLK t1 t2 t3 SCLK period CS falling to SCLK falling CS falling to data output enable SCLK falling edge to data output valid Data output hold time after SCLK falling edge SDI setup time before SCLK rising edge SDI hold time after SCLK rising edge CS high time SCLK high time SCLK low time SCLK rising edge to DRDY high t5 t6 t7 t8 t9 t10 t11 t12 t13 t14 t15 SCLK rising edge to CS rising edge CS rising edge to DOUT/RDY output disable DOUT/RDY indicator pulse width Typ 16.384 Max 17 16 16 Fast mode Median mode Low power mode Rising DRDY edge to next rising DRDY edge, continuous conversion mode tMCLK = 1/MCLK t4 Min Time prior to DRDY rising edge where the ADC conversion register updates, single conversion read 1 x tMCLK ns 1.5 x tMCLK ns Falling MCLK to falling SYNC_OUT tMCLK + 16 50 0 10 4-wire interface Single conversion read only; time from last SCLK rising edge to DRDY high ns 3 ns 8 ns 10 20 20 1 x tMCLK ns ns ns ns In continuous read mode with RDY on, DOUT enabled, with SCLK idling high Rev. 0 | Page 11 of 76 ns ns ns ns 4 6 4 CS falling edge to SCLK rising edge SYNC_IN setup time before MCLK rising edge 6 15 ns 7 1 x tMCLK ns ns ns 2 ns 2 ns AD7768-1 Data Sheet Parameter t16 Description SYNC_IN pulse width Test Conditions/Comments t17 SCLK rising edge to RDY indicator rising edge DRDY rising edge to SCLK falling edge In continuous read mode with RDY enabled on DOUT In continuous read mode with RDY enabled on DOUT t18 Min 1.5 x tMCLK 1 Typ Max Unit ns ns 8 ns 1.8 V TIMING SPECIFICATIONS AVDD1 = 4.5 V to 5.5 V, AVDD2 = 2 V to 5.5 V, IOVDD = 1.7 V to 1.9 V, AVSS = DGND = 0 V, Input Logic 0 = 0 V, Input Logic 1 = IOVDD, and CLOAD = 20 pF, LV_BOOST bit (Bit 7, INTERFACE_FORMAT register, Address 0x14) enabled, unless otherwise noted. These specifications were sample tested during the initial release to ensure compliance. All input signals are specified with tR = tF = 5 ns (10% to 90% of IOVDD and timed from a voltage level of IOVDD/2. See Figure 2 to Figure 8 for the timing diagrams. These specifications are not production tested but are supported by characterization data at initial product release. Table 4. Parameter MCLK tMCLK_HIGH tMCLK_LOW fMOD Description Frequency MCLK high time MCLK low time Modulator frequency tDRDY Conversion period tDRDY_HIGH DRDY high time tMCLK_DRDY MCLK to DRDY tMCLK_RDY tUPDATE MCLK to RDY indicator on the DOUT/RDY pin ADC data update tSTART START pulse width tMCLK_SYNC_OUT MCLK to SYNC_OUT tSCLK t1 t2 t3 SCLK period CS falling to SCLK falling CS falling to data output enable SCLK falling edge to data output valid Data output hold time after SCLK falling edge SDI setup time before SCLK rising edge SDI hold time after SCLK rising edge CS high time SCLK high time SCLK low time t4 t5 t6 t7 t8 t9 Test Conditions/Comments Min Typ 16.384 Max 17 16 16 Fast mode Median mode Low power mode Rising DRDY edge to next rising DRDY edge, continuous conversion mode tMCLK = 1/MCLK Rising MCLK edge to DRDY rising edge Rising MCLK edge to RDY falling edge Time prior to DRDY rising edge where the ADC conversion register updates MCLK/2 MCLK/4 MCLK/16 fMOD/DEC_RATE tMCLK - 5 1 x tMCLK 13 19 25 ns 13 19 25 ns ns 1 x tMCLK ns 1.5 x tMCLK ns Falling MCLK to falling SYNC_OUT, see the Synchronization of Multiple AD7768-1 Devices section tMCLK + 31 ns 11 19 ns ns ns ns 50 0 14 4-wire interface Rev. 0 | Page 12 of 76 Unit MHz ns ns Hz Hz Hz Hz 7 ns 3 ns 8 ns 10 23 23 ns ns ns Data Sheet AD7768-1 Parameter t10 Description SCLK rising edge to DRDY high t11 t12 SCLK rising edge to CS rising edge CS rising edge to DOUT/RDY output disable DOUT/RDY indicator pulse width t13 t14 t15 t16 t17 t18 Test Conditions/Comments Time from last SCLK rising edge to DRDY high; if this is exceeded, conversion N + 1 is missed; single conversion read Min 1 x tMCLK Typ Max 6 7.5 13 In continuous read mode with RDY on, DOUT enabled, with SCLK idling high CS falling edge to SCLK rising edge SYNC_IN setup time before MCLK rising edge SYNC_IN pulse width SCLK rising edge to RDY indicator rising edge DRDY rising edge to SCLK falling edge 1 x tMCLK In continuous read mode with RDY on, DOUT enabled In continuous read mode with RDY on, DOUT enabled 1.5 x tMCLK 5.5 ns ns 15 ns t12 t14 t9 SCLK R/W ADDRESS 1 DOUT/RDY t8 t2 t11 DATA BEING READ, 8 BITS/24 BITS Figure 2. SPI Read Timing Diagram t14 CS SCLK FS R/W t5 LSB t11 Figure 3. SPI Write Timing Diagram Rev. 0 | Page 13 of 76 16481-003 t6 SDI 16481-002 FS SDI ns ns ns CS tSCLK ns ns 2.5 2 Timing Diagrams t1 Unit ns AD7768-1 Data Sheet tMCLK_DRDY tMCLK_HIGH tUPDATE MCLK tMCLK_LOW tDRDY_HIGH tDRDY DRDY t7 CS t10 tSCLK t1 t8 SCLK t4 t9 t3 16481-004 t2 DOUT/RDY Figure 4. Reading Conversion Result in Continuous Conversion Mode (CS Toggling) tMCLK_DRDY MCLK tDRDY_HIGH tDRDY DRDY tMCLK_RDY DOUT/RDY 1 0 MSB t3 0 MSB t17 16481-005 t18 1 LSB SCLK Figure 5. Reading Conversion Result in Continuous Conversion Mode, Continuous Read Mode with RDY Enabled (CS Held Low) MCLK tDRDY_HIGH 1 x MCLK DRDY t13 SCLK 16481-006 DOUT/RDY CONTINUOUS READBACK MODE ENTERED Figure 6. DOUT/RDY Behavior Without SCLK Applied Rev. 0 | Page 14 of 76 Data Sheet AD7768-1 MCLK t15 SYNC_IN 16481-007 t15 t16 Figure 7. Synchronous SYNC_IN Pulse MCLK START (GPIO INPUT) tSTART 1 x MCLK tMCLK_SYNC_OUT Figure 8. Asynchronous START and SYNC_OUT Rev. 0 | Page 15 of 76 16481-008 SYNC_OUT AD7768-1 Data Sheet ABSOLUTE MAXIMUM RATINGS THERMAL RESISTANCE Table 5. Parameter AVDD1, AVDD2 to AVSS1 AVDD1 to DGND IOVDD to DGND IOVDD, REGCAPD to DGND (IOVDD Tied to REGCAPD for 1.8 V Operation) IOVDD to AVSS AVSS to DGND Analog Input Voltage to AVSS Reference Input Voltage to AVSS Digital Input Voltage to DGND Digital Output Voltage to DGND XTAL1 to DGND Operating Temperature Range Storage Temperature Range Pb-Free Temperature, Soldering Reflow (10 sec to 30 sec) Maximum Junction Temperature Maximum Package Classification Temperature 1 Thermal performance is directly linked to printed circuit board (PCB) design and operating environment. Close attention to PCB thermal design is required. Rating -0.3 V to +6.5 V -0.3 V to +6.5 V -0.3 V to +6.5 V -0.3 V to +2.25 V Table 6. Thermal Resistance -0.3 V to +7.5 V -3.25 V to +0.3 V -0.3 V to AVDD1 + 0.3 V -0.3 V to AVDD1 + 0.3 V -0.3 V to IOVDD + 0.3 V -0.3 V to IOVDD + 0.3 V -0.3 V to +2.1 V -40C to +125C -65C to +150C 260C Package Type CP-28-12 JA1 35 JC2 0.83 Unit C/W Thermal impedance simulated values are based on a JEDEC 2S2P thermal test board. See JEDEC JESD-51. Based on a 1S0P test PCB with cold plate attached to the package top surface. 3 Measured to exposed pad. 1 2 ESD CAUTION 150C 260C Transient currents of up to 100 mA do not cause silicon controlled rectifier (SCR) latch-up. Stresses at or above those listed under Absolute Maximum Ratings may cause permanent damage to the product. This is a stress rating only; functional operation of the product at these or any other conditions above those indicated in the operational section of this specification is not implied. Operation beyond the maximum operating conditions for extended periods may affect product reliability. Rev. 0 | Page 16 of 76 Data Sheet AD7768-1 VCM AIN+ AIN- REF- REF+ AVDD1 PIN CONFIGURATION AND FUNCTION DESCRIPTIONS 28 27 26 25 24 23 RESET SYNC_IN SYNC_OUT REGCAPD IOVDD PIN/SPI DGND CLKSEL 1 2 3 4 5 6 7 8 AD7768-1 TOP VIEW (Not to Scale) 22 21 20 19 18 17 16 15 AVDD2 AVSS REGCAPA DRDY MODE3/GPIO3 (START) MODE2/GPIO2 MODE1/GPIO1 MODE0/GPIO0 NOTES 1. NEGATIVE ANALOG SUPPLY. NOMINALLY GND (0V). RELATES TO AVDD1 AND AVDD2 SUPPLIES. 16481-009 DOUT/RDY SCLK SDI CS XTAL1 MCLK/XTAL2 9 10 11 12 13 14 Figure 9. Pin Configuration Table 7. Pin Function Descriptions Pin No. 1 Mnemonic RESET Type 1 DI 2 SYNC_IN DI 3 SYNC_OUT DO 4 REGCAPD AO 5 IOVDD P 6 PIN/SPI DI 7 8 DGND CLKSEL P DI 9 DOUT/RDY DO Description Hardware Asynchronous Reset Input. After the device is powered up, it is recommended to reset the device using either the RESET pin or via a software reset. See the Reset section for further details. Synchronization Input. SYNC_IN receives the synchronous signal from SYNC_OUT or from the main controller. SYNC_IN enables synchronization of multiple AD7768-1 devices that require simultaneous sampling. A SYNC_IN pulse is always required when the device configuration changes in any way (for example, if the filter decimation rate changes). Apply SYNC_IN pulses directly after a DRDY pulse occurs. Synchronization Output. SYNC_OUT is a digital output that is synchronous to the MCLK. To initiate this output, write a sync command over the SPI or provide a START signal via the GPIO3 pin. SYNC_OUT can then be connected to the SYNC_IN pin of its own AD7768-1 via an external trace and can then be routed to other AD7768-1 devices locally, ensuring synchronization of devices that share a common MCLK. Digital Low Dropout (LDO) Regulator Output. Decouple this pin to DGND with a 1 F capacitor. For IOVDD 1.8 V, use a 10 F capacitor. Do not use the voltage output from REGCAPD in circuits external to the AD7768-1. Digital Supply. The IOVDD pin sets the logic levels for all interface pins. This pin powers the digital processing via the internal digital LDO. Supply the IOVDD pin with 1.8 V to 3.3 V with respect to DGND. PIN Control/SPI Control. This pin sets the configuration mode of the AD7768-1 to be either pin controlled or controlled via the SPI. Logic 0: control and configuration is pin driven only. Logic 1: control and configuration is over the SPI only. Digital Ground. Clock Selection Pin for the AD7768-1 in PIN Control Mode. When the AD7768-1 is in PIN control mode, the logic level on CLKSEL determines which external clock source the AD7768-1 expects. The low voltage differential signaling (LVDS) clock option is only available in SPI control mode (PIN/SPI = 1). Hold the CLKSEL pin at Logic 0 or tie this pin to DGND in SPI control mode (PIN/SPI = 1). 0 = CMOS clock option. If the CMOS clock is selected, apply the clock signal to the MCLK/XTAL2 pin and connect the XTAL1 pin to DGND. 1 = crystal option. If the crystal option is selected, connect a suitable crystal across the XTAL1 and MCLK/XTAL2 pins. Serial Interface Data Output and Data Ready Signal Combined. This output data pin can be configured as either a DOUT pin only, or through the SPI control mode. The pin function can also include the ready signal (RDY). The ability to program the device to provide a combined DOUT/RDY signal can reduce the number of interface lines in isolated applications. Rev. 0 | Page 17 of 76 AD7768-1 Data Sheet Pin No. 10 11 12 13 Mnemonic SCLK SDI CS XTAL1 Type 1 DI DI DI DI 14 MCLK/XTAL2 DI 15 MODE0/GPIO0 DI/O 16 MODE1/GPIO1 DI/O 17 MODE2/GPIO2 DI/O 18 MODE3/GPIO3 (START) DI/O 19 20 DRDY REGCAPA DO AO 21 AVSS P 22 23 AVDD2 AVDD1 P P 24 REF+ AI 25 26 27 28 REF- AIN- AIN+ VCM AI AI AI AO EPAD (AVSS) P 1 Description Serial Interface Clock. Serial Interface Data Input. Serial Interface Chip Select Input. This pin is active low. Input 1 for Crystal or Connection to an LVDS Clock. When CLKSEL is 0, connect this pin to DGND. See the CLKSEL pin for details on the clock input configuration. Master Clock Signal (MCLK)/External Crystal (XTAL2). XTAL2 connects to the external crystal. The AD7768-1 provides the crystal excitation. LVDS clock: second LVDS input connected to this pin. CMOS clock: operates as MCLK input. CMOS input with logic level of IOVDD/DGND. Pin Control Mode (PIN/SPI = 0): MODE0 pin. The MODE0 to MODE3 pins are the mode select pins for the AD7768-1. SPI Control Mode (PIN/SPI = 1): GPIO0 pin. This pin operates as a general-purpose input/output pin, providing bidirectional input and output, read and write, relative to the IOVDD and DGND supply domain, which are accessed via the SPI and register map. Pin Control Mode (PIN/SPI = 0): MODE1 pin. The MODE0 to MODE3 pins are the mode select pins for the AD7768-1. SPI Control Mode (PIN/SPI = 1): GPIO1 pin. This pin operates as a general-purpose input/output pin, providing bidirectional input and output, read and write, relative to the IOVDD and DGND supply domain, which are accessed via the SPI and register map. Pin Control Mode (PIN/SPI = 0): MODE2 pin. The MODE0 to MODE3 pins are the mode select pins for the AD7768-1. SPI Control Mode (PIN/SPI = 1): GPIO2 pin. This pin operates as a general-purpose input/output pin, providing bidirectional input and output, read and write, relative to the IOVDD and DGND supply domain, which are accessed via the SPI and register map. Pin Control Mode (PIN/SPI = 0): MODE3 pin. The MODE0 to MODE3 pins are the mode select pins for the AD7768-1. SPI Control Mode (PIN/SPI = 1): GPIO3 pin. This pin operates as a general-purpose input/output pin, providing bidirectional input and output, read and write, relative to the IOVDD and DGND supply domain, which are accessed via the SPI and register map. Under SPI control, GPIO3 can be assigned specifically as the START input. This feature has an enable bit in the memory map (Register 0x1D, Bit 3, EN_GPIO_START). Apply START pulses directly after a DRDY pulse occurs. Data Ready. Periodic signal output to signify conversion results are available. Analog LDO Regulator Output. Decouple this pin to AVSS with a 1 F capacitor. Do not use the REGCAPA pin in circuits external to the AD7768-1. Negative Analog Supply. Nominally ground (0 V). The AVSS pin relates to the AVDD1 and AVDD2 supplies. Analog Supply Voltage, 2.0 V to 5.0 V with Respect to AVSS. Analog Supply Voltage, 5.0 V 10% with Respect to AVSS. This supply can run at 3 V in low power mode only. Reference Input Positive Reference. Apply an external reference between REF+ and REF- ranging from AVDD1 to AVSS + 1 V. The device functions with a reference voltage differential in the range from 1 V to |AVDD1 - AVSS|. Reference Input Negative Terminal. The REF- range is from AVSS to AVDD1 - 1 V. Negative Analog Input to the ADC. Positive Analog Input to the ADC. Common-Mode Voltage Output. VCM is set to (AVDD1 - AVSS)/2 by default. Configure VCM with multiple output voltage options via an SPI write. When driving capacitive loads larger than 0.1 F, place a 50 series resistor between VCM and the capacitive load for stability purposes. Negative Analog Supply. Nominally GND (0 V). AVSS relates to the AVDD1 and AVDD2 supplies. DI is digital input, DO is digital output, AO is analog output, P is power, DI/O is digital input or output, and AI is analog input. Rev. 0 | Page 18 of 76 Data Sheet AD7768-1 TYPICAL PERFORMANCE CHARACTERISTICS AVDD1 = 5 V, AVDD2 = 5 V, IOVDD = 1.8 V, VREF = 4.096 V, TA = 25C, low ripple FIR filter, decimation = x32, MCLK= 16.384 MHz, analog input precharge buffers on, and reference precharge buffers on, unless otherwise noted. -40 -60 -60 -80 -100 -120 -80 -100 -120 -140 -140 -160 -160 -180 -180 100 1k FREQUENCY (Hz) 10k 100k -200 16481-111 10 10 Figure 10. FFT, Fast Mode, Low Ripple FIR Filter, -0.25 dBFS 0 -40 -60 -60 -80 -100 -120 -100 -120 -140 -160 -160 -180 -180 1k FREQUENCY (Hz) -200 16481-112 100 10k 10 Figure 11. FFT, Median Mode, Low Ripple FIR Filter, -0.25 dBFS 0 AMPLITUDE (dB) -60 -80 -100 -120 -80 -100 -120 -140 -140 -160 -160 -180 -180 1k FREQUENCY (Hz) 10k 16481-113 AMPLITUDE (dB) -40 100 10k SNR = 111.2dB THD = -119.8dB -20 -60 10 1k FREQUENCY (Hz) 0 -40 -200 100 Figure 14. FFT, Median Mode, Sinc5 Filter, -0.25 dBFS SNR = 107.9dB THD = -119dB -20 100k -80 -140 10 10k SNR = 111dB THD = -119.1dB -20 AMPLITUDE (dB) AMPLITUDE (dB) 0 -40 -200 1k FREQUENCY (Hz) Figure 13. FFT, Fast Mode, Sinc5 Filter, -0.25 dBFS SNR = 107.8dB THD = -118.9dB -20 100 16481-114 AMPLITUDE (dB) -40 -200 SNR = 110.7dB THD = -120.2dB -20 16481-115 -20 AMPLITUDE (dB) 0 SNR = 107.7dB THD = -120.3dB Figure 12. FFT, Low Power Mode, Low Ripple FIR Filter, -0.25 dBFS -200 10 100 1k FREQUENCY (Hz) 10k Figure 15. FFT, Low Power Mode, Sinc5 Filter, -0.25 dBFS Rev. 0 | Page 19 of 76 16481-116 0 AD7768-1 Data Sheet 0 10000 SNR = 109dBFS THD = -135dB -20 NUMBER OF OCCURRENCES -40 -60 -80 -100 -120 -140 -160 -180 8000 7000 6000 5000 4000 3000 2000 1000 10 100 1k FREQUENCY (Hz) 10k 100k 0 16481-117 -200 -45 -35 -25 -15 -5 0 25 35 DYNAMIC RANGE = 111.8dB SNR = 113dB THD = -120dB -20 15 Figure 19. Shorted Input Noise, Sinc5 Filter, Three Power Modes, N = 32,768 Figure 16. FFT, Fast Mode, Low Ripple FIR Filter, -10 dBFS 0 5 SHORTED INPUT NOISE (V) 16481-120 AMPLITUDE (dB) FAST MEDIAN LOW POWER 9000 -50 -40 AMPLITUDE (dB) AMPLITUDE (dB) -60 -80 -100 -120 -100 -150 -140 -200 -160 -180 2k FREQUENCY (Hz) 20k -250 1 Figure 17. FFT, Fast Mode, Low Ripple FIR Filter, Decimate by 128, -0.1 dBFS 100 FREQUENCY (Hz) 1k Figure 20. FFT, One Shot Mode, Sinc5 Filter, Median Power Mode, 10 kSPS ODR, Shorted Inputs 21 7000 FAST MEDIAN LOW POWER 6000 19 17 5000 RMS NOISE (V) 4000 3000 2000 15 LOW RIPPLE FIR SINC5 SINC3 13 11 9 1000 0 -50 -40 -30 -20 -10 0 10 20 30 SHORTED INPUT NOISE (V) 40 50 16481-119 7 Figure 18. Shorted Input Noise, Low Ripple FIR Filter, Three Power Modes, N = 32,768 Rev. 0 | Page 20 of 76 5 -40 -20 0 20 40 60 TEMPERATURE (C) 80 100 120 16481-123 NUMBER OF OCCURRENCES 10 16481-122 200 20 16481-118 -200 Figure 21. RMS Noise vs. Temperature, Three Filter Types, Fast Mode Data Sheet AD7768-1 2.0 2.0 1.5 1.5 1.0 INL ERROR (ppm) INL ERROR (ppm) 1.0 0.5 0 -0.5 -1.0 0.5 0 -0.5 -2.5 -VREF -1.0 0 +VREF INPUT VOLTAGE (V) -1.5 -5 16481-124 Figure 22. INL Error vs. Input Voltage for Various Voltage Reference (VREF) Levels, Fast Mode -1 0 1 2 3 4 5 0.6 0.4 1.0 0.2 INL ERROR (ppm) INL ERROR (ppm) -2 Figure 25. INL Error vs. Input Voltage for Various Temperatures, Fast Mode 1.5 0.5 0 -0.5 0 -0.2 -0.4 -1.0 VREF = 5.000V VREF = 4.096V VREF = 2.500V FULL SCALE (-4.015V TO +4.015V) HALF SCALE (-2.008V TO +2.008V) 1/8 SCALE (-0.502V TO +0.502V) -0.6 0 +VREF INPUT VOLTAGE (V) -0.8 -1.0 16481-125 -2.0 -VREF -3 INPUT VOLTAGE (V) 2.0 -1.5 -4 -0.8 -0.6 -0.4 -0.2 0 0.2 0.4 0.6 0.8 1.0 INPUT VOLTAGE (VIN/VIN MAXIMUM) Figure 23. INL Error vs. Input Voltage for Various Voltage Reference (VREF) Levels, Median Mode 16481-128 -2.0 VREF = 5.000V VREF = 4.096V VREF = 2.500V 16481-127 +125C +85C +25C -20C -40C -1.5 Figure 26. INL Error vs. Input Voltage, Full-Scale, Half Scale, and 1/8 Scale Inputs, 4.096 V Reference 0.8 0 VREF = 5.000V VREF = 4.096V VREF = 2.500V 0.6 -15 THD THD + N -30 THD AND THD + N (dB) INL ERROR (ppm) 0.4 0.2 0 -0.2 -45 -60 -75 -90 -105 -0.4 INPUT VOLTAGE (V) +VREF Figure 24. INL Error vs. Input Voltage for Various Voltage Reference (VREF) Levels, Low Power Mode Rev. 0 | Page 21 of 76 -135 10 100 1k 10k INPUT FREQUENCY (Hz) Figure 27. THD and THD + N vs. Input Frequency, Fast Mode, Low Ripple FIR Filter 16481-130 0 16481-126 -0.6 -VREF -120 AD7768-1 Data Sheet 0 NUMBER OF OCCURRENCES -40 THD AND THD + N (dB) 12 LOW POWER THD LOW POWER THD + N MEDIAN THD MEDIAN THD + N FAST THD FAST THD + N -20 -60 -80 -100 -120 -140 N = 50 +125C +25C -40C 10 8 6 4 2 -120 -100 -80 -60 -40 0 -20 INPUT AMPLITUDE (dBFS) 0 -120 16481-131 -180 -140 40 60 120 14 LOW POWER THD LOW POWER THD + N MEDIAN THD MEDIAN THD + N FAST THD FAST THD + N N = 50 12 NUMBER OF OCCURRENCES -60 -80 -100 -120 -140 10 8 6 4 2 -160 -120 -100 -80 -60 -40 -20 0 INPUT AMPLITUDE (dBFS) 0 16481-132 -180 -140 10 15 20 25 30 35 40 45 50 55 60 65 70 75 80 85 90 95 100 OFFSET ERROR DRIFT (nV/C) 16481-202 THD AND THD + N (dB) 0 Figure 31. Offset Error Distribution, Fast Mode 0 -40 -40 OFFSET ERROR (V) Figure 28. THD and THD + N vs. Input Amplitude, Low Ripple FIR Filter -20 -80 16481-033 -160 Figure 32. Offset Error Drift, Fast Mode Figure 29 THD and THD + N vs. Input Amplitude, Sinc5 Filter -80 N = 50 +125C +25C -40C 18 MEDIAN POWER MODE NUMBER OF OCCURRENCES LOW POWER MODE -100 FAST POWER MODE -110 -120 15 12 9 6 8.50 8.19 5.00 16481-133 fMOD FREQUENCY (MHz) 4.25 4.09 2.50 1.25 1.06 1.02 0.75 0 -80 0.62 -140 0.37 3 0.31 -130 0.09 THD AND THD + N (dB) -90 Figure 30. THD and THD + N vs. fMOD Frequency, Low Ripple FIR Filter Rev. 0 | Page 22 of 76 -60 -40 -20 0 GAIN ERROR (ppm) Figure 33. Gain Error Distribution, Reference Buffers Off 20 16481-035 THD THD + N Data Sheet 20 30 N = 50 +125C +25C -40C 25 0 FAST MEDIAN LOW POWER MODE -20 -40 AMPLITUDE (dB) NUMBER OF OCCURRENCES AD7768-1 20 15 10 -60 -80 -100 -120 -140 -160 5 -180 -150 -120 -90 -60 -30 -200 -0.1 16481-036 0 0 GAIN ERROR (ppm) 0.1 0.3 0.5 0.7 0.9 1.1 1.3 1.5 NORMALIZED INPUT FREQUENCY (fIN/fODR) Figure 34. Gain Error Distribution, Reference Buffers On 16481-139 -180 Figure 37. Low Ripple FIR Filter Profile, Amplitude vs. Normalized Input Frequency (fIN/fODR) 9 0 7 -40 6 -60 5 4 3 -100 -120 GAIN ERROR DRIFT (ppm/C) 16481-203 0.60 0.55 0.50 3 2 AIN (V) 1 0 -1 -2 -3 -4 16481-138 7.782 6.963 6.144 5.324 4.505 3.942 3.328 2.713 2.099 1.484 1.024 0.826 0.628 0.431 0.233 4 5 6 16384000 15360000 14336000 13312000 12288000 11264000 10240000 9216000 8192000 7168000 6144000 5120000 4096000 3072000 2048000 1024000 0 DOUT AIN 0 0.036 3 4.0 3.5 3.0 2.5 2.0 1.5 1.0 0.5 0 -0.5 -1.0 -1.5 -2.0 -2.5 -3.0 -3.5 -4.0 -5 fMOD (MHz) 2 Figure 38. Sinc5 Filter Profile, Amplitude vs. Normalized Input Frequency (fIN/fODR) AIN PRECHARGE BUFFER OFF, LOW POWER AIN PRECHARGE BUFFER OFF, FAST POWER AIN PRECHARGE BUFFER OFF, MEDIAN POWER AIN PRECHARGE BUFFER ON, LOW POWER AIN PRECHARGE BUFFER ON, FAST POWER AIN PRECHARGE BUFFER ON, MEDIAN POWER 4 1 NORMALIZED INPUT FREQUENCY (fIN/fODR) 5 10 15 20 25 30 35 40 45 50 SAMPLES Figure 39. Step Response (AIN and DOUT) vs. Samples, Sinc5 Filter Figure 36. Gain Error vs. fMOD Rev. 0 | Page 23 of 76 DOUT (Code) 5 0 16481-141 0.45 0.40 0.35 0.30 -0.05 0.25 -180 0.20 0 0.15 -160 0.10 1 0 -140 0.05 2 Figure 35. Gain Error Drift Reference Buffers Off GAIN ERROR (ppm) -80 16481-140 AMPLITUDE (dB) 8 -20 -0.10 NUMBER OF OCCURRENCES N = 50 0.005 FAST MEDIAN LOW POWER MODE 0.001 AIN (V) -0.001 -0.003 0 0 0.05 0.10 0.15 0.25 0.20 0.30 0.35 0.40 0.45 NORMALIZED INPUT FREQUENCY (fIN/fODR) 51 102 153 204 12 15 18 21 60 16384000 15360000 14336000 13312000 12288000 11264000 10240000 9216000 8192000 7168000 6144000 5120000 4096000 3072000 2048000 DOUT AIN 1024000 0 255 DIFFERENTIAL COMPONENT, PRECHARGE OFF (A/V) DOUT (Code) ANALOG INPUT CURRENT (A) 50 40 30 20 COMMON-MODE COMPONENT, PRECHARGE OFF (A/V) 10 0 -10 TOTAL CURRENT, PRECHARGE BUFFERS ON (A) -20 SAMPLES -30 -40 125 25 TEMPERATURE (C) Figure 44. Analog Input Current vs. Temperature, Analog Input Precharge Buffers On/Off Figure 41. Step Response (AIN and DOUT) vs. Samples, Low Ripple Filter 0 14 -20 12 NUMBER OF OCCURRENCES VCM = (AVDD1 - AVSS)/2 N = 50 -40 -60 -80 -100 -120 +125C +25C -40C 10 8 6 4 2.499600 2.499575 2.499550 2.499525 2.499500 2.499475 2.499450 16481-046 VCM (V) Figure 42. Sinc3 Filter Profile with 50 Hz and 60 Hz Rejection Enabled, Amplitude vs. Input Frequency, 50 Hz ODR, Decimation x163,840 2.499425 2.499400 2.499375 2.499350 2.499325 2.499300 0 2.499275 250 2.499250 FREQUENCY (Hz) 200 2.499225 150 2.499200 100 2.499175 50 2.499150 0 16481-144 -160 2.499125 2 -140 2.499100 AMPLITUDE (dB) AIN (V) 9 Figure 43. Step Response (AIN and DOUT) vs. Samples, Sinc3 Filter 16481-143 0 6 SAMPLES Figure 40. Low Ripple FIR Filter Ripple, Amplitude vs. Normalized Input Frequency (fIN/fODR) 4.0 3.5 3.0 2.5 2.0 1.5 1.0 0.5 0 -0.5 -1.0 -1.5 -2.0 -2.5 -3.0 -3.5 -4.0 3 16481-142 -0.005 16384000 15360000 14336000 13312000 12288000 11264000 10240000 9216000 8192000 7168000 6144000 5120000 4096000 3072000 2048000 1024000 0 DOUT AIN 16481-146 AMPLITUDE (dB) 0.003 4.0 3.5 3.0 2.5 2.0 1.5 1.0 0.5 0 -0.5 -1.0 -1.5 -2.0 -2.5 -3.0 -3.5 -4.0 DOUT (Code) Data Sheet 16481-145 AD7768-1 Figure 45. VCM Output Voltage Distribution, VCM = (AVDD1 - AVSS)/2 Rev. 0 | Page 24 of 76 Data Sheet AD7768-1 7 6 VCM = 2.5V, 1.65V, 0.9V N = 50 +125C +25C -40C 5 SUPPLY CURRENT (mA) 5 4 3 2 3 2 1 1.0050 NORMALIZED VCM (MEASURED/NOMINAL) 0 -40 16481-047 1.0040 1.0030 1.0020 1.0010 1.0000 0.9990 0.9980 0.9970 0.9960 0.9950 0.9940 0.9930 0.9920 1 0 4 85 105 125 Figure 49. Supply Current vs. Temperature, AVDD2 78.0 4.0 FAST, SINC5 3.5 SUPPLY CURRENT (mA) 77.5 77.0 76.5 76.0 FAST, SINC3 2.5 MEDIAN, SINC5 2.0 MEDIAN, SINC3 1.5 LOW POWER, SINC5 1.0 25 125 TEMPERATURE (C) 0 -40 -20 25 85 105 125 TEMPERATURE (C) 16481-050 0.5 75.0 -40 Figure 50. Supply Current vs. Temperature, IOVDD, Sinc3 and Sinc5 Filter Figure 47. Reference Input Current vs. Temperature, Reference Precharge Buffers Off 10 9 FAST MEDIAN LOW POWER MODE 9 8 SUPPLY CURRENT (mA) 7 6 5 4 3 2 7 FAST MEDIAN LOW POWER MODE 6 5 4 3 2 1 0 0 -40 -20 25 85 105 125 TEMPERATURE (C) Figure 48. Supply Current vs. Temperature, AVDD1 16481-048 1 -40 -20 25 85 TEMPERATURE (C) 105 125 16481-051 8 3.0 LOW POWER, SINC3 75.5 16481-149 REFERENCE INPUT CURRENT (A/V) 25 TEMPERATURE (C) Figure 46. VCM Output Voltage Distribution, VCM = 2.5 V, 1.65 V, 0.9 V SUPPLY CURRENT (mA) -20 16481-049 NUMBER OF OCCURRENCES 6 FAST MEDIAN LOW POWER MODE Figure 51. Supply Current vs. Temperature, IOVDD, Low Ripple FIR Filter Rev. 0 | Page 25 of 76 Data Sheet 1400 1000 AC CMRR (dB) POWER CONSUMPTION (W) 1200 STANDBY, MCLK INACTIVE STANDBY, MCLK ACTIVE POWER-DOWN 800 600 400 0 -40 -20 0 20 40 60 80 100 120 TEMPERATURE (C) 16481-154 200 Figure 52. Power Consumption, Standby and Power-Down vs. Temperature, AVDD1, AVDD2 = 5 V, IOVDD = 1.8 V 30 CONTINUOUS CONVERSION, MCLK = 16.384MHz, DECIMATE BY 32 TO 1024 20 15 10 5 0 100 PERIODIC CONVERSION, MCLK = 16.384MHz, DECIMATE BY 32 CONTINUOUS CONVERSION, MCLK = 16.384MHz TO 1.5MHz, DECIMATE BY 32 1k 10k 100k 1M ODR (Hz) 16481-155 POWER CONSUMPTION (mW) 25 Figure 53. Power Consumption, Conversion Modes vs. ODR, Median Power Mode, Sinc5 Filter Rev. 0 | Page 26 of 76 0 -10 -20 -30 -40 -50 -60 -70 -80 -90 -100 -110 -120 -130 -140 -150 -160 -170 -180 10 100 1k 10k 100k 1M INPUT FREQUENCY (Hz) Figure 54. AC CMRR vs. Input Frequency 10M 16481-054 AD7768-1 Data Sheet AD7768-1 TERMINOLOGY Common-Mode Rejection Ratio (CMRR) CMRR is the ratio of the power in the ADC output at full-scale frequency, f, to the power of a 100 mV p-p sine wave applied to the common-mode voltage of AIN+ and AIN- at frequency, fS. Gain Error Drift Gain error drift is the ratio of the gain error change due to a temperature change of 1C and the full-scale range (2N). It is expressed in parts per million. Least Significant Bit (LSB) LSB is the smallest increment that a converter can represent. For a fully differential input ADC with N bits of resolution, the LSB expressed in volts is CMRR (dB) = 10 log(Pf/PfS) where: Pf is the power at frequency, f, in the ADC output. PfS is the power at frequency, fS, in the ADC output. Integral Nonlinearity (INL) Error INL error refers to the deviation of each individual code from a line drawn from negative full scale through positive full scale. The point used as negative full scale occurs 1/2 LSB before the first code transition. Positive full scale is defined as a level 11/2 LSB beyond the last code transition. The deviation is measured from the middle of each code to the true straight line. Dynamic Range Dynamic range is the ratio of the rms value of the full scale to the rms noise measured when input pins are shorted together. The value for dynamic range is expressed in decibels. Intermodulation Distortion (IMD) With inputs consisting of sine waves at two frequencies, fa and fb, any active device with nonlinearities creates distortion products at sum and difference frequencies of mfa and nfb, where m, n = 0, 1, 2, 3, and so on. Intermodulation distortion terms are those for which neither m nor n are equal to 0. For example, the secondorder terms include (fa + fb) and (fa - fb), and the third-order terms include (2fa + fb), (2fa - fb), (fa + 2fb), and (fa - 2fb). The AD7768-1 is tested using the Canadian Collision Industry Forum (CCIF) standard, where two input frequencies near the top end of the input bandwidth are used. In this case, the secondorder terms are usually distanced in frequency from the original sine waves, and the third-order terms are usually at a frequency close to the input frequencies. As a result, the second- and thirdorder terms are specified separately. The calculation of the intermodulation distortion is as per the THD specification, where it is the ratio of the rms sum of the individual distortion products to the rms amplitude of the sum of the fundamentals expressed in decibels. Gain Error The first transition (from 100 ... 000 to 100 ...001) occurs at a level 1/2 LSB above nominal negative full scale (-4.0959375 V for the 4.096 V range). The last transition (from 011 ... 110 to 011 ... 111) occurs for an analog voltage 11/2 LSB below the nominal full scale (+4.0959375 V for the 4.096 V range). The gain error is the deviation of the difference between the actual level of the last transition and the actual level of the first transition from the difference between the ideal levels. LSB (V) = VIN p-p/2N Power Supply Rejection Ratio (PSRR) Variations in power supply affect the full-scale transition but not the linearity of the converter. PSRR is the maximum change in the full-scale transition point due to a change in power supply voltage from the nominal value. Signal-to-Noise Ratio (SNR) SNR is the ratio of the rms value of the actual input signal to the rms sum of all other spectral components below the Nyquist frequency, excluding harmonics and dc. The value for SNR is expressed in decibels. Signal-to-(Noise-and-Distortion) Ratio (SINAD) SINAD is the ratio of the rms value of the actual input signal to the rms sum of all other spectral components below the Nyquist frequency, including harmonics but excluding dc. The value for SINAD is expressed in decibels. Spurious-Free Dynamic Range (SFDR) SFDR is the difference, in decibels relative to the carrier (dBc), between the rms amplitude of the input signal and the peak spurious signal (including harmonics). Total Harmonic Distortion (THD) THD is the ratio of the rms sum of the first five harmonic components to the rms value of a full-scale input signal and is expressed in decibels. Offset Error Offset error is the difference between the ideal midscale input voltage (0 V) and the actual voltage producing the midscale output code. Offset Error Drift Offset error drift is the ratio of the zero error change due to a temperature change of 1C and the full-scale code range (2N). It is expressed in nV/C. Rev. 0 | Page 27 of 76 AD7768-1 Data Sheet THEORY OF OPERATION The AD7768-1 is a low noise, wide bandwidth, 24-bit - ADC. The AD7768-1 uses a - modulator with a clock running at fMOD. The modulator samples the inputs at a rate of 2 x fMOD to convert the analog input into an equivalent digital representation. These samples represent a quantized version of the analog input signal. The - conversion technique is an oversampled architecture. This oversampled approach spreads the quantization noise over a wide frequency band (see Figure 55). To reduce the quantization noise in the signal band, the high-order modulator shapes the noise spectrum so that most of the noise energy is shifted out of the band of interest (see Figure 56). The digital filter that follows the modulator removes the large out of band quantization noise (see Figure 57). Figure 55. - ADC Quantization Noise (Linear Scale X-Axis) fMOD/2 16481-012 NOISE SHAPING BAND OF INTEREST Figure 58 shows the clock tree from the MCLK input to the modulator and the digital filter. There are divider settings for MCLK. A divider in conjunction with the power mode and digital filter decimation settings are important when operating the AD7768-1. Figure 56. - ADC Noise Shaping (Linear Scale X-Axis) MCLK DIGITAL FILTER CUTOFF FREQUENCY AIN+ Figure 57. - ADC Digital Filter Cutoff Frequency (Linear Scale X-Axis) For further information on the basic and advanced concepts of - ADCs, see the MT-022 Tutorial and the MT-023 Tutorial. Digital filtering has advantages over analog filtering. First, digital filtering is insensitive to component tolerances and the variation of component parameters over time and temperature. Because digital filtering on the AD7768-1 occurs after the analog-to-digital conversion, the device can remove some of the noise injected during the conversion process. Analog filtering cannot remove noise injected during conversion. Second, the digital filter combines low pass-band ripple with a steep roll-off and high stop-band attenuation while also maintaining a linear phase response, which is difficult to achieve in an analog filter implementation. CONTROL AND SPI INTERFACE DRDY CS SCLK DOUT/RDY SDI ADC MODULATOR DIGITAL FILTER POWER MODES: FAST MEDIAN LOW POWER DECIMATION RATES WB = x32, x64, x128, x256, x512, x1024 SINC5 = x8, x16, x32, x64, x128, x256, x512, x1024 SINC3: SPI PROGRAMMABLE, 50Hz AND 60Hz AIN- 16481-013 BAND OF INTEREST fMOD/2 MCLK_DIV: MCLK/2 MCLK/4 MCLK/16 DENOTED IN GRAY MEANS THIS OPTION IS AVAILABLE IN PIN MODE. Figure 58. Sampling Structure Defined by the MCLK and MCLK_DIV Settings Table 8. Decimation Rate Options Filter Option Low Ripple FIR Sinc5 Sinc3 Available Decimation Rates SPI Control Mode Pin Control Mode x32, x64, x128, x256, x32, x64 x512, x1024 x8, x16, x32, x64, x128, x8, x32, x64 x256, x512, x1024 Programmable 50 Hz and 60 Hz output only, based decimation rate on a 16.384 MHz MCLK To determine fMOD, select one of four clock divider settings: MCLK/2, MCLK/4, MCLK/8, or MCLK/16. Rev. 0 | Page 28 of 76 16481-014 16481-011 fMOD/2 The AD7768-1 core ADC receives a master clock signal (MCLK). The MCLK signal can be sourced from one of four options: a CMOS clock, a crystal connected between the XTAL1 and XTAL2 pins, an LVDS signal, and the internal clock. The MCLK signal received by the AD7768-1 defines the modulator clock rate (fMOD) and, in turn, the sampling frequency of the modulator of 2 x fMOD. The AD7768-1 has the ability to scale power consumption vs. the input bandwidth or noise desired. The user controls two parameters to achieve this scaling: MCLK division and power mode. When combined, these two settings determine the clock frequency of the modulator (fMOD) and the bias current supplied to the modulator. The power mode (fast, median, or low power) sets the noise, speed capability, and current consumption of the modulator. The power mode is the dominant control for scaling the power consumption of the ADC. QUANTIZATION NOISE BAND OF INTEREST CLOCKING, SAMPLING TREE, AND POWER SCALING Data Sheet AD7768-1 Although the MCLK division and power modes are independent settings, there are restrictions in valid combinations. A valid range of modulator frequencies exists for each power mode. Table 9 describes this recommended range, which allows the device to achieve the best performance while also minimizing power consumption. The AD7768-1 specifications do not cover the performance and function beyond the maximum fMOD for a given power mode. For example, in fast mode, to maximize the ODR or input bandwidth, an MCLK rate of 16.384 MHz is required. Select an MCLK divider (MCLK_DIV) equal to 2 for a modulator frequency of 8.192 MHz. Configuration A To maximize the dynamic range, use the following settings: * * * * * Table 9. Recommended fMOD Range for Each Power Mode Power Mode Low Power Median Fast approximately 25 kHz with the wideband filter, setting the ODR of the AD7768-1 to 62.5 kHz. Because of the low MCLK frequency available and the system power budget, median power mode is used. In median power mode, to achieve this 25 kHz input bandwidth, set the MCLK division and decimation ratio to balance using two configurations. This flexibility is possible only in SPI control mode. Recommended fMOD Range (MHz) 0.038 to 1.024 1.024 to 4.096 4.096 to 8.192 Control of the settings for the power mode and the modulator frequency differ in PIN control mode vs. SPI control mode. In SPI control mode, the user can program the power mode and MCLK_DIV independently. Independent selection of the power mode and MCLK_DIV allows full freedom in the MCLK speed selection to achieve a target modulator frequency, which can also result in a small power saving. For example, if the power mode is low power, it is more power efficient to use MCLK = 2.048 MHz with MCLK_DIV = 2 than MCLK = 16.384 MHz with MCLK_DIV = 16. Both options are valid selections and result in an fMOD frequency of 1.024 MHz. In PIN control mode, the MODEx pins determine the power mode and modulator frequency. The modulator frequency tracks the power mode, which means that fMOD is fixed at MCLK/16 for low power mode, MCLK/4 for median mode, and MCLK/2 for fast mode. In PIN control mode, the MODEx pins are also used to select the filter type and decimation rate. Power vs. Noise Performance Optimization Depending on the bandwidth of interest for the measurement, the user can choose a strategy of either lowest current consumption or highest resolution. This choice is due to an overlap in the coverage of each power mode. There are different ways to achieve the same ODR. Using a lower MCLK frequency in tandem with a lower decimation rate allows the user to achieve the same data rate as using a higher MCLK frequency with a higher decimation. Lower power can be achieved by using lower modulator clock frequencies. Conversely, to achieve the highest resolution, use higher modulator clock frequencies and maximize the amount of oversampling. MCLK = 8 MHz Median power fMOD = MCLK/2 Decimation = x64 (digital filter setting) ODR = 62.5 kHz This configuration maximizes the available decimation rate (or oversampling ratio) for the bandwidth required and the MCLK rate available. The decimation averages the noise from the modulator, maximizing the dynamic range. Configuration B To minimize power, use the following settings: * MCLK = 8 MHz * Median power * fMOD = MCLK/4 * Decimation = x32 (digital filter setting) * ODR = 62.5 kHz This configuration reduces the clocking speed of the modulator and the digital filter. Although the fMOD frequency is within the recommended frequency range in both cases, Configuration B saves nearly 5 mW of power compared to Configuration A. The trade-off in the case of Configuration B is that the digital filter must run at a 2x lower decimation rate. This 2x reduction in decimation rate (or oversampling ratio) results in a 3 dB reduction in the dynamic range vs. Configuration A. NOISE PERFORMANCE AND RESOLUTION Table 10 and Table 11 show the noise performance for the low ripple FIR and sinc5 digital filters of the AD7768-1 for various ODR values and power modes. The specified noise values and dynamic ranges are typical for the bipolar input range with an external 4.096 V reference (VREF). The rms noise is measured with shorted analog inputs, which are driven to (AVDD1 - AVSS)/2 using the on-board VCM buffer output. The ratio of the rms shorted input noise to the rms full-scale input signal range calculates the dynamic range. Dynamic Range (dB) = 20log10((2 x VREF/22)/(RMS Noise) The LSB size for a 4.096 V reference is 488 nV and is calculated as follows: Example of Power vs. Noise Performance Optimization Consider a system constraint with a maximum available MCLK of 8 MHz. The system is targeting a measurement bandwidth of Rev. 0 | Page 29 of 76 LSB (V) = (2 x VREF)/224 AD7768-1 Data Sheet Table 10. Low Ripple FIR Filter Noise for Performance vs. ODR (VREF = 4.096 V) ODR (kSPS) Fast Mode 256 128 64 32 16 8 Median Mode 128 64 32 16 8 4 Low Power Mode 32 16 8 4 2 1 -3 dB Bandwidth (kHz) Shorted Input Dynamic Range (dB) RMS Noise (V) 110.8 55.4 27.7 13.9 6.9 3.5 108.43 111.96 115.15 118.23 121.20 124.16 10.98 7.31 5.06 3.55 2.52 1.79 55.4 27.7 13.9 6.9 3.5 1.7 108.45 111.89 115.22 118.22 121.23 124.17 10.94 7.37 5.02 3.55 2.51 1.79 13.9 6.9 3.5 1.7 0.87 0.43 108.54 112.12 115.30 118.31 121.22 124.33 10.84 7.17 4.97 3.52 2.52 1.76 Table 11. Sinc5 Filter Noise for Performance vs. ODR (VREF = 4.096 V) ODR (kSPS) Fast Mode 1024 (16-Bit Output Only) 512 256 128 64 32 16 8 Median Mode 512 256 128 64 32 16 8 4 Low Power Mode 128 64 32 16 8 4 2 1 -3 dB Bandwidth (kHz) Shorted Input Dynamic Range (dB) RMS Noise (V) 208.896 104.448 52.224 26.112 13.056 6.528 3.264 1.632 92.93 107.32 111.57 115.30 118.29 121.27 124.15 127.16 65.39 12.46 7.64 4.97 3.53 2.50 1.80 1.27 104.448 52.224 26.112 13.056 6.528 3.264 1.632 0.816 92.56 107.88 112.06 115.22 118.46 121.34 124.34 127.20 68.20 11.69 7.22 5.02 3.46 2.48 1.76 1.26 26.112 13.056 6.528 3.264 1.632 0.816 0.408 0.204 92.41 107.82 112.15 115.37 118.35 121.27 124.24 127.28 69.39 11.77 7.15 4.93 3.50 2.50 1.78 1.25 Rev. 0 | Page 30 of 76 Data Sheet AD7768-1 CORE CONVERTER Figure 60 shows a top level implementation of the core signal chain. The - modulator oversamples the analog input and passes the digital representation to the digital filter block. The data is filtered, scaled for gain and offset (depending on the user settings), and then output on the SPI interface. The AD7768-1 can use up to a 5 V reference and converts the differential voltage between the analog inputs (AIN+ and AIN-) to a digital output. The analog inputs can be configured as either differential or pseudo differential inputs. As a pseudo differential input, either AIN+ or AIN- can be connected to a constant input voltage (such as 0 V, AVSS, or another reference voltage). The ADC converts the voltage difference between the analog input pins to a digital code on the output. Using a common-mode voltage of (AVDD1 - AVSS)/2 for the analog inputs, AIN+ and AIN-, maximizes the ADC input range. The 24-bit conversion result is in MSB first, twos complement format. Figure 59 shows the ideal transfer functions for the AD7768-1. 011 ... 111 011 ... 110 011 ... 101 100 ... 010 100 ... 001 100 ... 000 -FS -FS + 1LSB +FS - 1LSB +FS - 1.5LSB -FS + 0.5LSB ANALOG INPUT Figure 59. ADC Ideal Transfer Functions (FS is Full-Scale) Table 12. Output Codes and Ideal Input Voltages Description FS - 1 LSB Midscale + 1 LSB Midscale Midscale - 1 LSB -FS + 1 LSB -FS Analog Input (AIN+ - AIN-), VREF = 4.096 V +4.095999512 V +488 nV 0V -488 nV -4.095999512 V -4.096 V Digital Output Code, Twos Complement (Hex) 0x7FFFFF 0x000001 0x000000 0xFFFFFF 0x800001 0x800000 ADR440 TO ADR445 ADR4520 TO ADR4550 DGND 2.2V TO 5V 1.8V TO 3.3V AVDD2 REGCAPA REGCAPD IOVDD AD7768-1 /2 VCM REFERENCE BUFFERS AIN+ POWER SCALABLE - ADC AIN- AVSS MCLK/XTAL2 XTAL1 SYNC_OUT RESET SINC5 LOW LATENCY FILTER SINC3 FILTER ENABLING 50Hz/60Hz REJECTION PRECHARGE BUFFERS SYNC_IN 1.8V LDO WIDEBAND LOW RIPPLE FILTER +5V ADA4896-2, ADA4940-1, ADA4807-2, ADA4805-2, LTC6363, LTC6362 1.8V LDO CLKSEL ADC DATA SERIAL INTERFACE CONTROL BLOCK MODE3 TO MODE0 (GPIO3 TO GPIO0) PIN/SPI Figure 60. AD7768-1 Top Level Core Signal Chain and Control Rev. 0 | Page 31 of 76 DRDY CS DOUT/RDY SDI SCLK ISO DSP FPGA MICRO CLOCK SOURCE 16481-016 5.0V AVDD1 REF+ REF- 16481-015 ADC CODE (TWOS COMPLEMENT) ADC Core and Signal Chain AD7768-1 Data Sheet Analog Inputs and Precharge Buffering Figure 61 shows the analog front end of the AD7768-1. Protection diodes that protect the ADC from overvoltage and ESD events are shown on the signal path. An internal precharge amplifier that eases the driving requirement of the external buffer can drive the ADC internal sampling capacitors, shown as CS1 and CS2. The precharge amplifier charges the switched sampling capacitors for the initial part of the sampling period. The bypass switches, BPS+ and BPS-, switch out the precharge buffer. The external amplifier then drives the input capacitors for the remainder of the sampling period to fulfill the fine settling required on the input. As a result, the precharge buffer does not add noise to the conversion result, but allows lower power and lower bandwidth driver amplifiers to be used to drive the AD7768-1. The precharge buffer amplifier stage reduces the input current by a factor of 8x. Full settling of the analog inputs to the ADC requires the use of an external amplifier. Pair amplifiers, such as the ADA4805-2 for low power mode, the ADA4807-2 or ADA4940-1 for median mode, and the ADA4807-2 or ADA4896-2 for fast mode, can be used with the AD7768-1. The system can operate from a single 5 V rail if the ADA4940-1 is used with a 4.096 V reference to give the amplifier sufficient headroom and footroom to achieve the best distortion performance from the amplifier. Running the AD7768-1 in median and low power modes or reducing the MCLK rate reduces the load and speed requirements of the amplifier. Therefore, lower power amplifiers can be paired with the analog inputs to achieve optimal signal chain efficiency. 400 300 200 BPS+ 100 AIN (A) AVDD1 PHI 0 AIN+ CS1 PHI 1 0 -100 AVSS -200 PHI 1 CS2 -300 16481-017 0 Figure 61. Analog Front End of the AD7768-1 The precharge buffers can be turned on or off using a register write. In PIN control mode, the precharge buffers are enabled by default for optimum performance. When the precharge analog input buffers are disabled, the analog input current is sourced from the analog input source. Two components calculate the unbuffered analog input current: the differential input voltage on the analog input pair and the analog input voltage with respect to AVSS. The analog input current scales linearly with the modulator clock rate. For MCLK = 16 MHz and MCLK/2 in fast power mode, the differential input current is ~53 A/V and the current with respect to ground is ~17 A/V. 1.0 1.5 2.0 2.5 3.0 INPUT VOLTAGE (VDIFF) 3.5 4.0 0 -5 -10 -15 -20 -25 For example, if the precharge buffers are off, AIN+ = 5 V and AIN- = 0 V. AIN+ = 5 V x 53 A/V + 5 V x 17 A/V = 350 A 0.5 Figure 62. Analog Input Current (AIN) vs. Input Voltage, Analog Input Precharge Buffer Off, VCM = 2.5 V, fMOD = 8.192 MHz AIN (A) AVSS UNBUFFERED AIN+ UNBUFFERED AIN- -400 16481-018 PHI 0 AIN- PRECHARGE BUFFERED AIN+ PRECHARGE BUFFERED AIN- -30 0 0.5 1.0 1.5 2.0 2.5 3.0 INPUT VOLTAGE (VDIFF) 3.5 4.0 16481-019 BPS- AVDD1 Figure 63. Analog Input Current (AIN) vs. Input Voltage, Analog Input Precharge Buffer On, VCM = 2.5 V, fMOD = 8.192 MHz AIN- = 5 V x 53 A/V + 0 V x 17 A/V = - 265 A When the precharge buffers are enabled, the absolute voltage with respect to AVSS determines the majority of the current. The worst case input current is -25 A, measured when the analog input is close to either the AVDD1 or AVSS rails. The analog input current scales with the MCLK frequency and device power mode (see Figure 62 and Figure 63). Rev. 0 | Page 32 of 76 Data Sheet AD7768-1 The AD7768-1 provides a buffered common-mode voltage output on the VCM pin. This buffer can bias analog input signals. By incorporating this buffer into the ADC, the AD7768-1 reduces component count and board space. In PIN control mode, the VCM potential is fixed to (AVDD1 - AVSS)/2 and is on by default. In SPI mode, the VCM potential is configured using the ANALOG2 register (Register 0x17). The output can be enabled or disabled and set to (AVDD1 - AVSS)/2, 2.5 V, 2.05 V, 1.9 V, 1.65 V, 1.1 V, or 0.9 V referenced to AVSS. The default value is (AVDD1 - AVSS)/2. For MCLK = 16 MHz in fast mode, the differential input voltage is ~80 A/V unbuffered and 20 A/V with the precharge buffers enabled. With the precharge buffers off, REF+ = 5 V and REF- = 0 V. REF = 5 V x 80 A/V = + 400 A With the precharge buffers on, REF+ = 5 V, and REF- = 0 V. REF = approximately 20 A 400 300 200 100 0 -100 -200 VCM = 2.5V VCM = 2.1V VCM = 1.9V VCM = 1.65V VCM = 1.1V VCM = 0.9V VCM = (AVDD1 - AVSS)/2V -300 UNBUFFERED REF+ UNBUFFERED REF- 1.0 1.5 2.0 2.5 3.0 3.5 INPUT VOLTAGE (VDIFF) 4.0 4.5 5.0 16481-200 -400 0.5 Figure 65. Reference Input Current (REFIN) vs. Input Voltage, Unbuffered REF+ and REF- 20 PRECHARGE BUFFERED REF+ PRECHARGE BUFFERED REF- FULL BUFFER REF+ FULL BUFFER REF- 10 1k 10k 100k VCM OUTPUT BANDWIDTH (Hz) 1M REFIN (A) 400 380 360 340 320 300 280 260 240 220 200 180 160 140 120 100 80 60 40 20 0 100 16481-168 VCM OUTPUT NOISE (V rms) Figure 64 is a simulation of the VCM noise for each VCM setting, plotted over a bandwidth of 100 Hz to 1 MHz. An external resistor capacitor (RC) filter is required to set the bandwidth to meet the VCM noise requirement. For example, a VCM output of 2.5 V has 180 V rms of noise (see Figure 64). If the bandwidth is limited to 1 kHz, this noise can be reduced to approximately 65 V rms (see Figure 64). The reference input current scales linearly with the modulator clock rate. REFIN (A) VCM Output Figure 64. VCM Output Noise vs. VCM Output Bandwidth 0 -10 Reference Input and Buffering The reference inputs can be configured for a fully buffered input on each of the REF+ and REF- pins, a precharge buffered input, or to bypass both buffers. Use of either the full buffers or the precharge buffers reduces the burden on the external reference when driving large loads or multiple devices. The fully buffered input to the reference pins provides a high impedance input node and enables use of the AD7768-1 in ratiometric applications where the ultralow source impedance of a traditional external reference is not available. -30 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 INPUT VOLTAGE (VDIFF) 4.5 5.0 5.5 16481-201 -20 The AD7768-1 has differential reference inputs, REF+ and REF-. The absolute input reference voltage range is from 1 V to AVDD1 - AVSS. Figure 66. Reference Input Current (REFIN) vs. Input Voltage, Precharge Buffered REF+ and REF- and Full Buffer REF+ and REF- For the best performance and headroom, use a 4.096 V reference, such as the ADR444 or ADR4540, that can both be supplied by a 5 V rail and shared to the AVDD1 supply. A reference detect function is available in SPI control mode. See the Reference Detection section for details. In PIN control mode, the reference precharge buffers are on by default. In SPI mode, the user can choose fully buffered or precharge buffers. Rev. 0 | Page 33 of 76 AD7768-1 Data Sheet CLOCKING AND CLOCK SELECTION DIGITAL FILTERING The AD7768-1 has an internal oscillator that is used for initial power-up of the device. After the AD7768-1 completes the start-up routine, a clock handover occurs to the external MCLK. The AD7768-1 counts the falling edges of the external MCLK over a given number of internal clock cycles to determine if the clock is valid and of a frequency of at least 600 kHz. If there is a fault with the external MCLK, the handover does not occur, the AD7768-1 clock error bit is set, and the AD7768-1 continues to operate from the internal clock. The AD7768-1 offers three types of digital filters. The digital filters available on the AD7768-1 are Set the EN_ERR_EXT_CLK_QUAL bit (Bit 0 in Register 0x29) to turn off the clock qualification. Turning off the clock qualification allows the use of slower external MCLK rates outside the recommended MCLK frequency. * Sinc5 Filter Most precision - ADCs use a sinc filter. The sinc5 filter offered in the AD7768-1 enables a low latency signal path useful for dc inputs on control loops, or for where user specific post processing is required. The sinc5 filter has a -3 dB bandwidth of 0.204 x ODR. Table 11 shows the noise performance for the sinc5 filter across power modes and decimation ratios. 0 -20 -40 -60 -80 -100 -120 -140 CLKSEL Pin -160 If CLKSEL = 0 in PIN control mode, the CMOS clock option is selected and must be applied to the MCLK pin. In this case, tie the XTAL1 pin to DGND. -180 If CLKSEL = 1 in PIN control mode, the crystal option is selected and must be connected between the XTAL1 and XTAL2 pins. In SPI control mode, the CLKSEL pin does not determine the MCLK source used and CLKSEL must be tied to DGND. -200 0 2 4 6 8 10 12 14 16 NORMALIZED INPUT FREQUENCY (f/fODR) 16481-020 In PIN control mode, the CLKSEL pin sets the external MCLK source. Three clock options are available in PIN control mode: an internal oscillator, an external CMOS, or a crystal oscillator. The CLKSEL pin is sampled on power-up. Sinc5 low latency filter, -3 dB at 0.204 x ODR (8 rates) Sinc3 low latency filter, -3 dB at 0.2617 x ODR, widely programmable data rate Low ripple FIR filter, -3 dB at 0.43 x ODR (6 rates) AMPLITUDE (dB) In SPI control mode, use the clock source bits in Register 0x15 to set the external MCLK source. Four clock options are available: internal oscillator, external CMOS, crystal oscillator, or LVDS. If selecting the LVDS clock option, the clock source must be selected using the CLOCK_SEL bits (Bits[7:6] in Register 0x15). * * Figure 67. Sinc Filter Frequency Response The impulse response of the filter is five times the ODR. For 250 kSPS ODR, the time to settle data fully is 20 s. For the 1 MSPS ODR, the time to settle data fully is 5 s. Using the Internal Oscillator ANALOG INPUT In some cases, conversion using an internal clock oscillator may be preferred, such as in isolated applications where dc input voltages must be measured. Converting ac signals with the internal clock is not recommended because using the internal clock can result in degradation of SNR due to jitter. FULLY SETTLED 1/ODR 16481-021 ADC OUTPUT Figure 68. Sinc5 Filter Step Response The time from a SYNC_IN pulse to both the first DRDY and to fully settled data for various ODR values for the sinc5 filter is shown in Table 13. Rev. 0 | Page 34 of 76 Data Sheet AD7768-1 Table 13. Sinc5 Filter, SYNC_IN to Settled Data MCLK/4 MCLK/16 Decimation Ratio 8 16 32 64 128 256 512 1024 8 16 32 64 128 256 512 1024 8 16 32 64 128 256 512 1024 46 62 94 162 295 561 1,093 2,173 79 111 175 310 576 1,108 2,172 4,332 278 406 662 1,194 2,258 4,386 8,642 17,282 110 190 350 674 1,319 2,609 5,189 10,365 207 367 687 1,334 2,624 5,204 10,364 20,716 790 1,430 2,710 5,290 10,450 20,770 41,410 82,818 Sinc3 Filter The sinc3 filter offered in the AD7768-1 enables a low latency signal path useful for dc inputs on control loops, or for eliminating unwanted known interferers at specific frequencies. The sinc3 filter path incorporates a programmable decimation rate to achieve rejection of known interferers. Decimation rates from 32 to 185,280 are achievable using the sinc3 filter. The sinc3 filter has a -3 dB bandwidth of 0.26 x ODR. Table 14 and Table 15 show the minimum rejection measured at the frequencies of interest with a 50 Hz ODR. Table 14. Sinc3 Filter 50 Hz Rejection, 50 Hz ODR and Decimate by 163,840 Frequency Band (Hz) 50 1 100 2 150 3 200 4 Minimum Measured Rejection (dB) 101 102 102 102 Table 15. Sinc3 Filter 50 Hz and 60 Hz Rejection, 50 Hz ODR and Decimate by 163,840 Frequency Band (Hz) 50 1 60 1 100 2 120 2 150 3 180 3 200 4 240 4 Minimum Measured Rejection (dB) 81 67 83 72 86 78 90 87 The impulse response of the filter is three times the ODR. For 250 kSPS ODR, the time to settle data fully is 12 s. ANALOG INPUT FULLY SETTLED ADC OUTPUT 16481-167 MCLK Divide Setting MCLK/2 MCLK Periods Delay from First MCLK Rise After SYNC_IN Delay from First MCLK Rise After SYNC_IN Rise to First DRDY Rise Rise to Earliest Settled DRDY Rise 1/ODR Figure 69. Sinc3 Filter Step Response Rev. 0 | Page 35 of 76 AD7768-1 Data Sheet 0 Programming for 50 Hz, 60 Hz, and 50 Hz and 60 Hz Rejection -20 -40 SINC3 ROLL OFF (dB) To reject 50 Hz tones, program the ODR of the sinc3 filter to 50 Hz (see Figure 70). It is also possible to achieve simultaneous rejection of both 50 Hz and 60 Hz by setting Bit 7 in the DIGITAL_FILTER register (Address 0x19). Rejection of both 50 Hz and 60 Hz line frequencies is possible in this configuration (see Figure 42). -60 -80 -100 -120 -160 0 50 100 150 INPUT FREQUENCY (Hz) 200 250 16481-174 -140 Figure 70. Sinc3 Filter Frequency Response Showing 50 Hz Rejection, 50 Hz ODR, x163,840 Decimation Table 16. Sinc3 Filter, SYNC_IN to Settled Data MCLK Divide Setting MCLK/2 MCLK/4 MCLK/16 Decimation Ratio 32 64 128 256 512 1024 163,840 32 64 128 256 512 1024 81,920 32 64 128 256 512 1024 20,480 MCLK Periods Delay from First MCLK Rise After SYNC_IN Delay from First MCLK Rise After SYNC_IN Rise to First DRDY Rise Rise to Earliest Settled DRDY Rise 127 191 319 575 1,087 2,111 327,743 241 369 625 1,137 2,161 4,209 327,793 926 1,438 2,462 4,510 8,606 16,798 328,094 255 447 831 1,599 3,135 6,207 983,103 497 881 1,649 3,185 6,257 12,401 983,153 1,950 3,486 6,558 12,702 24,990 49,566 983,454 Rev. 0 | Page 36 of 76 Data Sheet AD7768-1 Low Ripple FIR Filter 0.010 The FIR filter is a low ripple, input pass-band up to 0.4 x ODR. The low ripple FIR filter has almost full attenuation at 0.5 x ODR (Nyquist), maximizing antialias protection. The frequency response of the low ripple FIR filter is shown in Figure 71. The low ripple FIR filter has a pass-band ripple of 0.005 dB, shown in Figure 72, and a stop band attenuation of 105 dB from Nyquist out to the chop frequency (fCHOP). For more information on antialiasing and fCHOP aliasing, see the Antialiasing Filtering section. The low ripple FIR filter is a 64-order digital filter. The group delay of the filter is 34/ODR. After a sync pulse, there is an additional delay from the SYNC_IN rising edge to fully settled data. The time from a SYNC_IN pulse to both the first DRDY and to fully settled data for various ODR values is shown in Table 17. 0.008 0.006 0.002 0 -0.002 -0.004 -0.006 -0.008 -0.010 0.05 0.10 0.15 0.20 0.25 0.30 0.35 0.40 0.45 0.50 NORMALIZED INPUT FREQUENCY (fIN/fODR) Figure 72. Low Ripple FIR Filter Pass-Band Ripple The low ripple FIR filter can be selected in one of six different decimation rates, allowing the user to choose the optimal input bandwidth and speed of the conversion vs. the desired resolution. 1.2 1.0 0 AMPLITUDE (dB) 0.8 -10 -20 -30 -40 -50 -60 0.6 0.4 0.2 -70 0 -80 -90 -0.2 -100 -110 0 10 20 30 40 50 60 70 OUTPUT DATA RATE SAMPLES -120 80 16481-026 AMPLITUDE (dB) 0 16481-025 AMPLITUDE (dB) 0.004 Figure 73. Low Ripple FIR Filter Step Response -140 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0 NORMALIZED INPUT FREQUENCY (fIN/fODR) 16481-024 -130 Figure 71. Low Ripple FIR Filter Frequency Response Table 17. Low Ripple FIR Filter SYNC_IN to Settled Data MCLK Divide Setting MCLK/2 MCLK/4 Decimation Ratio 32 64 128 256 512 1024 32 64 128 256 512 1024 MCLK Periods Delay from First MCLK Rise After SYNC_IN Delay from First MCLK Rise After SYNC_IN Rise to First DRDY Rise Rise to Earliest Settled DRDY Rise 284 413 797 1,565 3,101 6,157 428 812 1,580 3,116 6,188 12,300 4,252 8,349 16,669 33,309 66,589 133,133 8,364 16,684 33,324 66,604 133,164 266,252 Rev. 0 | Page 37 of 76 AD7768-1 1,674 3,202 6,274 12,418 24,706 49,154 33,418 66,690 133,250 266,370 532,610 1,064,962 DECIMATION RATE CONTROL The AD7768-1 has programmable decimation rates for the sinc and low ripple FIR digital filters. The decimation rates allow the user to band limit the measurement, which reduces the speed and input bandwidth, but increases the resolution because there is further averaging in the digital filter. Control of the decimation rate on the AD7768-1 when using the SPI control is set in the DIGITAL_FILTER register (Register 0x19) for the sinc5 and low ripple FIR filters. The decimation rate of the sinc3 filter is controlled using the SINC3_DEC_RATE_LSB register (Register 0x1A) and the SINC3_ DEC_RATE_MSB register (Register 0x1B). These registers combine to provide 13 bits of programmability. The decimation rate is set by incrementing the value in these registers by one and multiplying the value by 32. For example, setting a value of 0x5 in the SINC3_DEC_RATE_LSB register results in a decimation rate of 192 for the sinc3 filter. For the AD7768-1, the modulator input begins to saturate at fMOD/16 for a full-scale sine wave, input signal. Figure 74 shows where the modulator is vulnerable to saturation if the input at higher frequencies is greater in amplitude than the maximum signal allowable to prevent modulator saturation. To protect against modulator saturation, a minimum of a first-order antialiasing filter is required at a -3 dB corner frequency of fMOD/16. 0 -10 -20 -30 -40 -50 -60 -70 -80 -90 In PIN control mode, the MODE0 pin controls the decimation ratio. Only decimation rates of x32 and x64 are available for use with the sinc5 and wideband filter options. See Table 22 for the full list of options available in PIN control mode. E -100 -110 0.01 MAXIMUM SIGNAL ALLOWABLE TO PREVENT MODULATOR SATURATION LOW RIPPLE FIR FILTER PASS BAND 0.1 fIN/fMOD (Hz) E 1 16481-178 Decimation Ratio 32 64 128 256 512 1024 MCLK Periods Delay from First MCLK Rise After SYNC_IN Delay from First MCLK Rise After SYNC_IN Rise to First DRDY Rise Rise to Earliest Settled DRDY Rise INPUT AMPLITUDE (dB) MCLK Divide Setting MCLK/16 Data Sheet Figure 74. Modulator Saturation Area ANTIALIASING FILTERING When designing an antialiasing filter for the AD7768-1, there are three main aliasing regions to take into account. After the alias requirements of each zone are understood, the user can design an antialiasing filter to meet the needs of the specific application. The three zones for consideration are the modulator saturation point, the modulator unprotected zones, and the modulator chopping frequency. Modulator Saturation Point Think of the - modulator as a standard control loop employing negative feedback. The control loop ensures that the average processed error signal is very small over time. The control loop uses an integrator to remember preceding errors and force the mean error to zero. When the analog input slew rate is high enough, the error feedback is large, and the modulator begins to saturate due to the input. When in this state, the in band input signal converts. However, the noise floor rises significantly, affecting the parametric performance. Modulator Unprotected Zones The AD7768-1 modulator samples on the rising and falling edge of fMOD and outputs data to the digital filter at a rate of fMOD. There is a zero in the frequency response profile of the modulator centered at odd multiples of fMOD, which means that there is no foldback from frequencies at the fMOD rate and at odd multiples of this rate. The fact that there is no foldback from frequencies at the fMOD rate pushes the first unprotected zone of the AD7768-1 out to 2x fMOD, which is a distinct advantage vs. traditional - ADCs. Rev. 0 | Page 38 of 76 Data Sheet AD7768-1 However, the modulator is open to noise for even multiples of fMOD. There is no attenuation at these zones. Figure 75 shows the modulator frequency response when using the low ripple FIR filter. To protect against this additional noise, decide the level of attenuation to add to the analog signal path. A first-, second-, or third-order antialiasing filter may be required, depending on the environment of operation. SPI control mode includes the following features: * * * * * * 10 fCHOP = fMOD/32 fCHOP = fMOD/8 PIN control mode includes the following features: AMPLITUDE (dB) -10 * -30 * * * * -50 -70 NORMALIZED INPUT FREQUENCY (fIN/fODR) 16481-173 2.001 1.876 1.751 1.626 1.501 1.376 1.251 1.126 1.001 0.876 0.751 0.626 0.501 0.376 0.251 0.126 0.001 -90 -110 A superset of functions and flexibility. All the filters and ODR values. All the clock divide options to optimize the system clock frequency. Functional safety checking. Use of general-purpose input/outputs (GPIOs). Analog input and reference input buffer options. MODEx pins that can be set to a desired fixed function. The device assumes this operation on power-up, and no further configuration is required. Three power modes. Three filter types. A subset of decimation rates. Analog input precharge buffers on by default. SPI control offers the most flexibility, and PIN control is more suited to a fixed mode of operation, such as daisy-chaining multiple devices. Digital Filter Type and Decimation When selecting the digital filter type and decimate rate, consider Figure 75. Rejection of Out of Band Tones Modulator Chopping Frequency The AD7768-1 uses a chopping technique in the modulator similar to that of a chopped amplifier to remove offset, offset drift, and 1/f noise. The rate of chopping may result in out of band tones being aliased back to the bandwidth of interest. Figure 75 shows the rejection of out of band tones for both fCHOP = fMOD/32 (default) and fCHOP = fMOD/8. The fCHOP = fMOD/8 option is only available in SPI control mode. To protect against out of band tones aliasing back into the bandwidth of interest, the user must decide on the level of attenuation to add to the analog signal path. A first-, second-, or third-order antialiasing filter may be required, depending on the environment of operation. See the Antialiasing Filter Design Considerations section for more information. GETTING STARTED The AD7768-1 offers users a low power, small footprint, flexible measurement solution for ac and dc signal processing. There are initial key decisions for the system designer to consider. At the highest level, these decisions are related to control mode, power mode, and digital filtering and decimation requirements. * * * The input bandwidth, filter profile requirement, or requirement for 50 Hz and/or 60 Hz rejection. The maximum noise target. The ODR requirement. Power Mode The selected power mode has a significant effect on the overall power consumption achievable. When selecting the power mode, consider the speed of conversion, input bandwidth, noise performance, and power consumption. In SPI control mode, select the MCLK_DIV setting for the sampling clock of the system. The power mode must be sufficient to support the modulator clock frequency settings. See Table 9 for the recommended power mode and fMOD settings. In PIN control mode, the power mode and clock divide pairings are predetermined as follow: * * * Method of Configuration--PIN Control Mode or SPI Control Mode The control mode is determined at power-up and is based on the logic level of the PIN/SPI pin (tied to DGND or IOVDD). The two modes are SPI control mode and PIN control mode. Rev. 0 | Page 39 of 76 Fast mode = MCLK/2 Median mode = MCLK/4 Low power mode = MCLK/16 AD7768-1 Data Sheet *AVDD1 *AVDD2 *IOVDD *DECOUPLING CAPACITORS OF 0.1F AND 1F REQUIRED ON ALL *REGCAPA *REGCAPD VCM SYNC_OUT VOCM PIN PRECHARGE BUFFERS ON/OFF SYNC_IN RESET WIDEBAND LOW RIPPLE FILTER SYNCHRONIZING MULTIPLE CHANNELS TO SYSTEM SAMPLING TRIGGERS 5V SPI DATA OUTPUT AND CONTROL INTERFACE AIN0+ SINC5 LOW LATENCY FILTER 24-BIT - ADC ADA4940-1 AIN0- SINC3 LOW LATENCY FILTER 50Hz/60Hz REJECTION CAPABILITY REF BUFFER SETTINGS: ADA4805-2, ADA4084-2, ADA4807-2, ADA4500-2, ADA4896-2, ADA4899-1, LTC6363 MODE3/GPIO3 (START) MODE2/GPIO2 MODE1/GPIO1 MODE0/GPIO0 OFF PRECHARGE FULL RAIL TO RAIL AMPLIFIERS CHOSEN TO PAIR AND SCALE TO MATCH FAST, MEDIAN, AND LOW POWER REF+ AVSS REF- CLKSEL MCLK/XTAL2 XTAL1 VIN VIN DRDY CS SCLK DOUT/RDY SDI DGND PIN/SPI CONNECT TO DGND OR IOVDD CLOCK SOURCE VOUT 16481-028 CMOS, XTAL OR LVDS ADR430 TO ADR435 ADR440 TO ADR445 ADR4520 TO ADR4550 Figure 76. Typical Connection Diagram Table 18. Operation Requirements for the AD7768-1 and the Options Available Parameter Power Supplies External Reference External Driver Amplifier External Clock Microcontroller, FPGA, or DSP Description 5.0 V AVDD1 supply, 2.0 V to 5.0 V AVDD2 supply, 1.8 V to 3.3 V IOVDD supply (ADP7104/ADP7118). In low power mode, the supplies can be configured for single 3 V operation as follows: AVDD1 = AVDD2 = IOVDD = 3.0 V to 3.3 V. 2.5 V ADR4525, 4.096 V ADR4540, 5.0 V ADR4550. The ADA4896-2, the ADA4940-2, the ADA4805-2, or the ADA4807-2. Crystal, CMOS, or LVDS clock for the ADC modulator sampling. Input/output voltage of 1.8 V to 3.3 V. Table 19. Speed, Dynamic Range, THD, and Power Overview, Decimate by 32 1 Power Mode Fast Median Low Power 1 ODR 256 kSPS 128 kSPS 32 kSPS Dynamic Range (dB) 108.5 (low ripple FIR filter) 108.5 (low ripple FIR filter) 108.5 (low ripple FIR filter) THD (dB) -120 -120 -120 Power Dissipation (mW) Low Ripple FIR Filter Sinc Filter 36.8 26.4 19.7 14.4 6.75 5.4 Analog input precharge buffer on, reference precharge buffers on, and VCM disabled. Typical values are AVDD1 = 5.0 V, AVDD2 = 2.0 V, IOVDD = 1.8 V, VREF = 4.096 V, MCLK = 16.384 MHz, and TA = 25C. Rev. 0 | Page 40 of 76 Data Sheet AD7768-1 12V TO 20V INPUT The AD7768-1 has three independent power supply pins (AVDD1, AVDD2, and IOVDD). These pins are powered within the following ranges: * * * ADP2384 BUCK 6V ADP7118 LDO ADP7118 LDO AVDD1 = 5.0 V 10%, 2.5 V 10%, when AVSS = -2.5 V, and 3.3 V 10% (in low power mode only) AVDD2 = 2.0 V to 5.0 V IOVDD (with a regulator) = 1.8 V to 3.3 V AVDD1 and AVDD2 are referred to AVSS, and IOVDD is referred to DGND. 5V: AVDD1 3.3V: AVDD2/IOVDD Figure 77. Power Supply Configuration DEVICE CONFIGURATION METHOD The AD7768-1 has two options for controlling device functionality. On power-up, the mode is determined by the state of the PIN/ SPI pin. The two modes of configuration are * SPI: over a 3- or 4-wire SPI interface (complete configurability) PIN: pin strapped digital logic inputs (a subset of complete configurability) The AVDD1 supply powers the analog front end, reference input, and common-mode output circuitry. AVDD1 is referenced to AVSS. * The AD7768-1 can be used with a 2.5 V split supply configuration to enable converting a true bipolar input. When using split supplies, refer to the Absolute Maximum Ratings section, which describes the voltage allowed between the AVSS and IOVDD supplies. There is a limit on the tolerance in the voltage difference between IOVDD and AVSS. On power-up, the user must apply a soft or hard reset to the device when using either control mode. A SYNC_IN pulse is also recommended after the reset or after any change to the device configuration. Choose between controlling and configuring over the SPI or via pin connections only. The AVDD2 supply connects to an internal 1.8 V analog LDO regulator. This regulator powers the ADC core and enhances the PSRR. AVDD2 is referenced to AVSS. AVDD2 - AVSS can range from 5.5 V (maximum) to 2.0 V (minimum). For bipolar inputs, AVDD2 must remain within 5.5 V of the AVSS potential. The first design decision is setting the ADC in either the SPI or PIN mode of configuration. In either mode, the digital host reads the ADC data over the SPI port lines. PIN Configuration An overview of the PIN control mode features is as follows: IOVDD powers the internal 1.8 V digital LDO regulator. This regulator powers the digital logic of the ADC. IOVDD sets the voltage levels for the SPI interface of the ADC. IOVDD is referenced to DGND, and IOVDD - DGND can vary from 3.6 V (maximum) to 1.7 V (minimum). * * * * Single-Supply Mode * The AD7768-1 can operate from a single 3.3 V supply rail in low power mode. This feature eliminates the inefficiency of generating multiply supply rails or applications where only a 3.3 V rail is available. The single-supply operation is limited to 3.3 V 10% and is available only when operating in low power mode. The recommended compatible components for single-supply operation are the ADP7104-3.3 precision LDO, the ADR443 precision 3.0 V reference, and the ADA4807-2 or ADA4084-2 low power rail-to-rail input and output precision amplifiers. Recommended Power Supply Configuration Figure 77 shows the ADP2384 stepping down the supply voltage efficiently while the ADP7118 LDO provides a low noise voltage input. The ADP7118 provides positive supply rails for optimal converter performance, creating either a single 5 V, 3.3 V, or dual AVDD1/IOVDD supply, depending on the required supply configuration. Alternatively, the ADP7118 can operate from input voltages of up to 20 V if the design is space constrained. 16481-029 POWER SUPPLIES No SPI write access to the device. Pins control all functions. ADC results read back over the SPI pins. ADC result includes an 8-bit status header output after each conversion result. SDI pin can be used to create a daisy chain of multiple devices operating in PIN mode. SPI Control An overview of the SPI control mode features is as follows: * * * * Rev. 0 | Page 41 of 76 Standard SPI Mode 3 interface for register access, where the ADC always behaves as an SPI slave. Indication of a new conversion via the DRDY pin output. A second method allows the user to merge the ready signal within the DOUT output stream, which allows a reduction in the number of lines across an isolation barrier. Reading back conversions can be performed by writing 8 bits to address the ADC register and reading back the result from the register. Continuous readback mode, which is enabled via an SPI write. There is no need to supply the 8 bits to address the ADC_DATA register (Register 0x2C). Data readback occurs on the application of SCLK. The DRDY pin indicates that a conversion result is complete and can be used to trigger a readback of the conversion result. AD7768-1 Table 20. Modulator Rate for PIN Control Mode In continuous read back mode, there is the option to append either the 8-bit status header or an 8-bit CRC check, or both. PIN CONTROL MODE OVERVIEW PIN control mode eliminates the need for SPI communication to set the required mode of operation. For situations where the user requires a single, known configuration, reduce routing signals to the digital host. PIN control mode is useful in digitally isolated applications where minimal configuration is needed. PIN control mode offers a subset of the core functionality and ensures a known state of operation after power-up, reset, or a fault condition on the power supply. In PIN control mode, the analog input precharge buffers and reference input precharge buffers are enabled by default for best performance. An automatic sync pulse drives out on the SYNC_OUT pin in PIN control mode when the device is either initially powered up or after a reset. A SYNC_OUT pulse also occurs when a GPIOx pin toggles, meaning after a change to the PIN control mode settings of the device, the synchronization is automatically performed. For this synchronization to work, tie SYNC_OUT to SYNC_IN, eliminating the need to provide a synchronous SYNC_IN pulse. The SYNC_OUT of one device can also be tied to the SYNC_IN of many devices when the synchronization of multiple devices is required. If synchronization of multiple devices is required, all devices must share a common MCLK. Power Mode In PIN control mode, the device automatically scales the power mode of the ADC and divides the applied MCLK to a specified setting for that mode. Table 20 shows the modulator division for each power mode. Power Mode Fast Median Low Power Modulator Rate, fMOD MCLK/2 MCLK/4 MCLK/16 In SPI control mode, separate register bits control the power mode of the ADC and MCLK division independently. Take care to follow the recommended settings in Table 9 if setting the power mode and modulator rate independently. Data Output Format PIN control mode has a set output format for conversion data. The rising DRDY edge indicates that a new conversion is ready. The next 24 serial clock falling edges clock out the 24-bit ADC result. The following eight serial clocks output the status bits of the AD7768-1. The ADC data is output MSB first in twos complement format. If further SCLK falling edges are applied to the ADC after clocking out the status bits, the logic level applied to SDI is clocked out, similar to a daisy-chain scenario. In Figure 78, an extra serial clock edge (33rd falling edge) is shown. If an extra serial clock edge occurs, the logic level of the SDI pin clocks out. NEW ADC RESULT AVAILABLE DRDY DOUT ADC DATA 24 BITS STATUS SCLK FALLING SCLK EDGE CLOCKS DATA OUT Figure 78. PIN Mode Data Output Format (This Figure Does Not Show the CS Signal) Table 21. Differences in Control and Interface Pin Functions in PIN Control Mode and SPI Control Mode Mnemonic MODE0/GPIO0 MODE1/GPIO1 MODE2/GPIO2 MODE3/GPIO3 CS PIN Control Mode MODE0 configuration pin MODE1 configuration pin MODE2 configuration pin MODE3 configuration pin SPI pin for readback of ADC conversion results SCLK SPI pin for readback of ADC conversion results SDI SPI pin for readback of ADC conversion results DOUT/RDY SPI pin for readback of ADC conversion results SDI 8 BITS Pin Function SPI Control Mode GPIO0 pin GPIO1 pin GPIO2 pin GPIO3 pin SPI interface for full configuration of the AD7768-1 via a register read/write and readback of the ADC conversion results SPI interface for full configuration of the AD7768-1 via a register read/write and readback of the ADC conversion results SPI interface for full configuration of the AD7768-1 via a register read/write and readback of the ADC conversion results SPI interface for full configuration of the AD7768-1 via a register read/write and readback of the ADC conversion results Rev. 0 | Page 42 of 76 16481-076 * Data Sheet Data Sheet AD7768-1 Diagnostics and Status Bits PIN control mode offers a subset of diagnostics features. Internal errors are reported in the status header output with the data conversion results for each channel. The status header reports the internal CRC errors, memory map flipped bits, and the undetected external clock, indicating a reset is required. The status header also reports filter settled and filter saturated signals. Users can determine when to ignore data by monitoring these error flags. If a significant error shows in the status bits, a reset of the ADC using RESET pin is recommended because, like in PIN mode, there is no way to interrogate further for specific errors. Daisy-Chaining--PIN Control Mode Only Daisy-chaining devices allows multiple devices to use the same data interface lines by cascading the outputs of multiple ADCs from separate AD7768-1 devices. Daisy-chaining devices is only possible in PIN control mode. When configured for daisy-chaining, only one AD7768-1 device has its data interface in direct connection with the digital host. For the AD7768-1, cascading the DOUT/RDY pin of the upstream AD7768-1 device to the SDI pin of the next downstream AD7768-1 device in the chain implements this daisy-chaining. The ability to daisy-chain devices and the limit on the number of devices that can be handled by the chain is dependent on the serial clock frequency used and the time available to clock through multiple 32-bit conversion outputs (24-bit conversion + 8-bit status) before the next conversion is complete. The daisy-chaining feature is useful to reduce component count and to wire connections to the controller. Figure 79 shows an example of daisy-chaining multiple AD7768-1 devices. The daisy-chain scheme depends on all devices receiving the same MCLK and SCLK, being synchronized, and being configured with the same decimation rate. The chip select signal (CS) gates each conversion chain of data, its rising edge resetting the SPI to a known state after each conversion ripples through. The AD7768-1 device that is furthest from the controller must have its SDI pin tied to IOVDD, logic high. AD7768-1 B MCLK SYNCHRONIZATION LOGIC HOST DIGITAL FILTER (MICROPROCESSOR/ DSP) SYNC_IN DRDY IRQ SPI_SEL CS PIN/SPI MASTER CLOCK SCLK SCLK SDI MOSI DOUT/RDY MISO SPI PORT ( DATA ACCESS) GPIO AD7768-1 A SYNCHRONIZATION LOGIC DIGITAL FILTER SYNC_IN DRDY CS PIN/SPI IOVDD SCLK SDI DOUT/RDY Figure 79. Daisy-Chaining Multiple AD7768-1 Devices Rev. 0 | Page 43 of 76 16481-176 MCLK AD7768-1 Data Sheet DRDY DOUT/RDY ADC A ADC DATA READ FROM A SDI ADC B ADC DATA READ FROM A DOUT/RDY ADC B ADC DATA READ FROM B 16481-078 SCLK ADC DATA READ FROM A Figure 80. Data Output Format When Devices Daisy-Chained (PIN Control Mode Only) Table 22. PIN Control Settings for MODEx Pins MODEx (Hex) 0 1 2 3 4 5 6 7 8 9 A B C D MODEx Pin Settings MODE3/ MODE2/ MODE1/ GPIO3 GPIO2 GPIO1 0 0 0 0 0 0 0 0 1 0 0 1 0 1 0 0 1 0 0 1 1 0 1 1 1 0 0 1 0 0 1 0 1 1 0 1 1 1 0 1 1 0 MODE0/ GPIO0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 Power Mode Fast (MCLK/2) Fast (MCLK/2) Fast (MCLK/2) Fast (MCLK/2) Median (MCLK/4) Median (MCLK/4) Median (MCLK/4) Median (MCLK/4) Low power (MCLK/16) Low power (MCLK/16) Low power (MCLK/16) Low power (MCLK/16) Fast (MCLK/2) Fast (MCLK/2) E 1 1 1 0 Low power (MCLK/16) F 1 1 1 1 1 AD7768-1 Configuration Filter Decimation Low ripple FIR x32 Low ripple FIR x64 Sinc5 x32 Sinc5 x64 Low ripple FIR x32 Low ripple FIR x64 Sinc5 x32 Sinc5 x64 Low ripple FIR x32 Low ripple FIR x64 Sinc5 x32 Sinc5 x64 Sinc5 x8 x163,840 Sinc3 50 Hz and 60 Hz rejection1 x20,480 Sinc3 50 Hz and 60 Hz rejection1 Standby MCLK = 16.384 MHz ODR 256 kHz 128 kHz 256 kHz 128 kHz 128 kHz 64 kHz 128 kHz 64 kHz 32 kHz 16 kHz 32 kHz 16 kHz 1 MHz 50 Hz 50 Hz Sinc3 filter, rejection of 50 Hz and 60 Hz. Rejection of 50 Hz and 60 Hz is possible only if the MCLK applied in PIN control mode is equal to 16.384 MHz. The decimation rate is tuned internally for these pin mode settings so that the sinc filter notches fall at 50 Hz and 60 Hz. SPI CONTROL OVERVIEW SPI control offers a superset of flexibility and diagnostics to the user. The categories described in Table 23 define the major controls, conversion modes, and diagnostic monitoring abilities enabled in SPI control mode. Table 23. SPI Control Capabilities SPI Control Power Mode MCLK Division MCLK Source Digital Filter Style Interface Format Capabilities Fast, medium, low power, standby, power down MCLK/2 to MCLK/16 CMOS, crystal, LVDS, and internal clock Sinc5, low ripple FIR, sinc3 (programmable) Bit length Status bits CRC Data streaming Meaning for the User The ability to scale power and save power with full control. The ability to customize clock frequency relating to the bandwidth of interest. Allows the user a distributed or local clock capability. The ability to customize the latency and frequency response to the measurement target of the user and its bandwidth. The ability to change between a 24-bit and a 16-bit conversion length in continuous read mode. The ability to view output device status bits with the ADC conversion results. The ability to implement error checking when transmitting data. The ability to stream conversion data, eliminating interface write overhead. Rev. 0 | Page 44 of 76 Data Sheet SPI Control Analog Buffers AD7768-1 Capabilities Analog input precharge Reference input precharge Reference input full buffer Conversion Modes Single conversion One shot Continuous conversion Duty-cycled conversion Calibration Conversion Targets Analog inputs Temperature sensor Diagnostic sources GPIO Control Up to four GPIOx pins System Offset and Gain Correction System calibration routines Diagnostics Internal checks and flags Meaning for the User Eases requirements on the ADC driver amplifier. Allows use of a lower power or lower bandwidth driver amplifier. Reduces reference input current, making it easier to filter the reference. This full high impedance buffer enables filtering of reference source and enables high impedance sources, that is, reference resistors. The ability to return to standby after one conversion. The ability to perform a conversion similar to a timed successive approximation register (SAR) conversion, in which the AD7768-1 converts on a timed pulse. Normal operation keeps the modulator continually converting, offering the fastest response to a change on the input. The ability to save more power for point conversions. Times the rate of conversion and sets the time for the ADC to remain in standby after the conversion completes. The ability to run a calibration of the system and to save gain calibration or offset calibration results to the system settings of the user by reading back from the gain/offset registers. The ability to measure the input signal applied at the analog input pins. The ability to measure local temperatures with an on-chip temperature sensor. Used for relative temperature measurement. The ability to measure reference inputs and internal voltages for periodic functional safety checking. The ability to control other local hardware (such as gain stages),to power down other blocks in the signal chain, or read local status signals over the SPI interface of the AD7768-1. The ability to correct offset and/or gain by writing to registers when the environment changes (that is, the temperature increases). Requires characterization of system errors to feed these registers. Users can have the highest confidence in the conversion results. SPI CONTROL MODE entering power-down mode. See the power and clock control register (POWER_CLOCK), Address 0x15, for further details. MCLK Source and MCLK Division MCLK division bits control the divided ratio between the MCLK applied at the input to the AD7768-1 and the clock used by the ADC modulator. Select the division ratio best for configuration of the clocks. The following options are available as the MCLK input source in SPI mode: * * * LVDS External crystal CMOS input MCLK Pulling CLOCK_SEL low configures the AD7768-1 for a CMOS clock. Pulling CLOCK_SEL high enables the use of an external crystal. Pulling CLOCK_SEL high and setting Bits[7:6] of Register 0x15 enables the application of the LVDS clock to the MCLK pin. LVDS clocking is exclusive to SPI mode and requires the register selection for operation. Power-Down Mode Power-down mode has the lowest possible current consumption. All blocks on the ADC are turned off. A specific code is required to wake the ADC up. All register contents are lost when entering power-down mode. Disconnect all inputs to the ADC when Standby Mode Analog clocking and power functions are powered down. The digital LDO and register settings are retained when in standby mode. This mode is best used in scenarios where the ADC is not in use, briefly, and the user wants to save power. SPI Synchronization The AD7768-1 can be synchronized over the SPI. The final SCLK rising edge of the command is the instance of synchronization. This command initiates the SYNC_OUT pin to pulse active low and then back active high again. SYNC_OUT is a signal synchronized internally to the MCLK of the ADC. By connecting the output of SYNC_OUT to the SYNC_IN input, the user can synchronize that individual ADC. Routing SYNC_OUT to other AD7768-1 devices also ensures the devices are synchronized, as long as the devices share a common MCLK source. It is recommended to perform synchronization functions directly after the DRDY pulse. If the AD7768-1 SYNC_IN pulse occurs too close to the upcoming DRDY pulse edge, the upcoming DRDY pulse may still be output because the SYNC_IN pulse has not yet propagated through the device. Rev. 0 | Page 45 of 76 AD7768-1 Data Sheet When using the SYNC_OUT function with an IOVDD voltage of 1.8 V, it is recommended to set the SYNC_OUT_POS_EDGE bit to a one (Address 0x1D, Bit 6). Offset Calibration In SPI control mode, the AD7768-1 offers the ability to calibrate offset and gain. The user can alter the gain and offset of the AD7768-1 and its subsystem. These options are available in SPI control mode only. The offset correction registers provide 24-bit, signed, twos complement registers for channel offset adjustment. If the channel gain setting is at the ideal nominal value of 0x555555, an LSB of offset register adjustment changes the digital output by -4/3 LSBs. For example, changing the offset register from 0 to 100 changes the digital output by -133 LSBs. As offset calibration occurs before gain calibration, the LSB ratio of -4/3 changes linearly with gain adjustment via the gain correction registers. Further register information and calibration instructions are available in the Offset Registers section. Gain Calibration In SPI control mode, the user can alter the gain and offset of the AD7768-1 and its subsystem. These options are available in SPI control mode only. The ADC has an associated gain coefficient that is stored for each ADC after factory programming. Nominally, this gain is approximately the 0x555555 value (for an ADC channel). The user can overwrite the gain register setting. However, after a reset or power cycle, the gain register values revert to the hard coded, programmed factory setting. GPIO and START Functions When operating in SPI mode, the AD7768-1 has additional GPIO functionality. This fully configurable mode allows the device to operate four GPIOs. These pins can be configured as read or write in any order. GPIO read is a useful feature because it allows a peripheral device to send information to the input GPIO. Then, this information can be read from the SPI interface of the AD7768-1. The GPIOx pins can be set as inputs or outputs on a per pin basis, and there is an option to configure outputs as open-drain. In SPI control mode, one of the GPIOx pins can be assigned the function of the START input. The START function allows a signal asynchronous to MCLK to be used to generate the SYNC_OUT signal to reset the digital filter path of the AD7768-1. The START pin function can be enabled on GPIO3. SPI Mode Diagnostic Features The AD7768-1 includes diagnostic coverage across the internal blocks. The diagnostics in the following list allow the user to monitor the ADC and to increase confidence in the fidelity of the data acquired: * * * * * * * Reference detection Clock qualification CRC on SPI transaction Flags for detection of an illegal register write CRC checks POR monitor MCLK counter In addition, these diagnostics are useful in situations where instruments require remote checking of power supplies and references during initialization stages. 3 x VIN = x 221 - (Offset) x Data VREF Gain 4,194,300 x 4 242 The diagnostics are selectable by the user via enable registers. The flags for power-on reset (POR) and the clock qualification are on by default. The flags are readable via registers, but also ripple through to the top level status bits that can be output with each ADC conversion, if desired. Further register information and calibration instructions are available in the Gain Registers section. Reset over SPI Control Interface The user can issue a reset command to the AD7768-1 by writing to the SPI_RESET bits in the SYNC_RESET register. Two successive writes to these bits are required to initiate the device reset. Resume from Shutdown Shutdown mode features the lowest possible current consumption with all blocks on the device turned off, including the standard SPI interface. Therefore, to wake the ADC up from this mode, either a hardware reset on the RESET pin, or a specific code on the SPI SDI input, is required. The specific sequence required on SDI consists of a 1 followed by 63 zeros, clocked in by SCLK while CS is low, which allows the system to wake up the AD7768-1 from shutdown without using the RESET pin. This reset function is useful in isolated applications where the number of pins brought across the isolation barrier must be minimized. Reference Detection Write 1 to Bit 3 of the ADC_DIAG_ENABLE register (Address 0x29) to enable the reference detection block in SPI control mode. When enabled, the error flags in the ADC_DIAG_ STATUS register (Address 0x2F). Any error flags then propagate through to the MASTER_STATUS register (Address 0x2D). The reference error flags when the reference applied on the REF+ pin is below 1/3 of (AVDD1 - AVSS). Rev. 0 | Page 46 of 76 Data Sheet AD7768-1 Clock Qualification POR Monitor The clock qualification check attempts to detect when a valid MCLK is detected. When the MCLK applied is greater than 600 kHz, the clock qualification passes. The error flags in both the ADC_DIAG_STATUS register (Address 0x2F) and the MASTER_STATUS register (Address 0x2D). If the clock detected is below the 600 kHz frequency threshold, or if an external MCLK is not detected, the clock qualification error bit is set to 1. To disable the clock qualification check, write 0 to Bit 0 of the ADC_DIAG_ENABLE register (Address 0x29). The POR monitor flag appears in both the MASTER_STATUS register and the status bits when output. The POR flag indicates that a reset or a temporary supply brown out occurred. MCLK Counter See the SPI Control Interface Error Handling section for more details. The MCLK_COUNTER register (Address 0x31) updates every 64 MCLKs. The MCLK counter register verifies that the AD7768-1 is still receiving a valid MCLK. Read the MCLK counter register according to the specific MCLK to SCLK ratio to ensure that a valid read occurs. The SCLK applied to read the MCLK_COUNTER register must not be less than 2.1 x MCLK or greater than 4.6 x MCLK. For example, if MCLK = 2 MHz, the SCLK applied cannot be in the 4.2 MHz to 9.2 MHz range. If the MCLK to SCLK ratio is not adhered to, the read may corrupt because the MCLK may update during the read of the register, causing an error. CRC Checks Product Identification (ID) Number Enable CRC checks in the DIG_DIAG_ENABLE register (Register 0x2A) to check the state of the memory map of the AD7768-1 and the internal random access memory (RAM) and fuse settings. If any of these errors flag on the device, perform a reset to return the device to a valid state. The AD7768-1 contains ID registers that allow software interrogation of the silicon. The class of the product (precision ADC), product ID, device revision, and grade of device can all be read from the registry over the SPI. The vendor ID for Analog Devices, Inc., is also included in the registry for readback. These registers, in addition to a scratch pad that allows free reads from and writes to a specific register address, are methods of verifying the correct operation of the serial control interface. CRC on SPI Transaction See the CRC Check on Serial Interface section for more details. Flags for Detection of Illegal Register Write Table 24. Product Identification Registers Register Address (Hex) 0x03 0x04 0x05 0x06 0x0A 0x0C 0x0D Name Chip type Product ID [7:0] Product ID [15:8] Grade and revision Scratch pad Vendor ID Rev. 0 | Page 47 of 76 Bit Fields Reserved Grade Class PRODUCT_ID[7:0] PRODUCT_ID[15:8] DEVICE_REVISION Value VID[7:0] VID[15:8] AD7768-1 Data Sheet DIGITAL INTERFACE The AD7768-1 has a 4-wire SPI interface. The interface operates in SPI Mode 3. In SPI Mode 3, SCLK idles high, the first data is clocked out on the first falling or drive edge of SCLK, and data is clocked in on the rising or sample edge. Figure 82 shows SPI Mode 3 operation where the falling edge of SCLK is driving out the data and the rising edge of SCLK is when the data is sampled. AD7768-1 HOST (SLAVE) (MICROPROCESSOR/ DSP) DRDY IRQ CS SPI_SEL SCLK SDI MOSI DOUT/RDY MISO SPI PORT (MASTER) REGISTER AND DATA ACCESS 16481-080 SCLK REQUIRED OPTIONAL Figure 81. Basic Serial Port Connection Diagram SAMPLE EDGE 16481-081 DRIVE EDGE Figure 82. SPI Mode 3 SPI Reading and Writing To use SPI control mode, set the PIN/SPI pin high. The SPI control operates as a 4-wire interface allowing read and write access. In systems where CS can be tied low, such as those requiring isolation, the AD7768-1 can operate in a 3-wire configuration. Figure 81 shows a typical connection between the AD7768-1 and the digital host. The corresponding 3-wire interface involves tying the CS pin low and using SCLK, SDI, and DOUT/RDY. The format of the SPI read or write is shown in Figure 83. The MSB is the first bit in both read and write operations. An active low frame start signal (FS) begins the transaction, followed by the R/W bit that determines if the transaction being carried out is to a read (1) or a write (0). The next six bits are used for the address, and the eight bits of data to be written follow. All registers in the AD7768-1 are 8 bits in width, except for the ADC_DATA register (Register 0x2C), which is 24 bits in width. In the case where CS is tied low, the last SCLK rising edge completes the SPI transaction and resets the interface. When reading back data with CS held low, it is recommended that SDI idle high to prevent an accidental reset of the device where SCLK is free running (see the Reset section). CS SCLK FS 1 R/W ADDRESS 6-BIT DATA TO WRITE 8-BIT 16481-082 SDI DATA BEING READ 8-BIT/24-BIT ADDRESS DEPENDENT DOUT/RDY Figure 83. SPI Basic Read/Write Frame SDI 1 FS R/W ADDRESS 6-BIT DATA TO WRITE 8-BIT 16481-083 SCLK Figure 84. 3-Wire SPI Write Frame (CS = 0) SCLK 1 FS R/W ADDRESS 6-BIT SDO DATA BEING READ 8-BIT/24-BIT Figure 85. 3-Wire SPI Read Frame (CS = 0) Rev. 0 | Page 48 of 76 16481-084 SDI Data Sheet AD7768-1 SPI Control Interface Error Handling CRC Check on Serial Interface The AD7768-1 SPI control interface detects if an illegal command is received. An illegal command is a write to a read only register, a write to a register address that does not exist, or a read from a register address that does not exist. If any of these illegal commands are received by the AD7768-1, error bits are set in the SPI_DIAG_ STATUS register (Register 0x2E). The AD7768-1 can deliver up to 40 bits with each conversion result, consisting of 24 bits of data and eight status bits, with the option to add eight further CRC/XOR check bits in SPI mode only. Five sources of SPI error can be detected. These detectable error sources must be enabled in the SPI_DIAG_ENABLE register (Register 0x28). Only the EN_ERR_SPI_IGNORE (Bit 4) error is enabled on startup. The five detectable sources of SPI error are as follows: * * * * SPI CRC error. This error occurs when the received CRC/XOR does not match the calculated CRC/XOR. SPI read error. This error occurs when an incorrect read address is detected (for example, when the user attempts to access a register that does not exist). SPI write error. This error occurs when a write to an incorrect address is detected (for example, when the user attempts to write to a register that does not exist). SPI clock count error. When the SPI transaction is controlled by CS, this error flags when the SPI clock count during the frame is not equal to 8, 16, 24, 32, or 40. This error can be detected in both continuous read mode and normal SPI mode. SPI ignore error. This error flags when an SPI transaction is attempted before initial power-up completes. All SPI errors are sticky, meaning they can only be cleared if the user writes a 1 to the corresponding error location. The AD7768-1 uses a CRC polynomial to calculate the CRC message. The 8-bit CRC polynomial used is x8 + x2 + x + 1. To generate the checksum, shift the data by eight bits to create a number ending in eight Logic 1s. The polynomial is aligned such that the MSB is adjacent to the leftmost Logic 1 of the data. Apply an exclusive OR (XOR) function to the data to produce a new, shorter number. The polynomial is again aligned such that the MSB is adjacent to the leftmost Logic 1 of the new result, and the procedure is repeated. This process repeats until the original data is reduced to a value less than the polynomial, which is the 8-bit checksum. If enabled, the SPI writes always use CRC, regardless of whether the XOR option is selected in the INTERFACE_FORMAT register (Register 0x14). The initial CRC checksum for SPI transactions is 0x00, unless reading back data in continuous read mode, in which case the initial CRC is 0x03. If using the XOR option in continuous read mode, the initial value is set to 0x6C. The XOR option is only available for SPI reads. CS SCLK SDI DOUT/RDY IGNORED FS R/W ADDRESS 6 BITS DATA TO WRITE 8-BIT CRC 8-BIT DATA TO READ 24-BIT CRC/XOR 8-BIT Figure 86. Data Output Format When Using CRC Rev. 0 | Page 49 of 76 IGNORED 16481-085 * The status bits default per the description in the Status Header section. The CRC functionality is available only when operating in SPI control mode. When the CRC functionality is in use, the CRC message is calculated internally by the AD7768-1. The CRC is then appended to the conversion data and the optional status bits. AD7768-1 Data Sheet Conversion Read Modes Key considerations for users on the interface are as follows: The digital interface of the AD7768-1 is a 4-wire SPI implementation operating in Mode 3 SPI. An 8-bit write instruction is needed to access the memory map address space. All registers are eight bits wide, with the exception of the ADC data register. The AD7768-1 operates in a continuously converting mode by default. The user must decide whether to read the data. Two read modes are available to access the ADC conversion results: single-conversion read mode and continuous read mode * * * * * * Single-read mode is a basic SPI read cycle where the user must write an 8-bit instruction to read the ADC data register. The status register must be read separately, if needed * Write a 1 to the LSB of the INTERFACE_FORMAT register to enter continuous read mode. Subsequent data reads do not require an initial 8-bit write to query the ADC_DATA register. Simply provide the required number of SCLKs for continuous readback of the data. Figure 87 shows an SPI read in continuous read mode. Conversion data is available for readback after the rising edge of DRDY. In continuous read mode, the RDY function can be enabled, and the DRDY function can be ignored. Data is available for readback on the falling edge of RDY. The ADC conversion data register is updated internally 1 MCLK period prior to the rising DRDY edge. MCLK has a maximum frequency of 16.384 MHz. SCLK has a maximum frequency of 20 MHz. The DRDY high time is 1 x tMCLK In fast power mode, decimate by 32, the DRDY period is ~4 s, the fastest conversion can have a DRDY period of 1 s. The CS rising edge resets the serial data interface. If CS is tied low, the final rising SCLK edge of the SPI transaction resets the serial interface. The point at which the interface is reset corresponds to 16 x SCLKs for a normal read operation and up to 40 SCLKs when reading back ADC conversion data, plus the status and CRC headers. Single-Conversion Read Mode When using single-conversion read mode, the ADC_DATA register can be accessed in the same way as a normal SPI read transaction. The ADC_DATA register (Register 0x2C), is 24 bits wide. Therefore, 32 SCLKs are required to read a conversion result. tMCLK_DRDY tMCLK_HIGH MCLK tMCLK_LOW tDRDY_HIGH tDRDY DRDY t7 CS t1 t10 tSCLK t8 SCLK t4 t3 t9 16481-086 t2 DOUT/RDY Figure 87. Serial Interface Timing Diagram, Example Reflects Reading an ADC Conversion in Continuous Read Mode Rev. 0 | Page 50 of 76 Data Sheet AD7768-1 Continuous Read Mode To eliminate the overhead of needing to write a command to read the ADC data register each time, the user can place the ADC in continuous read mode so that the ADC register can be read directly after the data ready signal is pulsed. In continuous read mode, data is output on the falling edge of the first SCLK received. Therefore, only 24 SCLKs are required to read a conversion. In this continuous read mode, it is also possible to append one or both of the status or CRC headers (eight bits each) to the conversion result. If both the status and CRC headers are enabled, the data format is ADC data + status bits + CRC. When the RDY function is not used, the ADC conversion result can be read multiple times in the DRDY period, as is shown in Figure 88. When the RDY function is enabled, the DOUT/RDY pin goes high after reading the AD7768-1 conversion result and, therefore, the data cannot be read more than once (see Figure 89). Continuous readback is the readback mode used in PIN control mode. However, in this mode, the data output format is fixed. There is no option for RDY on the DOUT pin. See the Pin Control Mode Overview section for more details. When using continuous read mode with the LV_BOOST bit enabled (Bit 7 in the INTERFACE_FORMAT register, Address 0x14), it is necessary to re-enable LV_BOOST each time continuous read mode is exited. Exiting Continuous Read Mode To exit continuous read mode, write a key of 0x6C on the SDI, which allows access to the register map one more time and allows further configuration of the device. To comply with a normal SPI write, use the CS signal to reset the SPI interface after this key is entered. If CS cannot be controlled and is permanently held low, 16 SCLKs are needed to complete the transaction so that the SPI interface remains synchronized. For example, when CS is permanently tied low, write 0x006C to exit continuous read mode when using the 3-wire version of the interface. The exit command must be written between DRDY pulses to ensure that the device exits correctly. A software reset can also be written in this mode in the same way as the exit command, but by writing 0xAD instead of 0x6C. DRDY CS SCLK DOUT/RDY Z 0 DATA BEING READ 0 REPEAT BEING READ 0 16481-087 WAIT FOR TERMINATION CODE SDI Figure 88. Continuous ADC Read Data Format with RDY Function Disabled DRDY CS SCLK DOUT/RDY Z 1 0 DATA BEING READ 1 Figure 89. Continuous ADC Read Data Format with RDY Function Enabled on the DOUT/RDY Pin Rev. 0 | Page 51 of 76 16481-088 WAIT FOR TERMINATION CODE SDI AD7768-1 Data Sheet DATA CONVERSION MODES The four data conversion modes available in SPI control mode are as follows: * * * * Continuous conversion One shot conversion Single conversion Duty cycled conversion The default conversion mode is continuous conversion. A SYNC_IN pulse must be provided to the AD7768-1 after any change to the configuration of the device, including changing filter settings and data conversion modes. Continuous Conversion Mode In continuous conversion mode, the ADC continuously converts and a new ADC result is ready at an interval determined by the ODR, which is the default conversion operation in SPI control mode. This is the only data conversion mode in which the wideband filter is available. Two methods of data readback are available to the user in SPI control mode and are described in the Conversion Read Modes section. One Shot Conversion Mode Figure 90 shows the device operating in one shot conversion mode. In this mode, conversions occur on request by the master device, for example, the DSP or FPGA. The SYNC_IN pin receives the command initiating the data output. In one shot conversion mode, the ADC runs continuously. However, the SYNC_IN pin rising controls the point in time from which data is output. To receive data, the master device must pulse the SYNC_IN pin, which resets the filter and forces DRDY low. DRDY subsequently goes high to indicate to the master device that the device has valid settled data available. When the master asserts SYNC_IN and the AD7768-1 receives the rising edge of this signal, the digital filter is reset, the full settling time of the filter elapses before the data is settled, and the output is available. The duration of the settling time depends on the filter path and decimation rate. One shot conversion mode is only available for use with the sinc5 or sinc3 filters because these filters feature a minimal settling time. Continuous conversion mode is not available as an option for use with the low ripple FIR filter. When settled data is available, the DRDY signal pulses. The time from the SYNC_IN signal until the ADC path settles data (tSETTLE) is shown in Figure 90. After settled data is available, DRDY is asserted high, and the user can read the conversion result. The device then waits for another SYNC_IN signal before outputting more data. The settling time is calculated relative to the settling time of the filter used, with some added latency for starting the one shot conversion. This settling time limits the overall throughput achievable in one shot conversion mode. Because the ADC is sampling continuously, one shot conversion mode affects the sampling theory of the AD7768-1. Periodically sending a SYNC_IN pulse to the device is a form of subsampling of the ADC output. The bandwidth around this subsampling rate can now alias down to the baseband. Consider keeping the SYNC_IN pulse synchronous with the master clock to ensure coherent sampling and to reduce the effects of jitter on the frequency response, which otherwise heavily distort the output. Any SPI configuration of the AD7768-1 required is performed in continuous conversion mode before switching back to one shot conversion mode. SYNC_IN tSETTLED SETTLED DATA AVAILABLE SETTLED DATA AVAILABLE DOUT/RDY 16481-089 DRDY SCLK Figure 90. One Shot Conversion Mode, SYNC_IN Pin Driven with an External Source Rev. 0 | Page 52 of 76 Data Sheet AD7768-1 SCLK WRITE SYNC SDI tSPI _TO_SYNC SYNC_OUT SYNC_IN tSETTLE SETTLED DATA AVAILABLE SETTLED DATA AVAILABLE 16481-090 DOUT/RDY DRDY Figure 91. One Shot Conversion Mode, SYNC_IN Pulse Initiated by a Register Write Single-Conversion Mode In single-conversion mode, the ADC wakes up from standby, performs a conversion, and then returns to standby. Only use single-conversion mode when operating in low power and median power modes. The user must send a command to initiate the read and subsequently read back the ADC conversion result. Use a toggle of the SYNC_IN pin to exit the device from standby and to start a new conversion. Any SPI configuration of the AD7768-1 required must be performed in continuous conversion mode before then switching back to single-conversion mode. Duty Cycled Conversion Mode In duty cycled conversion mode, the ADC wakes up from standby, performs a conversion, and then returns to standby. The user can set the period between each conversion, and the ADC automatically performs the single conversion before returning to standby, repeating the single conversion performed by the ADC at a period specified by the user. Only use duty cycled conversion mode when operating in low power and median power modes. Duty cycled conversion mode allows a method to reduce the power consumption for dc point conversions, and to eliminate any overhead in timing and initiating the conversion. Use a toggle of the SYNC_IN pin to begin the duty cycled conversion mode sequence. DRDY toggles once when a settled result is reached. Then, the device enters standby one more time. The DUTY_CYCLE_RATIO register controls the determined idle time. SYNCHRONIZATION OF MULTIPLE AD7768-1 DEVICES An important consideration when using multiple AD7768-1 devices in a system is synchronization. The basic provision for synchronizing multiple devices is that each device is clocked with the same base MCLK signal. A SYNC_IN pulse must be provided to the AD7768-1 both after power-up and after any change to the configuration of the device. This pulse serves to flush out the digital filters and ensures that the device is in a known configuration, as well as synchronizing multiple devices in a system. The AD7768-1 offer three options to ease system synchronization. Choosing between the options depends on the system. However, the most basic consideration is whether the user can supply a synchronization pulse that is truly synchronous with the base MCLK signal. If a signal that is synchronous to the base MCLK signal cannot be provided, use one of the following methods: * * * Any SPI configuration of the AD7768-1 required must be performed in continuous conversion mode before switching back to duty cycled conversion mode. Rev. 0 | Page 53 of 76 Configure the GPIOx pin of one of the AD7768-1 devices in the system to be a START input. Apply a START pulse to the configured GPIOx pin. Route the SYNC_OUT pin output to the SYNC_IN input of that same device and all other devices that are to be synchronized. The AD7768-1 samples the asynchronous START pulse and generates a SYNC_OUT pulse related to the base MCLK signal for local distribution. Use synchronization over SPI (only available in SPI control mode). Write a synchronization command to one predetermined ADC device. Connect the SYNC_OUT pin of this device to its own SYNC_IN pin and to the SYNC_IN pin of any other device locally. Similar to the START pin method, the SPI synchronization is received by one device and, subsequently, the SYNC_OUT signal is routed to local devices to allow synchronization. AD7768-1 Data Sheet Synchronization in channel to channel isolated systems is shown in Figure 92. If a SYNC_IN signal synchronous to the base MCLK can be provided, apply the SYNC_IN synchronous signal to the SYNC_IN pin from a star point and connect directly to the pin of each AD7768-1 device. The SYNC_IN signal is sampled on the rising MCLK edge and, therefore, setup and hold times are associated with the SYNC_IN input relative to the AD7768-1 MCLK rising edge (see Figure 7). It is recommended to perform synchronization functions directly after the DRDY pulse. If the AD7768-1 SYNC_IN pulse occurs too close to the upcoming DRDY pulse edge, the upcoming DRDY pulse may still be output because the SYNC_IN pulse has not yet propagated through the device. In this case, SYNC_OUT is redundant and can remain opencircuit or tied to IOVDD. GPIOx can be used for a different purpose because it is not required for the START function. When using the SYNC_OUT function with an IOVDD voltage of 1.8 V, it is recommended to set the SYNC_OUT_POS_EDGE bit (Address 0x1D, Bit 6) to 1. AD7768-1 SYNCHRONIZATION LOGIC DIGITAL FILTER SYNC_IN SYNC_OUT DOUT/RDY SCLK SDI ISO AD7768-1 MCLK DSP/ FPGA SYNCHRONIZATION LOGIC DIGITAL FILTER SYNC_IN MASTER CLOCK SYNC_OUT DOUT/RDY SCLK SDI ISO Figure 92. Synchronization in Channel to Channel Isolated Systems Rev. 0 | Page 54 of 76 16481-091 MCLK Data Sheet AD7768-1 ADDITIONAL FUNCTIONALITY OF THE AD7768-1 * Reset After powering up the device, it is recommended to perform a full reset. There are multiple options available on the AD7768-1 to perform a reset, including * * * * Using the dedicated RESET pin. See the Pin Configuration and Function Descriptions section. When in continuous read mode, the AD7768-1 monitors for the exit command or a reset command of 0xAD. See the Exiting Continuous Read Mode section for more details. A software reset can be performed by two consecutive writes to the SYNC_RESET register (Register 0x1D). When CS is held low, it is possible to provide a reset by clocking in a 1 followed by 63 zeros on SDI, which is the SPI resume command reset function used to exit powerdown mode. The time taken from RESET to an SPI write must be at least 200 s. Status Header In SPI control mode, the status header can be output after the conversion result when operating the AD7768-1 in continuous read back mode. The status header mirrors the MASTER_ STATUS register (Register 0x2D). In PIN control mode, the status header is output by default after the conversion result. The status header contains the following bits and functions: * * * * * The MASTER_ERROR bit is an OR of all other errors present and can be monitored to provide a quick indication of a problem having occurred. The ADC_ERROR bit sets to 1 if any error is present in the ADC_DIAG_STATUS register (Address 0x2F). It is an OR of the error bits in the ADC_DIAG_STATUS register. The DIG_ERROR bit sets to 1 if any error is present in the DIG_DIAG_STATUS register (Address 0x30). It is an OR of the error bits in the DIG_DIAG_STATUS register. The ADC_ERR_EXT_CLK_QUAL bit sets if a valid clock is not detected (see the Clock Qualification section). The ADC_FILT_SATURATED bit sets to 1 if the digital filter is clipped on either positive or negative full scale. The clipping can be caused by the analog input exceeding the analog input range, or by a large step input to the device that causes a large overshoot in the digital filter. In addition, the filter may saturate if the ADC gain registers are incorrectly set. The combination of a full-scale signal and a large gain saturates the digital filter. * * * The ADC_FILT_NOT_SETTLED bit is set to 1 if the output of the digital filter is not settled. The digital filters are cleared following a RESET pulse, or after a SYNC_IN command is received. Table 13, Table 16, and Table 17 list the time for SYNC_IN to settled data for each filter type. When using the low ripple FIR filter, the filter not settled bit takes longer to update and propagate through the device than to read the status header. The filter not settled bit appears set when in fact the data output is settled. The worst case update delay is 128 MCLK cycles for the low ripple, wideband filter, decimate by 1024 setting. In this case, if the readback is delayed by 128 MCLK cycles, the filter not settled bit has time to update, and the time to settled data is equal to the data shown in Table 13, Table 16, and Table 17. The SPI_ERROR bit sets to 1 if any error is present in the SPI_DIAG_STATUS register (Address 0x2E). The bit is an OR of the error bits in the SPI_DIAG_STATUS register. The POR_FLAG bit detects if a reset or a temporary supply brown out occurred. In PIN control mode, instead of being the POR flag, this bit is always set to 1 and then detects if that the interface is operating correctly. Diagnostics Internal diagnostics are available on the AD7768-1 that allow the user to check both the functionality of the ADC and the environment in which the ADC is operating. The internal diagnostics are enabled in the conversion register (Register 0x18). To use the diagnostics, the device must be configured to low power mode, MCLK_DIV = MCLK/16, and the analog input precharge buffers must be enabled. The diagnostics available are as follows: * * * * Rev. 0 | Page 55 of 76 The temperature sensor is an on-chip temperature sensor that determines the approximate temperature. Temperature changes measured give approximately a 0.6 mV/C change in the dc converted voltage. For example, at ambient temperature, the conversion result is approximately 180 mV. A 50C increase in temperature reads back as approximately 210 mV, signaling, for example, a potential fault or the need to calibrate the system. The analog input short disconnects the AIN+ and AIN- pins from the external input and creates an internal short across the analog input pins that can detect a fault. The voltage converted is VREF+ for positive full scale, if selected. The voltage converted is VREF- for negative full scale, if selected. AD7768-1 Data Sheet APPLICATIONS INFORMATION ANALOG INPUT RECOMMENDATIONS The design of the AD7768-1 analog input circuitry has a significant effect on the overall performance of the system. The AD7768-1 incorporates precharge buffers on the analog inputs to aid the driver amplifier. Enabling the analog input precharge buffers allows a lower power amplifier to be used to drive the AD7768-1. See the Analog Inputs and Precharge Buffering section for more details. Recommended Driver Amplifiers Depending on the required input bandwidth to the ADC, or the power consumption considerations of the overall system, there are a range of amplifiers suitable to be paired with the AD7768-1 for a particular power mode. Table 25 describes the recommended driver amplifiers for the AD7768-1 based on the power mode selected. Each power mode selected ultimately corresponds to a modulator frequency and a maximum ODR. The driver amplifiers are selected for their suitability to settle the analog inputs for a particular power mode. The settings for both Table 25 and Table 26 are MCLK frequency = 16.384 MHz, input = 1 kHz, an applied tone of -0.5 dBFS, and a low ripple FIR filter is selected. Table 26 shows the benefits of the analog input precharge buffers. In this case, the ADA4807-2 is the ADC driver chosen to drive the AD7768-1 in fast power mode. Enabling the precharge buffers gives more than a 20 dB improvement in THD, allowing the amplifier to become a valid choice of the driver at the fastest data rate. Table 25. Amplifier Pairing Options for Various Power Modes for the Low Ripple FIR Filter AD7768-1 Power Mode Fast Median Low Power Amplifier ADA4940-1 ADA4896-2 ADA4807-2 ADA4805-2 ADA4805-2 LTC6363 Analog Input Precharge Buffer On On Off Off Off Off SNR (dB) 106.2 106 105.7 106.2 105.8 105.6 THD (dB) -117.3 -119.9 -121.3 -119.8 -120.5 -120 SNR (dB) 105.1 104.9 THD (dB) -104 -124.5 Table 26. Benefits of the Analog Input Precharge Buffers AD7768-1 Power Mode Fast Amplifier ADA4807-2 ADA4807-2 Analog Input Precharge Buffer Off On Rev. 0 | Page 56 of 76 Data Sheet AD7768-1 ANTIALIASING FILTER DESIGN CONSIDERATIONS 0 When designing the antialiasing filter for the AD7768-1, the modulator aliasing zones due to the modulator chopping (see the Antialiasing Filtering section) must be considered. If the environment in which the AD7768-1 operates is subject to large out of band tones at the input, the order of the antialiasing filter is critical. Figure 93 shows the roll-off for the input antialiasing filter from a simple second-order implementation to a more complex fourth-order roll-off. It is assumed in Figure 93 that the filter corner frequency is set at 3/4 x ODR for the decimate by 32 setting. Setting the corner frequency at 3/4 x ODR means that the flat pass band of the low ripple FIR filter can be maintained while also maximizing rejection at fMOD and 2 x fMOD. To prevent out of band tones appearing in band, at least a third-order antialiasing filter is needed to fully reject tones at 2 x fMOD. MODULATOR CHOP ALIAS x32 MODULATOR CHOP ALIAS x8 SECOND-ORDER AAF ROLL-OFF THIRD-ORDER AAF ROLL-OFF FOURTH-ORDER AAF ROLL-OFF AMPLITUDE (dB) -15 -35 -55 -75 -115 0.01 0.1 1 FREQUENCY (fIN/fMOD) 16481-192 -95 Figure 93. Combined Digital and Analog Filter Response for Various Orders of the Analog Antialiasing Filter One method of designing a third-order antialiasing filter is to use a multiple feedback architecture, as shown in Figure 94. Only one active component, the ADA4940-1 in the case of Figure 94, is needed to achieve a third-order roll-off response. The input to the ADA4940-1 is typically an instrumentation amplifier, such as the AD8421, for precision dc applications. This circuit can be tuned for a particular input range, noise, or power requirement, as necessary. 5V 3.3V 3.3V AVDD1 AVDD2 IOVDD 5V IN- REF+/REF- AIN+ AD7768-1 ADA4940-1 VCM IN+ AIN- -OUT VCM VCM AVSS DGND 16481-193 INSTRUMENTATION AMPLIFIER/ ANALOG INPUT ADR4540 +OUT Figure 94. Implementation of a Multiple Feedback, Low-Pass Filter Rev. 0 | Page 57 of 76 AD7768-1 Data Sheet RECOMMENDED INTERFACE 3. The AD7768-1 interface is flexible to allow the many modes of operation and for data output formats to work across different DSPs and microcontroller units (MCUs). To achieve maximum performance, the recommended interface configuration for reading conversion results is shown in Figure 95. This recommended implementation uses a synchronous SCLK to MCLK relationship. Recommended Interface for Reading Data The recommended interface for reading data is as follows: 4. 5. 6. 2. Tie the CS signal low during the conversion readback. Enter continuous readback mode to avoid needing to provide the address bits for the ADC_DATA register. Continuous readback mode is the default readback mode in PIN mode. 32 bits of data are clocked out, consisting of the 24-bit conversion result plus eight bits that can be selected to be either the status or CRC bits. In PIN mode, this is always the conversion result plus the eight status bits. Provide an SCLK that is a divided down version of MCLK. For example, SCLK = MCLK/2 in a case where decimate by 32 is selected. Clocking 32 bits ensures that the data readback operation fills the entire DRDY period when SCLK = MCLK/2. SCLK runs continuously. The readback spans the full DRDY period, thus spreading the dynamic current needed on IOVDD across the full ODR period. The DRDY signal can synchronize the data being read into the host controller. 3. 4. Resynchronization of the Recommended Interface Because the full ODR period is for clocking data, the RDY signal no longer flags after each LSB outputs. This signal only flags if the AD7768-1 is in continuous readback mode, or if the AD7768-1 does not count 32 SCLKs within 1 x tMCLK before DRDY, as is shown in Figure 95. The RDY function is only available in continuous readback mode. In normal readback, where the ADC_DATA register must be addressed each time, the DOUT line is reset 1 x tMCLK before DRDY, as per t10 in the Timing Specifications section. If DRDY is used, the device operates as normal, and conversion readback is timed from the DRDY pulse. In the case where RDY detects the beginning of each sample, and where the data readback loses synchronization, the SCLK timing can be recovered by one of the following two methods: Figure 95 shows how the recommended interface operates. The data read back spans the entire length of the DRDY period and the LSB remains until DRDY goes high for the next conversion. Initializing the Recommended Interface To configure the recommended interface, take the following steps: 1. 2. Configure the device settings, such as power mode, decimation ratio, filter type, and so on. Enter continuous readback mode. * Using CS to reset the interface and to observe the RDY transition. Stopping SCLK toggling until the RDY transition is detected one more time. * MCLK DRDY SCLK DRIVE EDGE SAMPLE EDGE SDI DOUT/RDY LSB + 1 SCLK = MCLK/2 t4 LSB t3 MSB MSB - 1 tMCLK_DRDY LSB REMAINS UNTIL DRDY GOES HIGH Figure 95. Recommended Interface for Reading Conversions, SPI Control, Continuous Readback Mode Rev. 0 | Page 58 of 76 16481-092 3. Synchronize the host controller with the DRDY or RDY pulse. See Figure 6 for details on the RDY behavior before data is clocked out. Generate SCLK based on the DRDY or RDY timing. SCLK is high when the DRDY signal goes high and transitions on the MCLK falling edges (see Figure 95) to ensure that the LSB can be read correctly as the DOUT/RDY output is reset on the DRDY rising edge. However, SCLK rising occurs before this transition. The MSB is clocked out on the next falling edge of SCLK. In PIN control mode, the LSB of the conversion output is the last bit of the status output. In PIN control mode, this bit is always 1 and, therefore, does not need to be read. 1. Configure the interface as follows to achieve the recommended operation: 1. 2. Issue a synchronization pulse to apply the changes to the digital domain and to reset the digital filter. Issue the pulse immediately after DRDY goes high. Data Sheet AD7768-1 PROGRAMMABLE DIGITAL FILTER If there are additional filter requirements outside of the digital filters offered by default on the AD7768-1, there is the added option of designing and uploading a custom digital filter to memory. This upload overwrites the default low ripple FIR filter coefficients to be replaced by a set of user defined coefficients. * * The AD7768-1 filter path has three separate stages: * * * The coefficients uploaded are subject to the following required conditions: Initial sinc filter Sinc compensation filter Low ripple FIR filter * The user cannot change the first two stages. The only programmable stage is the third stage, where the default low ripple FIR filter coefficients can be replaced by a set of userdefined coefficients. * The data rate into the third stage is double the final ODR due to a fixed decimation by two that occurs after the final stage of filtering. Therefore, the programmable FIR stage receives data at a rate that is decimated from fMOD by rates of 16, 32, 64, 128, 256, and 512. After the final decimation by 2, the overall decimation values are given and are in the range of decimate by 32 to decimate by 1024. The data rates into the final FIR stage are listed in Table 27. Table 27 describes the data rate into the final filter stage for each power mode, assuming the correct MCLK_DIV setting is selected for the corresponding power mode. For example, when median power mode is selected, MCLK_DIV must be MCLK/4. Filter Coefficients The AD7768-1 low ripple FIR filter uses a set of 112 coefficients. By writing the appropriate key to the AD7768-1, these coefficients can be overwritten. Then, the customized filter coefficients can upload and lock into memory. If the AD7768-1 is reset, these coefficients must be rewritten. The number of coefficients in a full set is 112, which is made up of 56 coefficients that are mirrored to make the total coefficients sum 112. Therefore, only 56 coefficients are written to during any one filter upload. Coefficients written must be in integer form. The format used is twos complement. The coefficient data register to be written is 24 bits wide, which is the only 24-bit register write used on the AD7768-1. Only 23 bits are used for the coefficients. The remaining MSB is a control bit, detailed in the Register 0x33. Filter coefficients are scaled such that the 56 coefficients must sum to 222. The total (112) coefficients, therefore, sum to 223. For example, if the filter coefficient to be written to is -0.0123, this value is scaled to -0.0123 x 222 = -51,590. In twos complement format, this value is represented by 0x7F367A. Each filter coefficient is written by first selecting the coefficient address. Then, a separate write of the data occurs, which is repeated for all 56 coefficients from Address 0 to Address 55. Because the FIR size cannot be changed, the filter group delay remains fixed at 34/ODR when using the programmable filter option. If a shorter number of coefficients are required, padding the end coefficients with zeros can achieved this requirement. The group delay of the uploaded filter must always be equal to the group delay of the default AD7768-1 FIR filter that equals approximately 34/ODR. Each time either the coefficient address register or the coefficient data register (COEFF_CONTROL or COEFF_DATA) are accessed, the user must wait a period before performing another read or write. The following equation determines the wait time: tWAIT = 512/MCLK This wait time allows time for the register contents to update. Then, the coefficients are written to memory. Table 27. Data Rates into the Final FIR Input Stage Power Mode Fast Median Low Power 512 kHz Yes Not applicable Not applicable Input to Third Stage, Programmable FIR (MCLK = 16.384 MHz) 256 kHz 128 kHz 64 kHz 32 kHz 16 kHz 8 kHz 4 kHz Yes Yes Yes Yes Yes Not applicable Yes Yes Yes Yes Yes Yes Not applicable Not applicable Not applicable Yes Yes Yes Yes Yes Rev. 0 | Page 59 of 76 2 kHz Not applicable Not applicable Yes AD7768-1 Data Sheet Upload Sequence To program the filter, take the following steps: To program a user defined set of filter coefficients, perform the following sequence: 1. 1. 2. 3. 4. 5. 6. 7. 8. 9. 4. a. Set the coefficient address to Address 0. 6. b. Enable the access to memory (COEFFACCESSEN = 1). c. Allow a write to the coefficient memory (COEFFWRITEEN = 1). The address of the first coefficient is selected. Write the required coefficient to the COEFF_DATA register (Register 0x33), and then wait for tWAIT sec. Always wait tWAIT sec between writes to Register 0x32 and Register 0x33. Repeat Step 4 and Step 5 for each of the 56 coefficients. For example, write 0xC1 to COEFF_CONTROL to select coefficient Address 1. After waiting tWAIT sec, enter the coefficient data. Increment the data until Coefficient 55 is reached. (Coefficient 55 is a write of 0xF7 to COEFF_ CONTROL.) Disable writing to the coefficients by first writing 0x80 to COEFF_CONTROL. Then, wait tWAIT sec. Then, write 0x00 to COEFF_CONTROL to disable coefficient access. Set USERCOEFFEN = 1 by writing 0x800 to COEFF_DATA to allow the user to toggle the synchronization pulse and to begin reading data. Exit the filter upload by writing 0x55 to the ACCESS_KEY register (Register 0x34). Send a synchronization pulse to the AD7768-1. One way of sending this pulse is by writing to the SYNC_RESET register (Register 0x1D). The filter upload is now complete. The RAM CRC error check fails when the digital filter uploads. To disable this check, use the DIG_DIAG_ENABLE register (Register 0x2A). See the Register Details for further details on the register bits. 3. 5. 7. 8. 9. 10. 11. 12. 13. 14. 15. 16. 17. 0 -50 AMPLITUDE (dB) 2. Write 0x4 to the filter bits in the DIGITAL_FILTER register (Register 0x19, Bits[6:4]). The following key must be written to access the filter upload. First, write 0xAC to the ACCESS_KEY register (Register 0x34). Second, write 0x45 to the ACCESS_KEY register. Bit 0 (the key bit) of the ACCESS_KEY register can be read back to check if the key is entered correctly. Write 0xC0 to the COEFF_CONTROL register (Register 0x32). Wait for tWAIT sec to perform the following actions: Write 0x4 to the filter bits in the DIGITAL_FILTER register (Register 0x19, Bits[6:4]). Enter the key by writing to the ACCESS_KEY register (Register 0x34). Write 0xC0 to the COEFF_CONTROL register, Register 0x32, (COEFFADDR = 0, COEFFACCESSEN = 1, and COEFFWRITEEN = 1). Wait tWAIT sec. Write 0x000000 to COEFF_DATA (Register 0x33). Wait tWAIT sec. Write 0xC1 to the COEFF_CONTROL register (COEFFADDR = 1). Wait tWAIT sec. In this case, the coefficient in Address 0 is equal to Address 1 and, therefore, the value in COEFF_DATA does not change. Write 0xC2 to the COEFF_CONTROL register (COEFFADDR = 2). Wait tWAIT sec. Increment the address of the COEFF_CONTROL register (COEFFADDR = 23) until the write of 0xD7. Continue to wait tWAIT sec. Write 0xD8 to COEFF_CONTROL (COEFFADDR = 24). Write 0x010000 to COEFF_DATA. Wait tWAIT sec. Write 0xD9 to COEFF_CONTROL (COEFFADDR = 25). Wait tWAIT sec. Write 0xDA to COEFF_CONTROL (COEFFADDR = 26) Wait tWAIT sec. Increment the address of the COEFF_CONTROL register (COEFFADDR = 55) until the write 0xF7. Wait tWAIT sec. Disable write and access by first writing 0x80 to the COEFF_CONTROL register. Wait tWAIT sec. Then, write 0x00 to the COEFF_CONTROL register. Set USERCOEFFEN = 1 to allow the user to toggle synchronization without reloading the default coefficients. (Write 0x800000 to COEFF_DATA.) Exit the write by writing 0x55 to the ACCESS_KEY register. Toggle synchronization. Gather data. The resulting filter profile is shown in Figure 96. -100 -150 Example Filter Upload Rev. 0 | Page 60 of 76 -200 -250 0 20 40 60 80 100 FREQUENCY (kHz) Figure 96. Example Filter Profile Upload 120 140 16481-196 The following sequence programs a sinc1 filter. The coefficients in Address 0 to Address 23 = 0. The coefficients from Address 24 to Address 55 = 131,072 (222/32). When MCLK = 16.384 MHz and ODR = 256 kHz, the filter notch appears at 8 kHz and multiplies of 8 kHz. This filter provides low noise and is recognizable by the distinctive filter profile shown in Figure 96. Data Sheet AD7768-1 Filter Upload Verification Radiated Immunity To check that the filter coefficients are uploaded correctly, it is possible to read back the values written to the COEFF_DATA register. This read can be performed after an upload by taking the following steps: Radiated immunity testing was carried out as per IEC 62132-2. The test characterizes the immunity to electromagnetic interference (EMI) from radio frequencies during the normal operation of the device. The test frequency is from 150 kHz to 1 GHz, and the results seen in Table 28 were collected with both amplitude modulated (AM) and continuous wave (CW) interference applied. The AD7768-1 achieves Class A performance for both AM and CW radiated immunity to the maximum tested rating of 100 V/m. 1. 2. 3. 4. 5. 6. 7. Enter the key by writing to the ACCESS_KEY register (Register 0x34). First, write 0xAC to the ACCESS_KEY register, and then write 0x45 to the ACCESS_KEY register. Write 0x80 to the COEFF_CONTROL register, Register 0x32, (COEFFADDR = 0, COEFFACCESSEN = 1, COEFFWRITEEN = 0). Wait tWAIT sec. Read back the contents of the 24-bit COEFF_DATA register (Register 0x33). Check that the coefficient matches the uploaded value. Write 0x81 to the COEFF_CONTROL register (COEFFADDR = 1). Wait tWAIT sec. Read the 24-bit COEFF_DATA register for Address 1. Increment and continue to read back the data. Continue to wait tWAIT sec between updates to the COEFF_CONTROL register. Disable the coefficient access by writing 0x00 to the COEFF_CONTROL register. Exit the readback process by writing 0x55 to the ACCESS_KEY register. ELECTROMAGNETIC COMPATIBILITY (EMC) TESTING The AD7768-1 is suitable for a wide variety of applications, including applications requiring isolated channels in an industrial environment, or in condition-based monitoring solutions. To ensure robust operation in harsh environments, the AD7768-1 was tested at an IC level for various EMC standards. The EMC testing was carried out to IEC standards and includes radiated immunity (IEC 62132-2), radio frequency radiated emissions (IEC 61967-2) and Electrical Fast Transients (EFT, IEC 62215-3). The decoupling capacitors required for correct operation of the device are in place for any EMC testing carried out. Table 28. Radiated Immunity Test Results as per IEC 62132-2 Standard Test Type AM CW Test Level (V/m) 100 100 Class A A Radiated Emissions Radiated emissions testing was carried out as per IEC 61967-2. The test characterizes the electromagnetic frequencies generated during normal operation of the device. The test frequency was from 150 kHz to 1 GHz. The results shown in Table 29 were collected with an externally applied MCLK equal to 16.384 MHz applied to the device. The highest amplitudes radiated from the devices measured occurred at multiples of the MCLK frequency. Table 29. Maximum Radiated Emissions Measured as per the IEC 61967-2 Standard, MCLK = 16.384 MHz, Low Ripple FIR Filter, Fast Power Mode Frequency (MHz) 65.52 32.76 49.14 Amplitude (dB V) 22.37 22.15 20.22 Electrical Fast Transients (EFTs) EFT testing was carried out as per the IEC 62215-3 standard. EFT testing involves coupling multiple fast transient pulses to the pins of the device under test (DUT). The input is a transient pulse train applied at both the 5 kHz and 100 kHz input frequencies, according to IEC 61000-4-4. The results of the EFT testing are shown in Table 30, with the AD7768-1 achieving Class A performance up to 1 kV. Table 30. EFT Testing Results AD7768-1 Pin AVDD1 AVDD2 IOVDD Rev. 0 | Page 61 of 76 Test Level (V) 1000 1000 1000 Performance Class A A A AD7768-1 Data Sheet AD7768-1 SUBSYSTEM LAYOUT The layout for the AD7768-1 and the surrounding subsystem is approximately shown in Figure 97. Analog inputs, reference inputs, and analog supplies are applied to the top left corner. The IOVDD supply, digital interface, and clocking are all applied to the bottom right corner. ADC REFERENCE ANALOG SUPPLY ADC DRIVER GPIOs MCLK INPUT ANALOG INPUTS AD7768-1 SPI INTERFACE SYNCHRONIZATION Figure 97. Subsystem Layout Rev. 0 | Page 62 of 76 16481-197 IOVDD SUPPLY Data Sheet AD7768-1 REGISTER SUMMARY Table 31. Register Summary Reg (Hex) 03 04 16 Bit Name CHIP_TYPE PRODUCT_ ID_L PRODUCT_ ID_H CHIP_GRADE SCRATCH_ PAD VENDOR_L VENDOR_H INTERFACE_ FORMAT POWER_ CLOCK Analog 17 ANALOG2 [7:0] 18 Conversion [7:0] 19 DIGITAL_ FILTER SINC3_DEC_ RATE_MSB SINC3_DEC_ RATE_LSB DUTY_ CYCLE_RATIO SYNC_RESET [7:0] 05 06 0A 0C 0D 14 15 1A 1B 1C 1D Bits [7:0] [7:0] Bit 7 Bit 6 Bit 5 [7:0] [7:0] [7:0] [7:0] [7:0] RESERVED EN_SPI_CRC PRODUCT_ID[7:0] Reset 0x07 0x01 R/W R R PRODUCT_ID[15:8] 0x00 R Bit 0 0x00 0x00 R R/W 0x56 0x04 0x00 R R R/W 0x00 R/W 0x00 R/W 0x00 R/W CONV_MODE 0x00 R/W DEC_RATE 0x00 R/W 0x00 R/W DEVICE_REVISION VID[7:0] VID[15:8] STATUS_EN CONVLEN CRC_TYPE [7:0] CLOCK_SEL MCLK_DIV [7:0] REF_BUF_POS REF_BUF_NEG CHOP_ FREQUENCY EN_RDY_ DOUT POWER_ MOD_ DOWN OUTPUT Reserved Reserved DIAG_MUX_SELECT EN_60HZ_REJ [7:0] CONV_ DIAG_ SELECT Reserved Filter Reserved Reserved EN_CONT_ READ PWRMODE AIN_ BUFF_ POS_OFF VCM AIN_ BUFF_ NEG_OFF SINC3_DEC[12:8] [7:0] SINC3_DEC[7:0] 0x00 R/W [7:0] IDLE_TIME 0x00 R/W 0x80 R/W [7:0] SPI_START UGPIO_EN SYNC_OUT_ POS_EDGE GPIO2_OPEN_ DRAIN_EN 1F GPIO_WRITE [7:0] Reserved 20 GPIO_READ [7:0] Reserved 21 22 23 24 25 26 28 OFFSET_HI OFFSET_MID OFFSET_LO GAIN_HI GAIN_MID GAIN_LO SPI_DIAG_ ENABLE [7:0] [7:0] [7:0] [7:0] [7:0] [7:0] [7:0] 29 ADC_DIAG_ ENABLE [7:0] 2A DIG_DIAG_ ENABLE [7:0] 2C ADC_DATA [23:16] SPI_DIAG_ STATUS Bit 1 Value [7:0] 2E Bit 2 Grade GPIO_ CONTROL MASTER_ STATUS Bit 3 Class [7:0] 1E 2D Bit 4 Reserved [15:8] [7:0] [7:0] [7:0] Reserved GPIO1_ OPEN_ DRAIN_EN Reserved Reserved EN_ERR_ DLDO_ PSM Reserved MASTER_ERROR ADC_ERROR Reserved GPIO0_ OPEN_ DRAIN_EN EN_GPIO_ START Reserved GPIO3_ OP_EN GPIO2_ OP_EN GPIO1_ OP_EN GPIO0_ OP_EN 0x00 R/W GPIO_ WRITE_3 GPIO_ READ_3 GPIO_ WRITE_2 GPIO_ READ_2 GPIO_ WRITE_1 GPIO_ READ_1 GPIO_ WRITE_0 GPIO_ READ_0 0x00 R/W 0x00 R 0x00 0x00 0x00 0x00 0x00 0x00 0x10 R/W R/W R/W R/W R/W R/W R/W Offset[23:16] Offset[15:8] Offset[7:0] Gain[23:16] Gain[15:8] Gain[7:0] EN_ERR_ EN_ERR_ SPI_ SPI_CLK_ IGNORE CNT EN_ERR_ Reserved ALDO_ PSM EN_ERR_ EN_ERR_ MEMMAP_ RAM_CRC CRC ADC_READ_DATA[23:16] DIG_ ERROR ADC_READ_DATA[15:8] ADC_READ_DATA[7:0] ADC_ERR_ ADC_FILT_ EXT_CLK_ SATURATED QUAL ERR_SPI_ ERR_SPI_ IGNORE CLK_CNT Rev. 0 | Page 63 of 76 SPI_RESET EN_ERR_ SPI_RD EN_ERR_ SPI_WR Reserved EN_ERR_ FILTER_ SATURATED EN_ERR_ FILTER_ NOT_ SETTLED Reserved EN_ERR_ EXT_CLK_ QUAL 0x07 R/W EN_FREQ_ COUNT 0x0D R/W 0x000 000 R EN_ERR_ FUSE_CRC ADC_FILT_ NOT_ SETTLED ERR_ SPI_RD SPI_ ERROR POR_FLAG 0x00 R ERR_ SPI_WR ERR_SPI_ CRC 0x00 R/W AD7768-1 Reg (Hex) 2F Data Sheet Bit Name ADC_DIAG_ STATUS Bits [7:0] 30 DIG_DIAG_ STATUS [7:0] 31 [7:0] 33 MCLK_ COUNTER COEFF_ CONTROL COEFF_DATA 34 ACCESS_KEY 32 [7:0] [23:16] [15:8] [7:0] [7:0] Bit 7 Bit 6 Reserved Reserved COEFFACCESSEN USERCOEFFEN Bit 5 ADC_ERR_ DLDO_ PSM Bit 4 ADC_ERR_ ALDO_ PSM Bit 3 Reserved ERR_ ERR_RAM_ MEMMAP_ CRC CRC MCLK_COUNTER COEFFWRITEEN Bit 2 ADC_FILT_ SATURATED ERR_FUSE_ CRC Bit 1 Bit 0 ADC_ ADC_ FILT_ ERR_EXT_ NOT_ CLK_QUAL SETTLED Reserved COEFFADDR[5:0] COEFFDATA[22:16] COEFFDATA[15:8] COEFFDATA[7:0] Reserved Rev. 0 | Page 64 of 76 Key Reset 0x00 R/W R 0x00 R 0x00 R 0x00 R/W 0x000 000 R/W 0x00 R Data Sheet AD7768-1 REGISTER DETAILS COMPONENT TYPE REGISTER Address: 0x03, Reset: 0x07, Name: CHIP_TYPE Table 32. Bit Descriptions for CHIP_TYPE Bits [7:4] [3:0] Bit Name Reserved Class Description Reserved. Chip type. 111: analog to digital converter. Reset 0x0 0x7 Access R R UNIQUE PRODUCT ID REGISTERS Address: 0x04, Reset: 0x01, Name: PRODUCT_ID_L Table 33. Bit Descriptions for PRODUCT_ID_L Bit(s) [7:0] Bit Name PRODUCT_ID[7:0] Description Product ID [7:0] Reset 0x1 Access R Address: 0x05, Reset: 0x00, Name: PRODUCT_ID_H Table 34. Bit Descriptions for PRODUCT_ID_H Bit(s) [7:0] Bit Name PRODUCT_ID[15:8] Description Product ID [15:8] Reset 0x0 Access R Reset 0x0 0x0 Access R R DEVICE GRADE AND REVISION REGISTER Address: 0x06, Reset: 0x00, Name: CHIP_GRADE Table 35. Bit Descriptions for CHIP_GRADE Bit(s) [7:4] [3:0] Bit Name Grade DEVICE_REVISION Description Device grade Device revision ID USER SCRATCHPAD REGISTER Address: 0x0A, Reset: 0x00, Name: SCRATCH_PAD Table 36. Bit Descriptions for SCRATCH_PAD Bit(s) [7:0] Bit Name Value Description Scratch pad; read and/or write area communication Reset 0x0 DEVICE VENDOR ID REGISTERS Address: 0x0C, Reset: 0x56, Name: VENDOR_L Table 37. Bit Descriptions for VENDOR_L Bit(s) [7:0] Bit Name VID[7:0] Description Vendor ID [7:0]. Analog Devices vendor ID. Reset 0x56 Access R Reset 0x4 Access R Address: 0x0D, Reset: 0x04, Name: VENDOR_H Table 38. Bit Descriptions for VENDOR_H Bit(s) [7:0] Bit Name VID[15:8] Description Vendor ID [15:8]. Analog Devices vendor ID. Rev. 0 | Page 65 of 76 Access R/W AD7768-1 Data Sheet INTERFACE FORMAT CONTROL REGISTER Address: 0x14, Reset: 0x00, Name: INTERFACE_FORMAT Table 39. Bit Descriptions for INTERFACE_FORMAT Bit(s) 7 Bit Name LV_BOOST 6 EN_SPI_CRC 5 CRC_TYPE 4 STATUS_EN 3 CONVLEN 2 EN_RDY_DOUT 1 0 Reserved EN_CONT_READ Description Boosts drive strength of SPI output for use with IOVDD levels of 1.8 V, or when a high capacitive load is present on the DOUT/RDY pin. The default state is LV_BOOST enabled when in PIN control mode. 0: disables LV_BOOST. 1: enables LV_BOOST. This bit must be re-enabled following an exit from continuous read mode, if applicable. Activates CRC on all SPI transactions. 0: disable CRC function on all SPI transfers. 1: enable CRC function on all SPI transfers. Selects CRC method as XOR or 8-bit polynomial. 1: XOR instead of CRC (applied to read transactions only). 0: CRC bits are based on CRC-8 polynomial. CRC check of interface transfers uses 8-bit CRC polynomial. Enables status bits output. In SPI control mode, the status bits can be output after the ADC conversion result by setting the bits in this bit field. In PIN control mode, the status bits are output after the ADC conversion result by default. 0: disable output of status bits with ADC conversion result in continuous read mode. 1: output status bits with ADC conversion result in continuous read mode. Conversion result output length. 0: full, 24-bit. 1: output only 16 MSB of the ADC result. Enables the RDY signal on the DOUT/RDY pin. Enables the RDY indicator on the DOUT/RDY pin in continuous read mode. By default, when in continuous read mode, the DOUT/RDY pin indicates when new ADC conversion data is ready. Setting this bit causes DOUT/RDY to stop signaling the availability of ADC conversion data. 0: enables RDY function on SDO in continuous read mode. 1: disables RDY function on SDO in continuous read mode. Reserved. Continuous read enable bit. 0: disables continuous read mode. 1: enables continuous read mode. Reset 0x0 Access R/W 0x0 R/W 0x0 R/W 0x0 R/W 0x0 R/W 0x0 R/W 0x0 0x0 R R/W Reset 0x0 Access R/W 0x0 R/W POWER AND CLOCK CONTROL REGISTER Address: 0x15, Reset: 0x00, Name: POWER_CLOCK Table 40. Bit Descriptions for POWER_CLOCK Bit(s) [7:6] Bit Name CLOCK_SEL [5:4] MCLK_DIV Description Options for setting the clock used by the device. 0: CMOS clock on MCLK/XTAL2. 1: crystal oscillator. 10: LVDS input enable. 11: internal coarse RC clock (diagnostics). Sets the division of the MCLK to create the ADC modulator frequency (fMOD). 0: modulator CLK is equal to master clock divided by 16. 1: modulator CLK is equal to master clock divided by 8. 10: modulator CLK is equal to master clock divided by 4. 11: modulator CLK is equal to master clock divided by 2. Rev. 0 | Page 66 of 76 Data Sheet Bit(s) 3 Bit Name POWER_DOWN 2 MOD_OUTPUT [1:0] PWRMODE AD7768-1 Description Places device into a power-down state. All blocks including the SPI are powered down. The standard SPI is not active in this state. Power-down is the lowest power consumption mode. To enter power-down mode, write 0x08 to this register. If the user attempts to set Bit 3 while also setting other bits in this register, the SPI write command is ignored, the device does not enter power-down, and the other bits are not set. Power-down mode can be exited in three ways: by a reset using the AD7768-1 RESET pin, by issuing the SPI resume command over SDI and SCLK, or by using the power cycle of the device. 0: device powered on. 1: device powered down. Selects modulator output mode. Selecting modulator mode forces the power mode to low power mode and ignores any user changes to the power mode bits (PWRMODE, Bits[1:0]) in this register. 0: disables raw modulator output. 1: enables raw modulator output. Sets the power consumption mode of the ADC core. This setting, in conjunction with MCLK_DIV, creates the conditions for power scaling the ADC vs. input bandwidth/throughput. 0: low power mode. 10: median power mode. 11: fast power mode. Reset 0x0 Access R/W 0x0 R/W 0x0 R/W Reset 0x0 Access R/W 0x0 R/W 0x0 0x0 R R/W 0x0 R/W ANALOG BUFFER CONTROL REGISTER Address: 0x16, Reset: 0x00, Name: Analog Used to turn on or off front end buffering. Table 41. Bit Descriptions for Analog Bit(s) [7:6] Bit Name REF_BUF_POS [5:4] REF_BUF_NEG [3:2] 1 Reserved AIN_BUFF_POS_OFF 0 AIN_BUFF_NEG_OFF Description Buffering options for the reference positive input. 0: precharge reference buffer on. 1: unbuffered reference input. 10: full reference buffer on. Buffering options for the reference negative input. 0: precharge Reference buffer on. 1: unbuffered input. 10: full Reference buffer on. Reserved. AIN+ precharge buffer disabled. Setting this bit disables the precharge buffer on the positive analog input. 0: AIN+ precharge buffer enabled. 1: AIN+ precharge buffer disabled. AIN- precharge buffer disabled. Setting this bit disables the precharge buffer on the negative analog input. 0: AIN- precharge buffer enabled. 1: AIN- precharge buffer disabled. Rev. 0 | Page 67 of 76 AD7768-1 Data Sheet VCM CONTROL REGISTER Address: 0x17, Reset: 0x00, Name: ANALOG2 Table 42. Bit Descriptions for ANALOG2 Bit(s) 7 Bit Name CHOP_FREQUENCY [6:3] [2:0] Reserved VCM Description Selects the chop frequency for use within the modulator. 0: sets the chopping frequency of the modulator. This is the default chop setting of fMOD/32. Setting the chop rate to fMOD/32 gives the best offset and offset drift performance. 1: sets the chopping frequency of the modulator. This sets the chop rate to fMOD/8. Setting the chop rate to fMOD/8 allows the user to push the first chop alias further from the pass band. See Figure 75. Reserved. Sets output from the VCM pin. The VCM output voltage can be used as a common-mode voltage within the amplifier preconditioning circuits external to the AD7768-1. 000: VCM output set to (AVDD1 - AVSS)/2. 001: VCM output set to 2.5 V. 010: VCM output set to 2.05 V. 011: VCM output set to 1.9 V. 100: VCM output set to 1.65 V. 101: VCM output set to 1.1 V. 110: VCM output set to 0.9 V. 111: VCM output off. Reset 0x0 Access R/W 0x0 0x0 R R/W Reset 0x0 Access R/W 0x0 R/W 0x0 R/W CONVERSION SOURCE SELECT AND MODE CONTROL REGISTER Address: 0x18, Reset: 0x00, Name: Conversion Table 43. Bit Descriptions for Conversion Bit(s) [7:4] Bit Name DIAG_MUX_SELECT 3 CONV_DIAG_SELECT [2:0] CONV_MODE Description Selects which signal to route through the diagnostic mux. Perform diagnostic checks in low power mode only. 0: temperature sensor. 1000: AIN short (zero check). 1001: positive full scale. 1010: negative full scale. Selects the input for conversion as AIN or the diagnostic mux. 0: set the input for conversion from AIN. 1: set the input for conversion from the diagnostic mux. Sets the conversion mode of the ADC. 000: continuous conversion mode. The modulator is converting continuously. Continuous DRDY pulse for every filter conversion. 001: continuous one shot mode. One shot is the method of using the SYNC_IN time to start a conversion. It is similar to a conversion start signal when using one shot mode. The ADC modulator is continuously running while waiting on a SYNC_IN rising edge. On release of a pulse (low to high transition) to the SYNC_IN pin, a new conversion begins, converting and integrating over the settling time of the filter selected. DRDY toggles when the conversion completes, indicating it is available for readback over the SPI. 010: single-conversion standby mode. In single-conversion standby mode, the ADC runs one conversion with the selected filter, sampling and integrating over the full settling time of the filter before providing a single conversion result. After the conversion is complete, the ADC goes into standby. Initiating another single conversion from standby means that there is a start-up time to come out of standby before the ADC begins converting to produce the single conversion. This mode is recommended for use in low power mode. Rev. 0 | Page 68 of 76 Data Sheet Bit(s) Bit Name AD7768-1 Description 011: periodic conversion standby mode. Low power periodic conversion is a method of setting the single conversion to run in a timed loop. A separate register sets the ratio for the time spent in standby vs. converting. The ADC automatically comes out of standby periodically, performs a single conversion, and then returns to standby again without the need for the user to initiate the single conversion over the SPI. 100: standby. Sets the device to standby mode. 101: sets the device to standby mode. 110: sets the device to standby mode. 111: sets the device to standby mode. Reset Access Reset 0x0 Access R/W 0x0 R/W 0x0 0x0 R R/W DIGITAL FILTER AND DECIMATION CONTROL REGISTER Address: 0x19, Reset: 0x00, Name: DIGITAL_FILTER Table 44. Bit Descriptions for DIGITAL_FILTER Bit(s) 7 Bit Name EN_60HZ_REJ [6:4] Filter 3 [2:0] Reserved DEC_RATE Description For use with the sinc3 filter only. First, program the sinc3 filter to output at 50 Hz. Subsequently selecting the EN_60HZ_REJ bit allows one zero of the sinc3 filter to fall at 60 Hz. This bit only enables rejection of both 50 Hz and 60 Hz if it is set in combination with programming the sinc3 filter for the 50 Hz ODR. 0: sinc3 filter optimized for single-frequency rejection, 50 Hz or 60 Hz. 1: filter operation is modified to allow both 50 Hz and 60 Hz rejection. Selects the style of filter for use. 000: sinc5 filter. Decimate x32 to x1024. Use the DEC_RATE bits to select one of the six available decimation rates from x32 to x1024. 001: sinc5 filter. Decimate x8 only. Enables a maximum data rate of 1 MHz. This path allows viewing of wider bandwidth; however, it is quantization noise limited so that output data is reduced to 16 bits. 010: sinc5 filter. Decimate x16 only. Enables a maximum data rate of 512 kHz. This path allows viewing of wider bandwidths. However, it is quantization noise limited so that output data is reduced to 16 bits. 011: sinc3 filter. Decimation rate is selected via 13 bits in sinc 3 decimation rate register. The sinc3 filter can be tuned to reject 50 Hz or 60 Hz, and with the EN_60HZ_REJ bit can allow rejection of both 50 Hz and 60 Hz. Decimation rate is selected via SINC3_DEC bits in sinc3 decimation rate MSB and LSB registers. The sinc3 filter can be tuned to reject 50 Hz or 60 Hz and with the EN_60HZ_REJ bit set can allow rejection of both 50 Hz and 60 Hz when used with a 16.384 MHz MCLK. 100: low ripple FIR filter. FIR filter with low ripple pass band and sharp transition band. Use DEC_RATE bits to select one of six available decimation rates from x32 to x1024. 101: not used. 110: not used. 111: not used. Reserved. Selects the decimation rate for the sinc5 filter and the brick wall, low-pass FIR filter. 0: decimate x32. 1: decimate x64. 10: decimate x128. 11: decimate x256. 100: decimate x512. 101: decimate x1024. 110: decimate x1024. 111: decimate x1024. Rev. 0 | Page 69 of 76 AD7768-1 Data Sheet SINC3 DECIMATION RATE (MSB REGISTER) Address: 0x1A, Reset: 0x00, Name: SINC3_DEC_RATE_MSB Table 45. Bit Descriptions for SINC3_DEC_RATE_MSB Bit(s) [7:5] [4:0] Bit Name Reserved SINC3_DEC[12:8] Description Reserved. Determines the decimation rate used with the sinc3 filter. Value entered is incremented by 1 and multiplied by 32 to give the actual DEC_RATE. Reset 0x0 0x0 Access R R/W Reset 0x0 Access R/W SINC3 DECIMATION RATE (LSB REGISTER) Address: 0x1B, Reset: 0x00, Name: SINC3_DEC_RATE_LSB Table 46. Bit Descriptions for SINC3_DEC_RATE_LSB Bit(s) [7:0] Bit Name SINC3_DEC[7:0] Description Determines the decimation rate of used with the sinc3 filter. Value entered is incremented by 1 and multiplied by 32 to give the actual DEC_RATE. PERIODIC CONVERSION RATE CONTROL REGISTER Address: 0x1C, Reset: 0x00, Name: DUTY_CYCLE_RATIO DUTY_CYCLE_RATIO sets the time used in periodic conversion mode. Only use periodic conversion mode in median mode or low power mode. Table 47. Bit Descriptions for DUTY_CYCLE_RATIO Bit(s) [7:0] Bit Name IDLE_TIME Description Sets idle time for periodic conversion when in standby. A 1 in this registers corresponds to time for one output from filter selected. The value in this register is incremented by one and doubled. Reset 0x0 Access R/W SYNCHRONIZATION MODES AND RESET TRIGGERING REGISTER Address: 0x1D, Reset: 0x80, Name: SYNC_RESET Table 48. Bit Descriptions for SYNC_RESET Bit(s) 7 Bit Name SPI_START 6 SYNC_OUT_POS_EDGE [5:4] 3 Reserved EN_GPIO_START 2 [1:0] Reserved SPI_RESET Description Trigger START signal. Allows user to initiate a SYNC_OUT pulse over the SPI. Setting this bit low drives a low pulse through SYNC_OUT that can be used as a SYNC_IN signal to the same device and other AD7768-1 devices where synchronized sampling is required. This bit clears itself after use. SYNC_OUT drive edge select. Setting this bit causes SYNC_OUT to be driven low by the positive edge of MCLK. Device default is that SYNC_OUT is driven low on the negative edge of MCLK. Reserved. Enable START function on the GPIO input. Allows the user to use one of the GPIOx pins as a START input pin. When enabled, a low pulse on the START input generates a low pulse through SYNC_OUT that can be used as a SYNC_IN signal to the same device and other AD7768-1 devices where synchronized sampling is required. When enabled GPIO3 becomes the START input. While the START function is enabled, the GPIOx pins cannot be used for general-purpose input/output reading and writing. The remaining GPIOs are set to outputs. 0: disabled 1: enabled Reserved. Enables device reset over SPI. Two writes to these bits are required to initiate the reset. The user must first set the bits to 11, and then set the bits to 10. When this sequence is detected on these two bits, the reset occurs. It is not dependent on other bits in this register being set or cleared. Rev. 0 | Page 70 of 76 Reset 0x1 Access R 0x0 R/W 0x0 0x0 R R/W 0x0 0x0 R R/W Data Sheet AD7768-1 GPIO PORT CONTROL REGISTER Address: 0x1E, Reset: 0x00, Name: GPIO_CONTROL Table 49. Bit Descriptions for GPIO_CONTROL Bit(s) 7 6 5 4 3 2 1 0 Bit Name UGPIO_EN GPIO2_OPEN_DRAIN_EN GPIO1_OPEN_DRAIN_EN GPIO0_OPEN_DRAIN_EN GPIO3_OP_EN GPIO2_OP_EN GPIO1_OP_EN GPIO0_OP_EN Description Universal enabling of GPIOx pins. This bit must be set high to change GPIO settings. Change GPIO2 output from strong driver to open drain. Change GPIO1 output from strong driver to open drain. Change GPIO0 output from strong driver to open drain. Output Enable for GPIO pin. 0 = input, 1 = output. Output Enable for GPIO pin. 0 = input, 1 = output. Output Enable for GPIO pin. 0 = input, 1 = output. Output Enable for GPIO pin. 0 = input, 1 = output. Reset 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 Access R/W R/W R/W R/W R/W R/W R/W R/W GPIO OUTPUT CONTROL REGISTER Address: 0x1F, Reset: 0x00, Name: GPIO_WRITE Table 50. Bit Descriptions for GPIO_WRITE Bit(s) [7:4] 3 2 1 0 Bit Name Reserved GPIO_WRITE_3 GPIO_WRITE_2 GPIO_WRITE_1 GPIO_WRITE_0 Description Reserved Write to this bit to set GPIO3 high. Write to this bit to set GPIO2 high. Write to this bit to set GPIO1 high. Write to this bit to set GPIO0 high. Reset 0x0 0x0 0x0 0x0 0x0 Access R R/W R/W R/W R/W GPIO INPUT READ REGISTER Address: 0x20, Reset: 0x00, Name: GPIO_READ Table 51. Bit Descriptions for GPIO_READ Bit(s) [7:4] 3 2 1 0 Bit Name Reserved GPIO_READ_3 GPIO_READ_2 GPIO_READ_1 GPIO_READ_0 Description Reserved Read the value from GPIO3. Read the value from GPIO2. Read the value from GPIO1. Read the value from GPIO0. Reset 0x0 0x0 0x0 0x0 0x0 Access R R R R R OFFSET CALIBRATION MSB REGISTER Address: 0x21, Reset: 0x00, Name: OFFSET_HI Table 52. Bit Descriptions for OFFSET_HI Bit(s) [7:0] Bit Name Offset[23:16] Description User offset calibration coefficient. The offset correction registers provide 24-bit, signed, twoscomplement registers for channel offset adjustment. If the channel gain setting is at its ideal nominal value of 0x555555, an LSB of offset register adjustment changes the digital output by -4/3 LSBs. For example, changing the offset register from 0 to 100 changes the digital output by -133 LSBs. The user offset calibration coefficient correction is applied to the digital filter output data before the gain calibration correction; therefore, the ratio above changes linearly with any gain adjustment applied via the gain calibration registers. Rev. 0 | Page 71 of 76 Reset 0x0 Access R/W AD7768-1 Data Sheet OFFSET CALIBRATION MID REGISTER Address: 0x22, Reset: 0x00, Name: OFFSET_MID Table 53. Bit Descriptions for OFFSET_MID Bit(s) [7:0] Bit Name Offset[15:8] Description User offset calibration coefficient. The offset correction registers provide 24-bit, signed, twoscomplement registers for channel offset adjustment. If the channel gain setting is at its ideal nominal value of 0x555555, an LSB of offset register adjustment changes the digital output by -4/3 LSBs. For example, changing the offset register from 0 to 100 changes the digital output by -133 LSBs. The user offset calibration coefficient correction is applied to the digital filter output data before the gain calibration correction; therefore, the ratio above changes linearly with any gain adjustment applied via the gain calibration registers. Reset 0x0 Access R/W Reset 0x0 Access R/W Reset 0x0 Access R/W Reset 0x0 Access R/W OFFSET CALIBRATION LSB REGISTER Address: 0x23, Reset: 0x00, Name: OFFSET_LO Table 54. Bit Descriptions for OFFSET_LO Bit(s) [7:0] Bit Name Offset[7:0] Description User offset calibration coefficient. The offset correction registers provide 24-bit, signed, twoscomplement registers for channel offset adjustment. If the channel gain setting is at its ideal nominal value of 0x555555, an LSB of offset register adjustment changes the digital output by -4/3 LSBs. For example, changing the offset register from 0 to 100 changes the digital output by -133 LSBs. The user offset calibration coefficient correction is applied to the digital filter output data before the gain calibration correction; therefore, the ratio above changes linearly with any gain adjustment applied via the gain calibration registers. GAIN CALIBRATION MSB REGISTER Address: 0x24, Reset: 0x00, Name: GAIN_HI Table 55. Bit Descriptions for GAIN_HI Bit(s) [7:0] Bit Name Gain[23:16] Description User gain calibration coefficient. The ADC has an associated factory programmed gain calibration coefficient. The coefficient is stored in the ADC during factory programming and the nominal value is around 0x555555. The user can read back the factory programmed value and may overwrite the gain register setting to apply their own calibration coefficient. The user offset calibration coefficient correction is applied to the digital filter output data before the gain calibration correction. GAIN CALIBRATION MID REGISTER Address: 0x25, Reset: 0x00, Name: GAIN_MID Table 56. Bit Descriptions for GAIN_MID Bit(s) [7:0] Bit Name Gain[15:8] Description User gain calibration coefficient. The ADC has an associated factory programmed gain calibration coefficient. The coefficient is stored in the ADC during factory programming and the nominal value is around 0x555555. The user can read back the factory programmed value and may overwrite the gain register setting to apply their own calibration coefficient. The user offset calibration coefficient correction is applied to the digital filter output data before the gain calibration correction. Rev. 0 | Page 72 of 76 Data Sheet AD7768-1 GAIN CALIBRATION LSB REGISTER Address: 0x26, Reset: 0x00, Name: GAIN_LO Table 57. Bit Descriptions for GAIN_LO Bit(s) [7:0] Bit Name Gain[7:0] Description User gain calibration coefficient. The ADC has an associated factory programmed gain calibration coefficient. The coefficient is stored in the ADC during factory programming and the nominal value is around 0x555555. The user can read back the factory programmed value and may overwrite the gain register setting to apply their own calibration coefficient. The user offset calibration coefficient correction is applied to the digital filter output data before the gain calibration correction. Reset 0x0 Access R/W SPI INTERFACE DIAGNOSTIC CONTROL REGISTER Address: 0x28, Reset: 0x10, Name: SPI_DIAG_ENABLE Table 58. Bit Descriptions for SPI_DIAG_ENABLE Bit(s) [7:5] 4 3 2 1 0 Bit Name Reserved EN_ERR_SPI_IGNORE EN_ERR_SPI_CLK_CNT EN_ERR_SPI_RD EN_ERR_SPI_WR Reserved Description Reserved SPI ignore error enabled SPI clock count error enabled SPI read error enabled SPI write error enabled Reserved Reset 0x0 0x1 0x0 0x0 0x0 0x0 Access R R/W R/W R/W R/W R ADC DIAGNOSTIC FEATURE CONTROL REGISTER Address: 0x29, Reset: 0x07, Name: ADC_DIAG_ENABLE Table 59. Bit Descriptions for ADC_DIAG_ENABLE Bit(s) [7:6] 5 4 3 2 1 0 Bit Name Reserved EN_ERR_DLDO_PSM EN_ERR_ALDO_PSM Reserved EN_ERR_FILTER_SATURATED EN_ERR_FILTER_NOT_SETTLED EN_ERR_EXT_CLK_QUAL Description Reserved DLDO PSM error enabled ALDO PSM error enabled Reserved Filter saturated error enabled Filter not settled error enabled Enable qualification check on external clock Reset 0x0 0x0 0x0 0x0 0x1 0x1 0x1 Access R R/W R/W R/W R/W R/W R/W DIGITAL DIAGNOSTIC FEATURE CONTROL REGISTER Address: 0x2A, Reset: 0x0D, Name: DIG_DIAG_ENABLE Table 60. Bit Descriptions for DIG_DIAG_ENABLE Bit(s) [7:5] 4 3 2 1 0 Bit Name Reserved EN_ERR_MEMMAP_CRC EN_ERR_RAM_CRC EN_ERR_FUSE_CRC Reserved EN_FREQ_COUNT Description Reserved Memory map CRC error enabled RAM CRC error enabled Fuse CRC error enabled Reserved Enable MCLK counter Rev. 0 | Page 73 of 76 Reset 0x0 0x0 0x1 0x1 0x0 0x1 Access R R/W R/W R/W R/W R/W AD7768-1 Data Sheet CONVERSION RESULT REGISTER Address: 0x2C, Reset: 0x000000, Name: ADC_DATA Table 61. Bit Descriptions for ADC_DATA Bit(s) [23:16] [15:8] [7:0] Bit Name ADC_READ_DATA[23:16] ADC_READ_DATA[15:8] ADC_READ_DATA[7:0] Description ADC read data ADC read data ADC read data Reset 0x0 0x0 0x0 Access R R R DEVICE ERROR FLAGS MASTER REGISTER Address: 0x2D, Reset: 0x00, Name: MASTER_STATUS See the Status Header section for additional information. Table 62. Bit Descriptions for MASTER_STATUS Bit 7 6 5 4 3 2 1 0 Bit Name MASTER_ERROR ADC_ERROR DIG_ERROR ADC_ERR_EXT_CLK_QUAL ADC_FILT_SATURATED ADC_FILT_NOT_SETTLED SPI_ERROR POR_FLAG Description Master error Any ADC error (OR) Any digital error (OR) No clock error; applied to master status register only Filter saturated Filter not settled Any SPI error (OR) POR flag Reset 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 Access R R R R R R R R SPI INTERFACE ERROR REGISTER Address: 0x2E, Reset: 0x00, Name: SPI_DIAG_STATUS Table 63. Bit Descriptions for SPI_DIAG_STATUS Bit(s) [7:5] 4 3 2 1 0 Bit Name Reserved ERR_SPI_IGNORE ERR_SPI_CLK_CNT ERR_SPI_RD ERR_SPI_WR ERR_SPI_CRC Description Reserved. SPI ignore error SPI clock count error SPI read error SPI write error SPI CRC error Reset 0x0 0x0 0x0 0x0 0x0 0x0 Access R R/W1C R R/W1C R/W1C R/W1C ADC DIAGNOSTICS OUTPUT REGISTER Address: 0x2F, Reset: 0x00, Name: ADC_DIAG_STATUS Table 64. Bit Descriptions for ADC_DIAG_STATUS Bit(s) [7:6] 5 4 3 2 1 0 Bit Name Reserved ADC_ERR_DLDO_PSM ADC_ERR_ALDO_PSM Reserved ADC_FILT_SATURATED ADC_FILT_NOT_SETTLED ADC_ERR_EXT_CLK_QUAL Description Reserved Digital low dropout (DLDO) power supply monitor (PSM) error Analog low dropout (ALDO) PSM error Reserved Filter saturated Filter not settled No clock error; applied to master status register only Rev. 0 | Page 74 of 76 Reset 0x0 0x0 0x0 0x0 0x0 0x0 0x0 Access R R R R R R R Data Sheet AD7768-1 DIGITAL DIAGNOSTICS OUTPUT REGISTER Address: 0x30, Reset: 0x00, Name: DIG_DIAG_STATUS Table 65. Bit Descriptions for DIG_DIAG_STATUS Bit(s) [7:5] 4 3 2 [1:0] Bit Name Reserved ERR_MEMMAP_CRC ERR_RAM_CRC ERR_FUSE_CRC Reserved Description Reserved Memory map CRC error RAM CRC error Fuse CRC error Reserved Reset 0x0 0x0 0x0 0x0 0x0 Access R R R R R MCLK DIAGNOSTIC OUTPUT REGISTER Address: 0x31, Reset: 0x00, Name: MCLK_COUNTER Table 66. Bit Descriptions for MCLK_COUNTER Bit(s) [7:0] Bit Name MCLK_COUNTER Description MCLK counter. This register increments after every 64 MCLKs. Reset 0x0 Access R COEFFICIENT CONTROL REGISTER Address: 0x32, Reset: 0x00, Name: COEFF_CONTROL Table 67. Bit Descriptions for COEFF_CONTROL Bit(s) 7 6 [5:0] Bit Name COEFFACCESSEN COEFFWRITEEN COEFFADDR Description Setting this bit to a 1 allows access to the coefficient memory. Enables write to the coefficient memory. Write a 1 to enable. Address to be accessed for the coefficient memory. The address ranges from 0 to 55 for 56 coefficients that form one symmetrical half of the 112 coefficients. Reset 0x0 0x0 0x00 Access R/W R/W R/W COEFFICIENT DATA REGISTER Address: 0x33, Reset: 0x00, Name: COEFF_DATA Table 68. Bit Descriptions for COEFF_DATA Bit(s) 23 Bit Name USERCOEFFEN [22:0] COEFFDATA Description Setting this bit to a 1 prevents the coefficients from ROM over writing the user defined coefficients after a sync toggle. A sync pulse is required after every change to the AD7768-1 digital filter configuration, including a customized filter upload. Filter coefficients written to memory are written to these bits. These bits are 23 bits wide. Reset 0x0 Access R/W 0x000000 R/W ACCESS KEY REGISTER Address: 0x34, Reset: 0x00, Name: ACCESS_KEY Table 69. Bit Descriptions for ACCESS_KEY Bit(s) [7:1] 0 Bit Name Reserved Key Description Reserved. A specific key must be written to the ACCESS_KEY register prior to any filter upload. If written correctly, the key bit reads back as 1. Rev. 0 | Page 75 of 76 Reset Access 0x0 R/W AD7768-1 Data Sheet OUTLINE DIMENSIONS 0.30 0.25 0.18 5.10 5.00 4.90 2.70 2.60 2.50 1 3.70 3.60 3.50 EXPOSED PAD 0.50 BSC 15 TOP VIEW 0.80 0.75 0.70 END VIEW PKG-005005 SEATING PLANE PIN 1 INDIC ATOR AREA OPTIONS (SEE DETAIL A) 28 23 22 0.45 0.40 0.35 0.05 MAX 0.02 NOM COPLANARITY 0.08 0.203 REF 8 14 9 BOTTOM VIEW FOR PROPER CONNECTION OF THE EXPOSED PAD, REFER TO THE PIN CONFIGURATION AND FUNCTION DESCRIPTIONS SECTION OF THIS DATA SHEET. COMPLIANT TO JEDEC STANDARDS MO-220-WGHD-3 02-14-2017-A PIN 1 INDEX AREA DETAIL A (JEDEC 95) 4.10 4.00 3.90 Figure 98. 28-Lead Lead Frame Chip-Scale Package [LFCSP] 4 mm x 5 mm Body and 0.75 Package Height (CP-28-12) Dimensions shown in millimeters ORDERING GUIDE Model 1 AD7768-1BCPZ AD7768-1BCPZ-RL AD7768-1BCPZ-RL7 EV-AD7768-1FMCZ EVAL-SDP-CH1Z 1 Temperature Range -40C to +125C -40C to +125C -40C to +125C Package Description 28-Lead Lead Frame Chip-Scale Package [LFCSP] 28-Lead Lead Frame Chip-Scale Package [LFCSP] 28-Lead Lead Frame Chip-Scale Package [LFCSP] Evaluation Board Controller Board Z = RoHS Compliant Part. (c)2018 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D16481-0-5/18(0) Rev. 0 | Page 76 of 76 Package Option CP-28-12 CP-28-12 CP-28-12