Digital Delay Units series DDU-11H 5 Taps ECL Interfaced Test Conditions: @ Input pulse-width: 150% of total delay. = Input pulse rise-time: <6 ns. m@ Input pulse voltage: .7V m Rise-time measured from 20% to 80% of leading edge. = Delay time measured at 50% of leading edge. # All measurements taken V_;- = 5.2V and T, = 25C. = Unless otherwise specified, all time-delays Features: are referenced to the input pin. g Input & Output Buffered @ 5 Equally Spaced Taps g@ Fits in Standard 16 Pins DIP aco Specifications: t M@ Total Delay Tolerance: + 5% or better, | |e fd or 2 ns whichever is greater. : M@ No. Taps: 5 equally spaced. @ MW Rise-time: 2 ns typical. m@ Supply voltage: 5 Vdc +5%. TO | o0Tve. t @ Operating Temperature: 30C to 85C. 320 MAX. | , @ Power Dissipation: 200 mw typ. (no load). { | | Temperature coefficient: 100 PPM/C. Wi 1 We a @ DC Parameters: See ECL-10KH Logic Table on | | P. 100 ' 018 TYP age 6. + L |. Total Delay t ? > 5] ? ma | Part No. Delay Tap ow Tye ' | a0 (ns) (ns) | * DDU-11H-4 2 5+ 3 = _ %* DDU-11H-5 4 1+ 3 380 * DDU-11H-8 6 15+ 4 | eo DDU-11H-10 10 2+ 4 DDU-11H-20 20 4 + 5 tf or case stand-ofis DDU-11H-25 25 5 +10 DDU-11H-50 50 10 +20 Tapyt 2S 4 5 DDU-11H-75 75 15 +20 Pegi 9M 4 8 DDU-11H-100 100 20 +20 Ve r J yf DDU-11H-150 150 30 +20 DDU-11H-200 200 40 +20 DDU-11H-250 250 50 +25 DDU-11H-300 300 60 +30 DDU-11H-400 400 80 +40 GRO DDU-11H-500 500 100 +5.0 M6 bo 4 Pull-down resistor on outpul taps nat provided inside unit. Time delay measurements referenced to 1st tap. 1.5 ns 1 ns inherent delay. 3 Mt. Prospect Avenue, Clifton, New Jersey 07013 = (973) 773-2299 m Fax (973) 773-9672 14