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FEATURES
DESCRIPTION
DGG OR DL PACKAGE
(TOP VIEW)
1
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28
56
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OEA
LE1B
2B3
GND
2B2
2B1
VCC
A1
A2
A3
GND
A4
A5
A6
A7
A8
A9
GND
A10
A11
A12
VCC
1B1
1B2
GND
1B3
LE2B
SEL
OE2B
LEA2B
2B4
GND
2B5
2B6
VCC
2B7
2B8
2B9
GND
2B10
2B11
2B12
1B12
1B11
1B10
GND
1B9
1B8
1B7
VCC
1B6
1B5
GND
1B4
LEA1B
OE1B
Three 12-bit I/O ports (A1-A12, 1B1-1B12, and 2B1-2B12) are available for address and/or data transfer. The
SN74ALVCH16226012-BIT TO 24-BIT MULTIPLEXED D-TYPE LATCHWITH 3-STATE OUTPUTS
SCAS570I – MARCH 1996 – REVISED AUGUST 2004
•Member of the Texas Instruments Widebus™Family
•EPIC™ (Enhanced-Performance ImplantedCMOS) Submicron Process•B-Port Outputs Have Equivalent 26-ΩSeriesResistors, So No External Resistors AreRequired
•ESD Protection Exceeds 2000 V PerMIL-STD-883, Method 3015; Exceeds 200 VUsing Machine Model (C = 200 pF, R = 0)•Latch-Up Performance Exceeds 250 mA PerJESD 17•Bus Hold on Data Inputs Eliminates the Needfor External Pullup/Pulldown Resistors•Package Options Include Thin-ShrinkSmall-Outline (DGG) and Plastic ShrinkSmall-Outline (DL) PackagesNOTE:
For tape-and-reel order entry: The DGGR package isabbreviated to GR.
This 12-bit to 24-bit multiplexed D-type latch isdesigned for 1.65-V to 3.6-V V
CC
operation.
The SN74ALVCH162260 is used in applications inwhich two separate data paths must be multiplexedonto, or demultiplexed from, a single data path.Typical applications include multiplexing and/ordemultiplexing address and data information inmicroprocessor or bus-interface applications. Thisdevice also is useful in memory-interleavingapplications.
output-enable (OE1B, OE2B, and OEA) inputs control the bus transceiver functions. The OE1B and OE2Bcontrol signals also allow bank control in the A-to-B direction.
Address and/or data information can be stored using the internal storage latches. The latch-enable (LE1B, LE2B,LEA1B, and LEA2B) inputs are used to control data storage. When the latch-enable input is high, the latch istransparent. When the latch-enable input goes low, the data present at the inputs is latched and remains latcheduntil the latch-enable input is returned high.
The B outputs, which are designed to sink up to 12 mA, include equivalent 26-Ωresistors to reduce overshootand undershoot.
To ensure the high-impedance state during power up or power down, OE should be tied to V
CC
through a pullupresistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.
Active bus-hold circuitry is provided to hold unused or floating data inputs at a valid logic level.
The SN74ALVCH162260 is characterized for operation from -40°C to 85°C.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of TexasInstruments semiconductor products and disclaimers thereto appears at the end of this data sheet.Widebus, EPIC are trademarks of Texas Instruments.
PRODUCTION DATA information is current as of publication date.
Copyright © 1996–2004, Texas Instruments IncorporatedProducts conform to specifications per the terms of the TexasInstruments standard warranty. Production processing does notnecessarily include testing of all parameters.
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SN74ALVCH162260
12-BIT TO 24-BIT MULTIPLEXED D-TYPE LATCHWITH 3-STATE OUTPUTS
SCAS570I – MARCH 1996 – REVISED AUGUST 2004
FUNCTION TABLES
XXX
B TO A(OEB = H)
INPUTS
OUTPUT
A1B 2B SEL LE1B LE2B OEA
H X H H X L HL X H H X L LX X H L X L A
0
X H L X H L HX L L X H L LX X L X L L A
0
X X X X X H Z
A TO B(OEA = H)
INPUTS OUTPUTS
A LEA1B LEA2B OE1B OE2B 1B 2B
H H H L L H HL H H L L L LH H L L L H 2B
0
L H L L L L 2B
0
H L H L L 1B
0
HL L H L L 1B
0
LX L L L L 1B
0
2B
0
X X X H H Z ZX X X L H Active ZX X X H L Z ActiveX X X L L Active Active
2
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C1
1D
C1
1D
C1
1D
C1
1D
To 11 Other Channels
LE1B
LE2B
LEA1B
LEA2B
OE2B
OE1B
OEA
SEL
A1 1B1
2B1
27
2
30
55
56
29
1
28
823
6
G1
1
1
SN74ALVCH16226012-BIT TO 24-BIT MULTIPLEXED D-TYPE LATCHWITH 3-STATE OUTPUTS
SCAS570I – MARCH 1996 – REVISED AUGUST 2004
LOGIC DIAGRAM (POSITIVE LOGIC)
3
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ABSOLUTE MAXIMUM RATINGS
(1)
SN74ALVCH162260
12-BIT TO 24-BIT MULTIPLEXED D-TYPE LATCHWITH 3-STATE OUTPUTS
SCAS570I – MARCH 1996 – REVISED AUGUST 2004
over operating free-air temperature range (unless otherwise noted)
MIN MAX UNIT
V
CC
Supply voltage range -0.5 4.6 VExcept I/O ports
(2)
-0.5 4.6V
I
Input voltage range VI/O ports
(2) (3)
-0.5 V
CC
+ 0.5V
O
Output voltage range
(2) (3)
-0.5 V
CC
+ 0.5 VI
IK
Input clamp current V
I
< 0 -50 mAI
OK
Output clamp current V
O
< 0 -50 mAI
O
Continuous output current ±50 mAContinuous current through each V
CC
or GND ±100 mADGG package 81θ
JA
Package thermal impedance
(4)
DGV package 86 °C/WDL package 74T
stg
Storage temperature -65 150 °C
(1) Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratingsonly, and functional operation of the device at these or any other conditions beyond those indicated under "recommended operatingconditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.(2) The input negative-voltage and output voltage ratings may be exceeded if the input and output current ratings are observed.(3) This value is limited to 4.6 V maximum.(4) The package thermal impedance is calculated in accordance with JESD 51.
4
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RECOMMENDED OPERATING CONDITIONS
(1)
SN74ALVCH16226012-BIT TO 24-BIT MULTIPLEXED D-TYPE LATCHWITH 3-STATE OUTPUTS
SCAS570I – MARCH 1996 – REVISED AUGUST 2004
MIN MAX UNIT
V
CC
Supply voltage 1.65 3.6 VV
CC
= 1.65 V to 1.95 V 0.65 ×V
CC
V
IH
High-level input voltage V
CC
= 2.3 V to 2.7 V 1.7 VV
CC
= 2.7 V to 3.6 V 2V
CC
= 1.65 V to 1.95 V 0.35 ×V
CC
V
IL
Low-level input voltage V
CC
= 2.3 V to 2.7 V 0.7 VV
CC
= 2.7 V to 3.6 V 0.8V
I
Input voltage 0 V
CC
VV
O
Output voltage 0 V
CC
vV
CC
= 1.65 V -4V
CC
= 2.3 V -12High-level output current (A port)
V
CC
= 2.7 V -12V
CC
= 3 V -24I
OH
mAV
CC
= 1.65 V -2V
CC
= 2.3 V -6High-level output current (B port)
V
CC
= 2.7 V -8V
CC
= 3 V -12V
CC
= 1.65 V 4V
CC
= 2.3 V 12Low-level output current (A port)
V
CC
= 2.7 V 12V
CC
= 3 V 24I
OL
mAV
CC
= 1.65 V 2V
CC
= 2.3 V 6Low-level output current (B port)
V
CC
= 2.7 V 8V
CC
= 3 V 12∆t/∆v Input transition rise or fall rate 10 ns/VT
A
Operating free-air temperature -40 85 °C
(1) All unused control inputs of the device must be held at V
CC
or GND to ensure proper device operation. Refer to the TI application report,Implications of Slow or Floating CMOS Inputs, literature number SCBA004.
5
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ELECTRICAL CHARACTERISTICS
SN74ALVCH162260
12-BIT TO 24-BIT MULTIPLEXED D-TYPE LATCHWITH 3-STATE OUTPUTS
SCAS570I – MARCH 1996 – REVISED AUGUST 2004
over recommended operating free-air temperature range (unless otherwise noted)
PARAMETER TEST CONDITIONS V
CC
MIN TYP
(1)
MAX UNIT
I
OH
= -100 µA 1.65 V to 3.6 V V
CC
- 0.2I
OH
= -4 mA 1.65 V 1.2I
OH
= -6 mA 2.3 V 2A port 2.3 V 1.7I
OH
= -12 mA 2.7 V 2.23 V 2.4I
OH
= -24 mA 3 V 2V
OH
VI
OH
= -100 µA 1.65 V to 3.6 V V
CC
- 0.2I
OH
= -2 mA 1.65 V 1.2I
OH
= -4 mA 2.3 V 1.9B port 2.3 V 1.7I
OH
= -6 mA
3 V 2.4I
OH
= -8 mA 2.7 V 2I
OH
= -12 mA 3 V 2I
OL
= 100 µA 1.65 V to 3.6 V 0.2I
OL
= 4 mA 1.65 V 0.45I
OL
= 6 mA 2.3 V 0.4A port
2.3 V 0.7I
OL
= 12 mA
2.7 V 0.4I
OL
= 24 mA 3 V 0.55V
OL
I
OL
= 100 µA 1.65 V to 3.6 V 0.2 VI
OL
= 2 mA 1.65 V 0.45I
OL
= 4 mA 2.3 V 0.4B port 2.3 V 0.55I
OL
= 6 mA
3 V 0.55I
OL
= 8 mA 2.7 V 0.6I
OL
= 12 mA 3 V 0.8I
I
V
I
= V
CC
or GND 3.6 V ±5µAV
I
= 0.58 V 251.65 VV
I
= 1.07 V -25V
I
= 0.7 V 452.3 VI
I(hold)
V
I
= 1.7 V -45 µAV
I
= 0.8 V 753 VV
I
= 2 V -75V
I
= 0 to 3.6 V
(2)
3.6 V ±500I
OZ
(3)
V
O
= V
CC
or GND 3.6 V ±10 µAI
CC
V
I
= V
CC
or GND, I
O
= 0 3.6 V 40 µA∆I
CC
One input at V
CC
- 0.6 V, Other inputs at V
CC
or GND 3 V to 3.6 V 750 µAC
i
Control inputs V
I
= V
CC
or GND 3.3 V 3.5 pFC
io
A or B ports V
O
= V
CC
or GND 3.3 V 4.5 pF
(1) All typical values are at V
CC
= 3.3 V, T
A
= 25°C.(2) This is the bus-hold maximum dynamic current. It is the minimum overdrive current required to switch the input from one state toanother.
(3) For I/O ports, the parameter I
OZ
includes the input leakage current.
6
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TIMING REQUIREMENTS
SWITCHING CHARACTERISTICS
OPERATING CHARACTERISTICS
SN74ALVCH16226012-BIT TO 24-BIT MULTIPLEXED D-TYPE LATCHWITH 3-STATE OUTPUTS
SCAS570I – MARCH 1996 – REVISED AUGUST 2004
over recommended operating free-air temperature range (unless otherwise noted) (see Figure 1 through Figure 3)
V
CC
= 2.5 V V
CC
= 3.3 VV
CC
= 1.8 V V
CC
= 2.7 V±0.2 V ±0.3 V
UNITMIN MAX MIN MAX MIN MAX MIN MAX
f
clock
Clock frequency
(1)
150 150 150 MHzPulse duration, LE1B, LE2B, LEA1B, or LEA2Bt
w
(1)
3.3 3.3 3.3 nshigh
Setup time, data before LE1B, LE2B, LEA1B, ort
su
(1)
1.4 1.1 1.1 nsLEA2B high or lowHold time, data after LE1B, LE2B, LEA1B, ort
h
(1)
1.6 1.9 1.5 nsLEA2B high or low
(1) This information was not available at the time of publication.
over recommended operating free-air temperature range (unless otherwise noted) (see Figure 1 through Figure 3)
V
CC
= 2.5 V V
CC
= 3.3 VV
CC
= 1.8 V V
CC
= 2.7 VFROM TO
±0.2 V ±0.3 VPARAMETER UNIT(INPUT) (OUTPUT)
MIN TYP MIN MAX MIN MAX MIN MAX
f
max
(1)
150 150 150 MHzA B
(1)
1 5.9 5.8 1.2 4.9B A
(1)
1 5.7 5.1 1.2 4.3t
pd
A
(1)
1 5.6 5.2 1 4.4 nsLE
B
(1)
1 6.1 5.9 1 5SEL A
(1)
1 6.9 6.6 1.1 5.6A
(1)
1 6.7 6.4 1 5.4t
en
OE nsB
(1)
1 7.2 7.1 1 6A
(1)
1 5.7 5 1.3 4.6t
dis
OE nsB
(1)
1 6.2 5.5 1.3 5.1
(1) This information was not available at the time of publication.
T
A
= 25°C
V
CC
= 1.8 V V
CC
= 2.5 V V
CC
= 3.3 VPARAMETER TEST CONDITIONS UNITTYP TYP TYP
All outputs enabled
(1)
37 41Power dissipationC
pd
C
L
= 50 pF, f = 10 MHz pFcapacitance
All outputs disabled
(1)
4 7
(1) This information was not available at the time of publication.
7
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PARAMETER MEASUREMENT INFORMATION
VCC/2
VCC/2
VCC/2VCC/2
VCC/2VCC/2
VCC/2
VCC/2
VOH
VOL
th
tsu
From Output
Under Test
CL = 30 pF
(see Note A)
LOAD CIRCUIT
S1 Open
GND
1 kΩ
1 kΩ
Output
Control
(low-level
enabling)
Output
Waveform 1
S1 at 2 × VCC
(see Note B)
Output
Waveform 2
S1 at GND
(see Note B)
tPZL
tPZH
tPLZ
tPHZ
0 V
VOL + 0.15 V
VOH − 0.15 V
0 V
VCC
0 V
0 V
tw
VCC VCC
VOLTAGE WAVEFORMS
SETUP AND HOLD TIMES
VOLTAGE WAVEFORMS
PULSE DURATION
VOLTAGE WAVEFORMS
ENABLE AND DISABLE TIMES
Timing
Input
Data
Input
Input
tpd
tPLZ/tPZL
tPHZ/tPZH
Open
2 × VCC
GND
TEST S1
NOTES: A. CL includes probe and jig capacitance.
B. Waveform 1 is for an output with internal conditions such that the output is low, except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high, except when disabled by the output control.
C. All input pulses are supplied by generators having the following characteristics: PRR ≤ 10 MHz, ZO = 50 Ω, tr ≤ 2 ns, tf ≤ 2 ns.
D. The outputs are measured one at a time, with one transition per measurement.
E. tPLZ and tPHZ are the same as tdis.
F. tPZL and tPZH are the same as ten.
G. tPLH and tPHL are the same as tpd.
0 V
VCC
VCC/2
tPHL
VCC/2 VCC/2 VCC
0 V
VOH
VOL
Input
Output
VOLTAGE WAVEFORMS
PROPAGATION DELAY TIMES
VCC/2 VCC/2
tPLH
2 × VCC
VCC
SN74ALVCH162260
12-BIT TO 24-BIT MULTIPLEXED D-TYPE LATCHWITH 3-STATE OUTPUTS
SCAS570I – MARCH 1996 – REVISED AUGUST 2004
V
CC
= 1.8 V
Figure 1. Load Circuit and Voltage Waveforms
8
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PARAMETER MEASUREMENT INFORMATION
tPHL
tPLH
VCC/2
VCC/2
VCC/2VCC/2
VCC/2VCC/2
VCC/2
VCC/2
VOH
VOL
th
tsu
From Output
Under Test
CL = 30 pF
(see Note A)
LOAD CIRCUIT
S1 Open
GND
500 Ω
500 Ω
Output
Control
(low-level
enabling)
Output
Waveform 1
S1 at 2 × VCC
(see Note B)
Output
Waveform 2
S1 at GND
(see Note B)
tPZL
tPZH
tPLZ
tPHZ
0 V
VOL + 0.15 V
VOH − 0.15 V
0 V
VCC
0 V
0 V
tw
VCC VCC
VOLTAGE WA VEFORMS
SETUP AND HOLD TIMES
VOLTAGE WA VEFORMS
PULSE DURATION
VOLTAGE WA VEFORMS
ENABLE AND DISABLE TIMES
Timing
Input
Data
Input
Input
tpd
tPLZ/tPZL
tPHZ/tPZH
Open
2 × VCC
GND
TEST S1
NOTES: A. CL includes probe and jig capacitance.
B. Waveform 1 is for an output with internal conditions such that the output is low, except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high, except when disabled by the output control.
C. All input pulses are supplied by generators having the following characteristics: PRR ≤ 10 MHz, ZO = 50 Ω, tr ≤ 2 ns, tf ≤ 2 ns.
D. The outputs are measured one at a time, with one transition per measurement.
E. tPLZ and tPHZ are the same as tdis.
F. tPZL and tPZH are the same as ten.
G. tPLH and tPHL are the same as tpd.
0 V
VCC
VCC/2
VCC/2 VCC/2 VCC
0 V
VOH
VOL
Input
Output
VOLTAGE WA VEFORMS
PROPAGATION DELAY TIMES
VCC/2 VCC/2
2 × VCC
VCC
SN74ALVCH16226012-BIT TO 24-BIT MULTIPLEXED D-TYPE LATCHWITH 3-STATE OUTPUTS
SCAS570I – MARCH 1996 – REVISED AUGUST 2004
V
CC
= 2.5 V ±0.2 V
Figure 2. Load Circuit and Voltage Waveforms
9
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PARAMETER MEASUREMENT INFORMATION
tPHL
tPLH VOH
VOL
From Output
Under Test
CL = 50 pF
(see Note A)
LOAD CIRCUIT
S1 6 V
Open
GND
500 Ω
500 Ω
Output
Control
(low-level
enabling)
Output
Waveform 1
S1 at 6 V
(see Note B)
Output
Waveform 2
S1 at GND
(see Note B)
tPZL
tPZH
tPLZ
tPHZ
1.5 V1.5 V
1.5 V 1.5 V 2.7 V
0 V
1.5 V 1.5 V VOH
VOL
0 V
1.5 V VOL + 0.3 V
1.5 V VOH − 0.3 V
0 V
1.5 V 2.7 V
0 V
0 V
2.7 V
0 V
Input
2.7 V 2.7 V
3 V
VOLTAGE WA VEFORMS
SETUP AND HOLD TIMES
VOLTAGE WA VEFORMS
PROPAGATION DELAY TIMES
VOLTAGE WA VEFORMS
PULSE DURATION
VOLTAGE WA VEFORMS
ENABLE AND DISABLE TIMES
Timing
Input
Data
Input
Output
Input
tpd
tPLZ/tPZL
tPHZ/tPZH
Open
6 V
GND
TEST S1
1.5 V 1.5 V
tw
th
tsu
1.5 V 1.5 V
NOTES: A. CL includes probe and jig capacitance.
B. Waveform 1 is for an output with internal conditions such that the output is low, except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high, except when disabled by the output control.
C. All input pulses are supplied by generators having the following characteristics: PRR ≤ 10 MHz, ZO = 50 Ω, tr ≤ 2.5 ns, tf ≤ 2.5 ns.
D. The outputs are measured one at a time, with one transition per measurement.
E. tPLZ and tPHZ are the same as tdis.
F. tPZL and tPZH are the same as ten.
G. tPLH and tPHL are the same as tpd.
SN74ALVCH162260
12-BIT TO 24-BIT MULTIPLEXED D-TYPE LATCHWITH 3-STATE OUTPUTS
SCAS570I – MARCH 1996 – REVISED AUGUST 2004
V
CC
= 2.7 V AND 3.3 V ±0.3 V
Figure 3. Load Circuit and Voltage Waveforms
10
PACKAGING INFORMATION
Orderable Device Status (1) Package
Type Package
Drawing Pins Package
Qty Eco Plan (2) Lead/Ball Finish MSL Peak Temp (3)
SN74ALVCH162260DGGR OBSOLETE TSSOP DGG 56 None Call TI Call TI
SN74ALVCH162260DL ACTIVE SSOP DL 56 20 None CU NIPDAU Level-1-235C-UNLIM
SN74ALVCH162260DLR ACTIVE SSOP DL 56 1000 None CU NIPDAU Level-1-235C-UNLIM
SN74ALVCH162260GR ACTIVE TSSOP DGG 56 2000 Pb-Free
(RoHS) CU NIPDAU Level-1-250C-UNLIM
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in
a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) Eco Plan - May not be currently available - please check http://www.ti.com/productcontent for the latest availability information and additional
product content details.
None: Not yet available Lead (Pb-Free).
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements
for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered
at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Green (RoHS & no Sb/Br): TI defines "Green" to mean "Pb-Free" and in addition, uses package materials that do not contain halogens,
including bromine (Br) or antimony (Sb) above 0.1% of total product weight.
(3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDECindustry standard classifications, and peak solder
temperature.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is
provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the
accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take
reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on
incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited
information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI
to Customer on an annual basis.
PACKAGE OPTION ADDENDUM
www.ti.com 18-Feb-2005
Addendum-Page 1
MECHANICAL DATA
MSSO001C – JANUARY 1995 – REVISED DECEMBER 2001
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
DL (R-PDSO-G**) PLASTIC SMALL-OUTLINE PACKAGE
4040048/E 12/01
48 PINS SHOWN
56
0.730
(18,54)
0.720
(18,29)
4828
0.370
(9,40)
(9,65)
0.380
Gage Plane
DIM
0.420 (10,67)
0.395 (10,03)
A MIN
A MAX
0.010 (0,25)
PINS **
0.630
(16,00)
(15,75)
0.620
0.010 (0,25)
Seating Plane
0.020 (0,51)
0.040 (1,02)
25
24
0.008 (0,203)
0.0135 (0,343)
48
1
0.008 (0,20) MIN
A
0.110 (2,79) MAX
0.299 (7,59)
0.291 (7,39)
0.004 (0,10)
M
0.005 (0,13)
0.025 (0,635)
0°–ā8°
0.005 (0,13)
NOTES: A. All linear dimensions are in inches (millimeters).
B. This drawing is subject to change without notice.
C. Body dimensions do not include mold flash or protrusion not to exceed 0.006 (0,15).
D. Falls within JEDEC MO-118
MECHANICAL DATA
MTSS003D – JANUARY 1995 – REVISED JANUAR Y 1998
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
DGG (R-PDSO-G**) PLASTIC SMALL-OUTLINE PACKAGE
4040078/F 12/97
48 PINS SHOWN
0,25
0,15 NOM
Gage Plane
6,00
6,20 8,30
7,90
0,75
0,50
Seating Plane
25
0,27
0,17
24
A
48
1
1,20 MAX
M
0,08
0,10
0,50
0°–8°
56
14,10
13,90
48
DIM
A MAX
A MIN
PINS **
12,40
12,60
64
17,10
16,90
0,15
0,05
NOTES: A. All linear dimensions are in millimeters.
B. This drawing is subject to change without notice.
C. Body dimensions do not include mold protrusion not to exceed 0,15.
D. Falls within JEDEC MO-153
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