August 1998 VME01 16-Bit TTL Compatible Data Transceiver with Incident Wave Switching General Description Features The VME01 contains sixteen non-inverting bidirectional buffers with TRI-STATE (R) outputs designed with incident wave switching, live insertion support and enhanced noise margin for TTL backplane applications. n Supports the VME64 ETL specification n Functionally and pin compatible with TI SN74ABTE16245 n Improved TTL-compatible input threshold range n High drive TTL-compatible outputs (IOH = -60 mA, IOL = 90 mA) n Supports 25 incident wave switching on the A port n VCC Bias pin minimizes signal distortion during live insertion n BiCMOS design significantly reduces power dissipation. n Distributed VCC and GND pin configuration minimizes high-speed switching noise n 25 series-dampening resistor on B-port n Available in 48-pin SSOP and ceramic flatpak n Guaranteed output skew n Guaranteed simultaneous switching noise level and dynamic threshold performance n Guaranteed latchup protection A VCC bias pin provides for the precharging of the A side outputs during live insertion. When set at 5.0V, this pin will establish a voltage of 1.5V on the A port before VCC is connected. This precharge will minimize the capacitive discharge, and associated discontinuity, onto the active backplane during board insertion. The B port includes a bus hold circuit to latch the output to the value last forced on that pin. The B port of this device includes 25 series output resistors, which minimize undershoot and ringing. Logic Symbol DS100228-1 Pin Description Pin Names Description 1DIR-2DIR Transmit/Receive Inputs OE Output Enable Input (Active LOW) 1An, 2An Backplane Bus Inputs or TRI-STATE Outputs, with Live Insertion 1Bn, 2Bn Local Bus Input Pins or TRI-STATE VCC Bias Live Insertion Power Supply Outputs, with Bus Hold TRI-STATE (R) is a registered trademark of National Semiconductor Corporation. (c) 1998 National Semiconductor Corporation DS100228 www.national.com VME01 16-Bit TTL Compatible Data Transceiver with Incident Wave Switching PRELIMINARY Connection Diagram Functional Description The device uses byte-wide Direction (DIR) control and a singular Output Enable (OE) control. The DIR inputs determine the direction of data flow through the device. The OE input disables both the A and the B ports, effectively isolating both buses. The part contains active circuitry which keeps all outputs disabled when VCC is less than 2.2V to aid in live insertion applications. Pin Assignment for SSOP and Flatpak Truth Table (Each 8-bit Section) Inputs OE Operation DIR L L A Data to B Bus L H B Data to A Bus H X Isolation DS100228-2 Logic Diagram (Positive Logic) DS100228-3 www.national.com 2 ETL's Improved Noise Immunity TTL input thresholds are typically determined by temperature-dependent junction voltages which result in worst case input thresholds between 0.8V and 2.0V. By contrast, ETL provides greater noise immunity because its input thresholds are determined by current mode input circuits similar to those used for ECL or BTL. ETL's worst case input thresholds, between 1.4V and 1.6V, are compensated for temperature, voltage and process variations. Improved Input Threshold Characteristics of ETL DS100228-8 DS100228-5 ETL Worst Case VOUT-VIN TTL Worst Case VOUT-VIN Incident Wave Switching When TTL logic is used to drive fully loaded backplanes, the combination of low backplane bus characteristic impedance, wide TTL input threshold range and limited TTL drive generally require multiple waveform reflections before a valid signal can be received across the backplane. The VME International Trade Association (VITA) defined ETL to provide incident wave switching which increases the data transfer rate of a VME backplane and extends the life of VME applications. TTL compatibility with existing VME backplanes and modules was maintained. To demonstrate the incident wave switching capability, consider a VME application. A VME bus must be terminated to +2.94V with 190 at each end of its 21 card backplane. The surge impedance presented by a fully loaded VME backplane is approximately 25. If the output voltage/current of an ABTC driver is plotted with this load, the intersection at 1.2V for a falling edge and at 1.6V for a rising edge does not reach the worst case input threshold of a second ABTC circuit. This is shown in the two figures below. However, an ETL driver located at one end of the backplane is able to provide incident wave switching because it has a higher drive and a tighter input threshold. Estimated ETL/ABTC Initial Falling Edge Step DS100228-9 3 www.national.com Incident Wave Switching (Continued) Estimated ETL/ABTC Initial Rising Edge Step DS100228-11 Because ETL has a much more precise input threshold region, an ETL receiver will interpret its predicted falling input of 0.85V as a logic ZERO and the initial rising edge of 1.9V as a logic ONE. This comparison is for the case of a 25 surge impedance backplane driven from one end. The resulting ABTC and ETL waveform predictions and their input thresholds are compared below. This shows how ETL can achieve backplane speeds not always possible with conventional TTL compatible logic families. Comparing the Incident Wave Switching of ETL with ABTC DS100228-12 Live Insertion Module Replacement with an embedded ground plane and differential length connector pins. The differential length connector pins allow power sequencing to the module so that the signal pins can be controlled to a biased high impedance before they make contact with the backplane. VITA's ETL modules will use an early VCC power input, called VCC Bias, to control the ETL transceivers to a high impedance to minimize insertion disturbance. In addition, VCC To allow a system module to be replaced without disturbing signals passing between other operating modules requires careful design of operating systems, applications software and hardware. ETL supports live insertion module replacement with features that minimize backplane signal disturbance while a module is inserted. As specified by VITA, live insertion requires several backward-compatible system enhancements including: an improved backplane connector www.national.com 4 Live Insertion Module Replacement (Continued) When applying power to a printed circuit board containing ETL transceivers, the system VCC can be connected to VCC. Bias without damage to the device. If the advantages of Live Insertion are to be included in the system, then VCC Bias should be allowed to reach normal operating levels before VCC becomes higher than 2.2 volts. In addition, when removing a module, or turning off system power, VCC should be reduced below 2.2 volts before VCC. Bias is allowed to drop below normal operating limits. This sequencing is shown below. Bias is used to precharge the backplane driver output capacitance including the module connector pin and module etch. The precharge voltage is to 1.5V using a switched 40 k resistor. This precharge will minimize the capacitive discharge onto an active backplane as the signal connection is made. To allow designers to maintain this condition until after a module is fully powered and initialized, the OE pin can be used to maintain outputs in the high impedance, precharged state. Contact bounce during live insertion will charge each output pin to a logic ONE or ZERO. If the contact bounces open, the 40 k resistor will reestablish the 1.5V level in a few microseconds. The figure VCC Power-up Critical Voltages shows the relationship between VCC and OE while power is being applied and removed. This relationship holds if VCC Bias is within normal operating conditions or if VCC Bias is equal to VCC. DS100228-13 Power Sequencing to Achieve Live Insertion Precharging DS100228-14 VCC and OE Power-Up Relationship 5 www.national.com Absolute Maximum Ratings (Note 1) DC Latchup Source Current Over Voltage Latchup (I/O) If Military/Aerospace specified devices are required, please contact the National Semiconductor Sales Office/ Distributors for availability and specifications. Storage Temperature Ambient Temperature under Bias Junction Temperature under Bias Ceramic Plastic VCC Pin Potential to Ground Pin Input Voltage (Note 2) Input Current (Note 2) Voltage Applied to Any Output in the Disabled or Power-off State in the HIGH State Current Applied to Output in LOW State (Max) -500 mA 10V Recommended Operating Conditions -65C to +150C -55C to +125C Free Air Ambient Temperature Military Commercial Supply Voltage Military Commercial Minimum Input Edge Rate Data Input Enable Input -55C to +175C -55C to +150C -0.5V to +7.0V -0.5V to +7.0V -50 mA to +5.0 mA -55C to +125C -40C to +85C +4.5V to +5.5V +4.5V to +5.5V (t/V) 20 ns/V 50 ns/V Note 1: Absolute maximum ratings are values beyond which the device may be damaged or have its useful life impaired. Functional operation under these conditions is not implied. -0.5V to 5.5V -0.5V to VCC Note 2: Either voltage limit or current limit is sufficient to protect inputs. 128 mA DC Electrical Characteristics Symbol Parameter VME01 Min VIH VIL Input HIGH Voltage Input LOW Voltage VCD Input Clamp Diode Voltage VOH Output HIGH Voltage OE 2.0 Other Inputs 1.6 Typ Units OE 0.8 Other Inputs 1.4 B Port VOL Output LOW Voltage Bus Hold Current Recognized HIGH Signal V Recognized LOW Signal -1.2 V V 2.4 V 2.0 V V 2.0 V B Port 0.4 V 0.8 V A Port 0.55 V B Port 100 Min IIN = -18 mA (OEn, DIR) IOH = -100 A IOH = -1 mA Min IOH = -12 mA IOH = -1 mA IOH = -32 mA Min IOH = -60 mA IOL = 1 mA Min V 2.4 0.9 IHOLD Min V A Min -100 ICC Conditions V VCC - 1 VCC - 1 A Port VCC Max mA 100 A OE = HIGH, VO = 0.8V OE = HIGH, VO = 2.0V VCC = VCC Bias VCC Bias = 0 to 5.5V VCC Bias Supply Current 10 IOL = 12 mA IOL = 64 mA IOL = 90 mA IO = 0 IOFF II Output Current, Power Down Input Current Control Pins Military Commercial IIH + Output Leakage Current A Port IOZH www.national.com 6 0.0 VCC Bias = 0V 10 5 A 5.5 A 5.5 VI or VO 4.5V VIN = 0 or VCC VIN = 0 or VCC 50 A 5.5 VOUT = 2.7V, OE = 2.0V DC Electrical Characteristics Symbol (Continued) Parameter VME01 Min IIL + Output Leakage Current Typ A Port Units VCC Conditions -50 A 5.5 VOUT = 0.5V, OE = 2.0V Max IOZL ICCH Power Supply Current 40 mA Max All Outputs HIGH, OE = LOW, DIR = HIGH or LOW ICCL Power Supply Current 80 mA Max ICCZ Power Supply Current 40 All Outputs LOW, OE = LOW, DIR = HIGH or LOW OE = HIGH mA Max All Others at VCC or GND DIR = HIGH or LOW mA/ MHz Max ICCD Dynamic ICC 0.15 No Load (Note 3) VLI Output Live A Port Precharge Current 1.7 V 5.0 -20 -100 A 5.0 20 100 A 5.0 VO = 3V, VCC Bias = 5.0V, OE = High 1.0 V 5.0 V 5.0 TA = 25C (Note 4) CL = 50 pF; RL = 500 TA = 25C (Note 4) CL = 50 pF; RL = 500 V 5.0 V 5.0 V 5.0 A-Port VOLP Quiet Output Maximum Dynamic VOL VOLV Quiet Output Minimum -1.4 Dynamic VOL VOHV Minimum High Level Dynamic 2.7 Output Voltage (Note 3) VIHD Minimum High Level Dynamic 2.0 1.5 Input Voltage (Note 3) VILD One Bit Toggling, 50% Duty Cycle IOUT = 0 mA, OE = HIGH 1.3 Insertion Voltage IPRE Outputs Open n = GND, DIR = HIGH OE Maximum Low Level Dynamic 1.2 0.8 Input Voltage (Note 3) VCC Bias = 5.0V OE = HIGH, VO = 0V, VCC Bias = 5.0V TA = 25C (Note 6) CL = 50 pF; RL = 500 TA = 25C (Note 5) CL = 50 pF; RL = 500 TA = 25C (Note 5) CL = 50 pF; RL = 500 Note 3: Guaranteed, but not tested. Note 4: Max. number of outputs defined as (n). n - 1 data inputs are driven 0V to 3V. One output at LOW. Guaranteed, but not tested. Note 5: Max. number of data inputs (n) switching. n - 1 inputs switching 0V to 3V. Input-under-test switching: 3V to threshold (VILD), 0V to threshold (VIHD). Guaranteed, but not tested. Note 6: Max. number of outputs defined as (n). n - 1 data inputs are driven 0V to 3V. One output HIGH. Guaranteed, but not tested. AC Electrical Characteristics Symbol Parameter Commercial TA = +25C VCC = +5V Min Typ Max Military TA = -55C to +125C VCC = 4.5V-5.5V Commercial TA = -40C to +85C VCC = 4.5V-5.5V Min Max Min Max tPLH Propagation 1.5 7.0 1.5 7.0 1.5 7.0 tPHL Delay A-Port to B-Port 1.5 7.0 1.5 7.0 1.5 7.0 tPLH Propagation 1.5 7.0 1.5 7.0 1.5 7.0 tPHL Delay B-Port to A-Port 1.5 7.0 1.5 7.0 1.5 7.0 tPZH Output Enable 1.0 7.0 1.0 7.0 1.0 7.0 tPZL Time 1.0 7.0 1.0 7.0 1.0 7.0 7 Units Fig. No. ns Figures 1, 2, 3, 4, 6 ns Figures 1, 2, 3, 4, 6 ns Figures 1, 2, 3, 4, 5 www.national.com AC Electrical Characteristics Symbol Parameter Commercial TA = +25C (Continued) Military TA = -55C to +125C VCC = 4.5V-5.5V VCC = +5V Min Typ Max Commercial TA = -40C to +85C VCC = 4.5V-5.5V Units Fig. No. ns Figures 1, 2, 3, 4, 5 Min Max Min Max tPHZ Output Disable 1.0 7.0 1.0 7.0 1.0 7.0 tPLZ Time 1.0 7.0 1.0 7.0 1.0 7.0 tr Rise Time 1V 2V, 1.2 3.0 0.8 4.0 1.2 3.0 ns Figures 1, 2, 3, 4, 6 tf A-Port Outputs Fall Time 2V 1V, 1.2 3.0 0.8 4.0 1.2 3.0 ns Figures 1, 2, 3, 4, 6 A-Port Outputs Skew Symbol Parameter tOHS Pin-to-Pin Skew (Notes 7, 8) LH/HL A-Port to B-Port tOHS Pin-to-Pin Skew (Notes 7, 8) LH/HL B-Port to A-Port tPS Duty Cycle Skew (Notes 7, 8) B-Port to A-Port tPS Duty Cycle Skew (Notes 7, 8) A-Port to B-Port Commercial TA = -40C to +85C VCC = 4.5V-5.5V Military TA = -55C to +125C VCC = 4.5V-5.5V Units Conditions 16 Outputs Switching 16 Outputs Switching Max Max 1.3 1.3 ns Figures 1, 2, 3, 4, 6 1.3 1.3 ns Figures 1, 2, 3, 4, 6 2.0 2.0 ns Figures 1, 2, 3, 4, 6 2.0 2.0 ns Figures 1, 2, 3, 4, 6 VME Extended Skew Symbol Parameter tPV Device-to-Device Skew LH/HL (Notes 7, 8) Transitions B-Port to A-Port tPV Device-to-Device Skew LH/HL (Notes 7, 8) Transitions A-Port to B-Port tCP Change in Propagation Delay (Notes 7, 9) with Load B-Port to A-Port tCPV Device-to-Device, Change (Notes 7, 8, 9) in Propagation Delay with Commercial TA = -40C to +85C VCC = 4.5V-5.5V Military TA = -55C to +125C VCC = 4.5V-5.5V Units Conditions 16 Outputs Switching 16 Outputs Switching Max Max 4.0 4.5 ns Figures 1, 2, 3, 4, 6 2.5 3.0 ns Figures 1, 2, 3, 4, 6 4.0 4.5 ns Figures 1, 2, 3, 4, 6 6.0 7.0 ns Figures 1, 2, 3, 4, 6 Load B-Port to A-Port Note 7: Skew is defined as the absolute difference in delay between two outputs. The specification applies to any outputs switching HIGH to LOW, LOW to HIGH, or any combination switching HIGH-to-LOW or LOW-to-HIGH. This specification is guaranteed but not tested. Note 8: This is measured with both devices at the same value of VCC 1% and with package temperature differences of 20C from each other. Note 9: This is measured with Rx in Figure 1 at 13 for one unit and at 56 for the other unit. www.national.com 8 Capacitance Typ Max Units CIN Symbol Input Capacitance Parameter 5 8 pF CI/O (Note 10) Output Capacitance 9 12 pF Conditions, TA = 25C VCC = 0.0V (OEn, DIR) VCC = 5.0V (An) Note 10: CI/O is measured at frequency f = 1 MHz, per MIL-STD-883B, Method 3012. 9 www.national.com AC Loading Amplitude Rep. Rate tw tr tf 3.0V 1 MHz 500 ns 2.5 ns 2.5 ns FIGURE 3. Test Input Signal Requirements Test Port SW1 SW2 tPHZ, A, B Open Open Rx A, B +7 Open A Open Closed B Open Open tr, tf A Open Closed 26 tPV A Open Closed 26 tPV B Open Open tCP A Open Closed 13 then 56 tCPV A Open Closed 13 and 56 tPZH tPLZ, tPZL DS100228-4 tPLH, *Includes jig and probe capacitance 26 tPHL FIGURE 1. Standard AC Test Load tPLH, tPHL Note 11: Defined to emulate the range of VME bus transmission line loading as a function of board population and driver location. Rx = 13, 26 or 56 depending on test. FIGURE 4. DS100228-6 FIGURE 2. Input Pulse Requirements DS100228-7 FIGURE 5. TRI-STATE Output HIGH and LOW Enable and Disable Times DS100228-10 FIGURE 6. Rise, Fall Time and Propagation Delay Waveforms www.national.com 10 Ordering Information The device number is used to form part of a simplified purchasing code where the package type and temperature range are defined as follows: DS100228-15 11 www.national.com 12 Physical Dimensions inches (millimeters) unless otherwise noted 48-Lead SSOP (0.300" Wide) (SS) NS Package Number MS48A 48-Pin Ceramic Flatpak (FPFP) NS Package Number WA48A 13 www.national.com VME01 16-Bit TTL Compatible Data Transceiver with Incident Wave Switching LIFE SUPPORT POLICY NATIONAL'S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF NATIONAL SEMICONDUCTOR CORPORATION. As used herein: 2. A critical component in any component of a life support 1. Life support devices or systems are devices or sysdevice or system whose failure to perform can be reatems which, (a) are intended for surgical implant into sonably expected to cause the failure of the life support the body, or (b) support or sustain life, and whose faildevice or system, or to affect its safety or effectiveness. ure to perform when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant injury to the user. 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