Integrated Circuit Systems, Inc. ICS1523 High-Performance I2C Programmable Clock Generator General Description Features The ICS1523 is a low-cost but very high-performance frequency generator. It is perfectly suited to general purpose phase controlled clock synthesis as well as line-locked and genlocked high-resolution video applications. Using ICS's advanced low-voltage CMOS mixed-mode technology, the ICS1523 is an effective phase controlled clock synthesizer and also supports video projectors and displays at resolutions from VGA to beyond UXGA. * Very low jitter * Very wide input frequency ranges The ICS1523 offers clock outputs in both differential (to 250 MHz) and single-ended (to 150 MHz) formats. Dynamic Phase AdjustTM circuitry allows user control of the clock phase relative to the recovered sync signal. A second differential output at half the clock rate enables deMUXing of multiplexed analog-to-digital converters. The FUNC pin provides either the regenerated input from the phase-locked loop (PLL) divider chain output or a re-synchronized and sharpened input HSYNC. The advanced PLL uses either its internal programmable feedback divider or an external divider. The device is programmed by a standard I2C-busTM serial interface and is available in a 24-pin wide small-outline integrated circuit (SOIC) package. Block Diagram * 8 kHz to 100 MHz * Balanced PECL differential outputs * Up to 250 MHz * Single-ended SSTL_3 clock outputs * Up to 150 MHz * Dynamic Phase Adjust (DPA) for all outputs * Software controlled phase adjustment * 360o Adjustment down to 1/64 clock increments * Double buffered control registers * External or internal loop filter selection * Uses 3.3 VDC Inputs are 5 volt tolerant. * I2C-bus serial interface runs at either low speed (100 kHz) or high speed (400 kHz). * Hardware and Software PLL Lock detection * 24-pin 300-mil SOIC package Applications * Generic frequency synthesis * LCD monitors and video projectors * Genlocking multiple video subsystems Pin Configuration 24-Pin SOIC 2 I C-bus is a trademark of Philips Corporation. ICS1523 Rev T 6/06/2002 1 ICS reserves the right to make changes in the device data identified in this publication without further notice. ICS advises its customers to obtain the latest version of all device data to verify that any information being relied upon by the customer is current and accurate. ICS1523 Document Revision History Rev P (First Release) Pin Descriptions changed to add type column. (pg 3) Added SDA and AC Input Characteristics. (pg 18) Changed VCO Output, Intrinsic Jitter graph to show slow and fast cases (pg 19) Timing diagram changes to reference t0 to REF and notes on test conditions added (pg 22) Lock Renamed Lock/Ref (Throughout). General cleanup for readability. Rev Q Added typical external loop filter values. (pg 17) Added section on power supply considerations and SSTL_3 outputs. (pg 18) Correct labels and scale on VCO Output, Intrinsic Jitter graph. (pg 20) Correct depiction of timing diagram and added typical transition timing. (pg 23) Added Document Revision History. (pg 25) Rev R Change to descriptions for pins 20 to 23. (pg 3) Change to description for Reg 0h bits 0 and 1, added table. (pg 6) Within table for Reg 0h bits 6 and 7, changed Osc_En to IN_SEL . (pg 6) Moved Reg 0 bits 4 through 7 from pg 6 to new pg 7. Change to Software Programming Flow diagram. (pg 13). Under Recommend Operating Conditions, PECL Outputs, Output Low Voltage, added a note and added page 19 Added under Absolute Maximum Ratings ESD ratings and warning. (pg 19) Under Recommend Operating Conditions, SSTL-3 Outputs, Output Low Voltage, changed direction of symbols. (pg 19) Change to VCO Output Frequency and Intrinsic Jitter graph to reflect correct VCO frequency (pg 20) Rev S Moved Revision History from last page of data sheet to second page. (pg 2) In Layout Guideline 2, changed shunt capacitor value from 150 pF to 33 pF. (pg 19) Changed various cross-references within Layout Guidelines. (pg 19) Rev T Miscellaneous, non-substantiative changes to clarify general purpose, non-line-locked applications. Register bit summary tables merged with detailed register bit description tables for each register. Layout Guidelines corrected and updated. (pg 17) PDen / PD_Pol table corrected. (pg 7) ICS1523 Rev T 6-06-2002 2 ICS1523 Overview The ICS1523 is a high-performance user programmable, general purpose clock generator that also addresses stringent graphics system line-locked and genlocked applications and provides the clock signals required by high-performance analog-to-digital converters. Included are a phase-locked loop (PLL) with a 500 MHz voltage controlled oscillator (VCO), a Dynamic Phase Adjust to provide a user-programmed clock delay, the means for deMUXing multiplexed ADCs, and both balanced-programmable (PECL) and single-ended (SSTL_3) high-speed clock outputs. Phase-Locked Loop The phase-locked loop is a very wide input frequency range (8 kHz to 100 MHz), not only making it an excellent, general purpose clock synthesizer, but also is capable of line-locked operation. A high-performance Schmitt trigger preconditions the HSYNC input, whose pulses are from a remote source and of unknown quality. This preconditioned HSYNC signal is provided as a clean reference signal with a short transition time. A second high-frequency input such as a crystal oscillator and a 7-bit programmable divider can be selected. This selection allows the loop to operate from any appropriate source and is also useful for evaluating intrinsic jitter. A 12-bit programmable feedback divider completes the loop. Designers can also use an external divider. Either the conditioned HSYNC input or the loop output (recovered HSYNC) is available at the FUNC pin, phase aligned to the edge of the clock. Automatic Power-On Reset Detection The ICS1523 has automatic power-on reset detection circuitry and it resets itself if the supply voltage drops below threshold values. No external connection to a reset signal is required. Dynamic Phase AdjustTM The Dynamic Phase AdjustTM allows addition of a programmable delay to the clock output, relative to the recovered HSYNC signal. The ability to add delays is particularly useful when multiple video sources must be synchronized. A delay of up to one clock period is selectable in the following increments: * 1/64 period for clock rates to 40 MHz * 1/32 period for clock rates to 80 MHz * 1/16 period for clock rates to 160 MHz Output Drivers and Logic Inputs The ICS1523 utilizes low-voltage TTL (LVTTL) inputs as well as SSTL_3 (EIA/JESD8-8) and low-voltage PECL (pseudoECL) outputs, operating at 3.3-V supply voltage. The LVTTL inputs are 5 V-tolerant. The SSTL_3 and differential PECL output drivers drive resistive terminations or transmission lines. At lower clock frequencies, the SSTL_3 outputs can be operated unterminated. For more details reguarding the ICS1523's clock outputs, please see the ICS documents "Using SSTL-3 Outputs with CMOS or LVTTL Inputs" and "Designing a Custom PECL Interface for the ICS1523" available on www.icst.com. I2C Bus Serial Interface The ICS1523 utilizes a 5 Volt tolerant, industry-standard I2C-bus serial interface that runs at either low speed (100 kHz) or high speed (400 kHz). The interface uses 12 registers: one write-only, eight read/write, and three read-only. Two ICS1523 devices can be addressed, according to the state of the I2CADR pin. When this pin is low, the read address is 4Dh, and the write address is 4Ch. When the pin is high, the read address is 4Fh, and the write address is 4Eh. 3 ICS1523 Rev T 6-06-2002 ICS1523 Pin Descriptions PIN NO. P I N NA M E TYPE DESCRIPTION COMMENTS 1 VDDD PWR Digital supply 2 VSSD PWR Digital ground 3 S DA IN/OUT Serial data I 2 C - bu s 1 4 SCL IN Serial clock I 2 C - bu s 1 5 PDEN IN PFD enable S u s p e n d s c h a rg e p u m p 1 6 EXTFB IN External feedback in External divider input to P F D 1 7 HSYNC IN Horizontal sync Clock input to PLL1 8 EXTFIL IN External filter External PLL loop filter IN 3.3V to digital sections 9 XFILRET External filter return E x t e r n a l P L L l o o p fi l t e r r e t u r n 10 V D DA PWR Analog supply 3.3V for analog circuitry 11 VSSA PWR Analog ground Ground for analog circuitry 12 OSC Oscillator Input from crystal oscillator package1 , IN 2 2 13 14 I2 CADR LOCK/REF (SSTL) IN OUT I2 C address Chip I C address select Low = 4Dh read, 4Ch write High = 4Fh read, 4Eh write Lock indicator/reference Displays PLL or DPA lock or REF input 15 FUNC (SSTL) OUT Function output SSTL_3 selectable HSYNC output 16 CLK/2 (SSTL) OUT P i xe l c l o c k / 2 o u t SSTL_3 driver to ADC deMUX input 17 CLK (SSTL) OUT P i xe l c l o c k o u t SSTL_3 driver to ADC 18 VDDQ PWR Output driver supply 3.3V to output drivers 19 VSSQ PWR Output driver ground Ground for output drivers 20 CLK- (PECL) OUT P i xe l c l o c k o u t Inverted PECL driver to ADC. Open drain. 21 CLK+ (PECL) OUT P i xe l c l o c k o u t PECL driver to ADC. Open drain. P i xe l c l o c k / 2 o u t Inverted PECL driver to ADC deMUX input. Open drain. 22 CLK/2- (PECL) OUT 23 CLK/2+ (PECL) OUT P i xe l c l o c k / 2 o u t PECL driver to ADC deMUX input. Open drain. 24 IREF IN Reference current Reference current for PECL outputs Notes: 1. These LVTTL inputs are 5 V-tolerant. 2. Connect to ground if unused. ICS1523 Rev T 6-06-2002 4 ICS1523 Block Diagram 5 ICS1523 Rev T 6-06-2002 ICS1523 I2C Register Map Summary Register Index 0h 1h Name Input Control Loop Control Access R/W R/W * 2h FdBk Div 0 R/W * 3h FdBk Div 1 R/W * 4h 5h 6h 7h 8h DPA Offset DPA Control Output Enables Osc_Div Reset R/W Bit Name Bit # PDen 0 PD_Pol 1 0 Phase Detector Enable Polarity (0=Not Inverted, 1=Inverted) Ref_Pol 2 0 External Reference Polarity (0=Positive Edge, 1=Negative Edge) Fbk_Pol 3 0 External Feedback Polarity (0=Positive Edge, 1=Negative Edge) Fbk_Sel 4 0 External Feedback Select (0=Internal Feedback, 1=External) Func_Sel 5 0 Function Out Select (0=Recovered HSYNC, 1=Input HSYNC) EnPLS 6 1 Enable PLL Lock/Ref Status Output (0=Disable 1=Enable) EnDLS 7 0 Enable DPA Lock/Ref Status Output (0=Disable 1=Enable) Phase Detector Gain PFD0-2 0-2 0 Reserved 3 0 Reserved PSD0-1 4-5 0 Post-Scaler Divider (0 = 2, 1 = 4, 2 = 8, 3 = 16) Reserved 6-7 0 Reserved FBD0-7 0-7 FF PLL FeedBack Divider LSBs (bits 0-7) * FBD8-11 0-3 F PLL Feedback Divider MSBs (bits 8-11) * Reserved 4-7 0 Reserved DPA_OS0-5 0-5 0 Dynamic Phase Aligner Offset Reserved 6 0 Reserved Fil_Sel 7 0 Loop Filter Select (0=External, 1=Internal) R / W ** DPA_Res0-1 R/W R/W Write Reset Description Value 1 Phase Detector Enable (0=External Enable, 1=Always Enabled) 0-1 3 DPA Resolution (0=16 delay elements, 1=32, 2=Reserved, 3=64) Metal_Rev 2-7 0 Metal Mask Revision Number OE_Pck 0 0 Output Enable for PECL PCLK Outputs ( 0=High Z, 1=Enabled) OE_Tck 1 0 Output Enable for STTL_3 CLK Output ( 0=High Z, 1=Enabled) OE_P2 2 0 Output Enable for PECL CLK/2 Outputs ( 0=High Z, 1=Enabled) OE_T2 3 0 Output Enable for STTL_3 CLK/2 Output ( 0=High Z, 1=Enabled) Output Enable for STTL_3 FUNC Output ( 0=High Z, 1=Enabled) OE_F 4 0 Ck2_Inv 5 0 CLK/2 Invert (0=Not Inverted, 1= Inverted) Out_Scl 6-7 0 SSTL Clock Scaler (0 = 1, 1 = 2, 2 = 4, 3 = 8) Osc_Div 0-6 0-6 0 Osc Divider modulus In-Sel 7 1 Input Select (0=HSYNC Input, 1=Osc Divider) DPA 0-3 x Writing xAh resets DPA and loads working register 5 PLL 4-7 x Writing 5xh resets PLL and loads working registers 1-3 10h Chip Ver Read Chip Ver 0-7 17 Chip Version 23 Dec (17 Hex) as in 1523 11h Chip Rev Read Chip Rev 0-7 01 Initial value 01h. Value Increments with each all-layer change. 12h Rd_Reg Read DPA_Lock 0 N/A DPA Lock Status (0=Unlocked, 1=Locked) PLL_Lock 1 N/A Reserved 2-7 0 PLL Lock Status (0=Unlocked, 1=Locked) Reserved * Identifies double-buffered registers. Working registers are loaded during software PLL reset. ** Identifies double-buffered register. Working registers are loaded during software DPA reset. ICS1523 Rev T 6-06-2002 6 ICS1523 Detailed Register Description Name: Input Control Register: 0h Access: Read/Write Bit Name Reset 0 PDen 1 Description Phase/Frequency Detector (PFD) Enable PD_Pol PDen Bit 1 Bit 0 0 0 x 1 1 0 P h a s e / F r e q u e n cy De t e c t o r E n a b l e d Wh e n : PDEN (pin 5) = 1 Always (Default) PDEN (pin 5) = 0 1 PD_Pol 0 PFD Enable Polarity 2 Ref_Pol 0 Phase/Frequency Detector External Reference Polarity Edge of input signal on which Phase Detector triggers. 0 = Rising Edge (default) 1 = Falling Edge 3 Fbk_Pol 0 External Reference Feedback Polarity Edge of EXTFB (pin 6) signal on which Phase/Frequency Detector triggers when external feedback is used (Reg0 [4]=1). 0 = Positive Edge (default) 1 = Negative Edge 4 Fbk_Sel 0 External Feedback Select 0 = Internal Feedback (default) 1 = External Feedback 5 Func_Sel 0 Function Output Select Selects re-clocked output to FUNC (pin 15). 0 = Recovered (Re-generated from Feedback Loop) HSYNC (default).. 1 = External HSYNC. Schmitt-trigger conditioned signal from HSYNC (pin 7). 6 EnPLS 1 LOCK/REF (pin14) Output Control. See Table Below. 7 EnDLS 0 EnPLS EnDLS IN_SEL LOCK/ REF( 14) 0 0 N/A 0 0 1 N/A 1 if DPA locked, 0 otherwise 1 0 N/A 1 if PLL locked, 0 otherwise Post Schmitt trigger 1 1 0 HSYNC(7) XOR Ref_Pol 1 1 1 Fosc / Osc_Div 7 ICS1523 Rev T 6-06-2002 ICS1523 Name: Register: Access: Loop Control Register 1h Read/Write* Bit Name Reset 0-2 PFD0-2 3 Reserved 4-5 PSD0-1 6-7 Reserved 0 Description Phase/Frequency Detector Gain Bit 2 Bit 1 Bit 0 PFD Ga i n ( A/ 2 r a d) 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 1 2 4 8 16 32 64 128 0 0 Post-Scaler Divider Divides the output of the VCO to the DPA and Feedback Divider. Bit 5 Bit 4 PSD Divider 0 0 1 1 0 1 0 1 2 (default) 4 8 16 0 * Double-buffered register. Working registers are loaded at the rising edge of SDA durring the final I2C ACK cycle after writing the software PLL reset value. See register 8h for details. ICS1523 Rev T 6-06-2002 8 ICS1523 Name: Registers: Access: Feedback Divider 0 / Feedback Divider 1 Register(s) 2h, 3h Read/Write* Bit Name Index Bit Value FBD0-7 2 0-7 FF FBD8-11 3 0-3 F Description PLL Feedback Divider LSB Bits 0-7.* Bit 0 = 0, total number of clocks per line is even. Bit 0 = 1, total number of clocks is odd. See AC Timing Characteristics Overview for more details. PLL Feedback Divider MSBs Bits 8-11* The value that is programmed into these two registers, plus 8, controls the total number of clocks that the ICS1523 generates between phase updates (normally HSYNCs). Program these registers with the hex digits equal to the decimal value of the total number of clocks per line minus 8. (i.e. 20hex = 40dec clocks) See AC Timing Characteristics Overview for more details. 3 Feedback Divider Modulus Reg 3 2 1 0 7 6 5 Reg 2 4 3 2 = 1 0 +8 12 Feedback Divider Modulus 4103 Reserved 3 4-7 Reserved 2 * Double-buffered register. Working registers are loaded at the rising edge of SDA durring the final I C ACK cycle after writing the software PLL reset value. See register 8h for details. 9 ICS1523 Rev T 6-06-2002 ICS1523 Name: Register: Access: DPA Offset Register 4h Read/Write Bit Name Reset 0-5 DPA_OS 0 Description Dynamic Phase Adjust Offset. Selects phase offset in discrete steps up to one clock period minus one step. Resolution (number of delay elements per clock cycle) is controlled by DPA_Res0-1 (Reg 5:0-1). Offsets equal or greater than one clock period are not recommended or supported. Example: DPA_Res0-1 = 01H, the clock can ONLY be delayed from 0 to 31 steps. 7 Fil_Sel 0 Loop Filter Selection 0 - Selects external loop filter (default) 1 - Selects Internal loop filter The use of an external loop filter is strongly recommended for all designs Suggested component values are available from the ICS1523 Demo Board Guide (1523DB.pdf) or the ICS1523 Register Tool (inst1523.exe) available on our web site at: (http://www.icst.com/products/pinfo/1523.htm). ICS1523 Rev T 6-06-2002 10 ICS1523 Name: Register: Access: DPA Control Register 5h Read/Write* Bit Name Reset 0-1 DPA_Res 11 Description Dynamic Phase Adjust (DPA) Resolution Select. It is not recommended to use the DPA above 160 MHz. Bit 1 0 0 1 1 2-7 Metal_Rev 00 Bit 0 0 1 0 1 CLK Range, MHz 48 24 80 Delay Elements 16 32 Reserved 64 12 160 40 Metal Mask Revision Number. After power-up, register bits 7:2 must be written with 111111. After this write, a read indicates the metal mask revision, as below Revision Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 A B C1 C2 D E F G 1 0 1 0 1 1 1 1 1 1 0 0 1 1 1 1 1 1 1 1 0 1 1 1 1 1 1 1 1 0 1 1 1 1 1 1 1 1 0 1 1 1 1 1 1 1 1 0 *2Double-buffered register. Working registers are loaded at the rising edge of SDA durring the final I C ACK cycle after writing the software DPA reset value. See register 8h for details. 11 ICS1523 Rev T 6-06-2002 ICS1523 Name: Register: Access: Output Enable Register 6h Read/Write Bit Name Reset Description 0 OE_Pck 0 Output Enable for CLK Outputs (PECL, Pins 21,20) 0 = High Z (default) 1 = Enabled 1 OE_Tck 0 Output Enable for CLK Output (SSTL_3, Pin 17) 0 = High Z (default) 1 = Enabled 2 OE_P2 0 Output Enable for CLK/2 Outputs (PECL, Pins 23, 22 ) 0 = High Z (default) 1 = Enabled 3 OE_T2 0 Output Enable for CLK/2 Output (SSTL_3, Pin 16) 0 = High Z (default) 1 = Enabled 4 OE_F 0 Output Enable for FUNC Output (SSTL_3, Pin 15) 0 = High Z (default) 1 = Enabled 5 Ck2_Inv 0 CLK/2 (Pin 16) Invert 0 = Not Inverted (default) 1 = Inverted 6-7 Out_Scl 00 Clock (CLK, Pin 17) Output Scaler ICS1523 Rev T 6-06-2002 Bit 7 Bit 6 CLK Divider 0 0 1 1 0 1 0 1 1 2 4 8 12 ICS1523 Name: Register: Access: Oscillator Divider Register 7h Read/Write Bit Name Reset Description 0-6 Osc_Div 0 Oscillator Divider Modulus. Divides the input from OSC (pin 12) by the set modulus. The modulus equals the programmed value, plus 2. Therefore, the modulus range is from 3 to 129. OSC signal will have 1 OSC input period high (and the rest low) per modulus cycle 7 In_Sel 1 Input Select Selects the input to the Phase/Frequency Detector 0 = HSYNC 1 = Osc Divider (default) Name: Register: Access: RESET Register 8h Write Bit Name Reset Description 0-3 DPA x Writing xAh to this register resets DPA working register 5 4-7 PLL x Writing 5xh to this register resets PLL working registers 1-3 Value Resets xA 5x 5A DPA PLL DPA and PLL Double-buffered register control. PLL and/or DPA Working registers are loaded at the rising edge of SDA durring the final I2C ACK cycle after writing the proper corresponding reset value to this register. 13 ICS1523 Rev T 6-06-2002 ICS1523 Name: Register: Access: Bit Name Chip Ver Chip Version Register 10h Read Bit # Reset Value 0-7 17 Name: Register: Access: Bit Name Chip Rev Description Chip Version 23 (decimal) Chip Revision Register 11h Read Bit # Reset Value 0 -7 01+ Name: Register: Access: Description Initial value 01h. +Value increments with each all-layer change. Status Register 12h Read Bit Name Reset Description 0 DPA_Lock n/a DPA Lock Status. Refer to Register 0h, bits 6 and 7 0 = Unlocked 1 = Locked 1 PLL_Lock n/a PLL Lock Status. Refer to Register 0h, bits 6 and 7 0 = Unlocked 1 = Locked 2-7 Reserved ICS1523 Rev T 6-06-2002 0 14 ICS1523 I2C Data Characteristics Bit transfer on the I2C-bus START and STOP conditions Acknowledge on the I 2C-bus These waveforms are from "The I2 C-bus and how to use it," published by Philips Semiconductor. This and other I2 C documents can be obtained from the Philips Semiconductor web site, www.philips.com 15 ICS1523 Rev T 6-06-2002 ICS1523 I2C Data Format RANDOM REGISTER WRITE PROCEDURE S 0 1 0 0 1 1 x WA 7 bit address START condition A register address Acknowledge WRITE command A P data Acknowledge STOP condition Acknowledge RANDOM REGISTER READ PROCEDURE S 0 1 0 0 1 1 X WA 7 bit address START condition register address Acknowledge WRITE command A S 0 1 0 0 1 1 X R A 7 bit address data Repeat START Acknowledge Acknowledge READ command A P STOP condition NO Acknowledge SEQUENTIAL REGISTER WRITE PROCEDURE S 0 1 0 0 1 1 X WA 7 bit address START condition A register address Acknowledge WRITE command A data Acknowledge A data Acknowledge A P Acknowledge Acknowledge STOP condition SEQUENTIAL REGISTER READ PROCEDURE S 0 1 0 0 1 1 X WA 7 bit address START condition Direction: register address Acknowledge WRITE command From bus host to device A S 0 1 0 0 1 1 X R A 7 bit address data Repeat START Acknowledge Acknowledge READ command A A P data NO Acknowledge Acknowledge STOP condition From device to bus host Note: 1. All values are transmitted with the most-significant bit first and the least-significant bit last. 2. The value of the X bit equals the logic state of pin 13 (I2CADR). 3. R = READ = 1 and W = WRITE = 0 ICS1523 Rev T 6-06-2002 16 ICS1523 General Layout Guidelines * Use a PC board with at least four layers: one power, one ground, and two signal. * Use at least one 4.7 uF Tantalum (or similar) capacitor for global VDD bulk decoupling. * All supply voltages must be supplied from a common source and must ramp together. * Any flux or other board surface debris can degrade the performance of the external loop filter. * Ensure that the 1523 area of the board is free of contaminants. Specific Layout Guidelines 1. Digital Supply (VDD) - Bypass pin 1 (VDD) to pin 2 (VSS) a 0.1-F capacitor, located as close as possible to the pins. A 0.01-F capacitor may be added for additional high frequency rejection. 2. External Loop Filter - Strongly recommended in All Designs. Locate loop filter components as close to pins 8 and 9 (EXTFIL and EXTFILRET) as possible with minimum length traces. Typical loop filter values are 6.8K Ohms for the series resistor, 3300 pF RF-type capacitor for the series capacitor, and 33 pF for the shunt capacitor. (For details, see the Frequently Asked Questions part of the ICS1523 Applications Guide, FAQ2 and FAQ3.) A ground isolated, surface trace can be useful to isolate this section from the rest of the board. 3. Analog PLL Supply (VDDA) - Decouple main VDD from pin 10 (VDDA) with a series ferrite bead. Bypass the supply end of the bead with 4.7-F. Bypass pin 10 to pin 11 (VSSA) with a 0.1-F capacitor. A 0.01-F capacitor may be added for additional high frequency rejection. Locate these components as close as possible to the pins. 4. PECL Current Set Resistor - Locate PECL current-set resistor as close as possible to pin 24 (IREF). Bypass pin 24 to ground with a 0.1 -F capacitor. 5. PECL Outputs - Implement these outputs as microstrip transmission lines. The trace widths shown are for 75 char- . acteristic impedance. Locate any optional series "snubbing" resistors as close as possible to the source pins. If the termination resistors are included on-board, locate them as close as possible to the load and connect directly to the power and ground planes. [These termination resistors are omitted if the load device implements them internally. For details, see the ICS application note on microstrip and striplines (1572AN1) and within the ICS1523 Applications Guide, the application note on Designing a Custom Interface for the ICS1523 (1523AN4.)] 6. Output Driver Supply - Bypass pin 18 (VDDQ) to pin 19 (VSSQ) with a 0.1-F capacitor, located as close as possible to the pins. A 0.01-F capacitor may be added for additional high frequency rejection. 7. SSTL_3 Outputs - SSTL_3 outputs can be used like conventional CMOS rail-to-rail logic or as a terminated transmission line system at higher-output frequencies. With terminated outputs, the considerations of item 5, "PECL Outputs" apply. See JEDEC documents JESD8-A and JESD8-8. Note: For illustrative purposes only, drawing is not to scale. 17 ICS1523 Rev T 6-06-2002 ICS1523 PECL Outputs For information on using the ICS1523's PECL output pins, please refer to Application Note 4: Designing a Custom PECL Interface for the ICS1523 SSTL_3 Outputs Unterminated Outputs In the ICS1523, unterminated SSTL_3 output pins display exponential transitions similar to those of rectangular pulses presented to RC loads. The 10-90% rise time is typically 1.6 ns, and the corresponding fall time is typically 700 ps. In turn, this asymmetry contributes to duty cycle asymmetry at higher output frequencies. In the absence of significant load capacitance (which can further increase rise and fall time), this asymmetry is the dominant factor determining high-frequency performance of these single-ended outputs. Typically, no termination is required either for the LOCK/REF, FUNC, and CLK/2 outputs or for CLK outputs up to approximately 135 MHz. Terminated Outputs SSTL_3 outputs are intended to terminate in low impedances to reduce the effect of external circuit capacitance. Use of transmission line techniques enables use of longer traces between source and driver without increasing ringing due to reflections. Where external capacitance is minimal and substantial voltage swing is required to meet LVTTL VIH and VOL requirements, the intrinsic rise and fall times of ICS1523 SSTL outputs are only slightly improved by termination in a low impedance. The ICS1523 SSTL output source impedance is typically less than 60 Ohms. Termination impedance of 100 reduces output swing by less than 30% which is more than enough to drive a single load of LVTTL inputs. For more information on using the ICS1523's SSTL output pins, please refer to Application Note 3: Using SSTL_3 Outputs with CMOS or LVTTL Inputs ICS1523 Rev T 6-06-2002 18 ICS1523 Power Supply Considerations The ICS1523 incorporates special internal power-on reset circuitry that requires no external reset signal connection. The supply voltage (VDD) must remain within the recommended operating conditions during normal operation. To reset the ICS1523, the supply voltage at the part must be reduced below the threshold voltage (Vth) of the power-on reset circuit. The supply voltage must remain below that threshold voltage such that board power conditioning capacitors are drained and the proper reset state is latched. The amount of time (td) to hold the voltage in a reset state varies with the design. However, a typical value of 10 ms should be sufficient. Absolute Maximum Ratings VDD, VDDA, VDDQ (measured to VSS) . . . . . . . . . . . . . . . . . . Digital Inputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Analog Outputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Digital Outputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Storage Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Junction Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Soldering Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.3 V VSS - 0.3V to 5.5V VSSA - 0.3V to VDDA +0.3V VSSQ - 0.3V to VDDQ +0.3V - 65C to +150C 175C 260C ESD Susceptibility* . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . > 2 KV (*Electrostatic-sensitive devices. Do not open or handle except in a static-free workstation.) 19 ICS1523 Rev T 6-06-2002 ICS1523 Recommended Operating Conditions VDD, VDDQ, VDDA (measured to VSS) . . . 3.0 to 3.6 V Operating Temperature (Ambient) . . . . . . . . . 0 to +70 C DC Supply Current MI N MAX UNI TS Supply Current, Digital PA R A ME T E R S YMB OL I DDD VDDD = 3.6V CONDI TI ONS -- 25 mA Supply Current, Output Drivers I DDQ VDDQ = 3.6V, no output drivers enabled. -- 6 mA Supply Current, Analog I DDA VDDA = 3.6V -- 5 mA Digital Inputs (SDA, SCL, PDEN, EXTFB, HSYNC, OSC, I 2C ADR) MI N MA X UNI T S Input High Voltage PA R A ME T E R S YMB OL VI H CONDI TI ONS 2 5. 5 V Input Low Voltage VI L VS S - 0 . 3 0. 8 V Input Hysteresis 0. 2 0. 6 V IIH VIH = VDD -- 10 A Input Low Current IIL VIL = 0 -- 200 A Input Capacitance Ci n -- 10 pF MI N MA X UNI T S 0. 4 V MI N MA X UNI T S IOUT = 0 -- VDD V VDDD = 3.3V -- 250 MH z IOUT = programmed value 1. 0 -- V Input High Current SDA (In Output Mode: SDA is Bidirectional) PA R A ME T E R Output Low Voltage S YMB OL VOL CONDI TI ONS IOUT = 3 mA. VOH = 6.0V maximum as determined by the external pull-up resistor. P E CL Ou t p u t s ( CL K+ , CL K- , CL K/ 2 + , CL K/ 2 - ) PA R A ME T E R Output High Voltage Maximum Output Frequency Output Low Voltage (Note: VOL must not fall below the level given so that the correct value for IOUT can be maintained.) S YMB OL VOH Fp MAX VOL CONDI TI ONS S S T L - 3 Ou t p u t s ( CL K, CL K/ 2 , F UNC, L OCK/ RE F ) PA R A ME T E R Output Resistance Maximum Output Frequency S YMB OL RO Fs MAX MI N MA X UNI T S 1 <VO<2V CONDI TI ONS -- 80 VDDD = 3.3V -- 150 MH z AC Input Characteristics PA R A ME T E R HSYNC Input Frequency OSC Input Frequency ICS1523 Rev T 6-06-2002 S YMB OL MI N MA X UNI T S fHSYNC Reg 7:7 = 0 CONDI TI ONS . 008 10 MH z fOSC Reg 7:7 = 1 . 02 100 MH z 20 ICS1523 VCO Output Frequency and Intrinsic Jitter 700 700 600 600 Frequency (Slow: 3.0V @ 70"C) Frequency (Nominal: 3.3V @ 30"C) Frequency (Fast: 3.6V @ 0"C) 500 500 Jitter (3.0V @ 70"C) Jitter (3.6V @ 0"C) 400 400 Frequency 300 300 200 200 Jitter 100 100 0 0 0 0.2 0.4 0.6 0.8 1 1.2 1.4 1.6 1.8 2 2.2 2.4 2.6 2.8 3 3.2 VCO Voltage 21 ICS1523 Rev T 6-06-2002 Jitter (ps) VCO Frequency (MHz) Jitter (3.3V @ 30"C) ICS1523 ns Delay DPA Delay-16 Element Resolution 20 18 16 14 12 10 8 6 4 2 0 50 MHz - SVGA @ 72 Hz 157.5 MHz - SXGA @ 85 Hz 0 4 8 16 12 DPA Setting DPA Delay - 32 Element Resolution 45 ns Delay 40 35 25.175 MHz - VGA @ 60 Hz 30 78.75 MHz - XGA @ 75 Hz 25 20 15 10 5 0 0 4 8 12 16 20 24 32 28 DPA Setting DPA Delay - 64 Element Resolution 90 80 ns Delay 70 12.27 MHz - NTSC 60 39.8 MHz - SVGA @ 60 50 40 30 20 10 0 0 4 8 12 16 20 24 28 32 36 DPA Setting Note: Maximum number of data points used for this graph. ICS1523 Rev T 6-06-2002 22 40 44 48 52 56 60 64 AC Timing Characteristics Overview 23 ICS1523 ICS1523 Rev T 6-06-2002 * Timing when Register 2, Bit 0 = 0 (Total number of clocks is even.) ** Timing when Register 2, Bit 0 = 1 (Total number of clocks is odd.) ICS1523 Output Timing Diagram Typical Transition Times* Symbol Timing Description Rise Fall Units tR REF 2.8 1.8 ns tP PECL CLK 1.0 1.2 ns tS tF SSTL-CLK FUNC_OUT 1.6 1.2 0.7 1.0 ns ns Min Typ Max Units Output Timing* Symbol Timing Description t0 HSYNC to REF delay 11.3 11.5 12 ns t1 REF to PECL clock delay -1.0 0.8 2.2 ns PECL clock duty cycle 45 50 55 % t4 PECL clock to SSTL_3 clock delay 0.2 0.75 1.2 ns t5 PECL clock to FUNC_OUT delay 1.5 1.9 2.3 ns t6 PECL clock to PECL/2 clock 1.0 1.3 1.5 ns t7 PECL clock to SSTL_3-CLK/2 delay 1.1 1.4 1.8 ns SSTL clock duty cycle 45 50 55 % t2, t3 t8, t9 *Note: Measured at 3.6V 0C, 135-MHz output frequency, PECL clock lines to 75 termination, SSTL_3 clock lines unterminated, 20-pF load. Transition times vary based on termination. ICS1523 Rev T 6-06-2002 24 ICS1523 24-Pin SOIC (wide body) Ordering Information Part/Order Number Marking Package Shipping ICS1523M ICS1523M SOIC-24 Tubes ICS1523MT ICS1523M SOIC-24 Tape and Reel While the information presented herein has been checked for both accuracy and reliability, Integrated Circuit Systems, Incorporated (ICS) assumes no responsibility for either its use or for infringement of any patents or other rights of third parties, which would result from its use. No other circuits, patents, or licenses are implied. This product is intended for use in normal commercial applications. Any other applications such as those requiring extended temperature range, high reliability, or other extraordinary environmental requirements are not recommended without additional processing by ICS. ICS reserves the right to change any circuitry or specifications without notice. ICS does not authorize or warrant any ICS product for use in life support devices or critical medical instruments. 25 ICS1523 Rev T 6-06-2002 ICS1523 NOTES ICS1523 Rev T 6-06-2002 26 ICS1523 Integrated Circuit Systems, Inc. Corporate Headquarters: 2435 Boulevard of the Generals P.O. Box 968 Valley Forge, PA 19482-0968 Telephone: 610-630-5300 Fax: 610-630-5399 San Jose Operations: 525 Race Street San Jose, CA 95126-3448 Telephone: 408-297-1201 Fax: 408-925-9460 Web Site: http://www.icst.com 27 ICS1523 Rev T 6-06-2002