ICS1523MT - Integrated Circuit Systems, Inc.

Integrated

Circuit

Systems, Inc.

General Description Features

ICS1523

ICS1523 Rev T 6/06/2002

Block Diagram

High-Performance I2C Programmable Clock Generator

• Very low jitter

• Very wide input frequency ranges

• 8 kHz to 100 MHz

• Balanced PECL differential outputs

• Up to 250 MHz

• Single-ended SSTL_3 clock outputs

• Up to 150 MHz

• Dynamic Phase Adjust (DPA) for all outputs

• Software controlled phase adjustment

• 360o Adjustment down to 1/64 clock increments

• Double buffered control registers

• External or internal loop filter selection

• Uses 3.3 VDC Inputs are 5 volt tolerant.

•I

2C-bus serial interface runs at either low speed

(100 kHz) or high speed (400 kHz).

• Hardware and Software PLL Lock detection

• 24-pin 300-mil SOIC package

The ICS1523 is a low-cost but very high-performance

frequency generator. It is perfectly suited to general pur-

pose phase controlled clock synthesis as well as

line-locked and genlocked high-resolution video applica-

tions. Using ICS’s advanced low-voltage CMOS

mixed-mode technology, the ICS1523 is an effective

phase controlled clock synthesizer and also supports video

projectors and displays at resolutions from VGA to beyond

UXGA.

The ICS1523 offers clock outputs in both differential (to

250 MHz) and single-ended (to 150 MHz) formats. Dy-

namic Phase Adjust™ circuitry allows user control of the

clock phase relative to the recovered sync signal. A second

differential output at half the clock rate

enables deMUXing of multiplexed analog-to-digital con-

verters. The FUNC pin provides either the regenerated

input from the phase-locked loop (PLL) divider chain out-

put or a re-synchronized and sharpened input HSYNC.

The advanced PLL uses either its internal programmable

feedback divider or an external divider. The device is pro-

grammed by a standard I2C-bus™ serial interface and is

available in a 24-pin wide small-outline integrated circuit

(SOIC) package.

I2C-bus is a trademark of Philips Corporation.

ICS reserves the right to make changes in the device data identified in this

publication without further notice. ICS advises its customers to obtain the

latest version of all device data to verify that any information being relied

upon by the customer is current and accurate.

Applications

•Generic frequency synthesis

•LCD monitors and video projectors

•Genlocking multiple video subsystems

24-Pin SOIC

Pin Configuration

ICS1523

ICS1523 Rev T 6-06-2002

Document Revision History

Rev P (First Release)

Pin Descriptions changed to add type column. (pg 3)

Added SDA and AC Input Characteristics. (pg 18)

Changed VCO Output, Intrinsic Jitter graph to show slow and fast cases (pg 19)

T iming diagram changes to reference t0 to REF and notes on test conditions added (pg 22)

Lock Renamed Lock/Ref (Throughout).

General cleanup for readability.

Rev QAdded typical external loop filter values. (pg 17)

Added section on power supply considerations and SSTL_3 outputs. (pg 18)

Correct labels and scale on VCO Output, Intrinsic Jitter graph. (pg 20)

Correct depiction of timing diagram and added typical transition timing. (pg 23)

Added Document Revision History. (pg 25)

Rev RChange to descriptions for pins 20 to 23. (pg 3)

Change to description for Reg 0h bits 0 and 1, added table. (pg 6)

Within table for Reg 0h bits 6 and 7, changed Osc_En to IN_SEL . (pg 6)

Moved Reg 0 bits 4 through 7 from pg 6 to new pg 7.

Change to Software Programming Flow diagram. (pg 13).

Under Recommend Operating Conditions, PECL Outputs, Output Low Voltage, added a note and added page 19

Added under Absolute Maximum Ratings ESD ratings and warning. (pg 19)

Under Recommend Operating Conditions, SSTL-3 Outputs, Output Low Voltage, changed direction of symbols. (pg 19)

Change to VCO Output Frequency and Intrinsic Jitter graph to reflect correct VCO frequency (pg 20)

Rev S Moved Revision History from last page of data sheet to second page. (pg 2)

In Layout Guideline 2, changed shunt capacitor value from 150 pF to 33 pF. (pg 19)

Changed various cross-references within Layout Guidelines. (pg 19)

Rev TMiscellaneous, non-substantiative changes to clarify general purpose, non-line-locked applications.

Layout Guidelines corrected and updated. (pg 17)

PDen / PD_Pol table corrected. (pg 7)

ICS1523

ICS1523 Rev T 6-06-2002

Overview

The ICS1523 is a high-performance user programmable, general purpose clock generator that also addresses stringent graphics

system line-locked and genlocked applications and provides the clock signals required by high-performance analog-to-digital

converters. Included are a phase-locked loop (PLL) with a 500 MHz voltage controlled oscillator (VCO), a Dynamic Phase

Adjust to provide a user-programmed clock delay, the means for deMUXing multiplexed ADCs, and both balanced-program-

mable (PECL) and single-ended (SSTL_3) high-speed clock outputs.

Phase-Locked Loop

The phase-locked loop is a very wide input frequency range (8 kHz to 100 MHz), not only making it an excellent, general purpose

clock synthesizer, but also is capable of line-locked operation. A high-performance Schmitt trigger preconditions the HSYNC

input, whose pulses are from a remote source and of unknown quality . This preconditioned HSYNC signal is provided as a clean

reference signal with a short transition time.

A second high-frequency input such as a crystal oscillator and a 7-bit programmable divider can be selected. This selection al-

lows the loop to operate from any appropriate source and is also useful for evaluating intrinsic jitter.

A 12-bit programmable feedback divider completes the loop. Designers can also use an external divider.

Either the conditioned HSYNC input or the loop output (recovered HSYNC) is available at the FUNC pin, phase aligned to the

edge of the clock.

A utomatic P o wer -On Reset Detection

The ICS1523 has automatic power-on reset detection circuitry and it resets itself if the supply voltage drops below threshold

values. No external connection to a reset signal is required.

Dynamic Phase Adjust™

The Dynamic Phase Adjust™ allows addition of a programmable delay to the clock output, relative to the recovered HSYNC

signal. The ability to add delays is particularly useful when multiple video sources must be synchronized. A delay of up to one

clock period is selectable in the following increments:

• 1/64 period for clock rates to 40 MHz

• 1/32 period for clock rates to 80 MHz

• 1/16 period for clock rates to 160 MHz

Output Drivers and Logic Inputs

The ICS1523 utilizes low-voltage TTL (LVTTL) inputs as well as SSTL_3 (EIA/JESD8-8) and low-voltage PECL (pseudo-

ECL) outputs, operating at 3.3-V supply voltage. The LVTTL inputs are 5 V-tolerant. The SSTL_3 and differential PECL output

drivers drive resistive terminations or transmission lines. At lower clock frequencies, the SSTL_3 outputs can be operated

unterminated. For more details reguarding the ICS1523’s clock outputs, please see the ICS documents “Using SSTL-3 Outputs

with CMOS or LVTTL Inputs” and “Designing a Custom PECL Interface for the ICS1523” available on www.icst.com.

I2C Bus Serial Interface

The ICS1523 utilizes a 5 Volt tolerant, industry-standard I2C-bus serial interface that runs at either low speed (100 kHz) or high

speed (400 kHz). The interface uses 12 registers: one write-only , eight read/write, and three read-only . Two ICS1523 devices can

be addressed, according to the state of the I2CADR pin. When this pin is low, the read address is 4Dh, and the write address is

4Ch. When the pin is high, the read address is 4Fh, and the write address is 4Eh.

ICS1523

ICS1523 Rev T 6-06-2002

Pin Descriptions

Notes:

1. These LVTTL inputs are 5 V-tolerant.

2. Connect to ground if unused.

.ONNIPEMANNIPEPYTNOITPIRCSEDSTNEMMOC

1DDDVRWPylppuslatigiDsnoitceslatigidotV3.3

2DSSVRWPdnuorglatigiD

3ADSTUO/NIatadlaireSI

sub-C

4LCSNIkcolclaireSI

sub-C

5NEDPNIelbaneDFPpmupegrahcsdnepsuS

6BFTXENInikcabdeeflanretxEottupniredividlanretxEDFP

7CNYSHNIcnyslatnoziroHLLPottupnikcolC

8LIFTXENIretliflanretxEretlifpoolLLPlanretxE

9TERLIFXNInruterretliflanretxEnruterretlifpoolLLPlanretxE

01ADDVRWPylppusgolanAyrtiucricgolanarofV3.3

11ASSVRWPdnuorggolanAyrtiucricgolanarofdnuorG

21CSONIrotallicsOrotallicsolatsyrcmorftupnIegakcap

2,1

31I

RDACNII

sserddaC IpihC

tcelessserddaC etirwhC4,daerhD4=woL etirwhE4,daerhF4=hgiH

41 FER/KCOL )LTSS( TUOecnerefer/rotacidnikcoLtupniFERrokcolAPDroLLPsyalpsiD

51)LTSS(CNUFTUOtuptuonoitcnuFtuptuoCNYSHelbatceles3_LTSS

61)LTSS(2/KLCTUOtuo2/kcolclexiPtupniXUMedCDAotrevird3_LTSS

71)LTSS(KLCTUOtuokcolclexiPCDAotrevird3_LTSS

81QDDVRWPylppusrevirdtuptuOsrevirdtuptuootV3.3

91QSSVRWPdnuorgrevirdtuptuOsrevirdtuptuorofdnuorG

02)LCEP(–KLCTUOtuokcolclexiP.niardnepO.CDAotrevirdLCEPdetrevnI

12)LCEP(+KLCTUOtuokcolclexiP.niardnepO.CDAotrevirdLCEP

22)LCEP(–2/KLCTUOtuo2/kcolclexiP .tupniXUMedCDAotrevirdLCEPdetrevnI .niardnepO

32)LCEP(+2/KLCTUOtuo2/kcolclexiP .niardnepO.tupniXUMedCDAotrevirdLCEP

42FERINItnerrucecnerefeRstuptuoLCEProftnerrucecnerefeR

ICS1523

ICS1523 Rev T 6-06-2002

Block Diagram

ICS1523

ICS1523 Rev T 6-06-2002

I2C Register Map Summary

Index N ame A ccess B i t Nam e B i t # Reset

Value Description

0h Input Control R / W P Den 0 1 Phas e D et e c t or Ena ble (0=E x t ernal Enable, 1=A lways Enabled)

P D_P ol 1 0 Phase Detector E na bl e Polarity (0= Not Inver ted, 1= Inverted)

R ef_P ol 2 0 Ex ternal Ref erence Pol a r it y (0= Posit ive Edge, 1= Negati v e E dge)

F bk _P ol 3 0 Ex ternal F eedback Polarit y ( 0= Posit ive Edge, 1= N egative Edge)

F bk _S el 4 0 Ex ternal F eedback Select (0= Int ernal Feedbac k, 1=External)

Func_Sel 5 0 Function Out Select (0=Recovered HSYNC, 1=Input HSYNC)

EnPLS 6 1 Enable PLL Lock/Ref Status Output (0=Disable 1=Enable)

E nDLS 7 0 E nable DP A Loc k/R ef Stat us Output ( 0= Disable 1=Enable)

1h Loop C ont rol R / W * P FD 0- 2 0- 2 0 P hase Detect or G ain

Reserved 3 0 Reserved

P SD 0- 1 4- 5 0 P ost- Scaler D ivider (0 = 2, 1 = 4, 2 = 8, 3 = 16)

Reserved 6-7 0 Reserved

2h F dBk D iv 0 R / W * F BD 0- 7 0- 7 F F P LL FeedB ack D ivider LSB s ( bit s 0- 7) *

3h F dBk D iv 1 R / W * F BD 8- 1 1 0-3 F PLL F eedbac k D ivid er MSB s ( b i ts 8-11) *

Reserved 4-7 0 Reserved

4h DPA Offset R / W DPA_OS0-5 0-5 0 Dynamic Phase Aligner Offset

Reserved 6 0 Reserved

F il_ S e l 7 0 Loop F il ter Select (0=Exter nal, 1= Int ernal)

5h DPA Control R / W ** DPA_Res0-1 0-1 3 DPA Resolution (0=16 delay elements, 1=32, 2=Reserved, 3=64)

Metal_R ev 2- 7 0 Metal Mask R evision Number

6h O ut pu t Enables R / W O E _Pck 0 0 Out put Enable f or P EC L P C LK O ut puts ( 0= H igh Z , 1= Enabl e d)

O E _Tck 1 0 Out pu t Enable f or ST TL_3 C LK O utput ( 0=H igh Z, 1= Enabled)

OE_P2 2 0 Output Enable for PECL CLK/2 Outputs ( 0=High Z, 1=Enabled)

O E _T2 3 0 Out pu t Enable f or ST TL_3 C LK/2 Outpu t ( 0= High Z, 1= Enabl ed )

O E _F 4 0 Out put Enable f or S TTL_3 F UNC Output ( 0=Hi gh Z, 1=Enabled)

Ck2_Inv 5 0 CLK/2 Invert (0=Not Inverted, 1= Inverted)

O ut _Scl 6- 7 0 S ST L Cl ock S caler ( 0 = 1, 1 = 2, 2 = 4, 3 = 8)

7h Osc_Div R / W Osc_Div 0-6 0-6 0 Osc Divider modulus

In-Sel 7 1 I nput Select (0=HS YN C I nput, 1= O sc Di vider)

8h R eset Wr it e D PA 0- 3 x Wr it ing xAh r esets DP A and loads working r egist er 5

P LL 4-7 x Writing 5xh resets PLL and l oads w or king register s 1- 3

10h Chip Ver Read Chip Ver 0-7 17 Chip Version 23 Dec (17 Hex) as in 1523

11h C hip Rev R ead C hip Rev 0- 7 01 I nit i al valu e 01h. V al ue Increments wit h eac h al l-layer ch ange.

12h Rd_Reg Read DPA_Lock 0 N/A DPA Lock Status (0=Unlocked, 1=Locked)

P LL_Lock 1 N/A PLL Lock Status (0= U nlocked, 1= Locked)

Reserved 2-7 0 Reserved

* I denti f ies doubl e- buffer ed r egister s . Working registers ar e loaded dur ing sof twar e PLL rese t.

** I dent ifi es double-buffere d r egist er. Wor king register s ar e loaded during softw are DPA r eset.

ICS1523

ICS1523 Rev T 6-06-2002

Detailed Register Description

Name: Input Control

Access: Read/Write

Bit Name Reset Description

0 PDen 1 Phase/Frequency Detector (PFD) Enable

1 PD_Pol 0 PFD Enable Polarity

2 Ref_Pol 0 Phase/Frequency Detector External Reference Polarity

Edge of input signal on which Phase Detector triggers.

0 = Rising Edge (default)

1 = Falling Edge

3 Fbk_Pol 0 External Reference Feedback Polarity

Edge of EXTFB (pin 6) signal on which Phase/Frequency Detector triggers when

external feedback is used (Reg0 [4]=1).

0 = Positive Edge (default)

1 = Negative Edge

4 Fbk_Sel 0 External Feedback Select

0 = Internal Feedback (default)

1 = External Feedback

5 Func_Sel 0 Function Output Select

Selects re-clocked output to FUNC (pin 15).

0 = Recovered (Re-generated from Feedback Loop) HSYNC (default)..

1 = External HSYNC. Schmitt-trigger conditioned signal from HSYNC (pin 7).

6 EnPLS 1 LOCK/REF (pin14) Output Control. See Table Below.

7 EnDLS 0

SLPnESLDnELES_NI)41(FER/KCOL

00 A/N0

01 A/Nesiwrehto0,dekcolAPDfi1

10 A/Nesiwrehto0,dekcolLLPfi1

110 reggirtttimhcStsoP loP_feRROX)7(CNYSH

111 F

cso

÷viD_csO

loP_DP 1tiB neDP 0tiB rotceteDycneuqerF/esahP :nehWdelbanE

00 1=)5nip(NEDP

x1 )tluafeD(syawlA

10 0=)5nip(NEDP

ICS1523

ICS1523 Rev T 6-06-2002

Name: Loop Control Register

Access: Read/Write*

Bit Name Reset Description

0-2 PFD0-2 0 Phase/Frequency Detector Gain

3 Reserved 0

4-5 PSD0-1 0 Post-Scaler Divider

Divides the output of the VCO to the DPA and Feedback Divider.

6-7 Reserved 0

*Double-buffered register. Working registers are loaded at the rising edge of SDA durring the final I2C ACK

cycle after writing the software PLL reset value. See register 8h for details.

2tiB1tiB0tiB2/Aµ(niaGDFP π)dar

000 1

001 2

010 4

011 8

100 61

101 23

110 46

111 821

5tiB4tiBrediviDDSP

00 )tluafed(2

01 4

10 8

11 61

ICS1523

ICS1523 Rev T 6-06-2002

Name: Feedback Divider 0 / Feedback Divider 1 Register(s)

Access: Read/Write*

Bit Name Index Bit Value Description

FBD0-7 2 0-7 FF PLL Feedback Divider LSB Bits 0-7.*

Bit 0 = 0, total number of clocks per line is even.

Bit 0 = 1, total number of clocks is odd.

See AC Timing Characteristics Overview for more details.

FBD8-11 3 0-3 F PLL Feedback Divider MSBs

Bits 8-11*

The value that is programmed into these two registers, plus 8, controls the total

number of clocks that the ICS1523 generates between phase updates (normally

HSYNCs). Program these registers with the hex digits equal to the decimal value of

the total number of clocks per line minus 8. (i.e. 20hex = 40dec clocks) See AC

Timing Characteristics Overview for more details.

Reserved 3 4-7 Reserved

*Double-buffered register. Working registers are loaded at the rising edge of SDA durring the final I2C ACK

cycle after writing the software PLL reset value. See register 8h for details.

Feedback Divider Modulus =

12 ≤ Feedback Divider Modulus ≤ 4103

3geR2geR

321076543210

ICS1523

ICS1523 Rev T 6-06-2002

Name: DPA Offset Register

Access: Read/Write

Bit Name Reset Description

0-5 DPA_OS 0 Dynamic Phase Adjust Offset.

Selects phase offset in discrete steps up to one clock period minus one step.

Resolution (number of delay elements per clock cycle) is controlled by

DPA_Res0-1 (Reg 5:0-1).

Offsets equal or greater than one clock period are not recommended or supported.

Example: DPA_Res0-1 = 01H, the clock can ONLY be delayed from 0 to 31 steps.

7 Fil_Sel 0 Loop Filter Selection

0 - Selects external loop filter (default)

1 - Selects Internal loop filter

The use of an external loop filter is strongly recommended for all designs

Suggested component values are available from the ICS1523 Demo Board Guide

(1523DB.pdf) or the ICS1523 Register Tool (inst1523.exe) available on our web site

at: (http://www.icst.com/products/pinfo/1523.htm).

ICS1523

ICS1523 Rev T 6-06-2002

Name: DPA Control Register

Access: Read/Write*

Bit Name Reset Description

0-1 DPA_Res 11 Dynamic Phase Adjust (DPA) Resolution Select.

It is not recommended to use the DPA above 160 MHz.

2-7 Metal_Rev 00 Metal Mask Revision Number .

After power-up, register bits 7:2 must be written with 111111. After this write,

a read indicates the metal mask revision, as below

*Double-buffered register. Working registers are loaded at the rising edge of SDA durring the final

I2C ACK cycle after writing the software DPA reset value. See register 8h for details.

B it 1 B it 0 Del ay Elem ents

00 16 48 160

01 32 24 80

10 Reserved

11 64 12 40

CLK Range, M Hz

noisiveR7tiB6tiB5tiB4tiB3tiB2tiB

A 111111

B 011111

1C 101111

2C 001111

D110111

E 111011

F 111101

G 111110

ICS1523

ICS1523 Rev T 6-06-2002

Name: Output Enable Register

Access: Read/Write

Bit Name Reset Description

0 OE_Pck 0 Output Enable for CLK Outputs (PECL, Pins 21,20)

0 = High Z (default)

1 = Enabled

1 OE_Tck 0 Output Enable for CLK Output (SSTL_3, Pin 17)

0 = High Z (default)

1 = Enabled

2 OE_P2 0 Output Enable for CLK/2 Outputs (PECL, Pins 23, 22 )

0 = High Z (default)

1 = Enabled

3 OE_T2 0 Output Enable for CLK/2 Output (SSTL_3, Pin 16)

0 = High Z (default)

1 = Enabled

4 OE_F 0 Output Enable for FUNC Output (SSTL_3, Pin 15)

0 = High Z (default)

1 = Enabled

5 Ck2_Inv 0 CLK/2 (Pin 16) Invert

0 = Not Inverted (default)

1 = Inverted

6-7 Out_Scl 00 Clock (CLK, Pin 17) Output Scaler

7tiB6tiBrediviDKLC

00 1

01 2

10 4

11 8

ICS1523

ICS1523 Rev T 6-06-2002

Name: Oscillator Divider Register

Access: Read/Write

Bit Name Reset Description

0-6 Osc_Div 0 Oscillator Divider Modulus.

Divides the input from OSC (pin 12) by the set modulus.

The modulus equals the programmed value, plus 2.

Therefore, the modulus range is from 3 to 129.

OSC signal will have 1 OSC input period high (and the rest low) per modulus cycle

7 In_Sel 1 Input Select

Selects the input to the Phase/Frequency Detector

0 = HSYNC

1 = Osc Divider (default)

Name: RESET Register

Access: Write

Bit Name Reset Description

0-3 DPA x Writing xAh to this register resets DPA working register 5

4-7 PLL x Writing 5xh to this register resets PLL working registers 1-3

eulaVsteseR

AxAPD

x5LLP

A5LLPdnaAPD

Double-buffered register control. PLL and/or DPA Working registers are loaded at the rising edge of SDA durring

the final I2C ACK cycle after writing the proper corresponding reset value to this register.

ICS1523

ICS1523 Rev T 6-06-2002

Name: Chip V ersion Register

Access: Read

Bit Name Bit # Reset Value Description

Chip Ver 0-7 17 Chip Version 23 (decimal)

Name: Chip Revision Register

Access: Read

Bit Name Bit # Reset Value Description

Chip Rev 0-7 01+ Initial value 01h.

+Value increments with each all-layer change.

Name: Status Register

Access: Read

Bit Name Reset Description

0 DPA_Lock n/a DPA Lock Status.

Refer to Register 0h, bits 6 and 7

0 = Unlocked

1 = Locked

1 PLL_Lock n/a PLL Lock Status.

Refer to Register 0h, bits 6 and 7

0 = Unlocked

1 = Locked

2-7 Reserved 0

ICS1523

ICS1523 Rev T 6-06-2002

I2C Data Characteristics

Bit transfer on the I2C-bus

START and STOP conditions

Acknowledge on the I2C-bus

These waveforms are from "The I2C-bus and how to use it," published by Philips Semiconductor. This and other I2C documents can be obtained from the

Philips Semiconductor web site, www.philips.com

ICS1523

ICS1523 Rev T 6-06-2002

I2C Data Format

RANDOM REG ISTER WRITE PROCEDURE

S010011xWA A AP

7 bit addr ess regis ter address data

Ac k n owled g e Ac k n owledge STOP c o ndition

START con d ition WRIT E c ommand Ackno wle dge

RANDOM REG ISTER READ PROCEDURE

S010011XWA AS010011XRA AP

7 bit address r egister address 7 bit addre ss data

Ac k n owled g e Re peat START Ac k n owled g e STOP co ndition

START con dition WRIT E c ommand Ack nowledge READ comman d NO Ackno wle dge

SEQ UENTI AL REG I ST ER WRI TE PRO CEDURE

S010011XWA A A A AP

7 bit addr ess regis ter address data data

Acknowledge Acknowledge Acknowledge Acknowledge Acknowledge

START con dition WRI TE comman d STOP condition

SEQ UENTI AL REG I S TER READ PRO CEDURE

S010011XWA AS010011XRA A AP

7 bit address r egister address 7 bit addre ss data data

Ac k n owled g e Repeat START Ac k n owledge NO Ackno wle dge

START con dition WRIT E c omman d Acknowled g e READ comman d Acknowled ge STOP c o ndition

Direction: From bus host t o devi ce From devic e to bus host

Note:

1. All values are transmitted with the most-significant bit first and the least-significant bit last.

2. The value of the X bit equals the logic state of pin 13 (I2CADR).

3. R = READ = 1 and W = WRITE = 0

ICS1523

ICS1523 Rev T 6-06-2002

Specific Layout Guidelines

1. Digital Supply (VDD) – Bypass pin 1 (VDD) to pin 2 (VSS) a 0.1-µF capacitor, located as close as possible to the pins.

A 0.01-µF capacitor may be added for additional high frequency rejection.

2. External Loop Filter – Strongly recommended in All Designs. Locate loop filter components as close to pins 8 and 9

(EXTFIL and EXTFILRET) as possible with minimum length traces. T ypical loop filter values are 6.8K Ohms for the series

resistor , 3300 pF RF-type capacitor for the series capacitor, and 33 pF for the shunt capacitor . (For details, see the Frequently

Asked Questions part of the ICS1523 Applications Guide, FAQ2 and FAQ3.) A ground isolated, surface trace can be useful

to isolate this section from the rest of the board.

3. Analog PLL Supply (VDDA) – Decouple main VDD from pin 10 (VDDA) with a series ferrite bead. Bypass the supply

end of the bead with 4.7-µF. Bypass pin 10 to pin 1 1 (VSSA) with a 0.1-µF capacitor . A 0.01-µF capacitor may be added for

additional high frequency rejection. Locate these components as close as possible to the pins.

4. PECL Curr ent Set Resistor – Locate PECL current-set resistor as close as possible to pin 24 (IREF). Bypass pin 24 to

ground with a 0.1 -µF capacitor.

5. PECL Outputs – Implement these outputs as microstrip transmission lines. The trace widths shown are for 75 Οηµ char-

acteristic impedance. Locate any optional series “snubbing” resistors as close as possible to the source pins. If the

termination resistors are included on-board, locate them as close as possible to the load and connect directly to the power and

ground planes.

[These termination resistors are omitted if the load device implements them internally. For details, see the ICS application

note on microstrip and striplines (1572AN1) and within the ICS1523 Applications Guide, the application note on Designing

a Custom Interface for the ICS1523 (1523AN4.)]

6. Output Driver Supply – Bypass pin 18 (VDDQ) to pin 19 (VSSQ) with a 0.1-µF capacitor , located as close as possible

to the pins. A 0.01-µF capacitor may be added for additional high frequency rejection.

7. SSTL_3 Outputs – SSTL_3 outputs can be used like conventional CMOS rail-to-rail logic or as a terminated transmis-

sion line system at higher-output frequencies. W ith terminated outputs, the considerations of item 5, “PECL Outputs” apply .

See JEDEC documents JESD8-A and JESD8-8.

General Layout Guidelines

•Use a PC board with at least four layers: one power, one ground, and two signal.

•Use at least one 4.7 uF Tantalum (or similar) capacitor for global VDD bulk decoupling.

•All supply voltages must be supplied from a common source and must ramp together.

•Any flux or other board surface debris can degrade the performance of the external loop filter.

•Ensure that the 1523 area of the board is free of contaminants.

Note: For illustrative purposes only, drawing is not to scale.

ICS1523

ICS1523 Rev T 6-06-2002

PECL Outputs

For information on using the ICS1523’s PECL output pins, please refer to Application Note 4: Designing a Custom PECL Inter-

face for the ICS1523

SSTL_3 Outputs

Unterminated Outputs

In the ICS1523, unterminated SSTL_3 output pins display exponential transitions similar to those of rectangular pulses presented

to RC loads. The 10-90% rise time is typically 1.6 ns, and the corresponding fall time is typically 700 ps. In turn, this asymmetry

contributes to duty cycle asymmetry at higher output frequencies. In the absence of significant load capacitance (which can fur-

ther increase rise and fall time), this asymmetry is the dominant factor determining high-frequency performance of these

single-ended outputs. Typically, no termination is required either for the LOCK/REF, FUNC, and CLK/2 outputs or for CLK

outputs up to approximately 135 MHz.

Terminated Outputs

SSTL_3 outputs are intended to terminate in low impedances to reduce the effect of external circuit capacitance. Use of transmis-

sion line techniques enables use of longer traces between source and driver without increasing ringing due to reflections. Where

external capacitance is minimal and substantial voltage swing is required to meet L VTTL VIH and VOL requirements, the intrinsic

rise and fall times of ICS1523 SSTL outputs are only slightly improved by termination in a low impedance.

The ICS1523 SSTL output source impedance is typically less than 60 Ohms. Termination impedance of 100 Οηµσ reduces out-

put swing by less than 30% which is more than enough to drive a single load of LVTTL inputs.

For more information on using the ICS1523’s SSTL output pins, please refer to Application Note 3: Using SSTL_3 Outputs with

CMOS or LVTTL Inputs

ICS1523

ICS1523 Rev T 6-06-2002

Absolute Maximum Ratings

VDD, VDDA, VDDQ (measured to VSS). . . . . . . . . . . . . . . . . . 4.3 V

Digital Inputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . VSS –0.3 V to 5.5 V

Analog Outputs. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . VSSA –0.3 V to VDDA +0.3 V

Digital Outputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . VSSQ –0.3 V to VDDQ +0.3 V

Storage Temperature. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –65°C to +150°C

Junction Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 175°C

Soldering Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 260°C

ESD Susceptibility* . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . > 2 KV

(*Electrostatic-sensitive devices. Do not open or handle except in a static-free workstation.)

Power Supply Considerations

The ICS1523 incorporates special internal power-on reset circuitry that requires no external reset signal connection. The supply

voltage (VDD) must remain within the recommended operating conditions during normal operation. T o reset the ICS1523, the

supply voltage at the part must be reduced below the threshold voltage (Vth) of the power-on reset circuit. The supply voltage

must remain below that threshold voltage such that board power conditioning capacitors are drained and the proper reset state is

latched. The amount of time (td) to hold the voltage in a reset state varies with the design. However, a typical value of 10 ms

should be sufficient.

ICS1523

ICS1523 Rev T 6-06-2002

Recommended Operating Conditions

VDD, VDDQ, VDDA (measured to VSS). . . 3.0 to 3.6 V

Operating Temperature (Ambient) . . . . . . . . . 0 to +70°C

tnerruCylppuSCD

RETEMARAPLOBMYSSNOITIDNOCNIMXAMSTINU

latigiD,tnerruCylppuSDDDIV6.3=DDDV —52Am

srevirDtuptuO,tnerruCylppuSQDDI.delbanesrevirdtuptuoon,V6.3=QDDV —6Am

golanA,tnerruCylppuSADDIV6.3=ADDV —5Am

,CSO,CNYSH,BFTXE,NEDP,LCS,ADS(stupnIlatigiDI

C)RDA

RETEMARAPLOBMYSSNOITIDNOCNIMXAMSTINU

egatloVhgiHtupnIHIV25.5V

egatloVwoLtupnILIV3.0-SSV8.0V

siseretsyHtupnI 2.06.0V

tnerruChgiHtupnIHIIV

DDV= —01±Aµ

tnerruCwoLtupnILIIV

0= —002±Aµ

ecnaticapaCtupnIniC —01Fp

)lanoitceridiBsiADS:edoMtuptuOnI(ADS

RETEMARAPLOBMYSSNOITIDNOCNIMXAMSTINU

egatloVwoLtuptuOLOV samumixamV0.6=HOV.Am3=TUOI .rotsiserpu-lluplanretxeehtybdenimreted 4.0V

)–2/KLC,+2/KLC,–KLC,+KLC(stuptuOLCEP

RETEMARAPLOBMYSSNOITIDNOCNIMXAMSTINU

egatloVhgiHtuptuOHOV0=TUOI —DDVV

ycneuqerFtuptuOmumixaMXAMpFV3.3=DDDV —052zHM

egatloVwoLtuptuO wolebllaftontsumLOV:etoN( tcerrocehttahtosnevigleveleht ebnacTUOIrofeulav ).deniatniam

LOVeulavdemmargorp=TUOI0.1 —V

KCOL,CNUF,2/KLC,KLC(stuptuO3-LTSS

)FER/

RETEMARAPLOBMYSSNOITIDNOCNIMXAMSTINU

ecnatsiseRtuptuOR

V<1

V2< —08 Ω

ycneuqerFtuptuOmumixaMXAMsFV3.3=DDDV —051zHM

scitsiretcarahCtupnICA

RETEMARAPLOBMYSSNOITIDNOCNIMXAMSTINU

ycneuqerFtupnICNYSHf

CNYSH

0=7:7geR800.01zHM

ycneuqerFtupnICSOf

CSO

1=7:7geR20.001zHM

ICS1523

ICS1523 Rev T 6-06-2002

VCO O utput Frequency and Intri nsic Ji tter

100

200

300

400

500

600

700

00.2 0.4 0.6 0.8 11.2 1.4 1.6 1.8 22.2 2.4 2.6 2.8 33.2

VCO Voltage

VCO Frequency (MHz)

100

200

300

400

500

600

700

Jitter (ps)

F requency (S lo w: 3.0V @ 70”C)

F requency (Nominal: 3.3V @ 30”C)

Frequency (Fast: 3.6V @ 0”C)

Jitter (3.0V @ 70”C)

Jitter (3.3V @ 30”C)

Jitter (3.6V @ 0”C)

Frequency

Jitter

ICS1523

ICS1523 Rev T 6-06-2002

DPA Delay-16 Element Reso lutio n

04812

DPA Sett in g

ns Delay

50 MHz - SVGA @ 72 Hz

157.5 MHz - SXGA @ 85 Hz

DPA Delay - 32 El ement Reso lutio n

0481216202428

DPA Setting

ns Delay

25.175 MH z - VGA @ 60 Hz

78.75 MH z - XGA @ 75 Hz

DPA Delay - 64 Elemen t Reso lu tion

0 4 8 12 16 20 24 28 32 36 40 44 48 52 56 60

DPA Se tting

ns Delay

12.27 MHz - NTSC

39.8 MHz - SVGA @ 60

Note:

Maximum number of data points used for this graph.

ICS1523

ICS1523 Rev T 6-06-2002

* Timing when Register 2, Bit 0 = 0 (Total number of clocks is even.)

** Timing when Register 2, Bit 0 = 1 (Total number of clocks is odd.)

A C Timing Characteristics Overvie w

ICS1523

ICS1523 Rev T 6-06-2002

Output Timing Diagram

lobmySnoitpircseDgnimiTniMpyTxaMstinU

yaledFERotCNYSH3.115.1121sn

yaledkcolcLCEPotFER0.1-8.02.2sn

elcycytudkcolcLCEP540555%

yaledkcolc3_LTSSotkcolcLCEP2.057.02.1sn

yaledTUO_CNUFotkcolcLCEP5.19.13.2sn

kcolc2/LCEPotkcolcLCEP0.13.15.1sn

yaled2/KLC–3_LTSSotkcolcLCEP1.14.18.1sn

elcycytudkcolcLTSS540555%

*Note: Measured at 3.6V 0°C, 135-MHz output frequency, PECL clock lines to 75 Οηµ termination, SSTL_3 clock lines

unterminated, 20-pF load. Transition times vary based on termination.

lobmySnoitpircseDgnimiTesiRllaFstinU

FER8.28.1sn

KLCLCEP0.12.1sn

KLC-LTSS6.17.0sn

TUO_CNUF2.10.1sn

T ypical T ransition Times*

Output Timing*

ICS1523

ICS1523 Rev T 6-06-2002

24-Pin SOIC (wide body)

rebmuNredrO/traPgnikraMegakcaPgnippihS

M3251SCIM3251SCI42-CIOSsebuT

TM3251SCIM3251SCI42-CIOSleeRdnaepaT

Ordering Information

While the information presented herein has been checked for both accuracy and reliability, Integr ated Circuit Systems , Incorporated (ICS) assumes no responsibility for either its use or for

infringement of any patents or other rights of third par ties, which would result from its use. No other circuits, patents, or licenses are implied. This product is intended for use in normal

commercial applications. Any other applications such as those requiring extended temperature range, high reliability, or other extraordinary environmental requirements are not recom-

mended without additional processing by ICS. ICS reserves the right to change any circuitry or specifications without notice. ICS does not authorize or warrant any ICS product for use in

life support devices or critical medical instruments.

ICS1523

ICS1523 Rev T 6-06-2002

NOTES

ICS1523

ICS1523 Rev T 6-06-2002

Corporate Headquarters: 2435 Boulevard of the Generals

P.O. Box 968

Valley For ge, PA 19482-0968

Telephone: 610-630-5300

Fax: 610-630-5399

San Jose Oper ations: 525 Race Street

San Jose, CA 95126-3448

Telephone: 408-297-1201

Fax: 408-925-9460

Web Site: http://www.icst.com

Integrated Circuit Systems, Inc.