© Copyright 2011 WIZnet Co., Inc. All rights reserved. Ver. 1.12 7
Internet Embedded MCU W7100A Datasheet
Figure 2.27 Second Byte of Internal Memory Wait States Register ................................. 38
Figure 2.28 Stack Pointer Register ....................................................................... 39
Figure 2.29 PHY Status Register .......................................................................... 39
Figure 2.30 Internal PHY Configuration Register ...................................................... 39
Figure 2.31 W7100A Configuration Register ............................................................ 40
Figure 2.32 Core clock count register ................................................................... 40
Figure 2.33 Core clock count register ................................................................... 41
Figure 2.34 Core clock count register ................................................................... 41
Figure 2.35 Core clock count register ................................................................... 41
Figure 3.1 Interrupt Enable Register .................................................................... 44
Figure 3.2 Interrupt Priority Register .................................................................... 44
Figure 3.3 Timer0, 1 Configuration Register ........................................................... 44
Figure 3.4 UART Configuration Register ................................................................. 45
Figure 3.5 Extended Interrupt Enable Register ........................................................ 45
Figure 3.6 Extended Interrupt Priority Register ....................................................... 45
Figure 3.7 Extended Interrupt Flag Register ........................................................... 46
Figure 3.8 Watchdog Control Register ................................................................... 46
Figure 4.1 Port0 Register .................................................................................. 47
Figure 4.2 Port1 Register .................................................................................. 47
Figure 4.3 Port2 Register .................................................................................. 47
Figure 4.4 Port3 Register .................................................................................. 47
Figure 4.5 Port0 Pull-down register ..................................................................... 48
Figure 4.6 Port1 Pull-down register ..................................................................... 48
Figure 4.7 Port2 Pull-down register ..................................................................... 48
Figure 4.8 Port3 Pull-down register ..................................................................... 49
Figure 4.9 Port0 Pull-up register ......................................................................... 49
Figure 4.10 Port1 Pull-up register ........................................................................ 49
Figure 4.11 Port2 Pull-up register ........................................................................ 49
Figure 4.12 Port3 Pull-up register ........................................................................ 49
Figure 5.1 Timer0, 1 Control Mode Register ............................................................ 51
Figure 5.2 Timer0, 1 Configuration Register ........................................................... 51
Figure 5.3 Interrupt Enable Register .................................................................... 51
Figure 5.4 Interrupt Priority Register .................................................................... 52
Figure 5.5 Timer0, 1 Configuration Register ........................................................... 52
Figure 5.6 Timer Counter0, Mode0: 13-Bit Timer/Counter .......................................... 53
Figure 5.7 Timer/Counter0, Mode1: 16-Bit Timer/Counter .......................................... 53
Figure 5.8 Timer/Counter0, Mode2: 8-Bit Timer/Counter with Auto-Reload ..................... 54
Figure 5.9 Timer/Counter0, Mode3: Two 8-Bit Timers/Counters ................................... 54