LT8311 Synchronous Rectifier Controller with Opto-Coupler Driver for Forward Converters DESCRIPTION FEATURES n n n n n n n Wide Input Supply Range: 3.7V to 30V Preactive Mode: n No Pulse Transformer Required n DCM Operation at Light Load SYNC Mode: n FCM or DCM Operation at Light Load n Achieves Highest Efficiency 1.5% Feedback Voltage Reference 10mA Opto-Coupler Driver Output Power Good Indicator Integrated Soft-Start Function The LT(R)8311 is used on the secondary side of a forward converter to provide synchronous MOSFET control and output voltage feedback through an opto-coupler. The LT8311's unique preactive mode allows control of the secondary-side MOSFETs without requiring a traditional pulse transformer for primary- to secondary-side communication. In preactive mode, the output inductor current operates in discontinuous conduction mode (DCM) at light load. If forced continuous mode (FCM) operation is desired at light load, the LT8311 can, alternatively, be used in SYNC mode, where a pulse transformer is required to send synchronous control signals from the primary-side IC to the LT8311. APPLICATIONS n n n Offline and HV Car Battery Isolated Power Supplies 48V Isolated Power Supplies Industrial, Automotive and Military Systems The LT8311 offers a full featured opto-coupler controller, incorporating a 1.5% reference, a transconductance error amplifier and a 10mA opto-driver. Power good monitoring and output soft-start/overshoot control are also included. The LT8311 is available in a 16-lead FE package with pins removed for high voltage spacing requirements. L, LT, LTC, LTM, Linear Technology and the Linear logo are registered trademarks of Linear Technology Corporation. All other trademarks are the property of their respective owners. TYPICAL APPLICATION 18V to 72V, 12V/8A Active Clamp Isolated Forward Converter VIN 18V to 72V 4:4 4.7F x3 100k * VIN 2.2F 100V UVLO_VSEC 5.9k 1.82k 71.5k 31.6k 34k 100nF 2k 2k LT3753 10k OUT IVSEC RT SYNC SOUT ISENSEP OC TAO ISENSEN INTVCC COMP SS2 FB 0.47F 1F 1.78k 1.78k 6m 1.5k 15nF 4.7F 100 10pF 2.94k 1F 22F x2 2.2nF + VOUT 12V 470F 100k FSW FB FG CSW 11.3k LT8311 CSP CG 2k 100k 68pF 20k AOUT TAS TOS TBLNK GND SS1 49.9k * 100nF OVLO 240kHz 6.8H VOUT VIN 100k CSN PGOOD OPTO INTVCC COMP SYNC PMODE SS TIMER GND 4.7F 2.2F 124k 1F 100k 8311 TA01 1k 2.2nF 8311f For more information www.linear.com/LT8311 1 LT8311 TABLE OF CONTENTS Features............................................................................................................................. 1 Applications........................................................................................................................ 1 Typical Application ................................................................................................................ 1 Description......................................................................................................................... 1 Absolute Maximum Ratings...................................................................................................... 3 Order Information.................................................................................................................. 3 Pin Configuration.................................................................................................................. 3 Electrical Characteristics......................................................................................................... 4 Typical Performance Characteristics........................................................................................... 7 Pin Functions......................................................................................................................11 Block Diagram.....................................................................................................................12 Operation..........................................................................................................................13 FUNDAMENTALS OF FORWARD CONVERTER OPERATION IN CCM...................................................................... 13 LT8311 SYNCHRONOUS CONTROL SCHEMES...................................................................................................... 17 PREACTIVE MODE SYNCHRONOUS CONTROL..................................................................................................... 17 SYNC MODE SYNCHRONOUS CONTROL.............................................................................................................. 19 OPTO-COUPLER CONTROL................................................................................................................................... 21 Applications Information........................................................................................................25 VIN BIAS SUPPLY................................................................................................................................................... 25 INTVCC BIAS SUPPLY............................................................................................................................................. 26 LT8311 OPTO CONTROL FUNDAMENTALS............................................................................................................ 27 LT8311 SYNCHRONOUS CONTROL FUNDAMENTALS........................................................................................... 31 PREACTIVE MODE SYNCHRONOUS CONTROL .................................................................................................... 37 SYNC MODE SYNCHRONOUS CONTROL ............................................................................................................. 38 Typical Applications..............................................................................................................40 Package Description.............................................................................................................47 Typical Application...............................................................................................................48 Related Parts......................................................................................................................48 8311f 2 For more information www.linear.com/LT8311 LT8311 ABSOLUTE MAXIMUM RATINGS PIN CONFIGURATION (Note 1) CSW, FSW, CSP........................................ -0.3V to 150V SYNC............................................................ -12V to 12V VIN, PGOOD................................................. -0.3V to 30V INTVCC, PMODE.......................................... -0.3V to 18V FB, SS, COMP............................................ -0.3V to 2.5V TIMER........................................................ -0.3V to 1.5V CSN............................................................ -0.3V to 0.4V OPTO, TIMER Short-Circuit Current Duration..................................... Infinite (Note 5) Operating Junction Temperature Range LT8311E (Notes 2, 3).......................... -40C to 125C LT8311I (Notes 2, 3)........................... -40C to 125C LT8311H (Notes 2, 3).......................... -40C to 150C LT8311MP (Notes 2, 3)....................... -55C to 150C Storage Temperature Range................... -65C to 150C Lead Temperature (Soldering, 10sec).................... 300C TOP VIEW CSW 1 20 CSP FSW 3 18 CSN FG 5 INTVCC 6 VIN 7 14 SS PMODE 8 13 PGOOD OPTO 9 12 TIMER COMP 10 21 GND 16 CG 15 SYNC 11 FB FE PACKAGE 20-LEAD PLASTIC TSSOP JA = 38C/W, JC = 10C/W EXPOSED PAD (PIN 21) IS GND, MUST BE SOLDERED TO PCB ORDER INFORMATION LEAD FREE FINISH TAPE AND REEL PART MARKING* PACKAGE DESCRIPTION TEMPERATURE RANGE LT8311EFE#PBF LT8311EFE#TRPBF LT8311FE 20-Lead Plastic TSSOP -40C to 125C LT8311IFE#PBF LT8311IFE#TRPBF LT8311FE 20-Lead Plastic TSSOP -40C to 125C LT8311HFE#PBF LT8311HFE#TRPBF LT8311FE 20-Lead Plastic TSSOP -40C to 150C LT8311MPFE#PBF LT8311MPFE#TRPBF LT8311FE 20-Lead Plastic TSSOP -55C to 150C Consult LTC Marketing for parts specified with wider operating temperature ranges. *The temperature grade is identified by a label on the shipping container. For more information on lead free part marking, go to: http://www.linear.com/leadfree/ For more information on tape and reel specifications, go to: http://www.linear.com/tapeandreel/ 8311f For more information www.linear.com/LT8311 3 LT8311 ELECTRICAL CHARACTERISTICS The l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25C, VIN = 12V, VINTVCC = 8V, PMODE = 5V, CCG = CFG = 100pF, unless otherwise noted. (Note 2) PARAMETER CONDITIONS MIN TYP MAX UNITS Supply VIN Operating Range l VIN UVLO VIN Rising Hysteresis Quiescent Current Not Switching 3.7 l 50 30 V 3.6 100 3.7 150 V mV 4.5 5.5 mA 1.227 1.245 V Error Amplifier Feedback Reference Voltage VIN = 12V l 1.209 Feedback Voltage Line Regulation 3.7V VIN 30V, % of FB Ref Voltage 0.015 0.1 % Feedback Voltage Load Regulation 1.3V COMP 1.8V, % of FB Ref Voltage 0.05 0.1 % Feedback Pin Bias Current Current Out of FB pin 120 200 nA Error Amplifier Transconductance 1.3V COMP 1.8V 370 mhos Error Amplifier Voltage Gain 1.3V COMP 1.8V 65 dB Error Amplifier Output Swing High FB = 1V 1.9 2.3 2.8 V Error Amplifier Output Swing Low FB = 1.5V 0.75 1 1.25 V 4 10 16 % Power Good Power NOT Good (Outside This Window) % Relative to FB Ref Voltage Power Good (Inside This Window) % Relative to FB Ref Voltage 7 % Power Good Indicator Wait Time Minimum Time That FB Must Stay within Power Good Window Before PGOOD Pin Goes Low 175 s Power Good Leakage PGOOD = 30V Power Good Output Low Voltage Current into PGOOD Pin = 1mA 0.2 l 1 A 0.3 V Soft-Start (SS) SS Wake-Up Slew Current Current Exists Upon Part Wake Up, Shuts Off After SS Wake Up Offset Voltage Is Satisfied (Note 6) 1 mA SS Wake-Up Offset Voltage VFB - VSS, Upon Part Wake Up SS Is Slewed Up to an Offset Voltage Below FB by SS Wake-Up Slew Current 16 mV SS Charge Current SS = 0V, FB = 0.6V (Note 9) SS Pull-Down Amplifier Offset Voltage VSS - VFB, Pull-Down Amplifier Prevents SS from Rising Beyond This Offset Voltage Above FB When the FB Pin Voltage Is Below 50% of the FB Reference Voltage 100 mV SS Pull-Down Amplifier Maximum Sink Current SS = 1.5V, FB = 0.6V (Note 7) 13 mA 2 V SS High Clamp Voltage l 9 1.8 10 11 A Opto Driver COMP Buffer Input Offset Voltage 1.3V COMP (Note 5) 0.9 V Opto-Driver Reference Voltage (Note 5) 1 V Opto-Driver DC Gain (Note 5) -7 V/ V 8311f 4 For more information www.linear.com/LT8311 LT8311 ELECTRICAL CHARACTERISTICS The l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25C, VIN = 12V, VINTVCC = 8V, PMODE = 5V, CCG = CFG = 100pF, unless otherwise noted. (Note 2) PARAMETER CONDITIONS Inverting DC Gain From COMP Pin to OPTO Pin (VOPTO /VCOMP), 1.290V COMP 1.310V MIN TYP -5 MAX UNITS V/ V (VOPTO /VCOMP), 1.490V COMP 1.510V -5.9 V/ V (VOPTO /VCOMP), 1.890V COMP 1.910V -6.2 V/ V Opto-Driver -3dB Bandwidth No Load (Note 5) 400 kHz Opto-Driver Output Swing Low FB = 1V, COMP = SS = OPTO = Open l Opto-Driver Output Swing High VIN = 3.7V, FB = 1.5V, COMP = SS = Open, IOPTO = 10mA l VIN = 30V, FB = 1.5V, COMP = SS = Open, IOPTO = 10mA l 0.5 0.85 VIN - 1.7 VIN - 1.4 5.2 6.5 V V V Opto-Driver Output Short-Circuit Current VIN = 30V, FB = 1.5V, COMP = SS = Open, OPTO = 0V (Note 6) l 10.5 15 18 mA Opto-Driver Output Sink Current FB = 1V, OPTO = 1.2V (Note 7) l 200 300 420 A INTVCC Regulation Voltage No Load l 6.5 7 7.5 V INTVCC Load Regulation (VINTVCC /IINTVCC), 0A IINTVCC 20mA 1.8 3 4.6 4.8 Internal Linear Regulator INTVCC UVLO Rising l INTVCC UVLO Falling l INTVCC OVLO Rising l INTVCC OVLO Falling l 14 15 l 38 48 4.1 4.3 16.5 mV/mA V V 17.5 V V INTVCC Current Limit INTVCC > IINTVCC_UVLO_RISING (= 4.6V) 58 mA INTVCC < IINTVCC_UVLO_FALLING (= 4.3V) 20 mA INTVCC Dropout Voltage VIN = 6V, IINTVCC = 10mA, Not Switching 400 mV Driver Output Rise Time CCG = CFG = 3.3nF, INTVCC = 8V (Note 4) 25 ns Driver Output Fall Time CCG = CFG = 3.3nF, INTVCC = 8V (Note 4) 25 ns CG and FG Gate Drivers Driver Output High Voltage l Driver Output Low Voltage l VINTVCC - 0.2 V 0.7 V 1.2 30 1.4 V mV 60 90 A 300 kHz PMODE Selection PMODE Trip Voltage PMODE Ramp Up Hysteresis l PMODE Input Current PMODE = 18V l 1 Preactive Mode (Tie PMODE to 0V) Preactive Mode Operating Frequency Range l 100 1 CSW High Trip Voltage CSW Ramp Up l CSW High Input Current CSW = 150V (Note 7) l CSW Low Trip Voltage CSW Ramp Down l -250 l 1 FSW Trip Voltage FSW High Input Current FSW = 150V (Note 7) l CG Falling Edge to CSW Rising Edge Prediction Delay CSW = 150kHz (Note 10), FSW = 0V, CSP = -500mV l CG Falling Edge Delay to FG Rising Edge CSW = 150kHz (Note 10), FSW = 0V, CSP = -500mV l 1.2 1.4 V 250 500 A -150 -50 mV 1.2 1.4 V 250 500 A 5 100 300 ns 10 50 80 ns 8311f For more information www.linear.com/LT8311 5 LT8311 ELECTRICAL CHARACTERISTICS The l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25C, VIN = 12V, VINTVCC = 8V, PMODE = 5V, CCG = CFG = 100pF, unless otherwise noted. (Note 2) PARAMETER CONDITIONS MIN TYP MAX UNITS SYNC Mode (Tie PMODE to INTVCC) SYNC High Trip Voltage SYNC Ramp Up Hysteresis l 0.9 1.2 -2.4 1.5 V V SYNC Low Trip Voltage SYNC Ramp Down Hysteresis l -1.5 -1.2 2.4 -0.9 V V SYNC Minimum Pulse Width SYNC = 0V to 2V Pulse SYNC = 0V to 6V Pulse (Note 5) l 40 20 100 ns ns SYNC Input Current -3.5V < SYNC < 3.5V SYNC = 10V (Note 6, 7) l 300 1 400 A A SYNC Rising Edge (0V to 2V) to CG Rising Edge (Note 8) SYNC Rising Edge (0V to 6V) to CG Rising Edge (Notes 5, 8) SYNC Falling Edge (0V to 2V) to FG Rising Edge (Note 8) SYNC Falling Edge (0V to 6V) to FG Rising Edge (Notes 5, 8), CCG = CFG = 3.3nF l 100 75 100 150 ns ns ns TIMER Timeout Frequency RTIMER = 41.2k RTIMER = 71.5k RTIMER = 221k l l l TIMER Short-Circuit Current TIMER = 0V l CSP Ramp Up, RCSP = RCSN = 0 l SYNC Propagation Delay To CG/FG Outputs l 150 85 425 255 80 ns 505 300 100 585 345 120 kHz kHz kHz 40 60 A 62 72 mV Current Comparator Current Comparator Trip Threshold 48 CSP Ramp Up, RCSP = RCSN = 1.62k (Note 5) 0 mV Current Comparator Blank Time in Preactive Mode From Rising CG Edge Until Blanking Ends (Note 5) 250 ns Current Comparator Blank Time in SYNC Mode From Rising CG Edge Until Blanking Ends 400 ns CSP Current at Low CSP Voltage CSP = 0V (Note 6) l CSP Current at High CSP Voltage CSP = 150V (Note 7) CSN Current CSN = 0V (Note 6) Note 1: Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. Exposure to any Absolute Maximum Rating condition for extended periods may affect device reliability and lifetime. Note 2: The LT8311 is tested under pulsed load conditions such that TJ ~ TA. The LT8311E is guaranteed to meet specifications from 0C to 125C junction temperature. Specifications over the -40C to 125C operating junction temperature are assured by design, characterization and correlation with statistical process controls. The LT8311I is guaranteed over the -40C to 125C operating junction temperature range. The LT8311H is guaranteed over the -40C to 150C operating junction temperature range, and the LT8311MP is guaranteed over the -55C to 150C operating junction temperature range. High junction temperatures degrade operating lifetimes; operating lifetime is derated for junction temperatures greater than 125C. Note 3: The LT8311 includes overtemperature protection that is intended to protect the device during momentary overload conditions. Junction 30 38 50 A l 200 500 A l 0.1 1 A temperature will exceed the maximum operating junction temperature when overtemperature is active. Continuous operating above the specified maximum operating junction temperature may impair device reliability. Note 4: Rise and fall times of are measured between 10% and 90% points of a signal edge. Note 5: Guaranteed by design and/or correlation to static test. Note 6: Current flows out of pin. Note 7: Current flows into pin. Note 8: Propagation delay is measured between 50% point of the two signal edges of interest. Note 9: SS charge current refers to current flowing out of SS pin after certain conditions satisfied upon LT8311 wake-up (see the flowchart for Opto-Control Operation at Start-Up in Figure 9). Note 10: CSW is a square waveform (duty cycle = 50%) with VHIGH = 7V and VLOW = -0.7V. 8311f 6 For more information www.linear.com/LT8311 LT8311 TYPICAL PERFORMANCE CHARACTERISTICS 30 PMODE = 0V INTVCC = 8V 175 25 PMODE = 0V INTVCC = 8V 70 100kHz 150 100kHz 125 20 JITTER (ns) DELAY CG FALLING TO CSW RISING (ns) 200 Jitter in CG Turn-Off Delay to CSW Rising Edge vs CSW Switching Frequency and Junction Temp DELAY CG FALLING TO FG RISING (ns) Delay from CG Turn-Off to CSW Rising Edge vs CSW Switching Frequency and Junction Temp TA = 25C, unless otherwise noted. 150kHz 100 75 150kHz 15 300kHz 10 50 300kHz 5 25 0 -75 -50 -25 0 25 50 0 -75 -50 -25 75 100 125 150 TEMPERATURE (C) 0 25 50 Preactive Scheme Waveforms (Active Clamp Reset, CCM) 60 50 40 IL 5A/DIV CSW 5A/DIV CSW 5A/DIV CG 10V/DIV CG 10V/DIV CG 10V/DIV FG 10V/DIV FG 10V/DIV FG 10V/DIV 2s/DIV 2s/DIV 8311 G04 Maximum CSW Duty Cycle Derating Curve vs CSW Switching Frequency and Junction Temperature 50 75 100 125 150 8311 G03 2s/DIV 8311 G05 8311 G06 Feedback Reference Voltage vs VIN Feedback Reference Voltage PMODE = 0V 80 100kHz, 200kHz 75 300kHz 70 400kHz 65 60 55 50 -75 -50 -25 0 25 50 75 100 125 150 TEMPERATURE (C) 8311 G07 1.2360 1.2360 1.2325 1.2325 FB VOLTAGE (V) 85 FB VOLTAGE (V) MAXIMUM CSW DUTY CYCLE (%) 90 25 Preactive Scheme Waveforms (Active Clamp Reset, Deep DCM) IL 5A/DIV CSW 5A/DIV 0 TEMPERATURE (C) 8311 G02 Preactive Scheme Waveforms (Active Clamp Reset, Light DCM) IL 5A/DIV PMODE = 0V INTVCC = 8V 30 -75 -50 -25 75 100 125 150 TEMPERATURE (C) 8311 G01 Delay from CG Turn-Off to FG Turn-On 1.2290 1.2255 1.2290 1.2255 1.2220 1.2220 1.2185 1.2185 1.2150 -75 -50 -25 0 25 50 75 100 125 150 TEMPERATURE (C) 8311 G08 1.2150 3 6 9 12 15 18 VIN (V) 21 24 27 30 8311 G09 8311f For more information www.linear.com/LT8311 7 LT8311 TYPICAL PERFORMANCE CHARACTERISTICS VIN Quiescent Current, No Switching Feedback Input Bias Current 133 115 98 0 25 50 5.0 12 4.5 SS PULL-DOWN AMP OFFSET VOLTAGE (mV) SS CHARGE CURRENT (A) 10.5 10.0 9.5 0 25 50 25 50 75 100 125 150 TEMPERATURE (C) 1000 125 750 100 75 0 25 50 1.40 8311 G12 Opto-Driver Output Swing Low 250 0 -75 -50 -25 0 25 50 75 100 125 150 TEMPERATURE (C) 8311 G14 8311 G15 Opto-Driver Output Swing High vs Line Voltage 7.0 7 6 6.5 OPTO HIGH VOLTAGE (V) OPTO HIGH VOLTAGE (V) 1.30 500 75 100 125 150 TEMPERATURE (C) 8311 G13 1.20 FB VOLTAGE (V) 150 50 -75 -50 -25 1.10 8311 G11 Opto-Driver Output Swing High 6.0 5.5 5.0 -75 -50 -25 8 0 1.00 75 100 125 150 SS Pull-Down Amplifier Offset Voltage 11.0 9.0 -75 -50 -25 0 TEMPERATURE (C) 8311 G10 SS Charge Current PGOOD = 100k to 12V 4 4.0 3.5 -75 -50 -25 75 100 125 150 TEMPERATURE (C) 16 OPTO LOW VOLTAGE (mV) 80 -75 -50 -25 Power Good Window 5.5 PGOOD VOLTAGE (V) VIN QUIESCENT CURRENT (mA) FB INPUT BIAS CURRENT (nA) 150 TA = 25C, unless otherwise noted. 5 4 3 0 25 50 75 100 125 150 TEMPERATURE (C) 2 3 6 8311 G16 9 12 15 18 VIN (V) 21 24 27 30 8311 G17 8311f 8 For more information www.linear.com/LT8311 LT8311 TYPICAL PERFORMANCE CHARACTERISTICS Opto-Driver Short-Circuit Current Opto-Driver Sink Current 5 -75 -50 -25 0 25 50 INTVCC VOLTAGE (V) INTVCC VOLTAGE (V) UVLO+ 4.4 UVLO- 4.2 4.0 -75 -50 -25 0 25 50 RISE/FALL TIME (ns) RISE/FALL TIME (ns) 15 10 -75 -50 -25 FG FALL TIME FG RISE TIME CG FALL TIME CG RISE TIME 0 25 50 75 100 125 150 TEMPERATURE (C) 8311 G24 INTVCC VOLTAGE (V) 50 OVLO- 25 50 10 12 INTVCC (V) INTVCC SHORT-CIRCUIT CURRENT 0 25 50 75 100 125 150 TEMPERATURE (C) 8311 G23 CSW/FSW Maximum Input Current 260 17.5 8 30 8311 G22 FG FALL TIME FG RISE TIME CG FALL TIME CG RISE TIME 6 8311 G20 INTVCC CURRENT LIMIT 10 -75 -50 -25 75 100 125 150 20.0 15.0 75 100 125 150 40 20 CG/FG Rise/Fall Time vs INTVCC Voltage 22.5 50 60 15.0 25.0 25 INTVCC Current Limit and Short-Circuit Current OVLO+ 0 0 TEMPERATURE (C) 8311 G19 TEMPERATURE (C) INTVCC 7V (NOT OVERDRIVEN) 5 3 -75 -50 -25 75 100 125 150 15.5 CG/FG Rise/Fall Time 20 50 16.0 8311 G21 25 25 INTVCC OVLO 14.5 -75 -50 -25 75 100 125 150 TEMPERATURE (C) 0 TEMPERATURE (C) 16.5 6 4 8311 G18 INTVCC UVLO 4.6 250 200 -75 -50 -25 75 100 125 150 TEMPERATURE (C) 300 INTVCC CURRENT (mA) 10 INTVCC Regulation Voltage 7 350 CSW/FSW MAXIMUM INPUT CURRENT (A) 15 30 8 400 OPTO CURRENT (A) OPTO CURRENT (mA) 20 4.8 TA = 25C, unless otherwise noted. 14 16 8311 G25 VCSW = VFSW = 150V 250 240 230 220 -75 -50 -25 0 25 50 75 100 125 150 TEMPERATURE (C) 8311 G26 8311f For more information www.linear.com/LT8311 9 LT8311 TYPICAL PERFORMANCE CHARACTERISTICS 2.0 VCSP = 150V 180 190 SYNC HIGH 160 0.5 0 -0.5 -1.0 170 PROPAGATION DELAY (ns) 1.0 180 SYNC LOW 25 50 75 100 125 150 TEMPERATURE (C) 600 25 50 130 120 110 100 90 60 -75 -50 -25 75 100 125 150 TEMPERATURE (C) 8311 G27 0 25 50 75 100 125 150 TEMPERATURE (C) 8311 G28 8311 G29 CSP Trip Voltage vs Series CSP Resistor (RCSP) 80 RTIMER = 41.2k 500 FREQUENCY (kHz) 0 TIMER Frequency 60 400 RTIMER = 71.5k 300 200 RTIMER = 221k 100 0 -75 -50 -25 140 70 -2.0 -75 -50 -25 CSP TRIP VOLTAGE (mV) 0 150 80 -1.5 160 -75 -50 -25 CG Rise/FG Fall, SYNC = 2V CG Rise/FG Fall, SYNC = 6V CG Rise/FG Fall, SYNC = 10V FG Rise/CG Fall, SYNC = 2V FG Rise/CG Fall, SYNC = 6V FG Rise/CG Fall, SYNC = 10V 170 1.5 SYNC VOLTAGE (V) CSW/FSW MAXIMUM INPUT CURRENT (A) Prop Delay from SYNC Input to CG/FG Outputs SYNC High/Low Trip Voltage CSP Maximum Input Current 200 TA = 25C, unless otherwise noted. 0 25 50 20 0 75 100 125 150 TEMPERATURE (C) 40 -20 0.1 0.4 8311 G30 0.7 1.0 1.3 RCSP (k) 1.6 1.9 8311 G31 8311f 10 For more information www.linear.com/LT8311 LT8311 PIN FUNCTIONS CSW (Pin 1): Catch MOSFET Drain Sense Pin. Connect this pin to the external N-channel catch MOSFET's drain through a 2k resistor (typical) in preactive mode. Minimize parasitic capacitance on the pin. Connect to GND in SYNC mode. FSW (Pin 3): Forward MOSFET Drain Sense Pin. Connect this pin to the external N-channel forward MOSFET's drain through 2k resistor (typical) in preactive mode. Minimize parasitic capacitance on the pin. Connect to GND in SYNC mode. FG (Pin 5): Forward MOSFET Gate Driver Pin. This pin drives the gate of the external N-channel forward MOSFET. Minimize trace length between this pin and the forward MOSFET gate. INTVCC (Pin 6): Internal Linear Regulator's Output Pin. INTVCC powers the gate drivers on the LT8311. The voltage on this pin is internally regulated to 7V. Alternatively, the pin can be overdriven externally. A minimum of 4.7F (ceramic capacitor) must be placed from this pin to GND. VIN (Pin 7): Input Supply Pin. This pin must be locally bypassed. PMODE (Pin 8): Preactive Mode Select Pin. Tying PMODE to GND enables preactive mode. Tying PMODE to INTVCC enables SYNC mode. OPTO (Pin 9): Opto Driver Output Pin. Tie this pin, through a series resistor, to the input of the opto-coupler. This pin can source up to 10mA, sink 300A typically, and is short-circuit protected. COMP (Pin 10): Error Amplifier Output Pin. Tie an external compensation network to this pin when using the LT8311's transconductance error amplifier as part of a voltage feedback loop. FB (Pin 11): Feedback Pin. This is the inverting input of the LT8311's internal error amplifier. The FB pin voltage tracks the lower of the internal 1.227V reference and the SS pin voltage. 75nA (bias current) typically flows out of the pin. Tie this pin to a resistor divider network from the output to set the desired output voltage. TIMER (Pin 12): Switching Period Timeout Pin. A resistor from this pin to ground sets an upper limit on the sum of the forward and catch MOSFET on times (including dead time between the two MOSFETs on period), every cycle. If the sum of the on times of the catch and forward MOSFET, per cycle (including the dead time), exceeds the timeout period programmed by the TIMER resistor, then all synchronous conduction will be shut down. Synchronous conduction resumes when the timeout period is reset again. See the Applications Information section for more details on programming the TIMER resistor. Keep the ground return trace of this pin short, and away from paths with switching noise. PGOOD (Pin 13): Output Power Good Pin. The open-drain output will be pulled to ground when the FB pin voltage stays within 7% of the internal 1.227V reference for a period of 175s. The internal PGOOD comparator has a hysteresis of 3%. Therefore, when FB exists outside 10% of the 1.227V reference, the PGOOD pin will be pulled high by an external pull-up resistor or current source. SS (Pin 14): Soft-Start Pin. A capacitor from the SS pin to GND will be charged up by SS's internally trimmed 10A current source. Since FB tracks the lower of the SS pin voltage and the internal reference of 1.227V, the charge rate of the SS pin can be used to set the slew rate at which the FB pin charges up to its regulation voltage of 1.227V. The SS pin typically charges up to 2V. When using the LT8311 as part of voltage feedback loop, place a ceramic capacitor of at least 1nF on this pin to GND. For details on SS start-up and overshoot control functions, please refer to the Applications Information section. SYNC (Pin 15): Synchronization Pin. The SYNC pin, used only in SYNC mode, serves as an edge-sensitive input to receive timing information for synchronous switching. It is typically driven with PWM synchronization signals from the primary-side IC through a pulse transformer. A negative voltage slew on the SYNC pin (-1.2V threshold) turns on the forward MOSFET and turns off the catch MOSFET. Equivalently, a positive voltage slew (1.2V threshold) turns on the catch MOSFET and turns off the forward MOSFET. Tie the SYNC pin to GND in preactive mode. CG (Pin 16): Catch MOSFET Gate Driver Pin. This pin drives the gate of the external N-channel catch MOSFET. Minimize trace length between this pin and the catch MOSFET gate. CSN, CSP (Pin 18, Pin 20): Current Sense Differential Inputs. CSP and CSN are the positive and negative inputs, respectively, of the LT8311's internal current sense comparator. The pins are typically connected across the catch 8311f For more information www.linear.com/LT8311 11 LT8311 PIN FUNCTIONS voltage offsets created by the input bias current (100nA) of the current comparator. In preactive mode, the CSP and CSN pins must be configured to trip at zero or positive values of source to drain current in the catch MOSFET (current in catch MOSFET cannot be allowed to flow from drain to source in preactive mode). MOSFET to perform VDS current sensing. Alternatively, if a more precise current sensing mechanism is desired, the pins may be connected across a sense resistor at the catch MOSFET's source. The current comparator trips at 62mV typical. The CSP pin sources 38A current, allowing trip voltages less than 62mV to be set by placing a resistor in series with the CSP pin. It is recommended to place an identical resistor in series with the CSN pin to match any GND (Exposed Pad Pin 21): Ground. Exposed pad must be soldered directly to local ground plane. BLOCK DIAGRAM PRIMARY SIDE VIN(SYS) * CRST PRIMARY IC NP SECONDARY SIDE LOUT * NS 1 M1 RFSW 3 5 7 CSW VIN FSW 7V 20 + INTVCC SYNCHRONOUS CONTROLLER CSP UVLO + 1.227 REFERENCE + 62mV -+ INTVCC MCG 16 RCSN 18 8 + - CG + - CSN + - 1.2V PMODE - + + - A2 SSDOWNAMP 10A 1V + - 2k 600mV VIN UVLO 1.227V 140k 1.14V COMP 10 CF RC 20k SYNC 15 5.7V CPL 11 +- 1.31V 20k RE RTIMER RFB1 100mV -+ 12 5.7V 1.227V S1 OPTO TIMER FB 0.9V VIN CINTVCC 1.2V SYNCHRONOUS MODE SELECT A1 + + - 9 1.2V 6 UVLO/ OVLO SWITCHING TIMEOUT OSCILLATOR - 300k RD - FG 38A RCSP COUT CVIN INTVCC MFG TO PRIMARYSIDE CIRCUITS VOUT RCSW + - + - VIN RPGOOD PGOOD 13 RFB2 GND 21 + - SS 14 8311 BD CSS CC 8311f 12 For more information www.linear.com/LT8311 LT8311 OPERATION The LT8311 controls the synchronous MOSFETs and optocoupler on the secondary side of a forward converter. Synchronous control of low RDS(ON) MOSFETs can typically lead to lower power dissipation in forward converters. The lower power dissipation can improve converter efficiency, resulting in long term cost savings by lowering input power requirements to support a certain level of output power. Improved efficiency can also reduce the size of heat sinks required to dissipate the heat generated in the rectifiers; consequently increasing the operating ambient temperature range which may be useful in many industrial applications. The LT8311 also offers opto-coupler control for accurate output voltage regulation over line and load. The LT8311's opto-coupler control circuitry comes with a host of start-up and steady-state functions to ensure robust transient response during power-on and output short-circuit recovery. FUNDAMENTALS OF FORWARD CONVERTER OPERATION IN CCM The timing diagram of a forward converter operating in continuous conduction mode (CCM) is shown in Figure 2. The timing diagram is broken into six regions of operation. Please refer to Figures 1 and 2 for the following explanation of each region of operation. ACTIVE CLAMP RESET (RED) RESONANT RESET (BLUE) Region 1 (Figure 2) When OUT goes high, M1 turns on. CG should already be at 0V before OUT goes high, to ensure that MCG does not cross conduct with M1. The LT8311's preactive mode, which will be explained later, is an innovative scheme to turn off MCG before M1 turns on. FG must be high during this period to keep the forward MOSFET, MFG on, thereby conducting the output inductor current, ILOUT, (via the transformer's secondary winding) through a low impedance path. During this phase, magnetizing current, ILMAG, builds up in the transformer's magnetic core, and flows from VIN to GND through M1. Output inductor current, ILOUT, ramps up at a rate of (VCSW - VOUT)/ LOUT. Region 2 (Figure 2) When OUT goes low, and turns off M1, the transformer becomes high impedance, and stops conducting ILOUT. Since current in the output inductor cannot go to zero instantaneously, it pulls the drain of the catch MOSFET, CSW, towards ground. Ultimately CSW gets clamped at a diode voltage below ground by MCG's body diode which now sources the output inductor current (similar to a catch diode in a traditional buck converter). CSW collapsing equivalently causes the transformer's secondary winding voltage to become smaller. Through transformer action, CSW VIN LMAG ILMAG NP * * LOUT ILOUT NS COUT VOUT RLOAD MCG PRIMARY IC VCL CAOUT VDRAIN_M2 + - M2 AOUT D2 CG CCL SWP CRST FSW M1 MFG SECONDARY IC FG OUT 8311 F01 Figure 1. Forward Converter with Active Clamp Reset (in Red) or Resonant Reset (in Blue) 8311f For more information www.linear.com/LT8311 13 LT8311 OPERATION AOUT 0V 0.7 (CLAMPED BY D2) 0.7 (CLAMPED BY D2) VGATE M2 (M2 SOURCE = 0V) M2 OFF M2 ON OUT (M1 SOURCE = 0V) M1 ON M1 OFF M2 OFF M2 ON 0V M1 OFF M1 ON PRIMARY NMOS SWITCH GATE PRIMARY-SIDE WAVEFORMS 0.7V SWP tRES = L MAG * CRST di V = IN dt LMAG PRIMARY NMOS SWITCH DRAIN 0V 0A VIN * D * tPER LMAG NS NP VIN * VIN 1- D di -1 VIN * D = * dt LMAG 1- D ILMAG ACTIVE CLAMP PMOS GATE 0V VIN 1+ (D * t PER ) 2 LMAG*CRST VIN ACTIVE CLAMP PMOS CONTROL SIGNAL TRANSFORMER MAGNETIZING INDUCTANCE CURRENT CATCH FET DRAIN CSW 0V 0.7V MCG OFF CG 0V MCG ON MCG OFF 0V CATCH FET GATE MCG ON 0V VOUT * t PER 2 * LMAG * CRST FSW FG 0V VOUT 1- D 0V 0.7V MFG ON SECONDARY-SIDE WAVEFORMS MFG OFF MFG ON 0V FORWARD FET GATE MFG OFF 0V di VCSW -VOUT = dt LOUT 0V di -VOUT = dt LOUT 0V VOUT RLOAD OUTPUT INDUCTOR CURRENT ILOUT VOUT * (1- D) * t PER LOUT D * tPER REGIONS OF OPERATION FORWARD FET DRAIN tPER 1 2 3 4 5 6 TIME 8311 F02 Figure 2. Active Clamp Forward Converter Timing Diagram in CCM. Resonant Reset Waveforms in Blue 8311f 14 For more information www.linear.com/LT8311 LT8311 OPERATION the primary winding voltage gets smaller too, effectively moving SWP towards VIN. Since MFG is still on, and MCG's body diode is on, the secondary winding voltage gets clamped at about a diode voltage. Through transformer action, SWP gets clamped to approximately VIN. ILMAG flows in the secondary windings, as shown in Figure 3, flowing from the drain to source of MFG, to ground. MCG's body diode sources ILOUT and ILMAG. capacitor. In resonant reset, ILMAG flows into CRST as soon as MFG turns off, causing SWP's voltage to rise up quasisinusoidally, with a time constant set by LMAG and CRST. In active clamp reset, when MFG turns off, ILMAG intially slews up SWP's voltage quickly. As shown in Figure 2, ILMAG does not flow into the active clamp capacitor as soon as MFG turns off. The voltage across CCL (= VCL = VIN /(1-D)) initially reverse biases M2's body diode. Only when SWP's voltage gets high enough to forward bias M2's body diode, does ILMAG begin to flow into CCL. The voltage where this happens is when SWP = VCL + 0.7V. At this point, SWP's voltage rises up at a rate determined by the time constant of LMAG and the active clamp capacitor, which is typically much larger than the resonant reset capacitor. Region 3 (Figure 2) When FG goes low, it allows transformer reset action to begin. ILMAG no longer has a low impedance path through MFG on the secondary side. As a result, it "jumps back" to the primary side, flowing into the primary-side resonant ILMAG LOUT VIN LMAG ILMAG NP * * ILOUT NS MCG CG OFF MFG FG ON M1 OFF 8311 F03 Figure 3. With FG On, ILMAG Is Conducted Through MFG to Ground on the Secondary Side When M1 Turns Off tRISE PROPORTIONAL TO LMAG AND CCL VCL = VIN 1- D VCL + 0.7V VCL SWP VIN 0.7V 0V VDRAIN_M2 MFG TURNS OFF VIN - VCL M2 BODY DIODE OFF M2 BODY DIODE ON M2 ON TIME 8311 F04 Figure 4. Detail of Region 3 from the Timing Diagram in Figure 2. When MFG Turns Off in Active Clamp Reset, ILMAG Initially Slews Up SWP's Voltage from VIN to VCL + 0.7V, at Which Point M2's Body Diode Turns On and Allows ILMAG to Flow into CCL 8311f For more information www.linear.com/LT8311 15 LT8311 OPERATION The ultimate goal of both reset mechanisms is to raise the SWP node to a voltage higher than VIN, imposing appropriate volt seconds on LMAG, and allowing the magnetizing current to reset. Resetting the magnetic core every cycle prevents magnetic flux buildup within the core, and thereby prevents transformer saturation. FSW tracks the SWP node during transformer reset. CG going high, allows ILOUT to switch over from being conducted by MCG's body diode to MCG itself. Region 4 (Figure 2) 1. Active Clamp Reset Case (red waveform): AOUT going low causes the gate of M2 to be driven below ground by the decoupling capacitor, CAOUT. This causes M2, the active clamp PMOS, to turn on. M2 must be turned on before ILMAG becomes negative, to allow ILMAG to sustain conduction through the active clamp capacitor and get fully reset. Active clamp reset completes by the end of region 4, and ILMAG is reset to a negative value. 2. Resonant Reset Case (blue waveform): Resonant reset ultimately completes when SWP's quasi-sinusoidal waveform returns to VIN, by which point ILMAG is reset to a negative value. FSW is eventually clamped by MFG's body diode, and conducts ILMAG, through the secondary windings, towards the output inductor (similar to Figure 3, but with ILMAG direction reversed on primary and secondary sides). With a diode voltage imposed across the secondary windings, transformer action causes the primary winding to have a similar voltage (scaled by turns ratio), resulting in SWP's voltage getting clamped to VIN. MCG continues conducting ILOUT - ILMAG. Region 5 (Figure 2) Active Clamp Reset Case: AOUT goes high, turning off M2. ILMAG, being negative, causes the voltage on SWP (M1's drain) to get pulled towards VIN, resulting in the transformer's primary winding voltage becoming smaller. By transformer action, the secondary winding voltage also becomes smaller. With MCG on (holding CSW at 0V), and the transformer secondary winding voltage becoming smaller, FSW collapses towards 0V. Region 6 (Figure 2) Eventually, in similar fashion to the resonant reset case, FSW is clamped to a diode voltage below GND by MFG's body diode, which now conducts ILMAG through the secondary windings, towards the output inductor. With MFG's body diode on, and MCG on, the secondary winding voltage gets clamped to about a diode voltage. Through transformer action, SWP gets clamped to approximately VIN. CG goes low, turning off MCG before M1 can turn on. ILOUT - ILMAG is conducted through MCG's body diode. FG goes high, turning on MFG. Eventually, when M1 turns on, ILOUT will be conducted through the transformer's secondary winding, and will flow from the source to drain of MFG. 8311f 16 For more information www.linear.com/LT8311 LT8311 OPERATION LT8311 SYNCHRONOUS CONTROL SCHEMES The LT8311 offers two modes of synchronous control: 1. Preactive Mode: No pulse transformer needed; DCM operation at light load. Enabled by tying the PMODE pin to 0V. Use a Schottky diode across MCG (Figure 20). 2. SYNC Mode: Pulse Transformer needed; FCM or DCM operation at light load. Enabled by tying the PMODE pin to INTVCC. PREACTIVE MODE SYNCHRONOUS CONTROL MCG Turn-On/Off Timings in Preactive Mode "Preactive" is short for "predictive" + "reactive". In preactive mode, the LT8311 controls the secondary synchronous MOSFETs without any communication from the primaryside IC. In preactive mode, the catch MOSFET, MCG, is turned on (CG rising edge in Figure 5) when the voltage on its drain, CSW, is detected to be below -150mV, and the forward MOSFET, MFG, is detected to be off. MCG is turned off when the first of two events after MCG's turnon occurs: * Predictive MCG Turn-Off (Figure 5): In predictive turnoff, the LT8311 predicts when M1 will turn on in the next cycle, and turns off MCG 100ns prior to this event. Predictive turn-off of MCG prevents cross conduction between MCG and M1. M1's turn-on timings are predicted by phase locking to the rising edge of present and past CSW cycles. Predictive turn-off relies on the periodicity of M1's turn-on edge, an inherent aspect of fixed-frequency operation. Furthermore, the predictive turn-off is designed to be independent of the duty cycle of the system, which allows MCG to be correctly turned off, even during load/line transients. Predictive turn-off will typically be the dominant turn-off mechanism for MCG in CCM. * Reactive MCG Turn-Off (Figure 6): Reactive turn-off forces the forward converter to operate in DCM at light load. In reactive turn-off, the LT8311 turns off MCG when the current in MCG (IMCG) trips the LT8311's internal current comparator. The inputs to this current comparator are the CSP and CSN pins. Typically, the CSP and CSN pins will be configured to trip at almost zero current in MCG, which should correspond to nearly zero current in the output inductor. Reactive turn-off will typically be the dominant turn-off mechanism for MCG in DCM. The LT8311's seamless transition between predictive and reactive portions of preactive mode allows the catch MOSFET to be turned off at the correct time to avoid cross conduction or avalanching. MFG Turn-On/Off in Preactive Mode In preactive mode, MFG is turned on after MCG's turn-off edge is detected, and the voltage on the drain of the forward MOSFET, FSW, is detected to be below 1.2V. Waiting for FSW to fall below 1.2V ensures that transformer reset is close to completion. MFG is turned off when the voltage on CSW is detected to be below -150mV. Since preactive mode requires each MOSFET to be turned on only after the other MOSFET's turn-off edge is detected, the system requires a start point where one of the two MOSFETs begins switching. Preactive mode's start point happens by turning on MCG first to commence switching. Preactive Mode Shutdown and Start-Up Preactive mode is designed with many features to facilitate smooth start-up of synchronous control and shut down of the scheme when necessary. Prior to starting switching activity, the LT8311 evaluates conditions on the forward converter's secondary side to determine if switching can commence. The evaluation period ends when four specific conditions, are satisfied for a period of three continuous CSW switching cycles (rising edge to rising edge). If any of the conditions are violated, the evaluation period is reset, and switching activity is kept shut off. During this evaluation period, the secondary side current will flow through the body diodes of MCG and MFG. The four conditions are: 1. VIN must be greater than its UVLO voltage 2. INTVCC must be within its UVLO/OVLO limits 3. The TIMER pin should not have timed out. This feature exists to ensure that the LT8311 ceases switching in the event that the primary side stops switching. 8311f For more information www.linear.com/LT8311 17 LT8311 OPERATION VIN * NP LOUT * NS PRIMARY IC OUT LT8311 CSW FSW RESET MECHANISM PRIMARY-SIDE IC CONTROLS TIMING OF OUT SIGNAL ILOUT CSW M1 FSW CSP MCG MFG CG IMCG VOUT COUT LT8311 USES CSW/FSW INFORMATION TO DETERMINE FG/CG CONTROL TIMINGS DURING THE PREDICTIVE PORTION OF PREACTIVE MODE CSN FG OUT M1 TURN-ON EDGE M1 TURN-ON EDGE 0V 0V 0V CSW WAVEFORMS IN CCM MCG TURN-OFF EDGE CG MCG TURN-OFF EDGE 75ns PREDICTIVE DELAY TIME 8311 F05 Figure 5. During the Predictive Portion of Preactive Mode, the LT8311 Phase Locks into the CSW Rising Edge and Turns Off MCG 75ns Prior to This Edge OUT M1 TURN-ON EDGE 0V PRIMARY-SIDE IC CONTROLS TIMING OF OUT SIGNAL M1 TURN-ON EDGE 0V 0V LT8311 USES IMCG INFORMATION TO DETERMINE FG/CG CONTROL TIMINGS DURING THE REACTIVE PORTION OF PREACTIVE MODE CSW WAVEFORMS IN DCM ILOUT 0A IMCG WHEN CSP-CSN TRIPS INTERNAL CURRENT COMPARATOR MCG TURNS OFF 0A CG TIME 8311 F06 Figure 6. During the Reactive Portion of Preactive Mode, the LT8311 Turns Off MCG When the Current in MCG, IMCG, Trips the LT8311's Internal Current Comparator. The Inputs to the Comparator Are CSP and CSN and the Current Sense Trip Voltage Is Programmed by Choosing Appropriate CSP/CSN Series Resistors 8311f 18 For more information www.linear.com/LT8311 LT8311 OPERATION 4. The CSP and CSN pins must not trip the internal current comparator within a 150ns period of time called "current sample window." This function helps the LT8311 detect very light load conditions, during which time it will keep synchronous conduction shut off, thereby improving system efficiency. How the current sample window works: The current sample window exists regardless of whether MCG is turned on or not, in any given cycle. When CSW is detected to fall below -150mV, the LT8311 starts a blank time of 200ns. Upon completion of this blank time, the LT8311 starts a 150ns current sample window. If the CSP/CSN pin inputs cause the internal current comparator to trip during this 150ns window, the LT8311 will interpret this as a condition of very light load, at which point it will stop synchronous conduction and start the evaluation period again. Please see "Configuring CSP/ CSN Inputs of Current Sense Comparator in Preactive Mode" in the Applications Information section. When all four conditions are valid for three continuous CSW cycles, the evaluation period ends and the LT8311 gets ready to start switching. Switching commences with the LT8311 turning on MCG for its minimum on-time. If any of the four conditions listed are violated at any point during switching activity, the LT8311 will shut down all synchronous conduction and restart the evaluation period. During preactive mode start-up, the LT8311 internally softstarts the on-time of MCG, allowing the forward converter to gradually transition from full cycles of nonsynchronous MCG conduction (secondary-side current flowing through body diode of MCG) to full cycles of synchronous MCG conduction. SYNC MODE SYNCHRONOUS CONTROL SYNC mode allows the LT8311 to operate in forced continuous mode (FCM) at light loads. In SYNC mode, a pulse transformer (see T2 in Figure 7) is required to allow the LT8311 to receive synchronization control signals from the primary-side IC. These control signals are interpreted digitally (high or low) by the LT8311 to turn on/off the catch and forward MOSFETs. FCM operation allows the forward converter to avoid operation in discontinuous conduction mode (DCM) at light loads, by letting the inductor current go negative. Hence, even at zero load, the inductor current remains continuous and the converter runs at a fixed frequency. MCG Turn-On/Off Timings in SYNC Mode In SYNC mode, MCG turns on when the signal on the SYNC pin is higher than 1.2V. MCG turns off when the signal on the SYNC pin is lower than -1.2V. MFG Turn-On/Off Timings in SYNC Mode In SYNC mode, MFG turns on when the signal on the SYNC pin is lower than -1.2V. MFG turns off when the signal on the SYNC pin is higher than 1.2V. The RSYNC and CSYNC time constant must be appropriately chosen to generate a sufficient pulse width at a particular overdrive voltage (see "Picking Pulse Transformer and High Pass Filter" in the Applications Information section). Typical values for CSYNC and RSYNC are 220pF and 560, respectively. 8311f For more information www.linear.com/LT8311 19 LT8311 OPERATION SYNC Mode Shutdown 4. The CSP and CSN pins have tripped the LT8311's internal current comparator during MCG's on-time. The current in MCG, IMCG, is sensed after a 400ns blank time has expired. This blank time starts at the turn-on edge of MCG. See the Applications Information section for details on configuring the CSP and CSN pins in SYNC mode. In SYNC mode, the LT8311 will shut off both secondaryside MOSFETs, MCG and MFG, if any of the following conditions are true: 1. VIN is less than its UVLO voltage 2. INTVCC outside its UVLO/OVLO limits 3. The TIMER pin has timed out (see the Applications Information section for details on programming the TIMER pin resistor). LOUT T1 VIN * * NP FG CSN CG CSP OUT T2 * * SYNC RSYNC M1 TURN-ON EDGE M1 TURN-ON EDGE 0V SOUT LT8311 CONTROLS FG AND CG TIMING BASED ON SYNC INPUT SIGNAL IN SYNC MODE LT8311 CSYNC 0V 0V 0V 0V 0V 1.2V 0V SYNC MCG TURN-ON EDGE CG FG IMCG MFG M1 PRIMARY IC SOUT OUT MCG NS RESET PRIMARY-SIDE IC CONTROLS TIMING OF OUT AND SOUT SIGNALS VOUT COUT 0V 0V MFG TURN-ON EDGE -1.2V MCG TURN-ON EDGE 0V 0V 0V 0V MFG TURN-ON EDGE 0V TIME 8311 F07 Figure 7. In SYNC Mode, the Primary Side IC Sends SOUT Signals Through a Pulse Transformer to the LT8311's SYNC Pin. SYNC < 1.2V Turns on MFG and Turns Off MCG. SYNC > 1.2V Turns On MCG and Turns Off MFG 8311f 20 For more information www.linear.com/LT8311 LT8311 OPERATION OPTO-COUPLER CONTROL The LT8311 offers opto-coupler control to allow output voltage feedback from the secondary to the primary side in a forward converter. Used in conjunction with a primary-side IC, the entire system offers fixed frequency peak current mode control that has excellent line/load regulation and quick transient response. A basic understanding of the LT8311's opto-coupler control scheme can be obtained by referring to Figure 8. The LT8311 senses the output voltage through a resistor divider (RFB1 and RFB2) connected to its FB pin. The FB pin voltage is compared to the lower of two inputs: * An internal voltage reference of 1.227V * Soft-start (SS) pin At start-up, the SS pin capacitor, CSS, is charged up by the LT8311's internally trimmed 10A current source. Since FB tracks the lower of the SS pin and the 1.227V refer- * NP * NS LT8311 OPTO CONTROL 10A SS RSNS VC IS ALSO REFERRED TO AS COMP IN SOME PRIMARY-SIDE ICs R2 VREF 9 RD + A2 - OPTO 1V + 20k CSS - 0.9V + - A1 + 140k 2k R1 CF 14 1.227V COMP 10 RE RLOAD CG FG M1 VOUT COUT GAIN + A3 - When the SS pin voltage gets higher than the 1.227V reference, the FB pin starts to track the 1.227V reference. The output, therefore, regulates at a voltage set by the RFB1/ RFB2 divider network, and the FB pin's regulation voltage of 1.227V. The SS pin capacitor continues to get charged up by the 10A current source until it reaches its internal clamp voltage of 2V. MCG MFG VC NOTE: To ensure that the soft-start time of the converter is controlled by the LT8311's SS capacitor, CSS, it is important to program the primary IC's soft-start faster, to get out of the way. If this is not done, the converter's soft-start time will be dominated by the primary IC's soft start, and the LT8311 will simply adjust its SS pin voltage and slew rate to match the slower soft start time set by the primary-side IC. LOUT VIN + A4 - ence, the FB pin (and by extension the output voltage) is forced to soft-start at the slew rate set by the capacitor, CSS, connected to the SS pin. 1.227V FB CPL RFB1 11 RFB2 8311 F08 RC CC Figure 8. The LT8311 Provides Voltage Feedback, as Part of a Peak Current Mode Control System, in a Forward Converter 8311f For more information www.linear.com/LT8311 21 LT8311 OPERATION VIN > 3.7V OPTO-DRIVER DEACTIVATION 1. ERROR AMP DISABLED: COMP PIN VOLTAGE CHARGED UP TO COMP HI CLAMP = 2.2V; tRISE 1.1 * 10k * CC 2. SS PULL-DOWN AMPLIFIER DISABLED 3. SS PULL-UP AMPLIFIER ACTIVATED. THIS AMPLIFIER ONLY HAS SOURCING CAPABILITY (1mA SLEW CURRENT), AND WILL DRIVE SS PIN VOLTAGE CLOSE TO FB PIN VOLTAGE (VFB - VSS 16mV) 4. SS 10A CHARGE CURRENT ACTIVATED 5. OPTO-DRIVER DISABLED: OPTO PIN VOLTAGE HELD AT 0V YES COMP < 2.2V NO OPTO-DRIVER ACTIVATION 1. ERROR AMP ENABLED: ERROR AMP CAN NOW DRIVE COMP BASED ON COMPARING FB VOLTAGE WITH SS VOLTAGE OR 1.227V REFERENCE 2. OPTO-DRIVER ENABLED: OPTO-DRIVER CAN NOW DRIVE OPTO PIN AS A FUNCTION OF COMP PIN VOLTAGE NO SS > FB - 16mV YES SS PULL-DOWN AMPLIFIER ENABLED 1. SS PULL-UP AMPLIFIER DISABLED 2. SS PULL-DOWN AMPLIFIER ENABLED: THIS AMPLIFIER ONLY ACTIVATED WHEN FB PIN VOLTAGE IS LESS THAN 50% OF FB REFERENCE VOLTAGE. THIS AMPLIFIER ONLY HAS SINKING CAPABILITY (12mA SLEW CURRENT) AND WILL DRIVE SS PIN VOLTAGE TO BE NO HIGHER THAN 90mV ABOVE FB 8311 F09 Figure 9. Flowchart for LT8311 Opto Control Operation at Start-Up With SS charged up to 2V, the transconductance error amplifier, A1, sinks or sources current from its output, COMP, if there is any voltage difference between the FB pin voltage and the 1.227V reference. The COMP pin, offset by 0.9V, serves as the input to the opto-driver, A2. If an increase in output load current causes the FB pin voltage to be lower than 1.227V, A1 drives the COMP pin high. COMP going high forces A2 to drive OPTO low, sourcing less current through RD into the opto-coupler. Since an opto-coupler's output current is directly proportional to its input current, this decreased input current for the opto-coupler will cause its output current, and therefore its emitter voltage at RE, to decrease as well. The drop in RE voltage causes A3, through its inverting action, to drive its output, VC, higher. An increase in the VC voltage causes the comparator, A4, to command a higher sense voltage across the RSNS resistor, commanding M1 to run at a higher peak current. Since the current through M1 is 8311f 22 For more information www.linear.com/LT8311 LT8311 OPERATION directly proportional to the output inductor current (M1 Current * NP/NS = ILOUT), an increase in M1's peak current translates into an increase in the output inductor's peak current. In essence, the feedback loop is commanding the output inductor peak current to meet the demands of the increased load current, with the ultimate goal of helping the output voltage recover from a load step and stay regulated. its VIN UVLO voltage, so that upon getting power, it can tolerate up to a 100mV drop on its VIN pin before losing power again. Even more importantly, the LT8311 has an opto-control start-up system that keeps the LT8311's "opto-control brains" turned off until all relevant node voltages within the voltage loop are prebiased to a state where they will not cause switching activity to cease when the loop is eventually enabled. Opto-Control Operation at Start-Up As shown in Figure 9 and the scope shot in Figure 10, the LT8311's opto-control operation at start-up involves slewing the SS pin voltage close to the FB pin voltage, slewing the COMP pin voltage to its high clamp voltage, and keeping the OPTO pin voltage held low. During this phase, the inductor current (and by extension, the output voltage) is controlled by the soft-start function provided by the primary-side IC. Upon completion of the state machine, the LT8311 allows the feedback loop to be functional again, and the FB pin voltage tracks the LT8311's SS pin voltage until FB finally gets to its regulation target of 1.227V. For applications connecting the LT8311's VIN pin directly to the converter output, the LT8311 includes intelligent circuitry to ensure no interruption in the switching of the primary-side MOSFET upon the LT8311's turn-on. The LT8311 turns on when its VIN pin (and therefore the converter output voltage when VIN is directly connected to the output) exceeds 3.7V. Without intelligent circuitry, this VOUT level will cause the FB pin voltage of the LT8311 to be greater than the voltage on the LT8311's SS pin (which is typically at 0V upon turn-on of the IC), causing amplifier A1 to drive the COMP pin low. This drives the OPTO pin high, which causes full current into the opto-coupler and terminates switching of the primary-side MOSFET. Termination of the primary-side MOSFET's switching can lead to the converter's output voltage dropping, which could cause the LT8311 to lose power and shut off. The LT8311's intelligent circuitry prevents this situation using two unique features. It has a built-in 100mV hysteresis on COMP 1V/DIV Power Good The LT8311 offers output power good monitoring to assist with system level design. The LT8311's PGOOD pin is pulled low internally when the FB pin voltage stays within a 7% window of the 1.227V reference for a period of 175s. Waiting for 175s to elapse prevents the PGOOD pin from indicating false positives during transient events. PGOOD 5V/DIV FB 200mV/DIV FB 500mV/DIV SS 200mV/DIV OPTO 500mV/DIV 8311 F10 5ms/DIV Figure 10. Opto Control Operation at Start-Up 2ms/DIV 8311 F11 Figure 11. Power Good Activates (PGOOD = Low) When the LT8311's FB Pin Voltage Is Within 7% of Its Regulated Target (1.227V). The PGOOD Pin Is Pulled Up Externally to a 12V Housekeeping Supply Through a 100k External Resistor 8311f For more information www.linear.com/LT8311 23 LT8311 OPERATION The PGOOD comparator has 3% hysteresis. Therefore, when the FB pin voltage is driven away from its regulated value of 1.227V by 10%, the PGOOD pin's internal pulldown shuts off immediately. As a result, the pin is pulled high by an external resistor or external current source connected to a supply voltage. The PGOOD pin's output can be fed to a microcontroller that make decisions based on the state of the output voltage. Output Overshoot Control Helps with Short-Circuit Recovery The LT8311 provides output overshoot control by activating its soft-start pull-down amplifier (SSDOWNAMP in the Block Diagram) any time the FB pin voltage is less than 50% of the FB reference voltage (1.227V). This is particularly helpful with output voltage recovery after the removal of a short-circuit condition or after a heavy load transient. The SS pull-down amplifier will sink whatever current is necessary (up to its maximum sink capability of 13mA), to ensure that the SS pin voltage gets no higher than 100mV above the FB pin voltage. During output short-circuit events, when the FB pin voltage is pulled to ground, the SS pulldown amplifier gets activated and pulls the SS pin voltage to 100mV above the FB pin voltage. Eventually, when the short-circuit condition is over, the FB pin voltage gradually rises up with the SS pin at a slew rate set by CSS and the 10A charge current. This allows the output to recover gradually from the short-circuit condition. Note that when the LT8311 has its VIN pin powered directly from the output of the forward converter, it will lose all its brains during a short-circuit event. Under this scenario, output overshoot control will not be in effect until the LT8311 gets brains again, until which point, the output inductor current and the output voltage will be controlled by the primary-side IC's soft-start function. PGOOD 10V/DIV PGOOD 10V/DIV SS 500mV/DIV SS 500mV/DIV FB 500mV/DIV FB 500mV/DIV 1ms/DIV 8311 F12a (a) Output Overshoot Control with CSS = 1nF. LT8311 VIN Powered from a 12V Housekeeping Supply, Which Also Pulls Up on the PGOOD Pin Through a 100k External Resistor 2ms/DIV 8311 F12b (b) Output Overshoot Control with CSS = 33nF. LT8311 VIN Powered from a 12V Housekeeping Supply, Which Also Pulls Up on the PGOOD Pin Through a 100k External Resistor Figure 12. Output Overshoot Control at Start-Up 8311f 24 For more information www.linear.com/LT8311 LT8311 APPLICATIONS INFORMATION VIN BIAS SUPPLY The LT8311's VIN pin can be powered in various ways. Place at least a 2.2F ceramic bypass capacitor close to the pin. Picking an appropriate bias supply to power up the LT8311 requires consideration of the following criteria: 1. The VIN pin, in certain configurations, may be the only supply to the LT8311's INTVCC pin, which provides gate drive to the catch and forward MOSFETs. In such situations, VIN's bias supply must be high enough to provide adequate gate-drive voltage (typically 5V to 7V) for both synchronous MOSFETs. 2. VIN's bias supply must be able to source: a. LT8311's VIN current (4.5mA typical) b. INTVCC gate-drive current when using VIN to supply the INTVCC pin (typically 10mA to 30mA) c. Opto-driver source current (typically 1mA to 5mA) 3. VIN start-up and short-circuit conditions: a. VIN must come up in reasonable time to allow the LT8311 to begin synchronous and opto-coupler control. While synchronous control is shut off, the secondary-side current will flow through the body diodes of the secondary synchronous MOSFETs. While opto-control is off, the forward converter will operate open-loop, using a volt-second clamp to control VOUT if operating with LT3752, LT3752-1 or LT3753 on the primary side. b. VIN may be shorted to GND during transient events. For instance, VIN powered from the output voltage, will be driven to 0V during an output short-circuit. The forward converter must be able to ride through the momentary loss of power to the LT8311, which is often easily accomplished by appropriately configuring soft-start control on the primary-side ICs. Refer to the LT3752/LT8310 data sheets for details on configuring soft-start control on the primary-side IC. With the previous criteria in mind, there are three methods (1-3), listed below, for powering up the LT8311. For preactive mode, use method 1, 2 or 3. For SYNC mode FCM, use method 1 or 3; for DCM, use method 1, 2 or 3. 1. Power from the LT3752's housekeeping supply (see Figure 21 in the Typical Application section). Being a flyback converter rather than a LDO, the LT3752's housekeeping supply is an efficient supply source. It can be connected through an external winding to the LT8311's VIN and INTVCC pins, and can be set high enough to provide adequate gate drive for the catch and forward MOSFETs, but low enough to minimize efficiency and thermal losses. The housekeeping supply comes up as soon as the LT3752 receives input power, so power is delivered to the LT8311 without delay. 2. Power directly from VOUT. At output voltages lower than 10V, careful consideration must be given to the output voltage start-up time, ensuring that the LT8311 can turn on and provide synchronous/opto control well before the output voltage approaches regulation. It is also important to ensure, at these lower output voltages, that sufficient gate drive voltage can be provided to the external MOSFETs. At higher VOUT voltages, efficiency and thermal considerations related to the IC's internal power dissipation can become important criteria. In addition, at higher VOUT voltages, it is important to ensure that voltage transients on the VIN pin do not exceed the pin's abs max rating of 30V. 3. Use a buck circuit from an auxiliary transformer winding, as shown in Figure 13. This circuit has the benefit of being highly efficient, and is fairly simple to design. It is particularly useful for low output voltage applications (3.3V or 5V) that do not have an external housekeeping supply, and where powering directly from the output voltage is inadequate. In this configuration, the buck circuit's output voltage derives its energy from secondary-side switching pulses that also source energy to the forward converter's main output voltage, VOUT. Careful consideration must be given to ensure that the buck output voltage comes up well in time, and turns on the LT8311 to provide synchronous and opto control before the forward converter's actual output voltage gets close to regulation. If there is a need to speed up 8311f For more information www.linear.com/LT8311 25 LT8311 APPLICATIONS INFORMATION the time taken by the buck converter output voltage to get to its target, relative to the forward converter's main output voltage, often a simple technique is to slow down the main output voltage start-up time by increasing the soft-start capacitor on the primary-side IC. INTVCC BIAS SUPPLY The INTVCC pin powers the catch and forward MOSFET gate drivers of the LT8311. Two configurations exist for biasing up the INTVCC pin, as shown in Figure 14: 1. In the first configuration, the LT8311's on-chip LDO regulates the INTVCC pin voltage from the VIN supply. When the VIN pin voltage is low, the internal LDO will operate in drop-out, driving the INTVCC pin to about 400mV below the VIN pin voltage. When the VIN pin voltage is high, the internal LDO will regulate INTVCC's voltage to 7V. Ensure that VIN's supply voltage does not exceed VIN's abs max voltage of 30V. If INTVCC drops below its UVLO voltage (4.6V rising and 4.3V falling), all synchronous switching will be stopped. The maximum guaranteed current that the INTVCC LDO can source is 40mA. Ensure that the total gate charge (Qg) current required by both secondary MOSFETs, MCG and MFG, is less than 40mA: IMOSFET_TOTAL = fSW * (Qg_MCG + Qg_MFG) < 40mA where fSW is the converter's switching frequency, Qg_MCG is the gate charge (Qg) rating of MCG and Qg_MFG is the gate charge (Qg) rating of MFG. This configuration, utilizing the LT8311's internal LDO, will suffice for most applications, limited only by thermal considerations related to the LDO's power dissipation. Keeping the power dissipation to a minimum will help lower the operating junction temperature of the LT8311, potentially allowing the system to operate over a wider ambient temperature range: LDO Power Dissipation = (VIN - INTVCC) * IMOSFET_TOTAL LT8311 Operating Junction Temperature JA * (VIN * 4.5mA + LDO Power Dissipation + VIN * IOPTO) + TA where JA is LT8311's junction-to-ambient thermal resistance and is typically 38C/W; IOPTO is the current N VAUX = VOUT * AUX NS BUCK AUXILLIARY SUPPLY * VAUX LT8311 VIN VIN LDO INTVCC NAUX VIN < 30V LT8311 INTVCC REGULATED to 7V 4.7F VIN NP * * VOUT NS MCG LT8311 VIN M1 VIN < 16V MFG LDO INTVCC 8311 F13 4.7F 8311 F14 Figure 13. Buck Circuit Generates VAUX Supply, Which Powers LT8311's VIN and INTVCC Pins Figure 14. VIN and INTVCC Pin Configurations 8311f 26 For more information www.linear.com/LT8311 LT8311 APPLICATIONS INFORMATION sourced into the opto-coupler by the LT8311's OPTO pin; 4.5mA is the typical VIN current of the LT8311; TA is the ambient temperature. 2. In the second configuration, the VIN pin's bias supply drives the INTVCC pin through a direct connection, bypassing the internal LDO. This configuration reduces power dissipation inside the IC by not having to incur any power loss within the INTVCC LDO. Use this optional configuration for VIN voltages that are below 16V, allowing sufficient margin for INTVCC to stay below its OVLO(+) voltage of 16.5V. Ensure that VIN, during transients, does not exceed INTVCC's abs max voltage of 18V. When an external supply or auxiliary winding is available, use this configuration (tying VIN and INTVCC together) to deliver power to the IC. This configuration is most applicable when using the LT3752 as a primary-side IC. The LT3752's housekeeping supply can be connected to the LT8311's VIN and INTVCC through an auxiliary winding, as shown in Figure 21 in the Typical Applications section. INTVCC should be bypassed with a minimum of 4.7F ceramic capacitor to ground for all three configurations. Place the capacitor close to the INTVCC pin, ensuring that the ground terminal of the capacitor has the shortest possible return path to the LT8311's ground (exposed pad). LT8311 OPTO CONTROL FUNDAMENTALS Setting Output Voltage Figure 15 shows how to program the forward converter's output voltage with a resistor divider feedback network. Connect the top of RFB1 to VOUT, the tap point of RFB1/ RFB2 to the FB pin, and the bottom of RFB2 to ground. The ground return of RFB2 must be kept as close as possible to the ground of the LT8311, and must be kept away from the forward converter's power path. The power path contains switching currents, and possibly large value currents (depending upon the load) which may introduce unintended noise, or I * R drops into the FB resistor divider path. The FB pin regulates to 1.227V and has a typical input pin bias current of 120nA flowing out of the pin. The output voltage is set by the formula: R VOUT = 1.227 * 1+ FB1 - 120nA * RFB1 RFB2 VOUT LT8311 120nA RFB1 FB RFB2 GND 8311 F15 Figure 15. Setting Output Voltage of Forward Converter 8311f For more information www.linear.com/LT8311 27 LT8311 APPLICATIONS INFORMATION IOUT VIN * * NP LT3752 OR LT8310 VCOMP_PRIMARY OUT (GATE) + - CURR_GAIN = 7.5V/V, 5V/V ISENSEP (SENSE) FG M1 + - VREF FB (FBX) MAX COMP/VC SRC CURRENT ~ 11mA, 13A MAX COMP/VC SINK CURRENT 11mA, 12.5A COUT2 RLOAD RESR LT8311 VIN(LT8311) - 1.7V < VCC(OPTO) < 6V VCC(OPTO) VISENSEP + - OPTO RSNS IF MF 1V 20k - COPTO RD gmEA = 350umhos ROUTEA = 4.5M + 0.9V 140k COMP/VC VOLTAGE TO COMMAND MAX RSNS CURRENT 2V, 1.2V VREF = 1.25V, 1.60V COUT1 CG MFG COMP/VC VOLTAGE TO COMMAND 0 RSNS CURRENT 1.25V, 0.7V TRUE VOLTAGE AMP TRANSCONDUCTANCE AMP VOUT MCG NS IPRIMARY LOUT + - CPL RFB1 1.227V FB 2k MAX OPTO SOURCE CURRENT = 10mA MAX COMP SRC CURRENT = 20A COMP MAX COMP SINK CURRENT = 30A RFB2 8311 F16 IOPTO_OUT RIN(OPTO) = 1/gm(OPTO) R1 CF RC CC VX RE COMP (VC) R2 R2 (TYPICAL) 33k, 150k R1 = R2 / GAIN 1 < GAIN (TYPICAL) < 2 Figure 16. Forward Converter Voltage Feedback Loop with LT8311 on Secondary Side and LT3752 (or) LT8310 on Primary Side Picking Loop Compensation Components Figure 16 shows a typical loop associated with a forward converter, using the LT8311 on the secondary side, and the LT3752 or LT8310 as the primary-side ICs. Parametric values specific to the LT3752 are shown in red, while those specific to the LT8310 are shown in blue. The forward converter loop shown is a peak current mode control system. The optimum values for loop compensation depend on the IC used on the primary side and the LT8311, as well as the operating conditions of the converter (input voltage range, output voltage, load current, etc.). To compensate the voltage feedback loop around the LT8311, a series resistor/capacitor network is usually connected from the LT8311's COMP pin to GND. For most applications, the capacitor CC should be in the range of 4.7nF to 47nF, and the resistor RC should be in the range of 2k to 20k. If the RC value is too large, the part will be more susceptible to high frequency noise and jitter. If the RC value is too small, the transient performance will suffer. The value choice for CC is somewhat the inverse of the RC choice: if too small a CC value is used, the loop may be unstable and if too large a CC value is used, the transient performance may suffer. A small capacitor, CF, is often connected in parallel with the RC compensation network to attenuate the COMP pin voltage ripple induced from the output voltage ripple (through the internal error amplifier). The CF capacitor usually ranges in value from 10pF to 100pF. For certain applications, a phase-lead zero capacitor CPL (in parallel with RFB1 resistor), or a pole-zero pair (COPTO and RD) on the OPTO pin may help improve the transient performance of the loop. A practical approach to design the compensation network is to start with one of the circuits in this data sheet that is similar to your application, and tune the compensation network to optimize the performance. Stability should then be checked across all operating conditions, including load current, input voltage range and temperature. 8311f 28 For more information www.linear.com/LT8311 LT8311 APPLICATIONS INFORMATION Picking the Opto-Coupler where IOPTO_OUT is the output current of the opto-coupler and IF is the opto-coupler's input LED current The voltage feedback loop, explained earlier, uses an opto-coupler to convey output voltage information from the secondary side to the primary side (see Figure 17). An opto-coupler is used because of its wide prevalence, relatively low cost, and its ability to convey DC signal information over an isolation boundary with potential differences of up to 5000V. Opto-couplers have historically been disliked, and justifiably so, for having CTRs that degrade with operating lifetime, at higher operating temperatures, and at higher input currents (IF). Much of this CTR degradation comes from a reduction in the quantum efficiency of the input LED, which is a function of the LED's operating current (IF), operating temperature and operating lifetime. The input of an opto-coupler typically consists of an infrared light-emitting diode (LED), while the output is typically a phototransistor. Current flowing into the opto-coupler's input LED, called IF, causes photons to be emitted. These photons cross the opto-coupler's isolation barrier and get collected in the base of the output phototransistor. This photo current, which essentially forms the phototransistor's base current, is gained up by the phototransistor's (current gain) before flowing out of the opto-coupler, and is called IOPTO_OUT. The key parameter of interest in an opto-coupler is the current transfer ratio (CTR). CTR is typically expressed in units of %, and is calculated as follows: I CTR(%) = OPTO _ OUT IF Fortunately, LED technology has matured over the last couple of decades, and has allowed improvements in optocoupler performance, a discussion of which is beyond the scope of this data sheet. Avago Technologies has published documentation showing 3-sigma CTR degradation of no more than 10% over 30 field years of operation for their opto-couplers manufactured with AlGaAs type LEDs running 5mA of input current (IF) at 100% duty cycle, and at 85C ambient temperature. Please refer to the application/design notes from optocoupler vendors such as Avago Technologies, CEL and Vishay, to procure further information on opto-couplers. A typically recommended opto-coupler is the PS2801 from California Eastern Laboratories (CEL). ISOLATION BOUNDARY PRIMARY SIDE VCC SECONDARY SIDE RD OPTOCOUPLER PRIMARY SIDE OF VOLTAGE FEEDBACK LOOP IOPTO_OUT IF OPTO LT8311 8311 F17 RE Figure 17. Typical Opto-Coupler Configuration in a Voltage Feedback Loop 8311f For more information www.linear.com/LT8311 29 LT8311 APPLICATIONS INFORMATION Opto-Coupler Design Guidance An opto-coupler's CTR degradation affects a forward converter's voltage feedback loop in two ways: 1. Large Signal Effect: A drop in CTR means that to sustain the same output current from the opto-coupler, the input current of the opto-coupler will have to increase. The input current of the opto-coupler is sourced by the LT8311's OPTO pin. The opto-feedback loop should be designed such that, at the lowest CTR possible, the LT8311's OPTO pin is not current limited. The maximum current that the LT8311's internal opto-driver can source out of the OPTO pin is 10mA. Design the system so that, nominally, the OPTO pin is sourcing 2mA to 3mA maximum current into the opto-coupler's input. 2. Small Signal Effect: A reduction in CTR by 2x will cause the DC gain and crossover frequency of the forward converter's voltage feedback loop to drop by 2x, assuming all other parameters are constant. Likewise, an increase in CTR by 2x, assuming no change in other parameters, will cause the DC gain and the crossover frequency of the voltage feedback loop to increase by 2x. The voltage feedback loop must be designed ensuring that at CTR(MAX) (maximum CTR of the optocoupler), the crossover frequency of the feedback loop stays well within the Nyquist frequency of the system (= switching frequency/2). A good rule of thumb is to design the voltage feedback loop's crossover at about 1/10 of the switching frequency for an opto-coupler at the nominal value of CTR. As explained earlier, improvements in opto-coupler technology have allowed CTR changes over the operating lifetime of an opto-coupler to become significantly smaller and well controlled. However, the more challenging design aspect of an opto-coupler is the absolute variation in its CTR over a large sample size and operating temperature range. It is this spread in CTR that must be accounted for when designing an opto-coupler based voltage feedback loop. Picking an opto-coupler whose CTR variation is no more than 2x its nominal value, is typically a good starting point (see Table 1 for a list of opto-couplers with small CTR spreads at room temperature). The following guidelines help calculate initial values for the input and output resistors of the opto-coupler (RD and RE, respectively) for a generic application. The final values for RD and RE should be determined after bread-boarding a system. Use Figure 16 as a reference when reading the following guidelines: Step 1: Pick resistors, R1 and R2, that set the inverting gain of the primary-side IC's error amplifier. A typical starting value for R1 would be 22k on the LT3752, and 100k on the LT8310. A typical starting value for R2 would be 33k on the LT3752, and 150k on the LT8310. Step 2: Calculate the maximum voltage required at the emitter of the opto-coupler's output transistor (VX_MAX) to drive the primary-side IC's COMP or VC pin to the voltage needed to command zero inductor current (referred to as VC_LOW in the following equation): R1 R1 VX _ MAX = VREF 1+ - VC _ LOW * R2 R2 VC_LOW is approximately 0.7V for the LT8310, and 1.25V for the LT3752. VREF is 1.6V for the LT8310 and 1.25V for the LT3752. Step 3: Pick a maximum opto-coupler output current (IOPTO_OUT_HIGH) in the range of 1mA to 10mA. A typical choice for IOPTO_OUT_HIGH might be 2.5mA. Now calculate RE to be: RE = VX-MAX IOPTO _ OUT _ HIGH Step 4: Estimate the maximum input current (IF_HIGH) needed to be sourced into opto-coupler by the LT8311's OPTO pin, at the opto-coupler's minimum CTR (CTRMIN): IF _ HIGH = IOPTO _ OUT _ HIGH CTRMIN Ensure that IF_HIGH is well within the 10mA limit that the LT8311's OPTO pin can source. Step 5: Estimate the RD value needed for the OPTO pin to source the IF_HIGH current at the maximum OPTO pin 8311f 30 For more information www.linear.com/LT8311 LT8311 APPLICATIONS INFORMATION voltage (VOPTO(MAX)). The opto-coupler's input LED has a turn-on voltage of 1.2V: RD = VOPTO(MAX) - 1.2V - 0.5V IF _ HIGH The extra 0.5V in the equation is margin to account for the OPTO pin's linear range. The maximum OPTO pin voltage is 6V (minimum guaranteed), when the LT8311's VIN pin is at 8V or higher. At lower VIN pin voltages, VOPTO_MAX is VIN - 1.7V. The previous equations show how RD and RE ought to be calculated for large signal characteristics of an optocoupler-based voltage feedback loop. The final values chosen for RD and RE may need to be tweaked from the values calculated here to achieve a satisfactory compromise between the large and small signal characteristics of the voltage feedback loop. Picking Soft-Start Capacitor (CSS) for Output Soft-Start The Operation section explained how the LT8311's SS pin helps with output soft-start at start-up, with output overshoot control during short-circuit recovery, and to prebias the voltage feedback loop during start-up of the LT8311's opto-control scheme. The soft-start capacitor, CSS, is charged by the LT8311's internally trimmed 10A current source at start-up. Since the FB pin voltage tracks the SS pin voltage when the voltage on SS is below 1.227V, setting the SS pin's slew rate will set the FB pin's slew rate, setting the time taken by the output to come up to its regulation voltage. It is important to recognize that the tracking between the SS pin's slew rate and the FB's pin slew rate is only valid as long as the LT8311's soft-start of output voltage is slower than the primary-side IC's soft-start of output voltage, as explained in the Operation section. By observing this criteria, the following equation applies: VOUT VFB 10A = = t t CSS where CSS is the capacitor from the LT8311's SS pin to GND, VOUT is the output voltage of the forward converter, and VFB is the LT8311's FB pin voltage. In steady state, the SS pin voltage is clamped to a maximum of 2V by an internal clamp. LT8311 SYNCHRONOUS CONTROL FUNDAMENTALS Catch and Forward MOSFET Selection When selecting the secondary-side synchronous MOSFETs, it is important to choose the following parameters carefully to ensure robust operation of the system: maximum drain-source voltage, maximum drain-source current and maximum gate-source voltage. Furthermore, to maximize system efficiency, it is important to lower power dissipation in the MOSFETs by minimizing their on-resistance (RDS(ON)) and gate charge (Qg). Please use the following guidelines to choose appropriate catch and forward MOSFETs for a specific application: 1. Maximum VDS Rating The maximum voltage seen on the drain of the catch MOSFET is a function of the maximum input voltage (VIN(MAX)) of the system, and the transformer turns ratio (NS/NP). N Catch MOSFET VDS(MAX) = V IN(MAX) * S * Margin NP where Margin is a number from 1 to 3 (typically 1.5 to 2), allowing a certain safety margin in the catch MOSFET's VDS(MAX) equation. This will account for voltage spikes associated with the leakage inductance of the transformer's secondary winding. Using a snubber on the drain of the catch MOSFET will minimize leakage inductance spikes and allow Margin to approach the lower end of its range. The maximum voltage seen on the drain of the forward MOSFET is a function of the reset mechanism used on the primary side of the forward converter to reset the transformer's magnetic flux. When using active clamp reset: Forward MOSFET VDS(MAX) 1- VOUT VOUT NS NP where VIN(MIN) is the minimum input voltage of the system, and VOUT is the forward converter's output voltage. Note that this equation for the forward MOSFET's VDS(MAX) assumes that the primary side's active clamp capacitor (CCL) is large enough to be treated as a voltage source. V IN(MIN) * 8311f For more information www.linear.com/LT8311 31 LT8311 APPLICATIONS INFORMATION In reality, the drain voltage of the forward MOSFET will have some "bowing" over and above the voltage calculated here, associated with the energy shuttled between LMAG and CCL during the reset process. For most applications, this bowing can be accounted for by adding a 20% safety margin on the forward MOSFET's VDS(MAX) equation. where VIN(MAX) and VIN(MIN) are the maximum and minimum input voltages of the forward converter. When using resonant reset: ICAT _ RMS = Forward MOSFET VDS(MAX) fSW VOUT * 2 * LMAG * CRST where fSW is the forward converter's switching frequency, LMAG is the magnetizing inductance of the transformer's primary winding, and CRST is the resonant reset capacitor used on the primary side. Unlike the catch MOSFET, the VDS(MAX) equation of the forward MOSFET typically does not need to account for leakage inductance voltage spikes. This is because the turnon and turn-off events of the forward MOSFET, typically, do not involve the forward MOSFET's drain having to dissipate large amounts of stored leakage inductance energy. 2. Maximum IDS Rating Most power MOSFET data sheets have a rating for continuous-drain current, and pulse-drain current. Continuous-drain current is the RMS drain current of the catch and forward MOSFET, which is a function of the inductor current, and the duty cycle at which the forward converter is operating. Pulse-drain current is the instantaneous maximum drain current seen by the MOSFETs, and is typically the peak of the inductor current waveform. Prior to calculating the maximum continuous-drain current, it is useful to calculate the minimum, maximum and average duty cycles of the forward converter: DMIN = DMAX = DAVG = 32 VOUT N V IN(MAX) * S NP VOUT N V IN(MIN) * S NP DMAX + DMIN 2 The catch MOSFET's maximum continuous drain current, ICAT_RMS, can be calculated as: (1- DMIN ) * ILOAD(MAX) 2 + IRIPP(P-P) 2 12 where DMIN is the minimum duty cycle of the forward converter, ILOAD(MAX) is the maximum output load current of the forward converter, and IRIPP(P-P) is the peak-topeak ripple current in the output inductor. IRIPP(P-P) is calculated as follows: 1- DAVG IRIPP(P-P) = VOUT * fSW * LOUT where DAVG is the average duty cycle of the forward converter, fSW is the converter's switching frequency, and LOUT is the output inductance value. The forward MOSFET's maximum continuous-drain current (IFWD_RMS) is: IFWD _ RMS = DMAX 2 2 IRIPP(P-P) * ILOAD(MAX) + 12 Both, the forward and catch MOSFET should have a peak pulse current rating that is higher than the highest possible peak of the inductor current. This highest possible peak occurs at the maximum load current, and is equal to: ILOAD(MAX) + IRIPP(P-P) 2 3. Maximum VGS Rating As explained earlier in the INTVCC Bias Supply section, INTVCC is regulated internally to 7V by the LT8311. By extension, the catch and forward MOSFET gates can be driven as high as 7V when using the LT8311's internal LDO to regulate INTVCC. For applications using the LT8311's internal LDO, picking a maximum VGS greater than 10V should suffice. 8311f For more information www.linear.com/LT8311 LT8311 APPLICATIONS INFORMATION Alternatively, the INTVCC pin can be overdriven externally up to 16V. For such applications, picking MOSFETs with a maximum VGS of 20V should suffice. 4. Calculating MOSFET Losses Due to RDS(ON) The conduction/ohmic loss associated with the catch and forward MOSFET is a function of the MOSFET's RMS current and its on-resistance. For the vast majority of forward converter applications, which typically have high maximum load currents on the output (5A or higher), minimizing losses associated with the MOSFET's RDS(ON) will be far more critical than minimizing losses associated with the MOSFET's gate charge. Catch MOSFET Ohmic Loss = (ICAT_RMS)2 * RCAT where RCAT is the on-resistance (RDS(ON)) of the catch MOSFET. Forward MOSFET Ohmic Loss = (IFWD_RMS)2 * RFWD where RFWD is the on-resistance (RDS(ON)) of the forward MOSFET. 5. Calculating Qg Based Loss There are two aspects to the gate charge (Qg) based loss associated with the secondary synchronous MOSFETs: A. Qg Based MOSFET Switching Loss: The catch MOSFET's turn-on and turn-off timings, regardless of preactive or SYNC mode, are ZVS (zero voltage switching) events. The catch MOSFET turns on after the inductor current is already flowing through its body diode. Similarly, when the catch MOSFET turns off, the inductor current subsequently flows through its body diode. As a result, the voltage across the drainsource terminals of the catch MOSFET is small during switching events, resulting in the catch MOSFET having insignificant switching loss. The forward MOSFET's turn-on and turn-off timings, regardless of preactive or SYNC mode, are ZVS (zero voltage switching) and ZCS (zero current switching) events, respectively. The forward MOSFET turns on after transformer reset is complete. Transformer reset completion is marked by the transformer's magnetizing current flowing through the forward MOSFET's body diode, which allows the forward MOSFET to turn on with a small drain-to-source voltage across it. Similarly, the forward MOSFET typically turns off after the primaryside MOSFET has turned off. When the primary-side MOSFET turns off, the only current flowing through the forward MOSFET is the transformer magnetizing current, which for all intents and purposes, can be assumed to be zero. Consequently, the forward MOSFET has insignificant switching losses. B. Qg Based Converter Power Loss: As explained earlier in the INTVCC Bias Supply section, there is a power loss incurred in turning on/off the catch and forward MOSFETs, associated with supplying gate charge (Qg) to the gates of these MOSFETs. This charge is supplied either by the supply voltage connected to the LT8311's VIN pin, when using the internal LDO to regulate INTVCC, or by the supply voltage connected to the LT8311's INTVCC pin, when driving the INTVCC pin externally. In either case, the total loss associated with supplying the gate charge is: Power Loss = VSUPP * (QgCAT + QgFWD) * fSW where VSUPP is the supply voltage connected to the LT8311's VIN pin when INTVCC is internally regulated. Alternatively VSUPP is the supply voltage connected to the LT8311's INTVCC pin when INTVCC is externally driven. QgCAT and QgFWD is the gate charge (Qg) of the catch and forward MOSFETs, respectively. fSW is the forward converter's switching frequency. 8311f For more information www.linear.com/LT8311 33 LT8311 APPLICATIONS INFORMATION Setting RTIMER in Preactive Mode In preactive mode, the TIMER pin resistor, RTIMER, programs the maximum period that can elapse between two CSW rising edges before a timeout period is triggered. Timeout allows the LT8311 to stop all synchronous activity in the event that the primary-side IC stops switching. Since CSW rising edges represent primary-side switching activity, timeout of CSW rising edges is interpreted as stoppage of switching--at which point the LT8311 ceases all secondary-side synchronous switching, and starts its evaluation period. Refer to the Operation section for details on the evaluation period. Secondary-side switching resumes when all conditions within the evaluation period are satisfied. Timeout also ensures that switching activity within preactive mode occurs at a frequency that is within preactive mode's operating frequency range. As shown in Figure 18, every time the CSW pin voltage is detected to rise past 1.2V from a voltage level below -150mV, the LT8311 resets its internal timeout signal. The gate of the catch MOSFET, CG turns on (after some propagation delay) when CSW is detected to fall below -150mV. Upon CG going high, the catch MOSFET turns on and pulls its drain voltage (CSW) close to its source voltage, which is tied to GND. CG turns off predictively in CCM before an anticipated CSW rising edge. If a CSW rising edge (rising from below -150mV to above 1.2V) does not come along in time to reset the timeout signal, the signal eventually charges up to voltage VREF_TIMEOUT and triggers an internal timeout condition. Consequently, the LT8311 shuts down all synchronous conduction and starts the evaluation period. The evaluation period ends only when the four conditions listed in the Operation section, including the timely reset of the internal timeout signal, are satisfied for three consecutive CSW rising edges. Upon completion of the evaluation period, the LT8311 restarts synchronous control. VREF_TIMEOUT LT8311 INTERNAL TIMEOUT SIGNAL TIMEOUT CSW (PREACTIVE MODE) 1.2V -150mV CG PREDICTIVE TURN-OFF CG TIMEOUT RESETS ONLY WHEN CSW RISES PAST 1.2V, PRECEDED BY FALLING BELOW -150mV EVALUATION PERIOD 0V CG TURNS ON WHEN CSW < -150mV TIME 8311 F18 Figure 18. If Timeout Is Triggered in Preactive Mode, LT8311 Shuts Down All Synchronous Conduction and Starts the Evaluation Period (Note: CSW's ringing waveform is caused by the inductor current getting to 0A.) 8311f 34 For more information www.linear.com/LT8311 LT8311 APPLICATIONS INFORMATION The TIMER resistor is typically picked to set a timeout period that is 20% higher than the forward converter's nominal switching period. Timeout = 1.20 fSW where fSW is converter switching frequency in Hz. Once a timeout period is calculated, the TIMER pin resistor, RTIMER, can be calculated as follows: RTIMER (k) ~ 22.1E6 * Timeout where Timeout has units of seconds. The relationship between RTIMER and timeout is not perfectly linear. Table 1 shows RTIMER values (nearest 1%) for a range of typical forward converter switching frequencies: Table 1. RTIMER 1% Resistor Values for Different Forward Converter Switching Frequencies SWITCHING FREQUENCY (kHz) TIMEOUT (s) = 1.2/ fSW RTIMER (k) 100 12 267 150 8 178 200 6 133 250 4.8 107 300 4 88.7 400 3 66.5 500 2.4 53.6 Setting the timeout period at 1.2 * Switching Period will keep synchronous conduction shut off through frequency foldback in preactive mode, until the switching frequency approaches 80% of its final value. For 100kHz switching applications, this means that the LT8311 is ready for synchronous conduction in preactive mode, at 80kHz. Although 80kHz is outside the LT8311's data sheet specifications for preactive mode operating frequency range, the IC is designed to operate down to 80kHz to ride through such a frequency foldback event. Timeout may also shut off synchronous conduction during CSW pulse-skipping events at light output load currents. Setting RTIMER in SYNC Mode In SYNC mode, the functionality of the timeout period is similar to preactive mode, except that the resetting of the LT8311's internal timeout signal happens every time the SYNC pin voltage falls below -1.2V. The goal of the timeout function in SYNC mode is primarily to limit the catch MOSFET on-time in the event that the catch MOSFET stays on too long and conducts an unsafe level of reverse-output inductor current (current flows from the output capacitor back towards the drain of the catch MOSFET). Refer to the section, "Configuring CSP/CSN Inputs of the Current Sense Comparators in SYNC Mode," for further information on what constitutes an unsafe level of reverse-output inductor current. In SYNC mode, set the timeout period to be 20% longer than the longest switching period of the primary-side IC. Typically, the longest switching period of the primaryside IC corresponds to the smallest frequency foldback frequency (fSW_SMALLEST): Timeout = 1.2 fSW _ SMALLEST Once a timeout period is calculated, the TIMER pin resistor, RTIMER, can be calculated as follows: RTIMER(k) ~ 22.1E6 * Timeout where Timeout has units of seconds, and fSW_SMALLEST is in units of Hz. Configuring CSP/CSN Inputs of Current Sense Comparator in Preactive Mode The differential input current sense comparator in the LT8311 is used to provide the IC with information about the current in the catch MOSFET. Connect the CSP and CSN pins, through series resistors, to the drain and source of the catch MOSFET (MCG), to allow the LT8311 to sense the drain-source voltage of MCG, and make inferences about its current. Alternatively, CSP and CSN can be tied, through series resistors, across a sense resistor which is placed from the source of MCG to ground. As explained earlier in the Operation section, the CSP and CSN pins should be configured, in preactive mode, to trip at zero current in the catch MOSFET. Since the current comparator internally trips at 66mV, and the CSP pin sources 40A, 8311f For more information www.linear.com/LT8311 35 LT8311 APPLICATIONS INFORMATION placing 1%, 1.65k resistors in series with CSP and CSN should allow the LT8311 to trip with approximately zero volts across the catch MOSFET. Note that the current comparator has a propagation delay of 100ns nominally, so the time taken from the current comparator getting tripped to the catch MOSFET turning off is about 100ns. During this 100ns, the current in the output inductor can reverse and flow from the drain-to-source of the catch MOSFET. If negative current flow in MCG is not desired, the CSP pin series resistor can be chosen to trip at a positive value of source-to-drain catch MOSFET current. The following equation allows calculation of the resistor (RCSP) to be placed in series with the CSP pin for a desired value of catch MOSFET trip current (ITRIP): RCSP = 66mV - I TRIP * RSNS 40A where RSNS is the RDS(ON) of the catch MOSFET when the CSP and CSN pins are connected directly across the drainsource terminals of the catch MOSFET. Alternatively, RSNS is the sense resistor in the source of the catch MOSFET if the CSP/CSN pins are connected directly across the sense resistor. Once the resistor in series with the CSP pin (RCSP) is decided, place an identical resistor in series with the CSN pin. Configuring CSP/CSN Inputs of the Current Sense Comparator in SYNC Mode The LT8311 is typically operated in SYNC mode when the forward converter needs to be operated in FCM (forced continuous mode). In SYNC mode, the LT8311 receives synchronous control signals on its SYNC pin, through a pulse transformer, from the primary-side IC's SOUT pin. Connecting the LT8311's CSP/CSN pins across the catch MOSFET's drain and source, in SYNC mode, is done to protect the catch MOSFET from conducting too large a reverse inductor current at light load. The following guidelines offered (Steps 1 to 5) may be used to determine an appropriate catch MOSFET reverse current trip point (VTRIP): Step 1: Determine the worst-case negative inductor current value during regular FCM operation, which will likely happen at the smallest frequency foldback frequency, highest VIN, and at 0A load. An easy way to determine this is to run the forward converter with the LT8311 working in SYNC mode and keeping the CSP/CSN pins shorted to GND. Observing the inductor current waveform on an oscilloscope at start-up, with VIN at its maximum value, and the load at 0A, can quickly give the user an idea of the worst-case negative inductor current value (ICATCH_FET) during regular start-up operation. This will set a lower bound on the CSP/CSN trip point (VTRIP minimum): VTRIP Minimum = |ICATCH_FET| * RDS(ON) where RDS(ON) is the on-resistance of the catch MOSFET, and ICATCH_FET is the worst-case magnitude of negative inductor current (current flowing from drain to source of catch MOSFET) during FCM operation at startup. Step 2: Pick a trip point (VTRIP) that allows some margin from the value calculated in Step 1. Typical margin might be 20%, thereby setting a trip point of: VTRIP = 1.2 * VTRIP Minimum Step 3: Determine the selected catch MOSFET's single pulse avalanche energy rating (EAS in mJ) from the MOSFET's data sheet and its drain-source break down voltage (VBR(DSS) in V). Step 4: Make sure that the chosen CSP/CSN trip voltage does not allow so much negative current in the catch MOSFET, such that when the catch MOSFET turns off, its avalanche energy rating (based on the following equation) is violated: VTRIP (in Volts) < RDS(ON) * (1.3 * VBR(DSS) - VOUT ) 2 * E AS * (1.3 * VBR(DSS) * LOUT ) where, EAS (Joules) = Catch MOSFET's single-pulse avalanche energy rating. VBR(DSS) (V) = Catch MOSFET's drain-source break down voltage rating. 8311f 36 For more information www.linear.com/LT8311 LT8311 APPLICATIONS INFORMATION RDS(ON) () = Catch MOSFET's on-resistance rating from the MOSFET's data sheet. VOUT (V) = Forward converter's output voltage in steadystate. LOUT (H) = Output inductor. If the VTRIP voltage is too large, causing the catch MOSFET's avalanche energy rating to be violated, then go back to Steps 1 and 2, or pick a different MOSFET, until the avalanche energy experienced by the MOSFET in the application is within its data sheet specified SOA. Step 5: Upon selecting the appropriate trip point, the series resistors, RCSP and RCSN, may be determined based on the following equation: RCSP = RCSN = 66mV - VTRIP 40A Connect RCSP between the CSP pin and the catch MOSFET's drain, and RCSN between the CSN pin and the catch MOSFET's source. PREACTIVE MODE SYNCHRONOUS CONTROL Preactive Mode General Guidelines The following guidelines are meant to summarize the connections and operating conditions typically needed to set up the LT8311's synchronous control in preactive mode. While these guidelines are meant to serve as a starting point, they are not a substitute for bench evaluation. Ultimately, each application that uses the LT8311's preactive mode scheme must be evaluated for its specific requirements, and the IC must be configured accordingly. 1. Bias up VIN and INTVCC as per data sheet recommendations. 2. Place a minimum of 2.2F ceramic capacitor from the VIN pin to GND. 3. Place a minimum of 4.7F ceramic capacitor from the INTVCC pin to GND. 4. Tie the PMODE and SYNC pins to 0V. 5. Configure RTIMER to set a timeout period that is 20% higher than the steady-state switching period of the forward converter. 6. Connect the CSW and FSW pins, through 2k ceramic resistors, to the drains of the catch and forward MOSFET, respectively. Keep the connection as short in length as possible. 7. Connect the CSP and CSN pins, each through a 1.65k resistor, directly across the drain-source terminals of the catch MOSFET for VDS sensing. A small 10pF filter capacitor may be required across the CSP and CSN pins to filter out external noise that couples in. 8. Connect CG and FG to the gates of the catch and forward MOSFET, respectively, with connections that are as short as possible. Once synchronous control is up and running: 9. Ensure that the voltage at the CSW and FSW pins does not exceed the abs max rating of 150V. If the CSW or FSW pin voltage exceeds 150V, you may need to use a RC snubber on the drain of the catch and/or the forward MOSFET. 10.If the catch MOSFET current trip point is causing the inductor current to reverse (flowing from output back to the drain of the catch MOSFET) at light loads, reconfigure the CSP/CSN trip point to trip at a slightly positive value of source-to-drain current in the catch MOSFET. This typically involves increasing the CSP and CSN series resistors to a value greater than 1.65k. 11.If the catch MOSFET's current trip point does not seem consistent, and the catch MOSFET's turn-off edge seems to show jitter at the trip current, the filter capacitor across the CSP and CSN pins may need to be adjusted. Note that typically, the FB pin will be connected through a resistor divider network to the output voltage, when using the LT8311 as part of a voltage feedback loop. 8311f For more information www.linear.com/LT8311 37 LT8311 APPLICATIONS INFORMATION SYNC MODE SYNCHRONOUS CONTROL constraint, the equation below sets a limit on the minimum RSYNC * CSYNC product required: 50ns RSYNC * CSYNC 2V -1* n VMAX where VMAX is the maximum SOUT voltage, as shown in Figure 19. Picking the Pulse Transformer and High Pass Filter In SYNC Mode, the LT8311 determines the turn-on/off timings of the catch and forward MOSFETs based on voltage signals on its SYNC pin. Figure 7 in the Operation section shows a typical circuit used to communicate synchronous control signals from the primary-side IC's SOUT pin to the LT8311's SYNC pin. This circuit utilizes a pulse transformer (T2 in Figure 7) to provide isolation between the primary and secondary sides, and a high pass filter (RSYNC and CSYNC). CSYNC blocks DC signals from being applied directly to T2. Eliminating the DC component of the SOUT signal, through the highpass filter (RSYNC and CSYNC), allows the SYNC pin signal to go positive or negative at the rising and falling edges of SOUT, as shown in Figure 19. Positive and negative signals of equal magnitudes and duration allow equal positive and negative volt-seconds to be maintained on transformer T2, preventing any net magnetizing current build-up. 2. RSYNC must be small enough to ensure that the SYNC signal is sufficiently damped. An underdamped SYNC signal can cause ringing large enough to cause false triggering of the SYNC detection comparators, which may lead to improper secondary-synchronous control. The equation used to calculate RSYNC for optimal damping is given by: 1 Lm * RSYNC CSYNC 2 * where is the damping factor and should typically be chosen to be about 1. Lm is the magnetizing inductance of the pulse transformer's primary winding. Appropriate values of RSYNC and CSYNC must be chosen to satisfy all of the following criteria: Choosing Lm to be larger allows the damping factor to increase, so it would be wise to choose a pulse transformer with a larger primary winding inductance to increase the damping of the SYNC signal. 1. The RSYNC * CSYNC time constant must be large enough to allow a sufficiently long pulse width to be generated on the SYNC pin with sufficient overdrive voltage. This is shown in Figure 19 where t1 must be at least 50ns at a SYNC voltage of 2V (or greater over drive) to trip the SYNC comparators. Using this Smaller RSYNC values also reduce the sensitivity of the highpass filter to stray signals (parasitic magnetic fields) that may couple in. VMAX SOUT 0V VMAX 2V SYNC t1 0V t1 -2V -VMAX TIME 8311 F19 Figure 19. Positive and Negative SYNC Edges Are Generated on the Rising and Falling Edges of SOUT, Respectively. The LT8311 Requires Pulse Width Time, t1, to Be at Least 50ns (Typical) with the SYNC Pin Voltage at 2V (or Greater Overdrive) to Trigger the Internal SYNC Detect Comparators. 8311f 38 For more information www.linear.com/LT8311 LT8311 APPLICATIONS INFORMATION 3. RSYNC must be large enough to limit the amount of source/sink current required each time a positive or negative SYNC pin voltage signal is generated. The SOUT pin's gate drivers offer limited source current capability; RSYNC must be large enough to ensure that this constraint in current-drive is not violated. For instance, the LT3752's SOUT drivers are rated for a maximum current of about 100mA. This results in: V RSYNC MAX 100mA VMAX is the SOUT gate driver high voltage, which is typically about 8V to 12V for the LT3752. The following steps can be used as guidelines to calculate RSYNC and CSYNC values: Step 1: Choose Pulse Transformer. A typically recommended choice is the PE-68386NL from Pulse Electronics. Step 2: Determine the primary-side IC's maximum SOUT signal magnitude, VMAX (see Figure 19). This sets the maximum magnitude of the signal on the LT8311's SYNC pin. Step 3: Guess a capacitance value for CSYNC. A good starting value might be between 220pF and 1nF. Step 4: Pick RSYNC based on constraint shown in the following equation: 1 * 2 capability is about 100mA and LT8310's maximum current capability is about 300mA). It is recommended to design for an IMAX that is lower than the maximum recommended source current specified, to allow for design margin over process and temperature. If the RSYNC calculation in Step 4 yields an unreasonable resistance value, go back to steps 1 to 3, and change either Lm, VMAX, or CSYNC. Recalculate RSYNC in Step 4 until all criteria are satisfied. Design Example In a LT3752-LT8311 forward converter design, pulse transformer PE-68386NL is chosen for communication of LT3752 SOUT signals, through a highpass filter, to the LT8311's SYNC pin. Step 1: This transformer has a magnetizing inductance of Lm = 785H. Step 2: LT3752's VMAX = 12V. Step 3: Choose CSYNC = 220pF Step 4: Designing for IMAX = 70mA, Lm = 785H, CSYNC = 220pF, VMAX = 12V, results in the following calculation for RSYNC: 944 RSYNC Max {127, 171} Conclusion Lm C RSYNC MAX SYNC 50ns , VMAX CSYNC * -1 * IN(2V / VMAX ) IMAX In this example, RSYNC = 560 is chosen along with CSYNC = 220pF as the highpass filter to be used along with pulse transformer, PE-68386NL to communicate the LT3752's SOUT signals to the LT8311's SYNC pin. where IMAX is the maximum current source/sink capability of the primary-side IC's SOUT pin (LT3752's maximum 8311f For more information www.linear.com/LT8311 39 LT8311 TYPICAL APPLICATIONS 18V to 72V, 12V/8A Active Clamp Isolated Forward Converter L1 6.8H 4:4 T1 VIN 18V to 72V C1 4.7F x3 * R1 100k VIN UVLO_VSEC C9 100nF R2 5.9k R3 1.82k C10 2.2F 100V OVLO * D2 C11 100nF R16, 2k M2 AOUT R14 10k LT3753 R18, 1.78k M1 R4 71.5k OUT IVSEC 240kHz RT R5 SYNC 31.6k SOUT ISENSEP OC TAS TOS TBLNK GND SS1 R6 49.9k R7 34k R13, 2k R12 6m INTVCC COMP SS2 FB C3 0.47F C4 1F R8 100k C7 1F R9 100k R20, 1.5k C12 15nF C6 R11 4.7F 100 C5 10pF CSW + C20 470F CSP VIN CSN PGOOD OPTO INTVCC COMP SYNC PMODE SS TIMER GND R23 100k VOUT C15 4.7F C16 2.2F R22 154k R21 2.94k PS2801-1 VOUT 12V/8A R26 11.3k LT8311 CG R19, 1.78k ISENSEN TAO M4 D3 FB FG R17, 2k D1 C17 2.2nF R25 100k FSW M3 C18 68pF C19 22F x2 R24 20k C14 1F 8311 TA02 1k T1: T2: L1: M1: M2: M3: M4: D2: D3: 2.2nF CHAMPS B45R2-0404.04 CEL PS2801 CHAMPS PQR2050-08 INFINEON BSC077N12NS3 IR IRF6217PBF FAIRCHILD SEMI. FDMS86101DC INFINEON BSC077N12NS3 CENTRAL SEMI. CMMR1U-02 DIODES INC. SBRIU150 Efficiency and Power Loss at VIN = 48V 96 14 VIN = 48V 94 12 92 10 90 8 POWER LOSS 88 6 86 4 84 2 82 1 3 5 LOAD CURRENT (A) 7 9 POWER LOSS (W) EFFICIENCY (%) EFFICIENCY 0 8311 TA02b 8311f 40 For more information www.linear.com/LT8311 LT8311 TYPICAL APPLICATIONS 18V to 72V, 12V/12.5A, 150W Active Clamp Isolated Forward Converter VAUX UVLO_VSEC ISENSEN LT3752 SOUT INTVCC R5 22.6k R4 49.9k R7 34k R6 7.32k R9 31.6k R8 71.5k C3 22nF C2 0.33F COMP FB HCOMP SS2 SS1 RT TBLNK IVSEC GND TAS TOS R10 2.8k R24 C4 100k 22nF C13 22F 16V x2 HFB R23 100k R21 100 BSC077N12NS3 M1 VAUX R14 2k R15 0.006 * R13 560 INTVCC R11 10k R12 1.1k R25 100 C5 4.7F C16 1F R26 1k VIN R28 3.16k PS2801-1 R30 100k GND PGOOD SYNC T3 * C6 220pF C11 2.2F R27 100k R22 100 VAUX C12 4.7F LT8311 C17 220nF R20 499k FB C28 68pF R31 11.3k C18 68pF R29 13.7k C19 4.7nF 8311 TA03a 2.2nF T1: CHAMPS G45R2_0404.04D T2: BH ELECTRONICS L00-3250 T3: PULSE PE-68386NL L1: CHAMPS G45AH2-0404-D4 D1, D2, D3: BAS516 D4: CENTRAL SEMI CMMR1U-02 Efficiency vs Load Current 96 94 EFFICIENCY (%) R3 1.82k OC ISENSEP OVLO M4 M3 + VOUT 12V 12.5A D1 OUT SYNC TAO R2 5.9k AOUT M2 C14 470F 16V C24 2.2nF 250V BSC077N12NS3 FDMS86101 Si2325DS R16 10k HOUT HISENSE VIN R1 100k R18 0.15 D4 C8 15nF C7 100nF R38 20k CSN CSP ZVN4525E6 M5 * COMP * R17 499 * C10 2.2F SS D3 CG * CSW T2 INTVCC PMODE TIMER * FG D2 C9 2.2F L1 6.8H FSW INTVCC C1 4.7F 100V x3 T1 4:4 OPTO VIN 18V TO 72V 92 90 24VIN 48VIN 72VIN 88 86 0 3 9 6 LOAD CURRENT (A) 12 15 8311 TA03b 8311f For more information www.linear.com/LT8311 41 LT8311 TYPICAL APPLICATIONS 18V to 72V, 12V/12.5A, 150W No-Opto, Active Clamp Isolated Forward Converter VAUX VIN R1 100k R16 10k AOUT LT3752 OVLO SOUT INTVCC R5 22.6k R4 49.9k R7 34k R6 7.32k R9 31.6k R8 60.4k C3 22nF C2 0.33F FB HCOMP SS2 SS1 RT TBLNK IVSEC TAS TOS TAO GND R10 2.8k C4 22nF COMP R3 1.82k ISENSEN HFB R21 100 BSC077N12NS3 M1 V OUT UVLO_VSEC R2 5.9k M4 M3 C14 470F 16V + C13 22F 16V x2 D1 OC ISENSEP SYNC C24 2.2nF 250V BSC077N12NS3 FDMS86101 Si2325DS M2 R18 0.15 HOUT HISENSE R38 20k D4 C8 15nF C7 100nF M5 ZVN4525E6 * AUX R14 2k R15 0.006 * C6 220pF R11 10k R12 1.1k C11 2.2F R13 560 LT8311 FB GND PGOOD SYNC T3 * VIN R22 100 CSN CSP * R17 499 * C10 2.2F VOUT 12V 12.5A COMP D3 SS * CG T2 CSW * INTVCC PMODE TIMER D2 C9 2.2F FG INTVCC L1 6.8H FSW C1 4.7F 100V x3 T1 4:4 OPTO VIN 18V TO 72V VAUX INTVCC C12 4.7F C5 4.7F R20 499k 2.2nF 8311 TA04a T1: CHAMPS G45R2_0404.04D T2: BH ELECTRONICS L00-3250 T3: PULSE PE-68386NL L1: CHAMPS G45AH2-0404-D4 D1, D2, D3: BAS516 D4: CENTRAL SEMI CMMR1U-02 VOUT vs Load Current (No-Opto) Efficiency vs Load Current 14.0 96 13.5 94 EFFICIENCY (%) 13.0 VOUT (V) 12.5 12.0 11.5 VIN = 70V VIN = 60V VIN = 48V VIN = 36V VIN = 20V 11.0 10.5 10.0 0 2 6 8 4 LOAD CURRENT (A) 10 92 90 24VIN 48VIN 72VIN 88 86 12 8311 TA04b 0 3 9 6 LOAD CURRENT (A) 12 15 8311 TA04c 8311f 42 For more information www.linear.com/LT8311 LT8311 TYPICAL APPLICATIONS 150V to 400V, 12V/16.7A, 200W Active Clamp Isolated Forward Converter T1 31:5 IPD60R1K4C6 R14 2k ISENSEN LT3752-1 R7 100k R6 13k R9 78.7k R8 124k T1: CHAMPS LT80R2-12AC-3124005 T2: WURTH 750817020 T3: PULSE PE-68386NL L1: COILCRAFT AGP2923-153 D1: CENTRAL SEMI CMR1U-10 D2, D3, D5: BAS516 D4: CENTRAL SEMI CMMR1U-02 COMP FB HCOMP SS2 SS1 HFB R12 806 R10 22k C4 3.3nF R24 22k * R13 560 R23 22k R28 3.16k R25 C5 100 4.7F PS2801-1 C16 1F R26 1.2k C12 4.7F R30 100k C28 68pF FB LT8311 VAUX C13 33F 16V x4 R22 100 C27 120pF GND + VOUT 12V 16.7A C17 1F R20 432k R31 11.3k C18 100pF R29 5.11k C19 22nF 8311 TA05a 2.2nF Efficiency vs Load Current 96 95 94 93 EFFICIENCY (%) R5 40.2k R4 95.3k C3 0.22F C2 0.47F * VIN PGOOD SYNC T3 INTVCC R11 10k C11 2.2F R27 100k R15 0.022 C6 220pF SOUT INTVCC GND R21 100 IPD65R25OC6 M1 VAUX UVLO_VSEC OVLO M3 C14 330F 16V C24 10nF 250V R38 0.002 CSP C21 0.22F OC ISENSEP SYNC M4 RJK0653DPB x2 M2 OUT R38 10k D4 COMP AOUT FDMS86200 x3 CSN R18 0.15 HISENSE TBLNK IVSEC R3 2.94k HOUT VIN VOUT ANODE CATHODE VEE * C8 47nF 630V D1 VCC * SS * R17 499 R19 402 VAUX R16 4.2 C15 C10 INTVCC 10nF 4.7F 630V ACPL-W346 D3 M5 BSP300 TAS TOS R2 5.76k * L1 15H INTVCC PMODE TIMER D5 TAO R1 499k T2 C9 10F C20 10F R34 499k * FG FSW CSW CG R36 374k D2 OPTO INTVCC R35 374k C1 2.2F 630V RT VIN 150V TO 400V 92 91 90 89 88 VIN = 150V VIN = 250V VIN = 350V VIN = 400V 87 86 85 0 2.5 7.5 10 12.5 5 LOAD CURRENT (A) 15 17.5 8311 TA05b 8311f For more information www.linear.com/LT8311 43 LT8311 TYPICAL APPLICATIONS 150V to 400V, 12V/16.7A, 200W No-Opto, Active Clamp Isolated Forward Converter T1 31:5 C21 0.22F OC ISENSEP SYNC UVLO_VSEC ISENSEN LT3752-1 OVLO R7 100k R6 13k R9 78.7k R8 107k C3 0.22F C2 0.47F FB HCOMP SS2 SS1 RT TBLNK IVSEC TAS TOS TAO R5 40.2k R4 95.3k R10 22k C4 3.3nF R21 100 IPD65R25OC6 M1 VAUX R14 2k R15 0.022 * C6 220pF SOUT INTVCC GND M3 IPD60R1K4C6 OUT C11 2.2F VIN R13 560 R12 806 C13 33F 16V x4 R22 100 C27 120pF LT8311 FB VAUX INTVCC R11 10k HFB + GND PGOOD SYNC T3 * C24 10nF 250V R38 0.002 C14 330F 16V CSP M2 CSN AOUT R38 10k D4 M4 RJK0653DPB x2 CG HOUT HISENSE VIN C8 47nF 630V FDMS86200 x3 CSW R18 0.15 * VOUT 12V 16.7A COMP VOUT ANODE CATHODE VEE * FG R17 499 D1 VCC M5 BSP300 R19 402 SS R3 2.94k VAUX R16 4.2 C15 C10 INTVCC 10nF 4.7F 630V ACPL-W346 D3 L1 15H INTVCC PMODE TIMER R2 5.76k * FSW R1 499k T2 * C20 10F R34 499k * C9 10F D5 R36 374k D2 OPTO INTVCC R35 374k C1 2.2F 630V COMP VIN 150V TO 400V C12 4.7F C5 4.7F R20 432k 8311 TA06a 2.2nF T1: CHAMPS LT80R2-12AC-3124005 T2: WURTH 750817020 T3: PULSE PE-68386NL L1: COILCRAFT AGP2923-153 D1: CENTRAL SEMI CMR1U-10 D2, D3, D5: BAS516 D4: CENTRAL SEMI CMMR1U-02 VOUT vs Load Current (No-Opto) Efficiency vs Load Current 96 14.0 95 13.5 94 93 EFFICIENCY (%) VOUT (V) 13.0 12.5 12.0 11.5 11.0 10.0 0 2 4 6 8 10 12 14 LOAD CURRENT (A) 16 91 90 89 88 VIN = 150V VIN = 250V VIN = 350V VIN = 400V 10.5 92 VIN = 150V VIN = 250V VIN = 350V VIN = 400V 87 86 85 18 8311 TA06b 0 2.5 7.5 10 12.5 5 LOAD CURRENT (A) 15 17.5 8311 TA06c 8311f 44 For more information www.linear.com/LT8311 LT8311 TYPICAL APPLICATIONS 150V to 400V, 12V/16.7A, 200W, Active Clamp Isolated Forward Converter (Using Gate Drive Transformer for High Side Active Clamp) T1 31:5 R14 2k ISENSEN LT3752-1 R9 78.7k R8 124k T1: CHAMPS LT80R2-12AC-3124005 T2: WURTH 750817020 T3: PULSE PE-68386NL T4: ICE GT05-111-100 L1: COILCRAFT AGP2923-153 D1: CENTRAL SEMI CMR1U-10 D2, D3, D5: BAS516 D4: CENTRAL SEMI CMMR1U-02 C4 3.3nF COMP FB SS2 SS1 HCOMP R10 22k * R11 10k R12 806k R23 22k * R13 560 R28 3.16k R25 C5 100 4.7F LT8311 PS2801-1 C16 1F VAUX C12 4.7F C17 1F R20 432k C13 33F 16V x4 R30 100k GND PGOOD SYNC T3 + VOUT 12V 16.7A R22 100 C27 120pF CSP VIN CG C11 2.2F R27 100k INTVCC HFB R24 22k C28 68pF FB R31 11.3k C18 100pF R29 5.11k C19 22nF 8311 TA07 R26 1.2k 2.2nF Efficiency vs Load Current 96 95 94 93 EFFICIENCY (%) R7 100k R6 13k R15 0.022 C6 220pF SOUT INTVCC GND R5 40.2k R4 95.3k R21 100 IPD65R25OC6 M1 VAUX UVLO_VSEC C3 0.22F C2 0.47F M3 COMP C21 470pF OUT C14 330F 16V C24 10nF 250V R38 0.002 IPD60R1K4C6 AOUT R38 10k D4 M4 RJK0653DPB x2 D1 OC ISENSEP OVLO FDMS86200 x3 CSN R16 10k R37 100 * SS * SYNC TBLNK IVSEC R3 2.94k C23 3.3nF T4 * R18 0.15 HOUT HISENSE TAS TOS R2 5.76k R17 499 VIN TAO R1 499k C22 220nF M5 BSP300 * CSW * R19 402 C8 47nF 630V M2 C15 10nF 630V VAUX C10 4.7F * L1 15H INTVCC PMODE TIMER C9 10F C20 10F R34 499k T2 FG R36 374k * FSW D5 D2 OPTO INTVCC R35 374k C1 2.2F 630V D3 RT VIN 150V TO 400V 92 91 90 89 88 VIN = 150V VIN = 250V VIN = 350V VIN = 400V 87 86 85 0 2.5 7.5 10 12.5 5 LOAD CURRENT (A) 15 17.5 8311 TA07b 8311f For more information www.linear.com/LT8311 45 LT8311 TYPICAL APPLICATIONS 75V to 150V, 24V/14A 340W Active Clamp Isolated Forward Converter (Using Gate Drive Transformer for High Side Active Clamp) T1 10:6 D1 R16 10k R37 100 C21 470pF OC ISENSEP UVLO_VSEC ISENSEN LT3752-1 R7 80.1k R6 10k R9 52.3k R8 82.5k T1: CHAMPS LT80R2-12AC-1006 T2: WURTH 750817020 T3: PULSE PE-68386NL T4: ICE GT05-111-100 L1: COILCRAFT AGP2923-153 D1: CENTRAL SEMI CMR1U-10 D2, D3, D5: BAS516 D4: CENTRAL SEMI CMMR1U-02 R10 22k C4 3.3nF COMP FB HCOMP SS2 SS1 RT TBLNK IVSEC TAS TOS R5 53k R4 93.1k C3 0.22F C2 0.47F R24 22k HFB R15 0.0075 C11 2.2F R27 100k * R13 560 INTVCC R11 10k R12 806 R25 C5 100 4.7F PS2801-1 C16 1F R22 100 R30 100k GND R28 3.16k R26 1.2k R23 22k VIN LT8311 PGOOD SYNC T3 * C6 220pF SOUT INTVCC GND TAO R14 2k C27 120pF VAUX C12 4.7F C17 0.33F R20 365k + VOUT 24V 14A C13 22F 25V x4 C24 10nF 250V R38 0.003 M3 IPB200N25N3 M1 VAUX OUT SYNC OVLO M4 BSC047N08NS3 x2 R21 100 AOUT C14 470F 25V CSP * R38 10k D4 C28 68pF FB R31 5.36k COMP R3 5.76k R18 0.15 HOUT HISENSE VIN * 1PB072N15N3G SS R2 6.04k R17 499 C23 3.3nF T4 * CSN R1 6.98k C22 220nF M5 BSP300 * CG * R19 1k C8 15nF 250V M2 IRFL214 C15 4.7nF 250V VAUX C10 4.7F * CSW C9 10F C20 10F R34 698k T2 INTVCC PMODE TIMER R36 102k * FG D5 D2 L1 15F FSW INTVCC R35 102k C1 2.2F 250V D3 OPTO VIN 75V TO 150V C18 100pF R29 5.11k C19 22nF 8311 TA08a 2.2nF Efficiency vs Load Current 96 95 EFFICIENCY (%) 94 93 92 91 90 89 VIN = 75V VIN = 100V VIN = 125V VIN = 150V 88 87 86 0 2.5 5 7.5 10 LOAD CURRENT (A) 12.5 15 8311 TA08b 8311f 46 For more information www.linear.com/LT8311 LT8311 PACKAGE DESCRIPTION Please refer to http://www.linear.com/designtools/packaging/ for the most recent package drawings. FE Package Variation: FE20(16) 20-Lead Plastic TSSOP (4.4mm) (Reference LTC DWG # 05-08-1924 Rev O) Exposed Pad Variation CB 6.40 - 6.60* (.252 - .260) 3.86 (.152) 3.86 (.152) 20 6.60 0.10 18 16 15 14 13 12 11 2.74 (.108) 4.50 0.10 6.40 2.74 (.252) (.108) BSC SEE NOTE 4 0.45 0.05 1.05 0.10 0.65 BSC 1 RECOMMENDED SOLDER PAD LAYOUT 4.30 - 4.50* (.169 - .177) 0.09 - 0.20 (.0035 - .0079) 0.25 REF 0.50 - 0.75 (.020 - .030) NOTE: 1. CONTROLLING DIMENSION: MILLIMETERS MILLIMETERS 2. DIMENSIONS ARE IN (INCHES) 3. DRAWING NOT TO SCALE 3 5 6 7 8 9 10 1.20 (.047) MAX 0 - 8 0.65 (.0256) BSC 0.195 - 0.30 (.0077 - .0118) TYP 0.05 - 0.15 (.002 - .006) FE20(16) (CB) TSSOP REV 0 0512 4. RECOMMENDED MINIMUM PCB METAL SIZE FOR EXPOSED PAD ATTACHMENT *DIMENSIONS DO NOT INCLUDE MOLD FLASH. MOLD FLASH SHALL NOT EXCEED 0.150mm (.006") PER SIDE 8311f For more information www.linear.com/LT8311 47 LT8311 TYPICAL APPLICATION 75V to 150V, 24V/14A 340W No-Opto, Active Clamp Isolated Forward Converter T1 10:6 C21 470pF 1PB200N25N3 M1 VAUX OUT OC SYNC ISENSEP R14 2k UVLO_VSEC ISENSEN LT3752-1 R15 0.0075 R7 80.1k R6 10k R9 52.3k R8 75k C3 0.1F C2 0.47F FB HCOMP SS2 SS1 RT TBLNK IVSEC TAS TOS R5 53k R4 93.1k HFB R10 22k C4 3.3nF * C6 220pF SOUT INTVCC GND TAO M3 R21 100 AOUT OVLO R38 0.003 C11 2.2F R13 560 LT8311 FB 8311 TA08a C12 4.7F C5 4.7F R12 806 R20 432k 2.2nF VOUT vs Load Current (No-Opto) T1: CHAMPS LT80R2-12AC-1006 T2: WURTH 750817020 T3: PULSE PE-68386NL T4: ICE GT05-111-100 L1: COILCRAFT AGP2923-153 D1: CENTRAL SEMI CMR1U-10 D2, D3, D5: BAS516 D4: CENTRAL SEMI CMMR1U-02 Efficiency vs Load Current 28 96 27 95 94 26 VOUT (V) 25 24 23 22 VIN = 75V VIN = 100V VIN = 125V VIN = 150V 21 20 R22 100 C27 120pF INTVCC R11 10k C13 22F 25V x4 GND PGOOD SYNC T3 * VIN + CSP D1 CSN HOUT HISENSE VIN R37 100 R16 10k C14 470F 25V VOUT 24V 14A COMP R18 0.15 * C24 10nF 250V M4 BSC047N08NS3 x2 SS R3 5.76k R17 499 * R38 10k D4 1PB072N15N3G EFFICIENCY (%) R2 6.04k C22 C23 3.3nF 220nF T4 M5 BSP300 * CG * * CSW R1 6.98k VAUX C10 4.7F * FG C9 10F C20 10F R34 698k T2 L1, 15H FSW R36 * R19 1k C8 15nF 250V M2 IRFL214 INTVCC PMODE TIMER D5 D2 C15 4.7nF 250V OPTO INTVCC R35 C1 2.2F 250V D3 COMP VIN 75V TO 150V 0 2 4 6 8 10 12 LOAD CURRENT (A) 14 93 92 91 90 89 VIN = 75V VIN = 100V VIN = 125V VIN = 150V 88 87 16 86 0 2.5 5 7.5 10 LOAD CURRENT (A) 8311 TA08b 12.5 15 8311 TA08c RELATED PARTS PART NUMBER DESCRIPTION COMMENTS LT3752/LT3752-1 Active Clamp Synchronous Forward Controllers with Internal Housekeeping Controller Ideal for Medium Power 24V, 48V and Up to 400V Input Applications LT3753 100V Input, Active Clamp Synchronous Forward Controller Ideal for Medium Power 24V and 48V Input Applications LTC3765/LTC3766 Isolated Synchronous No-Opto Forward Controller Chip Set Direct Flux Limit, Multiphase Capable Ideal for Medium Power 24V and 48V Input Applications LTC3722-1/ LTC3722-2 Synchronous Phase Modulated Full Bridge Controllers Ideal for High Power 24V and 48V Input Applications LT3748 Isolated Flyback Controller 5V VIN 100V, No-Opto Required MSOP-16 (12) LT8300 100V Micropower Isolated Flyback Converter Monolithic No-Opto with Integrated 260mA Switch, TSOT-23 LT3511/LT3512 100V Isolated Flyback Converters Monolithic No-Opto with Integrated 240mA/420mA Switch, MSOP-16(12) 8311f 48 Linear Technology Corporation 1630 McCarthy Blvd., Milpitas, CA 95035-7417 For more information www.linear.com/LT8311 (408) 432-1900 FAX: (408) 434-0507 www.linear.com/LT8311 LT 0314 * PRINTED IN USA LINEAR TECHNOLOGY CORPORATION 2014