LT8311
1
8311f
For more information www.linear.com/LT8311
TYPICAL APPLICATION
FEATURES DESCRIPTION
Synchronous Rectifier
Controller with Opto-Coupler
Driver for Forward Converters
The LT
®
8311 is used on the secondary side of a forward
converter to provide synchronous MOSFET control and
output voltage feedback through an opto-coupler. The
LT8311’s unique preactive mode allows control of the
secondary-side MOSFETs without requiring a traditional
pulse transformer for primary- to secondary-side com-
munication. In preactive mode, the output inductor current
operates in discontinuous conduction mode (DCM) at
light load. If forced continuous mode (FCM) operation is
desired at light load, the LT8311 can, alternatively, be used
in SYNC mode, where a pulse transformer is required to
send synchronous control signals from the primary-side
IC to the LT8311.
The LT8311 offers a full featured opto-coupler controller,
incorporating a 1.5% reference, a transconductance error
amplifier and a 10mA opto-driver. Power good monitoring
and output soft-start/overshoot control are also included.
The LT8311 is available in a 16-lead FE package with pins
removed for high voltage spacing requirements.
18V to 72V, 12V/8A Active Clamp Isolated Forward Converter
APPLICATIONS
n Wide Input Supply Range: 3.7V to 30V
n Preactive Mode:
n No Pulse Transformer Required
n DCM Operation at Light Load
n SYNC Mode:
n FCM or DCM Operation at Light Load
n Achieves Highest Efficiency
n 1.5% Feedback Voltage Reference
n 10mA Opto-Coupler Driver
n Output Power Good Indicator
n Integrated Soft-Start Function
n Offline and HV Car Battery Isolated Power Supplies
n 48V Isolated Power Supplies
n Industrial, Automotive and Military Systems
L, LT, LTC , LT M, Linear Technology and the Linear logo are registered trademarks of Linear
Technology Corporation. All other trademarks are the property of their respective owners.
8311 TA01
LT3753
UVLO_VSEC
OVLO
IVSEC
RT
TOS
TBLNK
TAO
TAS
GND SS1 SS2
INTVCC
AOUT
FB
SYNC
SOUT
71.5k
F
0.47µF
4.7µF
× 3
VIN
18V to
72V VIN
100k
5.9k
1.82k
31.6k
240kHz
34k
COMP
ISENSEN
OC
OUT
ISENSEP
49.9k
2.2µF
100V
100nF
4.7µF
2k
6mΩ
100Ω
F
1k
100k
100k
124k
LT8311
FSW
CSW
CSP
CG
CSN
OPTO
GND
COMP
SYNC PMODE
SS
FB
VIN
INTVCC
PGOOD
TIMER
VOUT
12V
VOUT
6.8µH
1.78k
1.5k
FG
2k 100k
20k
11.3k
22µF
× 2
2k
1.78k
470µF
68pF
15nF
2.94k
F
4.7µF
2.2µF
2.2nF
10k
100nF
4:4
100k
2.2nF
10pF
+
LT8311
2
8311f
For more information www.linear.com/LT8311
TABLE OF CONTENTS
Features ............................................................................................................................ 1
Applications ....................................................................................................................... 1
Typical Application ............................................................................................................... 1
Description......................................................................................................................... 1
Absolute Maximum Ratings ..................................................................................................... 3
Order Information ................................................................................................................. 3
Pin Configuration ................................................................................................................. 3
Electrical Characteristics ........................................................................................................ 4
Typical Performance Characteristics .......................................................................................... 7
Pin Functions .....................................................................................................................11
Block Diagram ....................................................................................................................12
Operation..........................................................................................................................13
FUNDAMENTALS OF FORWARD CONVERTER OPERATION IN CCM ..................................................................... 13
LT8311 SYNCHRONOUS CONTROL SCHEMES ..................................................................................................... 17
PREACTIVE MODE SYNCHRONOUS CONTROL .................................................................................................... 17
SYNC MODE SYNCHRONOUS CONTROL ............................................................................................................. 19
OPTO-COUPLER CONTROL .................................................................................................................................. 21
Applications Information .......................................................................................................25
VIN BIAS SUPPLY .................................................................................................................................................. 25
INTVCC BIAS SUPPLY ............................................................................................................................................ 26
LT8311 OPTO CONTROL FUNDAMENTALS ........................................................................................................... 27
LT8311 SYNCHRONOUS CONTROL FUNDAMENTALS .......................................................................................... 31
PREACTIVE MODE SYNCHRONOUS CONTROL ................................................................................................... 37
SYNC MODE SYNCHRONOUS CONTROL ............................................................................................................ 38
Typical Applications .............................................................................................................40
Package Description ............................................................................................................47
Typical Application ..............................................................................................................48
Related Parts .....................................................................................................................48
LT8311
3
8311f
For more information www.linear.com/LT8311
PIN CONFIGURATIONABSOLUTE MAXIMUM RATINGS
CSW, FSW, CSP ....................................... 0.3V to 150V
SYNC ...........................................................12V to 12V
VIN, PGOOD ................................................ 0.3V to 30V
INTVCC, PMODE ......................................... 0.3V to 18V
FB, SS, COMP ........................................... 0.3V to 2.5V
TIMER ....................................................... 0.3V to 1.5V
CSN ........................................................... 0.3V to 0.4V
OPTO, TIMER Short-Circuit
Current Duration .................................... Infinite (Note 5)
Operating Junction Temperature Range
LT8311E (Notes 2, 3) ......................... 40°C to 125°C
LT8311I (Notes 2, 3) .......................... 40°C to 125°C
LT8311H (Notes 2, 3) .........................40°C to 150°C
LT8311MP (Notes 2, 3) ...................... 55°C to 150°C
Storage Temperature Range .................. 65°C to 150°C
Lead Temperature (Soldering, 10sec)....................300°C
(Note 1)
FE PACKAGE
20-LEAD PLASTIC TSSOP
1
3
5
6
7
8
9
10
TOP VIEW
20
18
16
15
14
13
12
11
CSW
FSW
FG
INTVCC
VIN
PMODE
OPTO
COMP
CSP
CSN
CG
SYNC
SS
PGOOD
TIMER
FB
21
GND
θJA = 38°C/W, θJC = 10°C/W
EXPOSED PAD (PIN 21) IS GND, MUST BE SOLDERED TO PCB
ORDER INFORMATION
LEAD FREE FINISH TAPE AND REEL PART MARKING* PACKAGE DESCRIPTION TEMPERATURE RANGE
LT8311EFE#PBF LT8311EFE#TRPBF LT8311FE 20-Lead Plastic TSSOP –40°C to 125°C
LT8311IFE#PBF LT8311IFE#TRPBF LT8311FE 20-Lead Plastic TSSOP –40°C to 125°C
LT8311HFE#PBF LT8311HFE#TRPBF LT8311FE 20-Lead Plastic TSSOP –40°C to 150°C
LT8311MPFE#PBF LT8311MPFE#TRPBF LT8311FE 20-Lead Plastic TSSOP –55°C to 150°C
Consult LTC Marketing for parts specified with wider operating temperature ranges. *The temperature grade is identified by a label on the shipping container.
For more information on lead free part marking, go to: http://www.linear.com/leadfree/
For more information on tape and reel specifications, go to: http://www.linear.com/tapeandreel/
LT8311
4
8311f
For more information www.linear.com/LT8311
ELECTRICAL CHARACTERISTICS
PARAMETER CONDITIONS MIN TYP MAX UNITS
Supply
VIN Operating Range l3.7 30 V
VIN UVLO VIN Rising
Hysteresis
l
50 3.6
100 3.7
150 V
mV
Quiescent Current Not Switching 4.5 5.5 mA
Error Amplifier
Feedback Reference Voltage VIN = 12V l1.209 1.227 1.245 V
Feedback Voltage Line Regulation 3.7V ≤ VIN ≤ 30V, % of FB Ref Voltage 0.015 0.1 %
Feedback Voltage Load Regulation 1.3V ≤ COMP ≤ 1.8V, % of FB Ref Voltage 0.05 0.1 %
Feedback Pin Bias Current Current Out of FB pin 120 200 nA
Error Amplifier Transconductance 1.3V ≤ COMP ≤ 1.8V 370 µmhos
Error Amplifier Voltage Gain 1.3V ≤ COMP ≤ 1.8V 65 dB
Error Amplifier Output Swing High FB = 1V 1.9 2.3 2.8 V
Error Amplifier Output Swing Low FB = 1.5V 0.75 1 1.25 V
Power Good
Power NOT Good (Outside This Window) % Relative to FB Ref Voltage ±4 ±10 ±16 %
Power Good (Inside This Window) % Relative to FB Ref Voltage ±7 %
Power Good Indicator Wait Time Minimum Time That FB Must Stay within Power Good Window
Before PGOOD Pin Goes Low 175 µs
Power Good Leakage PGOOD = 30V ±1 µA
Power Good Output Low Voltage Current into PGOOD Pin = 1mA l0.2 0.3 V
Soft-Start (SS)
SS Wake-Up Slew Current Current Exists Upon Part Wake Up, Shuts Off After SS Wake Up
Offset Voltage Is Satisfied (Note 6) 1 mA
SS Wake-Up Offset Voltage VFB – VSS, Upon Part Wake Up SS Is Slewed Up to an Offset
Voltage Below FB by SS Wake-Up Slew Current 16 mV
SS Charge Current SS = 0V, FB = 0.6V (Note 9) l9 10 11 µA
SS Pull-Down Amplifier Offset Voltage VSS – VFB, Pull-Down Amplifier Prevents SS from Rising Beyond
This Offset Voltage Above FB When the FB Pin Voltage Is Below
50% of the FB Reference Voltage
100 mV
SS Pull-Down Amplifier Maximum
Sink Current SS = 1.5V, FB = 0.6V (Note 7) 13 mA
SS High Clamp Voltage 1.8 2 V
Opto Driver
COMP Buffer Input Offset Voltage 1.3V ≤ COMP (Note 5) 0.9 V
Opto-Driver Reference Voltage (Note 5) 1 V
Opto-Driver DC Gain (Note 5) –7 V/V
The l denotes the specifications which apply over the full operating
temperature range, otherwise specifications are at TA = 25°C, VIN = 12V, VINTVCC = 8V, PMODE = 5V, CCG = CFG = 100pF, unless
otherwise noted. (Note 2)
LT8311
5
8311f
For more information www.linear.com/LT8311
ELECTRICAL CHARACTERISTICS
The l denotes the specifications which apply over the full operating
temperature range, otherwise specifications are at TA = 25°C, VIN = 12V, VINTVCC = 8V, PMODE = 5V, CCG = CFG = 100pF, unless
otherwise noted. (Note 2)
PARAMETER CONDITIONS MIN TYP MAX UNITS
Inverting DC Gain From COMP Pin to
OPTO Pin (∆VOPTO/∆VCOMP), 1.290V ≤ COMP ≤ 1.310V –5 V/V
(∆VOPTO/∆VCOMP), 1.490V ≤ COMP ≤ 1.510V –5.9 V/V
(∆VOPTO/∆VCOMP), 1.890V ≤ COMP ≤ 1.910V –6.2 V/V
Opto-Driver –3dB Bandwidth No Load (Note 5) 400 kHz
Opto-Driver Output Swing Low FB = 1V, COMP = SS = OPTO = Open l0.5 0.85 V
Opto-Driver Output Swing High VIN = 3.7V, FB = 1.5V, COMP = SS = Open, IOPTO = 10mA lVIN – 1.7 VIN – 1.4 V
VIN = 30V, FB = 1.5V, COMP = SS = Open, IOPTO = 10mA l5.2 6.5 V
Opto-Driver Output Short-Circuit Current VIN = 30V, FB = 1.5V, COMP = SS = Open, OPTO = 0V (Note 6) l10.5 15 18 mA
Opto-Driver Output Sink Current FB = 1V, OPTO = 1.2V (Note 7) l200 300 420 µA
Internal Linear Regulator
INTVCC Regulation Voltage No Load l6.5 7 7.5 V
INTVCC Load Regulation (∆VINTVCC/∆IINTVCC), 0A ≤ IINTVCC ≤ 20mA 1.8 3 mV/mA
INTVCC UVLO Rising l4.6 4.8 V
INTVCC UVLO Falling l4.1 4.3 V
INTVCC OVLO Rising l16.5 17.5 V
INTVCC OVLO Falling l14 15 V
INTVCC Current Limit INTVCC > IINTVCC_UVLO_RISING (= 4.6V) l38 48 58 mA
INTVCC < IINTVCC_UVLO_FALLING (= 4.3V) 20 mA
INTVCC Dropout Voltage VIN = 6V, IINTVCC = 10mA, Not Switching 400 mV
CG and FG Gate Drivers
Driver Output Rise Time CCG = CFG = 3.3nF, INTVCC = 8V (Note 4) 25 ns
Driver Output Fall Time CCG = CFG = 3.3nF, INTVCC = 8V (Note 4) 25 ns
Driver Output High Voltage lVINTVCC
– 0.2 V
Driver Output Low Voltage l0.7 V
PMODE Selection
PMODE Trip Voltage PMODE Ramp Up
Hysteresis
l1 1.2
30 1.4 V
mV
PMODE Input Current PMODE = 18V l60 90 µA
Preactive Mode (Tie PMODE to 0V)
Preactive Mode Operating
Frequency Range
l100 300 kHz
CSW High Trip Voltage CSW Ramp Up l1 1.2 1.4 V
CSW High Input Current CSW = 150V (Note 7) l250 500 µA
CSW Low Trip Voltage CSW Ramp Down l–250 –150 –50 mV
FSW Trip Voltage l1 1.2 1.4 V
FSW High Input Current FSW = 150V (Note 7) l250 500 µA
CG Falling Edge to CSW Rising Edge
Prediction Delay CSW = 150kHz (Note 10), FSW = 0V, CSP = –500mV l5 100 300 ns
CG Falling Edge Delay to FG Rising Edge CSW = 150kHz (Note 10), FSW = 0V, CSP = –500mV l10 50 80 ns
LT8311
6
8311f
For more information www.linear.com/LT8311
ELECTRICAL CHARACTERISTICS
The l denotes the specifications which apply over the full operating
temperature range, otherwise specifications are at TA = 25°C, VIN = 12V, VINTVCC = 8V, PMODE = 5V, CCG = CFG = 100pF, unless
otherwise noted. (Note 2)
PARAMETER CONDITIONS MIN TYP MAX UNITS
SYNC Mode (Tie PMODE to INTVCC)
SYNC High Trip Voltage SYNC Ramp Up
Hysteresis
l0.9 1.2
–2.4 1.5 V
V
SYNC Low Trip Voltage SYNC Ramp Down
Hysteresis
l–1.5 –1.2
2.4 –0.9 V
V
SYNC Minimum Pulse Width SYNC = 0V to ±2V Pulse
SYNC = 0V to ±6V Pulse (Note 5)
l40
20 100 ns
ns
SYNC Input Current –3.5V < SYNC < 3.5V
SYNC = ±10V (Note 6, 7)
l
300 ±1
400 µA
µA
SYNC Propagation Delay To CG/FG
Outputs SYNC Rising Edge (0V to 2V) to CG Rising Edge (Note 8)
SYNC Rising Edge (0V to 6V) to CG Rising Edge (Notes 5, 8)
SYNC Falling Edge (0V to 2V) to FG Rising Edge (Note 8)
SYNC Falling Edge (0V to 6V) to FG Rising Edge (Notes 5, 8),
CCG = CFG = 3.3nF
l
l
100
75
100
85
150
150
ns
ns
ns
ns
TIMER Timeout Frequency RTIMER = 41.2k
RTIMER = 71.5k
RTIMER = 221k
l
l
l
425
255
80
505
300
100
585
345
120
kHz
kHz
kHz
TIMER Short-Circuit Current TIMER = 0V l40 60 µA
Current Comparator
Current Comparator Trip Threshold CSP Ramp Up, RCSP = RCSN = 0Ω l48 62 72 mV
CSP Ramp Up, RCSP = RCSN = 1.62kΩ (Note 5) 0 mV
Current Comparator Blank Time in
Preactive Mode From Rising CG Edge Until Blanking Ends (Note 5) 250 ns
Current Comparator Blank Time in
SYNC Mode From Rising CG Edge Until Blanking Ends 400 ns
CSP Current at Low CSP Voltage CSP = 0V (Note 6) l30 38 50 µA
CSP Current at High CSP Voltage CSP = 150V (Note 7) l200 500 µA
CSN Current CSN = 0V (Note 6) l0.1 1 µA
Note 1: Stresses beyond those listed under Absolute Maximum Ratings
may cause permanent damage to the device. Exposure to any Absolute
Maximum Rating condition for extended periods may affect device
reliability and lifetime.
Note 2: The LT8311 is tested under pulsed load conditions such that
TJ ~ TA. The LT8311E is guaranteed to meet specifications from 0°C to
125°C junction temperature. Specifications over the –40°C to 125°C
operating junction temperature are assured by design, characterization and
correlation with statistical process controls. The LT8311I is guaranteed
over the –40°C to 125°C operating junction temperature range. The
LT8311H is guaranteed over the –40°C to 150°C operating junction
temperature range, and the LT8311MP is guaranteed over the –55°C to
150°C operating junction temperature range. High junction temperatures
degrade operating lifetimes; operating lifetime is derated for junction
temperatures greater than 125°C.
Note 3: The LT8311 includes overtemperature protection that is intended
to protect the device during momentary overload conditions. Junction
temperature will exceed the maximum operating junction temperature
when overtemperature is active. Continuous operating above the specified
maximum operating junction temperature may impair device reliability.
Note 4: Rise and fall times of are measured between 10% and 90% points
of a signal edge.
Note 5: Guaranteed by design and/or correlation to static test.
Note 6: Current flows out of pin.
Note 7: Current flows into pin.
Note 8: Propagation delay is measured between 50% point of the two
signal edges of interest.
Note 9: SS charge current refers to current flowing out of SS pin after
certain conditions satisfied upon LT8311 wake-up (see the flowchart for
Opto-Control Operation at Start-Up in Figure 9).
Note 10: CSW is a square waveform (duty cycle = 50%) with VHIGH = 7V
and VLOW = –0.7V.
LT8311
7
8311f
For more information www.linear.com/LT8311
TYPICAL PERFORMANCE CHARACTERISTICS
Preactive Scheme Waveforms
(Active Clamp Reset, CCM)
Preactive Scheme Waveforms
(Active Clamp Reset, Light DCM)
Preactive Scheme Waveforms
(Active Clamp Reset, Deep DCM)
Maximum CSW Duty Cycle Derating
Curve vs CSW Switching Frequency
and Junction Temperature Feedback Reference Voltage
Feedback Reference Voltage
vs VIN
Delay from CG Turn-Off to CSW
Rising Edge vs CSW Switching
Frequency and Junction Temp
Jitter in CG Turn-Off Delay to CSW
Rising Edge vs CSW Switching
Frequency and Junction Temp
Delay from CG Turn-Off to
FG Turn-On
TA = 25°C, unless otherwise noted.
IL
5A/DIV
CSW
5A/DIV
CG
10V/DIV
FG
10V/DIV
8311 G04
2µs/DIV
IL
5A/DIV
CSW
5A/DIV
CG
10V/DIV
FG
10V/DIV
8311 G05
2µs/DIV
IL
5A/DIV
CSW
5A/DIV
CG
10V/DIV
FG
10V/DIV
8311 G06
2µs/DIV
TEMPERATURE (°C)
DELAY CG FALLING TO CSW RISING (ns)
150
175
125
100
25
0
75
200
50
8311 G01
100kHz
PMODE = 0V
INTVCC = 8V
–75 –25 25 75–50 0 125 15050 100
300kHz
150kHz
TEMPERATURE (°C)
JITTER (ns)
20
25
15
10
0
5
30
8311 G02
100kHz
PMODE = 0V
INTVCC = 8V
300kHz
150kHz
–75 –25 25 75–50 0 125 15050 100
TEMPERATURE (°C)
DELAY CG FALLING TO FG RISING (ns)
60
50
30
40
70
8311 G03
PMODE = 0V
INTVCC = 8V
–75 –25 25 75–50 0 125 15050 100
TEMPERATURE (°C)
MAXIMUM CSW DUTY CYCLE (%)
80
85
75
70
55
50
65
90
60
8311 G07
100kHz, 200kHz
PMODE = 0V
–75 –25 25 75–50 0 125 15050 100
300kHz
400kHz
TEMPERATURE (°C)
FB VOLTAGE (V)
1.2290
1.2325
1.2255
1.2220
1.2150
1.2185
1.2360
8311 G08
–75 –25 25 75–50 0 125 15050 100
VIN (V)
FB VOLTAGE (V)
1.2290
1.2325
1.2255
1.2220
1.2150
1.2185
1.2360
8311 G09
3 9 15 216 12 27 3018 24
LT8311
8
8311f
For more information www.linear.com/LT8311
TYPICAL PERFORMANCE CHARACTERISTICS
SS Charge Current
SS Pull-Down Amplifier
Offset Voltage Opto-Driver Output Swing Low
Opto-Driver Output Swing High
Opto-Driver Output Swing High
vs Line Voltage
Feedback Input Bias Current
VIN Quiescent Current,
No Switching Power Good Window
TA = 25°C, unless otherwise noted.
TEMPERATURE (°C)
FB INPUT BIAS CURRENT (nA)
133
115
80
98
150
8311 G10
–75 –25 25 75–50 0 125 15050 100
TEMPERATURE (°C)
VIN QUIESCENT CURRENT (mA)
5.0
4.5
3.5
4.0
5.5
8311 G11
–75 –25 25 75–50 0 125 15050 100
FB VOLTAGE (V)
PGOOD VOLTAGE (V)
12
8
0
4
16
8311 G12
PGOOD = 100kΩ to 12V
1.00 1.10 1.20 1.401.30
TEMPERATURE (°C)
SS CHARGE CURRENT (µA)
10.5
10.0
9.0
9.5
11.0
8311 G13
–75 –25 25 75–50 0 125 15050 100
TEMPERATURE (°C)
SS PULL-DOWN AMP OFFSET VOLTAGE (mV)
125
100
50
75
150
8311 G14
–75 –25 25 75–50 0 125 15050 100
TEMPERATURE (°C)
OPTO LOW VOLTAGE (mV)
750
500
0
250
1000
8311 G15
–75 –25 25 75–50 0 125 15050 100
TEMPERATURE (°C)
OPTO HIGH VOLTAGE (V)
6.5
6.0
5.0
5.5
7.0
8311 G16
–75 –25 25 75–50 0 125 15050 100
VIN (V)
OPTO HIGH VOLTAGE (V)
6
7
5
4
2
3
8311 G17
3 9 15 216 12 27 3018 24
LT8311
9
8311f
For more information www.linear.com/LT8311
Opto-Driver Short-Circuit Current
TYPICAL PERFORMANCE CHARACTERISTICS
INTVCC OVLO
INTVCC Current Limit and
Short-Circuit Current
CG/FG Rise/Fall Time
CG/FG Rise/Fall Time
vs INTVCC Voltage
CSW/FSW Maximum Input
Current
Opto-Driver Sink Current INTVCC Regulation Voltage
INTVCC UVLO
TA = 25°C, unless otherwise noted.
TEMPERATURE (°C)
OPTO CURRENT (mA)
15
5
10
20
8311 G18
–75 –25 25 75–50 0 125 15050 100
TEMPERATURE (°C)
OPTO CURRENT (µA)
350
300
250
200
400
8311 G19
–75 –25 25 75–50 0 125 15050 100
TEMPERATURE (°C)
INTVCC VOLTAGE (V)
7
8
6
5
3
4
8311 G20
–75 –25 25 75–50 0 125 15050 100
TEMPERATURE (°C)
INTVCC VOLTAGE (V)
4.6
4.8
4.4
4.2
4.0
8311 G21
UVLO+
UVLO
–75 –25 25 75–50 0 125 15050 100
TEMPERATURE (°C)
INTVCC VOLTAGE (V)
16.0
16.5
15.5
15.0
14.5
8311 G22
OVLO+
OVLO
–75 –25 25 75–50 0 125 15050 100
TEMPERATURE (°C)
INTVCC CURRENT (mA)
50
60
40
30
10
20
8311 G23
INTVCC CURRENT LIMIT
INTVCC SHORT-CIRCUIT CURRENT
–75 –25 25 75–50 0 125 15050 100
TEMPERATURE (°C)
RISE/FALL TIME (ns)
30
25
20
10
15
8311 G24
FG FALL TIME
FG RISE TIME
CG FALL TIME
CG RISE TIME
–75 –25 25 75–50 0 125 15050 100
INTVCC ≈ 7V (NOT OVERDRIVEN)
INTVCC (V)
RISE/FALL TIME (ns)
25.0
22.5
20.0
15.0
17.5
8311 G25
FG FALL TIME
FG RISE TIME
CG FALL TIME
CG RISE TIME
6 10 148 12 16
TEMPERATURE (°C)
CSW/FSW MAXIMUM INPUT CURRENT (µA)
250
240
220
230
260
8311 G26
VCSW = VFSW = 150V
–75 –25 25 75–50 0 125 15050 100
LT8311
10
8311f
For more information www.linear.com/LT8311
TA = 25°C, unless otherwise noted.
TYPICAL PERFORMANCE CHARACTERISTICS
CSP Trip Voltage vs Series CSP
Resistor (RCSP)
SYNC High/Low Trip Voltage
Prop Delay from SYNC Input to
CG/FG Outputs
TIMER Frequency
CSP Maximum Input Current
TEMPERATURE (°C)
CSW/FSW MAXIMUM INPUT CURRENT (µA)
190
180
160
170
200
8311 G27
VCSP = 150V
–75 –25 25 75–50 0 125 15050 100
TEMPERATURE (°C)
SYNC VOLTAGE (V)
1.0
1.5
0.5
0
–1.5
–2.0
–0.5
2.0
–1.0
8311 G28
SYNC HIGH
–75 –25 25 75–50 0 125 15050 100
SYNC LOW
TEMPERATURE (°C)
PROPAGATION DELAY (ns)
140
160
120
100
70
60
90
180
130
150
110
170
80
8311 G29
–75 –25 25 75–50 0 125 15050 100
CG Rise/FG Fall, SYNC = ±2V
CG Rise/FG Fall, SYNC = ±6V
CG Rise/FG Fall, SYNC = ±10V
FG Rise/CG Fall, SYNC = ±2V
FG Rise/CG Fall, SYNC = ±6V
FG Rise/CG Fall, SYNC = ±10V
TEMPERATURE (°C)
FREQUENCY (kHz)
400
500
300
200
0
100
600
8311 G30
RTIMER = 41.2kΩ
RTIMER = 221kΩ
RTIMER = 71.5kΩ
–75 –25 25 75–50 0 125 15050 100
RCSP (kΩ)
CSP TRIP VOLTAGE (mV)
60
80
40
20
–20
0
8311 G31
0.1 0.7 1.60.4 1.0 1.3 1.9
LT8311
11
8311f
For more information www.linear.com/LT8311
PIN FUNCTIONS
CSW (Pin 1): Catch MOSFET Drain Sense Pin. Connect
this pin to the external N-channel catch MOSFET’s drain
through a 2k resistor (typical) in preactive mode. Mini-
mize parasitic capacitance on the pin. Connect to GND in
SYNC mode.
FSW (Pin 3): Forward MOSFET Drain Sense Pin. Con-
nect this pin to the external N-channel forward MOSFET’s
drain through 2k resistor (typical) in preactive mode.
Minimize parasitic capacitance on the pin. Connect to
GND in SYNC mode.
FG (Pin 5): Forward MOSFET Gate Driver Pin. This pin
drives the gate of the external N-channel forward MOSFET.
Minimize trace length between this pin and the forward
MOSFET gate.
INTVCC (Pin 6): Internal Linear Regulator’s Output Pin.
INTVCC powers the gate drivers on the LT8311. The volt-
age on this pin is internally regulated to 7V. Alternatively,
the pin can be overdriven externally. A minimum of 4.7µF
(ceramic capacitor) must be placed from this pin to GND.
VIN (Pin 7): Input Supply Pin. This pin must be locally
bypassed.
PMODE (Pin 8): Preactive Mode Select Pin. Tying PMODE
to GND enables preactive mode. Tying PMODE to INTVCC
enables SYNC mode.
OPTO (Pin 9): Opto Driver Output Pin. Tie this pin, through
a series resistor, to the input of the opto-coupler. This
pin can source up to 10mA, sink 300μA typically, and is
short-circuit protected.
COMP (Pin 10): Error Amplifier Output Pin. Tie an ex-
ternal compensation network to this pin when using the
LT8311’s transconductance error amplifier as part of a
voltage feedback loop.
FB (Pin 11): Feedback Pin. This is the inverting input of
the LT8311’s internal error amplifier. The FB pin voltage
tracks the lower of the internal 1.227V reference and the
SS pin voltage. 75nA (bias current) typically flows out of
the pin. Tie this pin to a resistor divider network from the
output to set the desired output voltage.
TIMER (Pin 12): Switching Period Timeout Pin. A resistor
from this pin to ground sets an upper limit on the sum
of the forward and catch MOSFET on times (including
dead time between the two MOSFETs on period), every
cycle. If the sum of the on times of the catch and forward
MOSFET, per cycle (including the dead time), exceeds the
timeout period programmed by the TIMER resistor, then
all synchronous conduction will be shut down. Synchro-
nous conduction resumes when the timeout period is
reset again. See the Applications Information section for
more details on programming the TIMER resistor. Keep
the ground return trace of this pin short, and away from
paths with switching noise.
PGOOD (Pin 13): Output Power Good Pin. The open-drain
output will be pulled to ground when the FB pin voltage
stays within ±7% of the internal 1.227V reference for a
period of 175µs. The internal PGOOD comparator has a
hysteresis of ±3%. Therefore, when FB exists outside ±10%
of the 1.227V reference, the PGOOD pin will be pulled high
by an external pull-up resistor or current source.
SS (Pin 14): Soft-Start Pin. A capacitor from the SS pin to
GND will be charged up by SS’s internally trimmed 10µA
current source. Since FB tracks the lower of the SS pin
voltage and the internal reference of 1.227V, the charge
rate of the SS pin can be used to set the slew rate at which
the FB pin charges up to its regulation voltage of 1.227V.
The SS pin typically charges up to 2V. When using the
LT8311 as part of voltage feedback loop, place a ceramic
capacitor of at least 1nF on this pin to GND. For details on
SS start-up and overshoot control functions, please refer
to the Applications Information section.
SYNC (Pin 15): Synchronization Pin. The SYNC pin, used
only in SYNC mode, serves as an edge-sensitive input to
receive timing information for synchronous switching. It
is typically driven with PWM synchronization signals from
the primary-side IC through a pulse transformer. A nega-
tive voltage slew on the SYNC pin (–1.2V threshold) turns
on the forward MOSFET and turns off the catch MOSFET.
Equivalently, a positive voltage slew (1.2V threshold) turns
on the catch MOSFET and turns off the forward MOSFET.
Tie the SYNC pin to GND in preactive mode.
CG (Pin 16): Catch MOSFET Gate Driver Pin. This pin drives
the gate of the external N-channel catch MOSFET. Minimize
trace length between this pin and the catch MOSFET gate.
CSN, CSP (Pin 18, Pin 20): Current Sense Differential
Inputs. CSP and CSN are the positive and negative inputs,
respectively, of the LT8311’s internal current sense com-
parator. The pins are typically connected across the catch
LT8311
12
8311f
For more information www.linear.com/LT8311
BLOCK DIAGRAM
MOSFET to perform VDS current sensing. Alternatively, if
a more precise current sensing mechanism is desired, the
pins may be connected across a sense resistor at the catch
MOSFET’s source. The current comparator trips at 62mV
typical. The CSP pin sources 38µA current, allowing trip
voltages less than 62mV to be set by placing a resistor in
series with the CSP pin. It is recommended to place an
identical resistor in series with the CSN pin to match any
voltage offsets created by the input bias current (100nA)
of the current comparator. In preactive mode, the CSP and
CSN pins must be configured to trip at zero or positive
values of source to drain current in the catch MOSFET
(current in catch MOSFET cannot be allowed to flow from
drain to source in preactive mode).
GND (Exposed Pad Pin 21): Ground. Exposed pad must
be soldered directly to local ground plane.
PIN FUNCTIONS
8311 BD
INTVCC
INTVCC
VIN
VIN UVLO
CRST
COMP
1.227V
VIN
1V
10µA
1.2V
OPTO
1.227V
RCSW
SSDOWNAMP
SYNCHRONOUS
CONTROLLER
0.9V
RE
NS
NP
TO PRIMARY-
SIDE CIRCUITS
MFG
VIN(SYS)
PRIMARY
SIDE SECONDARY
SIDE
PRIMARY
IC
MCG
+
1.2V
1.2V
1.31V
1.14V
+
+
+
+
+
+
+
+
+
+
SWITCHING TIMEOUT
OSCILLATOR
UVLO + 1.227
REFERENCE UVLO/
OVLO
+
+
10
SS
14
CSS
140k
RD2k
100mV
62mV
38µA
300k
RCSN
RCSP
RFSW
M1
9
PMODE
8
CSN
18
CG
16
CSP
20
FG
5
FSW
3
CSW
1
20k
6
INTVCC
CINTVCC
7
VIN
12
TIMER
15
SYNC
7V
11
FB
13
PGOOD
21
GND
RTIMER
RPGOOD
RFB1
CVIN COUT
VOUT
CPL
VIN
5.7V
5.7V
RFB2
CC
RC
CF
20k
LOUT
A2
S1
A1
SYNCHRONOUS
MODE SELECT
600mV +
+
LT8311
13
8311f
For more information www.linear.com/LT8311
OPERATION
The LT8311 controls the synchronous MOSFETs and opto-
coupler on the secondary side of a forward converter.
Synchronous control of low RDS(ON) MOSFETs can typically
lead to lower power dissipation in forward converters. The
lower power dissipation can improve converter efficiency,
resulting in long term cost savings by lowering input power
requirements to support a certain level of output power.
Improved efficiency can also reduce the size of heat sinks
required to dissipate the heat generated in the rectifiers;
consequently increasing the operating ambient temperature
range which may be useful in many industrial applications.
The LT8311 also offers opto-coupler control for accurate
output voltage regulation over line and load. The LT8311’s
opto-coupler control circuitry comes with a host of start-up
and steady-state functions to ensure robust transient re-
sponse during power-on and output short-circuit recovery.
FUNDAMENTALS OF FORWARD CONVERTER
OPERATION IN CCM
The timing diagram of a forward converter operating in
continuous conduction mode (CCM) is shown in Figure 2.
The timing diagram is broken into six regions of operation.
Please refer to Figures 1 and 2 for the following explana-
tion of each region of operation.
Region 1 (Figure 2)
When OUT goes high, M1 turns on. CG should already be
at 0V before OUT goes high, to ensure that MCG does not
cross conduct with M1. The LT8311’s preactive mode,
which will be explained later, is an innovative scheme to
turn off MCG before M1 turns on. FG must be high during
this period to keep the forward MOSFET, MFG on, thereby
conducting the output inductor current, ILOUT, (via the
transformer’s secondary winding) through a low imped-
ance path. During this phase, magnetizing current, ILMAG,
builds up in the transformer’s magnetic core, and flows
from VIN to GND through M1. Output inductor current,
ILOUT, ramps up at a rate of (VCSW – VOUT)/ LOUT.
Region 2 (Figure 2)
When OUT goes low, and turns off M1, the transformer
becomes high impedance, and stops conducting ILOUT.
Since current in the output inductor cannot go to zero
instantaneously, it pulls the drain of the catch MOSFET,
CSW, towards ground. Ultimately CSW gets clamped at a
diode voltage below ground by MCG’s body diode which
now sources the output inductor current (similar to a catch
diode in a traditional buck converter). CSW collapsing
equivalently causes the transformer’s secondary winding
voltage to become smaller. Through transformer action,
Figure 1. Forward Converter with Active Clamp Reset (in Red) or Resonant Reset (in Blue)
8311 F01
VIN
VDRAIN_M2
NS
NP
PRIMARY
IC
OUT
VOUT
COUT
LOUT
ILOUT
CSW
SECONDARY
IC
FSWSWP
ILMAG
LMAG
MFG
M1
RLOAD
MCG
VCL CCL
AOUT M2
CAOUT CRST
D2
FG
CG
ACTIVE CLAMP RESET (RED)
RESONANT RESET (BLUE)
+
LT8311
14
8311f
For more information www.linear.com/LT8311
OPERATION
Figure 2. Active Clamp Forward Converter Timing Diagram in CCM. Resonant Reset Waveforms in Blue
D • tPER
tPER
AOUT
VGATE M2
(M2 SOURCE = 0V)
OUT
(M1 SOURCE = 0V)
SWP
ILMAG
CSW
CG
0.7 (CLAMPED BY D2) 0.7 (CLAMPED BY D2)
M2 OFF M2 OFFM2 ON M2 ON
M1 ON
0.7V
VIN
M1 ONM1 OFF
0V 0V
0V
0V
TIME
0V
0V
0V
0A
0V
0V
0V
0V
0V
0V 0V
MCG OFF MCG ON MCG OFF MCG ON
MFG ON MFG OFF MFG ON MFG OFF
M1 OFF
FSW
FG
ILOUT
ACTIVE CLAMP
PMOS CONTROL
SIGNAL
ACTIVE CLAMP
PMOS GATE
PRIMARY NMOS
SWITCH GATE
PRIMARY-SIDE
WAVEFORMS
SECONDARY-SIDE
WAVEFORMS
PRIMARY NMOS
SWITCH DRAIN
TRANSFORMER
MAGNETIZING
INDUCTANCE
CURRENT
CATCH FET DRAIN
CATCH FET GATE
FORWARD FET
DRAIN
FORWARD FET
GATE
OUTPUT INDUCTOR
CURRENT
REGIONS OF
OPERATION
0.7V
0.7V
8311 F02
di
dt=
V
IN
LMAG
di
dt=
1
LMAG
VIN D
1D
V
IN
D t
PER
LMAG
V
OUT
t
PER
2LMAG CRST
di
dt=
V
CSW
V
OUT
LOUT
di
dt=
V
OUT
LOUT
VOUT
RLOAD
V
OUT
(1D) t
PER
LOUT
VIN
N
S
NP
V
OUT
1D
V
IN
1D
2 31 4 65
LMAG CRST
tRES = π
VIN (
1+D t PER)
2 LMAGCRST
LT8311
15
8311f
For more information www.linear.com/LT8311
OPERATION
Figure 3. With FG On, ILMAG Is Conducted Through MFG to Ground
on the Secondary Side When M1 Turns Off
Figure 4. Detail of Region 3 from the Timing Diagram in Figure 2. When MFG Turns Off
in Active Clamp Reset, ILMAG Initially Slews Up SWP’s Voltage from VIN to VCL + 0.7V,
at Which Point M2’s Body Diode Turns On and Allows ILMAG to Flow into CCL
the primary winding voltage gets smaller too, effectively
moving SWP towards VIN. Since MFG is still on, and MCG’s
body diode is on, the secondary winding voltage gets
clamped at about a diode voltage. Through transformer
action, SWP gets clamped to approximately VIN. ILMAG
flows in the secondary windings, as shown in Figure 3,
flowing from the drain to source of MFG, to ground. MCG’s
body diode sources ILOUT and ILMAG.
Region 3 (Figure 2)
When FG goes low, it allows transformer reset action to
begin. ILMAG no longer has a low impedance path through
MFG on the secondary side. As a result, itjumps back” to
the primary side, flowing into the primary-side resonant
capacitor. In resonant reset, ILMAG flows into CRST as soon
as MFG turns off, causing SWP’s voltage to rise up quasi-
sinusoidally, with a time constant set by LMAG and CRST. In
active clamp reset, when MFG turns off, ILMAG intially slews
up SWP’s voltage quickly. As shown in Figure 2, ILMAG
does not flow into the active clamp capacitor as soon as
MFG turns off. The voltage across CCL (= VCL = VIN/(1-D))
initially reverse biases M2’s body diode. Only when SWP’s
voltage gets high enough to forward bias M2’s body diode,
does ILMAG begin to flow into CCL. The voltage where this
happens is when SWP = VCL + 0.7V. At this point, SWP’s
voltage rises up at a rate determined by the time constant
of LMAG and the active clamp capacitor, which is typically
much larger than the resonant reset capacitor.
VDRAIN_M2
SWP
M2 BODY
DIODE OFF M2 BODY
DIODE ON M2 ON
MFG TURNS OFF
VCL =
V
IN
1D
tRISE PROPORTIONAL
TO LMAG AND CCL
VCL + 0.7V
VCL
VIN
0.7V
0V
VIN – VCL
TIME
8311 F04
8311 F03
VIN
NS
NP
M1 OFF
LOUT
ILOUT
ILMAG
LMAG
MFG
MCG
FG ON
CG OFF
ILMAG
LT8311
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8311f
For more information www.linear.com/LT8311
The ultimate goal of both reset mechanisms is to raise
the SWP node to a voltage higher than VIN, imposing
appropriate volt seconds on LMAG, and allowing the
magnetizing current to reset. Resetting the magnetic core
every cycle prevents magnetic flux buildup within the
core, and thereby prevents transformer saturation. FSW
tracks the SWP node during transformer reset. CG going
high, allows ILOUT to switch over from being conducted
by MCG’s body diode to MCG itself.
Region 4 (Figure 2)
1. Active Clamp Reset Case (red waveform): AOUT going
low causes the gate of M2 to be driven below ground
by the decoupling capacitor, CAOUT. This causes M2,
the active clamp PMOS, to turn on. M2 must be turned
on before ILMAG becomes negative, to allow ILMAG to
sustain conduction through the active clamp capacitor
and get fully reset. Active clamp reset completes by the
end of region 4, and ILMAG is reset to a negative value.
2. Resonant Reset Case (blue waveform): Resonant reset
ultimately completes when SWP’s quasi-sinusoidal
waveform returns to VIN, by which point ILMAG is reset
to a negative value. FSW is eventually clamped by MFG’s
body diode, and conducts ILMAG, through the second-
ary windings, towards the output inductor (similar to
Figure 3, but with ILMAG direction reversed on primary
and secondary sides). With a diode voltage imposed
across the secondary windings, transformer action
causes the primary winding to have a similar voltage
(scaled by turns ratio), resulting in SWP’s voltage
getting clamped to VIN. MCG continues conducting
ILOUT – ILMAG.
Region 5 (Figure 2)
Active Clamp Reset Case: AOUT goes high, turning off
M2. ILMAG, being negative, causes the voltage on SWP
(M1’s drain) to get pulled towards VIN, resulting in the
transformer’s primary winding voltage becoming smaller.
By transformer action, the secondary winding voltage also
becomes smaller. With MCG on (holding CSW at 0V), and
the transformer secondary winding voltage becoming
smaller, FSW collapses towards 0V.
Region 6 (Figure 2)
Eventually, in similar fashion to the resonant reset case,
FSW is clamped to a diode voltage below GND by MFGs body
diode, which now conducts ILMAG through the secondary
windings, towards the output inductor. With MFG’s body
diode on, and MCG on, the secondary winding voltage gets
clamped to about a diode voltage. Through transformer
action, SWP gets clamped to approximately VIN. CG goes
low, turning off MCG before M1 can turn on. ILOUTILMAG
is conducted through MCG’s body diode. FG goes high,
turning on MFG. Eventually, when M1 turns on, ILOUT will be
conducted through the transformer’s secondary winding,
and will flow from the source to drain of MFG.
OPERATION
LT8311
17
8311f
For more information www.linear.com/LT8311
LT8311 SYNCHRONOUS CONTROL SCHEMES
The LT8311 offers two modes of synchronous control:
1. Preactive Mode: No pulse transformer needed; DCM
operation at light load. Enabled by tying the PMODE pin
to 0V. Use a Schottky diode across MCG (Figure 20).
2. SYNC Mode: Pulse Transformer needed; FCM or DCM
operation at light load. Enabled by tying the PMODE
pin to INTVCC.
PREACTIVE MODE SYNCHRONOUS CONTROL
MCG Turn-On/Off Timings in Preactive Mode
"Preactive" is short for "predictive" + "reactive". In preactive
mode, the LT8311 controls the secondary synchronous
MOSFETs without any communication from the primary-
side IC. In preactive mode, the catch MOSFET, MCG, is
turned on (CG rising edge in Figure 5) when the voltage
on its drain, CSW, is detected to be below –150mV, and
the forward MOSFET, MFG, is detected to be off. MCG is
turned off when the first of two events after MCG’s turn-
on occurs:
Predictive MCG Turn-Off (Figure 5): In predictive turn-
off, the LT8311 predicts when M1 will turn on in the
next cycle, and turns off MCG 100ns prior to this event.
Predictive turn-off of MCG prevents cross conduction
between MCG and M1. M1’s turn-on timings are pre-
dicted by phase locking to the rising edge of present
and past CSW cycles. Predictive turn-off relies on the
periodicity of M1’s turn-on edge, an inherent aspect of
fixed-frequency operation. Furthermore, the predictive
turn-off is designed to be independent of the duty cycle
of the system, which allows MCG to be correctly turned
off, even during load/line transients. Predictive turn-off
will typically be the dominant turn-off mechanism for
MCG in CCM.
Reactive MCG Turn-Off (Figure 6): Reactive turn-off
forces the forward converter to operate in DCM at light
load. In reactive turn-off, the LT8311 turns off MCG
when the current in MCG (IMCG) trips the LT8311’s
internal current comparator. The inputs to this current
comparator are the CSP and CSN pins. Typically, the
CSP and CSN pins will be configured to trip at almost
zero current in MCG, which should correspond to nearly
zero current in the output inductor. Reactive turn-off
will typically be the dominant turn-off mechanism for
MCG in DCM.
The LT8311’s seamless transition between predictive
and reactive portions of preactive mode allows the catch
MOSFET to be turned off at the correct time to avoid cross
conduction or avalanching.
MFG Turn-On/Off in Preactive Mode
In preactive mode, MFG is turned on after MCG’s turn-off
edge is detected, and the voltage on the drain of the forward
MOSFET, FSW, is detected to be below 1.2V. Waiting for
FSW to fall below 1.2V ensures that transformer reset is
close to completion. MFG is turned off when the voltage
on CSW is detected to be below –150mV.
Since preactive mode requires each MOSFET to be turned
on only after the other MOSFET’s turn-off edge is detected,
the system requires a start point where one of the two
MOSFETs begins switching. Preactive mode’s start point
happens by turning on MCG first to commence switching.
Preactive Mode Shutdown and Start-Up
Preactive mode is designed with many features to facilitate
smooth start-up of synchronous control and shut down of
the scheme when necessary. Prior to starting switching
activity, the LT8311 evaluates conditions on the forward
converter’s secondary side to determine if switching can
commence. The evaluation period ends when four specific
conditions, are satisfied for a period of three continuous
CSW switching cycles (rising edge to rising edge). If
any of the conditions are violated, the evaluation period
is reset, and switching activity is kept shut off. During
this evaluation period, the secondary side current will
flow through the body diodes of MCG and MFG. The four
conditions are:
1. VIN must be greater than its UVLO voltage
2. INTVCC must be within its UVLO/OVLO limits
3. The TIMER pin should not have timed out. This feature
exists to ensure that the LT8311 ceases switching in
the event that the primary side stops switching.
OPERATION
LT8311
18
8311f
For more information www.linear.com/LT8311
Figure 5. During the Predictive Portion of Preactive Mode, the LT8311 Phase Locks
into the CSW Rising Edge and Turns Off MCG 75ns Prior to This Edge
Figure 6. During the Reactive Portion of Preactive Mode, the LT8311 Turns Off MCG When the Current in MCG, IMCG,
Trips the LT8311’s Internal Current Comparator. The Inputs to the Comparator Are CSP and CSN and the Current Sense
Trip Voltage Is Programmed by Choosing Appropriate CSP/CSN Series Resistors
0V 0V 0V
PRIMARY-SIDE IC
CONTROLS TIMING
OF OUT SIGNAL
LT8311 USES IMCG INFORMATION
TO DETERMINE FG/CG CONTROL
TIMINGS DURING THE REACTIVE
PORTION OF PREACTIVE MODE
WAVEFORMS
IN DCM
WHEN CSP-CSN
TRIPS INTERNAL
CURRENT COMPARATOR
MCG TURNS OFF
8311 F06
OUT
IMCG
CSW
CG
TIME
0A
0A
ILOUT
M1
TURN-ON
EDGE
M1
TURN-ON
EDGE
0V 0V 0V
75ns PREDICTIVE DELAY
PRIMARY-SIDE IC
CONTROLS TIMING
OF OUT SIGNAL
LT8311 USES CSW/FSW INFORMATION
TO DETERMINE FG/CG CONTROL
TIMINGS DURING THE PREDICTIVE
PORTION OF PREACTIVE MODE
WAVEFORMS
IN CCM
8311 F05
OUT
M1
TURN-ON
EDGE
CSW
CG
TIME
M1
TURN-ON
EDGE
MCG
TURN-OFF
EDGE
MCG
TURN-OFF
EDGE
RESET
MECHANISM
PRIMARY IC
OUT
VIN VOUT
COUT
LT8311
FSW
CSW
CSP
CG
CSN
LOUT
ILOUT
FG
CSW
FSW
IMCG
NS
NP
MCG
M1 MFG
OPERATION
LT8311
19
8311f
For more information www.linear.com/LT8311
4. The CSP and CSN pins must not trip the internal
current comparator within a 150ns period of time
called "current sample window." This function helps
the LT8311 detect very light load conditions, dur-
ing which time it will keep synchronous conduc-
tion shut off, thereby improving system efficiency.
How the current sample window works:
The current sample window exists regardless of whether
MCG is turned on or not, in any given cycle. When CSW
is detected to fall below –150mV, the LT8311 starts a
blank time of 200ns. Upon completion of this blank time,
the LT8311 starts a 150ns current sample window. If the
CSP/CSN pin inputs cause the internal current compara-
tor to trip during this 150ns window, the LT8311 will
interpret this as a condition of very light load, at which
point it will stop synchronous conduction and start the
evaluation period again. Please see "Configuring CSP/
CSN Inputs of Current Sense Comparator in Preactive
Mode” in the Applications Information section.
When all four conditions are valid for three continuous
CSW cycles, the evaluation period ends and the LT8311
gets ready to start switching. Switching commences with
the LT8311 turning on MCG for its minimum on-time. If
any of the four conditions listed are violated at any point
during switching activity, the LT8311 will shut down
all synchronous conduction and restart the evaluation
period.
During preactive mode start-up, the LT8311 internally soft-
starts the on-time of MCG, allowing the forward converter
to gradually transition from full cycles of nonsynchronous
MCG conduction (secondary-side current flowing through
body diode of MCG) to full cycles of synchronous MCG
conduction.
SYNC MODE SYNCHRONOUS CONTROL
SYNC mode allows the LT8311 to operate in forced con-
tinuous mode (FCM) at light loads. In SYNC mode, a pulse
transformer (see T2 in Figure 7) is required to allow the
LT8311 to receive synchronization control signals from
the primary-side IC. These control signals are interpreted
digitally (high or low) by the LT8311 to turn on/off the
catch and forward MOSFETs.
FCM operation allows the forward converter to avoid
operation in discontinuous conduction mode (DCM) at
light loads, by letting the inductor current go negative.
Hence, even at zero load, the inductor current remains
continuous and the converter runs at a fixed frequency.
MCG Turn-On/Off Timings in SYNC Mode
In SYNC mode, MCG turns on when the signal on the SYNC
pin is higher than 1.2V. MCG turns off when the signal on
the SYNC pin is lower than –1.2V.
MFG Turn-On/Off Timings in SYNC Mode
In SYNC mode, MFG turns on when the signal on the SYNC
pin is lower than –1.2V. MFG turns off when the signal on
the SYNC pin is higher than 1.2V.
The RSYNC and CSYNC time constant must be appropriately
chosen to generate a sufficient pulse width at a particular
overdrive voltage (see "Picking Pulse Transformer and
High Pass Filter" in the Applications Information section).
Typical values for CSYNC and RSYNC are 220pF and 560Ω,
respectively.
OPERATION
LT8311
20
8311f
For more information www.linear.com/LT8311
Figure 7. In SYNC Mode, the Primary Side IC Sends SOUT Signals Through a Pulse Transformer to the LT8311’s SYNC Pin.
SYNC < 1.2V Turns on MFG and Turns Off MCG. SYNC > 1.2V Turns On MCG and Turns Off MFG
0V 0V 0V
0V
0V
0V 0V
0V 0V 0V
0V 0V 0V 0V
1.2V
–1.2V
PRIMARY-SIDE IC
CONTROLS TIMING
OF OUT AND
SOUT SIGNALS
LT8311 CONTROLS FG AND CG
TIMING BASED ON SYNC INPUT
SIGNAL IN SYNC MODE
8311 F07
OUT
SOUT
SYNC
CG
FG
TIME
RESET
PRIMARY IC
SOUT
OUT
VIN VOUT
COUT
LT8311
CSPCGCSN
LOUT
FG
SYNC
T1
T2
IMCG
NS
NP
RSYNC
CSYNC
M1
TURN-ON
EDGE
M1
TURN-ON
EDGE
MFG
TURN-ON
EDGE
MFG
TURN-ON
EDGE
MCG
TURN-ON
EDGE
MCG
TURN-ON
EDGE
MCG
M1 MFG
SYNC Mode Shutdown
In SYNC mode, the LT8311 will shut off both secondary-
side MOSFETs, MCG and MFG, if any of the following
conditions are true:
1. VIN is less than its UVLO voltage
2. INTVCC outside its UVLO/OVLO limits
3. The TIMER pin has timed out (see the Applications
Information section for details on programming the
TIMER pin resistor).
4. The CSP and CSN pins have tripped the LT8311’s in-
ternal current comparator during MCG’s on-time. The
current in MCG, IMCG, is sensed after a 400ns blank
time has expired. This blank time starts at the turn-on
edge of MCG. See the Applications Information section
for details on configuring the CSP and CSN pins in
SYNC mode.
OPERATION
LT8311
21
8311f
For more information www.linear.com/LT8311
OPTO-COUPLER CONTROL
The LT8311 offers opto-coupler control to allow output
voltage feedback from the secondary to the primary side in a
forward converter. Used in conjunction with a primary-side
IC, the entire system offers fixed frequency peak current
mode control that has excellent line/load regulation and
quick transient response.
A basic understanding of the LT8311’s opto-coupler
control scheme can be obtained by referring to Figure 8.
The LT8311 senses the output voltage through a resistor
divider (RFB1 and RFB2) connected to its FB pin. The FB
pin voltage is compared to the lower of two inputs:
An internal voltage reference of 1.227V
Soft-start (SS) pin
At start-up, the SS pin capacitor, CSS, is charged up by the
LT8311’s internally trimmed 10µA current source. Since
FB tracks the lower of the SS pin and the 1.227V refer-
ence, the FB pin (and by extension the output voltage) is
forced to soft-start at the slew rate set by the capacitor,
CSS, connected to the SS pin.
NOTE: To ensure that the soft-start time of the converter
is controlled by the LT8311’s SS capacitor, CSS, it is
important to program the primary IC’s soft-start faster,
to get out of the way. If this is not done, the converter’s
soft-start time will be dominated by the primary IC’s soft
start, and the LT8311 will simply adjust its SS pin voltage
and slew rate to match the slower soft start time set by
the primary-side IC.
When the SS pin voltage gets higher than the 1.227V refer-
ence, the FB pin starts to track the 1.227V reference. The
output, therefore, regulates at a voltage set by the RFB1/
RFB2 divider network, and the FB pin’s regulation voltage
of 1.227V. The SS pin capacitor continues to get charged
up by the 10µA current source until it reaches its internal
clamp voltage of 2V.
OPERATION
Figure 8. The LT8311 Provides Voltage Feedback, as Part of a Peak Current Mode Control System, in a Forward Converter
VIN VOUT
COUT
CG
FG
LOUT
NS
NP
+
VC IS ALSO
REFERRED TO
AS COMP IN SOME
PRIMARY-SIDE ICs
VREF
VC
+
R2
R1
A3
A4
LT8311 OPTO CONTROL
1V
+
140k
20k
A2
COMP
1.227V
10µA
1.227V
+
+
2k
0.9V
FB
SS
RFB1
CPL
RFB2
CC
RC
RLOAD
CF
A1
CSS
RSNS
RD
GAIN
OPTO
8311 F08
11
14
10
9
+
MCG
M1
MFG
RE
LT8311
22
8311f
For more information www.linear.com/LT8311
With SS charged up to 2V, the transconductance error
amplifier, A1, sinks or sources current from its output,
COMP, if there is any voltage difference between the FB pin
voltage and the 1.227V reference. The COMP pin, offset
by 0.9V, serves as the input to the opto-driver, A2. If an
increase in output load current causes the FB pin voltage
to be lower than 1.227V, A1 drives the COMP pin high.
COMP going high forces A2 to drive OPTO low, sourcing
less current through RD into the opto-coupler.
Since an opto-coupler’s output current is directly propor-
tional to its input current, this decreased input current for
the opto-coupler will cause its output current, and therefore
its emitter voltage at RE, to decrease as well. The drop
in RE voltage causes A3, through its inverting action, to
drive its output, VC, higher. An increase in the VC voltage
causes the comparator, A4, to command a higher sense
voltage across the RSNS resistor, commanding M1 to run
at a higher peak current. Since the current through M1 is
Figure 9. Flowchart for LT8311 Opto Control Operation at Start-Up
COMP < 2.2V
NO
SS PULL-DOWN AMPLIFIER ENABLED
OPTO-DRIVER ACTIVATION
8311 F09
1. ERROR AMP DISABLED: COMP PIN VOLTAGE CHARGED UP TO COMP HI CLAMP = 2.2V; tRISE 1.1 • 10kΩ • CC
2. SS PULL-DOWN AMPLIFIER DISABLED
3. SS PULL-UP AMPLIFIER ACTIVATED. THIS AMPLIFIER ONLY HAS SOURCING CAPABILITY (1mA SLEW CURRENT), AND
WILL DRIVE SS PIN VOLTAGE CLOSE TO FB PIN VOLTAGE (VFB – VSS 16mV)
4. SS 10µA CHARGE CURRENT ACTIVATED
5. OPTO-DRIVER DISABLED: OPTO PIN VOLTAGE HELD AT 0V
OPTO-DRIVER DEACTIVATION
VIN > 3.7V
1. SS PULL-UP AMPLIFIER DISABLED
2. SS PULL-DOWN AMPLIFIER ENABLED: THIS AMPLIFIER ONLY ACTIVATED WHEN FB PIN VOLTAGE IS LESS THAN 50%
OF FB REFERENCE VOLTAGE. THIS AMPLIFIER ONLY HAS SINKING CAPABILITY (12mA SLEW CURRENT) AND WILL
DRIVE SS PIN VOLTAGE TO BE NO HIGHER THAN 90mV ABOVE FB
1. ERROR AMP ENABLED: ERROR AMP CAN NOW DRIVE COMP BASED ON COMPARING FB VOLTAGE WITH SS VOLTAGE
OR 1.227V REFERENCE
2. OPTO-DRIVER ENABLED: OPTO-DRIVER CAN NOW DRIVE OPTO PIN AS A FUNCTION OF COMP PIN VOLTAGE
SS > FB – 16mV
YES
YES
NO
OPERATION
LT8311
23
8311f
For more information www.linear.com/LT8311
directly proportional to the output inductor current (M1
CurrentNP/NS = ILOUT), an increase in M1’s peak current
translates into an increase in the output inductor’s peak
current. In essence, the feedback loop is commanding
the output inductor peak current to meet the demands
of the increased load current, with the ultimate goal of
helping the output voltage recover from a load step and
stay regulated.
Opto-Control Operation at Start-Up
For applications connecting the LT8311’s VIN pin directly
to the converter output, the LT8311 includes intelligent
circuitry to ensure no interruption in the switching of
the primary-side MOSFET upon the LT8311’s turn-on.
The LT8311 turns on when its VIN pin (and therefore the
converter output voltage when VIN is directly connected to
the output) exceeds 3.7V. Without intelligent circuitry, this
VOUT level will cause the FB pin voltage of the LT8311 to
be greater than the voltage on the LT8311’s SS pin (which
is typically at 0V upon turn-on of the IC), causing ampli-
fier A1 to drive the COMP pin low. This drives the OPTO
pin high, which causes full current into the opto-coupler
and terminates switching of the primary-side MOSFET.
Termination of the primary-side MOSFET’s switching can
lead to the converter’s output voltage dropping, which
could cause the LT8311 to lose power and shut off. The
LT8311’s intelligent circuitry prevents this situation using
two unique features. It has a built-in 100mV hysteresis on
Figure 10. Opto Control Operation at Start-Up Figure 11. Power Good Activates (PGOOD = Low) When the
LT8311s FB Pin Voltage Is Within ±7% of Its Regulated Target
(1.227V). The PGOOD Pin Is Pulled Up Externally to a 12V
Housekeeping Supply Through a 100k External Resistor
its VIN UVLO voltage, so that upon getting power, it can
tolerate up to a 100mV drop on its VIN pin before losing
power again. Even more importantly, the LT8311 has an
opto-control start-up system that keeps the LT8311’s
“opto-control brains” turned off until all relevant node
voltages within the voltage loop are prebiased to a state
where they will not cause switching activity to cease when
the loop is eventually enabled.
As shown in Figure 9 and the scope shot in Figure 10,
the LT8311’s opto-control operation at start-up involves
slewing the SS pin voltage close to the FB pin voltage,
slewing the COMP pin voltage to its high clamp voltage,
and keeping the OPTO pin voltage held low. During this
phase, the inductor current (and by extension, the output
voltage) is controlled by the soft-start function provided by
the primary-side IC. Upon completion of the state machine,
the LT8311 allows the feedback loop to be functional again,
and the FB pin voltage tracks the LT8311’s SS pin voltage
until FB finally gets to its regulation target of 1.227V.
Power Good
The LT8311 offers output power good monitoring to
assist with system level design. The LT8311’s PGOOD
pin is pulled low internally when the FB pin voltage stays
within a ±7% window of the 1.227V reference for a period
of 175µs. Waiting for 175µs to elapse prevents the PGOOD
pin from indicating false positives during transient events.
OPERATION
COMP
1V/DIV
SS
200mV/DIV
FB
200mV/DIV
OPTO
500mV/DIV
8311 F10
5ms/DIV
PGOOD
5V/DIV
FB
500mV/DIV
8311 F11
2ms/DIV
LT8311
24
8311f
For more information www.linear.com/LT8311
OPERATION
The PGOOD comparator has ±3% hysteresis. Therefore,
when the FB pin voltage is driven away from its regulated
value of 1.227V by ±10%, the PGOOD pin’s internal pull-
down shuts off immediately. As a result, the pin is pulled
high by an external resistor or external current source
connected to a supply voltage. The PGOOD pin’s output
can be fed to a microcontroller that make decisions based
on the state of the output voltage.
Output Overshoot Control Helps with Short-Circuit
Recovery
The LT8311 provides output overshoot control by activating
its soft-start pull-down amplifier (SSDOWNAMP in the Block
Diagram) any time the FB pin voltage is less than 50%
of the FB reference voltage (1.227V). This is particularly
helpful with output voltage recovery after the removal of
a short-circuit condition or after a heavy load transient.
The SS pull-down amplifier will sink whatever current is
necessary (up to its maximum sink capability of 13mA), to
ensure that the SS pin voltage gets no higher than 100mV
above the FB pin voltage. During output short-circuit events,
when the FB pin voltage is pulled to ground, the SS pull-
down amplifier gets activated and pulls the SS pin voltage
to 100mV above the FB pin voltage. Eventually, when the
short-circuit condition is over, the FB pin voltage gradually
rises up with the SS pin at a slew rate set by CSS and the
10µA charge current. This allows the output to recover
gradually from the short-circuit condition. Note that when
the LT8311 has its VIN pin powered directly from the output
of the forward converter, it will lose all its brains during a
short-circuit event. Under this scenario, output overshoot
control will not be in effect until the LT8311 gets brains
again, until which point, the output inductor current and
the output voltage will be controlled by the primary-side
IC’s soft-start function.
(a) Output Overshoot Control with CSS = 1nF. LT8311 VIN
Powered from a 12V Housekeeping Supply, Which Also
Pulls Up on the PGOOD Pin Through a 100k External
Resistor
(b) Output Overshoot Control with CSS = 33nF. LT8311 VIN
Powered from a 12V Housekeeping Supply, Which Also Pulls
Up on the PGOOD Pin Through a 100k External Resistor
Figure 12. Output Overshoot Control at Start-Up
PGOOD
10V/DIV
SS
500mV/DIV
FB
500mV/DIV
8311 F12a
1ms/DIV
PGOOD
10V/DIV
SS
500mV/DIV
FB
500mV/DIV
8311 F12b
2ms/DIV
LT8311
25
8311f
For more information www.linear.com/LT8311
APPLICATIONS INFORMATION
VIN BIAS SUPPLY
The LT8311’s VIN pin can be powered in various ways.
Place at least a 2.2µF ceramic bypass capacitor close to
the pin.
Picking an appropriate bias supply to power up the LT8311
requires consideration of the following criteria:
1. The VIN pin, in certain configurations, may be the only
supply to the LT8311’s INTVCC pin, which provides
gate drive to the catch and forward MOSFETs. In such
situations, VIN’s bias supply must be high enough to
provide adequate gate-drive voltage (typically 5V to 7V)
for both synchronous MOSFETs.
2. VIN’s bias supply must be able to source:
a. LT8311’s VIN current (4.5mA typical)
b. INTVCC gate-drive current when using VIN to sup-
ply the INTVCC pin (typically 10mA to 30mA)
c. Opto-driver source current (typically 1mA to 5mA)
3. VIN start-up and short-circuit conditions:
a. VIN must come up in reasonable time to allow the
LT8311 to begin synchronous and opto-coupler
control. While synchronous control is shut off, the
secondary-side current will flow through the body
diodes of the secondary synchronous MOSFETs.
While opto-control is off, the forward converter
will operate open-loop, using a volt-second clamp
to control VOUT if operating with LT3752, LT3752-1
or LT3753 on the primary side.
b. VIN may be shorted to GND during transient events.
For instance, VIN powered from the output voltage,
will be driven to 0V during an output short-circuit.
The forward converter must be able to ride through
the momentary loss of power to the LT8311, which
is often easily accomplished by appropriately
configuring soft-start control on the primary-side
ICs. Refer to the LT3752/LT8310 data sheets for
details on configuring soft-start control on the
primary-side IC.
With the previous criteria in mind, there are three meth-
ods (1-3), listed below, for powering up the LT8311. For
preactive mode, use method 1, 2 or 3. For SYNC mode
FCM, use method 1 or 3; for DCM, use method 1, 2 or 3.
1. Power from the LT3752’s housekeeping supply (see
Figure 21 in the Typical Application section). Being
a flyback converter rather than a LDO, the LT3752’s
housekeeping supply is an efficient supply source. It
can be connected through an external winding to the
LT8311’s VIN and INTVCC pins, and can be set high
enough to provide adequate gate drive for the catch
and forward MOSFETs, but low enough to minimize
efficiency and thermal losses. The housekeeping supply
comes up as soon as the LT3752 receives input power,
so power is delivered to the LT8311 without delay.
2. Power directly from VOUT. At output voltages lower
than 10V, careful consideration must be given to the
output voltage start-up time, ensuring that the LT8311
can turn on and provide synchronous/opto control well
before the output voltage approaches regulation. It is
also important to ensure, at these lower output voltages,
that sufficient gate drive voltage can be provided to the
external MOSFETs. At higher VOUT voltages, efficiency
and thermal considerations related to the IC’s internal
power dissipation can become important criteria. In
addition, at higher VOUT voltages, it is important to
ensure that voltage transients on the VIN pin do not
exceed the pin’s abs max rating of 30V.
3. Use a buck circuit from an auxiliary transformer wind-
ing, as shown in Figure 13. This circuit has the benefit
of being highly efficient, and is fairly simple to design.
It is particularly useful for low output voltage applica-
tions (3.3V or 5V) that do not have an external house-
keeping supply, and where powering directly from the
output voltage is inadequate. In this configuration, the
buck circuit’s output voltage derives its energy from
secondary-side switching pulses that also source energy
to the forward converter’s main output voltage, VOUT.
Careful consideration must be given to ensure that the
buck output voltage comes up well in time, and turns
on the LT8311 to provide synchronous and opto control
before the forward converter’s actual output voltage
gets close to regulation. If there is a need to speed up
LT8311
26
8311f
For more information www.linear.com/LT8311
APPLICATIONS INFORMATION
the time taken by the buck converter output voltage to
get to its target, relative to the forward converter’s main
output voltage, often a simple technique is to slow down
the main output voltage start-up time by increasing the
soft-start capacitor on the primary-side IC.
INTVCC BIAS SUPPLY
The INTVCC pin powers the catch and forward MOSFET
gate drivers of the LT8311. Two configurations exist for
biasing up the INTVCC pin, as shown in Figure 14:
1. In the first configuration, the LT8311’s on-chip LDO
regulates the INTVCC pin voltage from the VIN supply.
When the VIN pin voltage is low, the internal LDO will
operate in drop-out, driving the INTVCC pin to about
400mV below the VIN pin voltage. When the VIN pin
voltage is high, the internal LDO will regulate INTVCC’s
voltage to 7V. Ensure that VIN’s supply voltage does not
exceed VIN’s abs max voltage of 30V. If INTVCC drops
below its UVLO voltage (4.6V rising and 4.3V falling), all
synchronous switching will be stopped. The maximum
guaranteed current that the INTVCC LDO can source is
Figure 13. Buck Circuit Generates VAUX Supply, Which
Powers LT8311’s VIN and INTVCC Pins
Figure 14. VIN and INTVCC Pin Configurations
8311 F13
VIN
BUCK AUXILLIARY SUPPLY
NS
NP
VOUT
VAUX LT8311
NAUX
VIN
INTVCC
VAUX =VOUT NAUX
NS
MCG
M1 MFG
40mA. Ensure that the total gate charge (Qg) current
required by both secondary MOSFETs, MCG and MFG,
is less than 40mA:
IMOSFET_TOTAL = fSW • (Qg_MCG + Qg_MFG) < 40mA
where fSW is the converter’s switching frequency,
Qg_MCG is the gate charge (Qg) rating of MCG and Qg_MFG
is the gate charge (Qg) rating of MFG.
This configuration, utilizing the LT8311’s internal LDO,
will suffice for most applications, limited only by thermal
considerations related to the LDO’s power dissipation.
Keeping the power dissipation to a minimum will help
lower the operating junction temperature of the LT8311,
potentially allowing the system to operate over a wider
ambient temperature range:
LDO Power Dissipation = (VININTVCC) • IMOSFET_TOTAL
LT8311 Operating Junction Temperature ≈
θJA • (VIN • 4.5mA + LDO Power Dissipation + VIN
IOPTO) + TA
where θJA is LT8311’s junction-to-ambient thermal
resistance and is typically 38°C/W; IOPTO is the current
8311 F14
INTVCC
VIN VIN < 30V
REGULATED to 7V
LT8311
LDO
4.7µF
INTVCC
VIN VIN < 16V
LT8311
LDO
4.7µF
LT8311
27
8311f
For more information www.linear.com/LT8311
APPLICATIONS INFORMATION
sourced into the opto-coupler by the LT8311’s OPTO
pin; 4.5mA is the typical VIN current of the LT8311;
TA is the ambient temperature.
2. In the second configuration, the VIN pin’s bias supply
drives the INTVCC pin through a direct connection,
bypassing the internal LDO. This configuration re-
duces power dissipation inside the IC by not having to
incur any power loss within the INTVCC LDO. Use this
optional configuration for VIN voltages that are below
16V, allowing sufficient margin for INTVCC to stay below
its OVLO(+) voltage of 16.5V. Ensure that VIN, during
transients, does not exceed INTVCC’s abs max voltage
of 18V.
When an external supply or auxiliary winding is available,
use this configuration (tying VIN and INTVCC together)
to deliver power to the IC. This configuration is most
applicable when using the LT3752 as a primary-side IC.
The LT3752’s housekeeping supply can be connected
to the LT8311’s VIN and INTVCC through an auxiliary
winding, as shown in Figure 21 in the Typical Applica-
tions section.
INTVCC should be bypassed with a minimum of 4.7µF
ceramic capacitor to ground for all three configurations.
Place the capacitor close to the INTVCC pin, ensuring that
the ground terminal of the capacitor has the shortest pos-
sible return path to the LT8311’s ground (exposed pad).
LT8311 OPTO CONTROL FUNDAMENTALS
Setting Output Voltage
Figure 15 shows how to program the forward converter’s
output voltage with a resistor divider feedback network.
Connect the top of RFB1 to VOUT, the tap point of RFB1/
RFB2 to the FB pin, and the bottom of RFB2 to ground. The
ground return of RFB2 must be kept as close as possible to
the ground of the LT8311, and must be kept away from the
forward converter’s power path. The power path contains
switching currents, and possibly large value currents (de-
pending upon the load) which may introduce unintended
noise, or IR drops into the FB resistor divider path. The
FB pin regulates to 1.227V and has a typical input pin
bias current of 120nA flowing out of the pin. The output
voltage is set by the formula:
VOUT =1.227 1+RFB1
R
FB2
120nA RFB
1
Figure 15. Setting Output Voltage of Forward Converter
8311 F15
GND
FB
LT8311
VOUT
120nA
RFB2
RFB1
LT8311
28
8311f
For more information www.linear.com/LT8311
Figure 16. Forward Converter Voltage Feedback Loop with LT8311 on Secondary Side and LT3752 (or) LT8310 on Primary Side
APPLICATIONS INFORMATION
VCC(OPTO)
VIN(LT8311) – 1.7V < VCC(OPTO) < 6V
gmEA = 350umhos
ROUTEA = 4.5MΩ
MAX OPTO SOURCE
CURRENT = 10mA MAX COMP SRC CURRENT = 20µA
MAX COMP SINK CURRENT = 30µA
VIN VOUT
COUT1
CG
FG
LOUT
COUT2
IOUT
NS
NP
+
RE
VX
COMP/VC VOLTAGE TO COMMAND 0
RSNS CURRENT 1.25V, 0.7V
COMP/VC VOLTAGE TO COMMAND MAX
RSNS CURRENT 2V, 1.2V
TRUE VOLTAGE AMP
TRANSCONDUCTANCE AMP
ISENSEP
(SENSE)
FB
(FBX)
OUT
(GATE)
VREF = 1.25V, 1.60V
MAX COMP/VC SRC CURRENT ~ 11mA, 13µA
MAX COMP/VC SINK CURRENT 11mA, 12.5µA
R2 (TYPICAL) 33k, 150k
VREF
COMP
(VC)
+
R1
LT8311
1V
+
140k
20k
COMP
1.227V
+
2k
0.9V
FB
RFB1
CPL
RFB2
CC
RC
RLOAD
CF
RSNS
RD
RIN(OPTO) = 1/gm(OPTO)
LT3752 OR LT8310
OPTO
8311 F16
IPRIMARY
VISENSEP
VCOMP_PRIMARY
IOPTO_OUT
COPTO
IF
+
CURR_GAIN =
7.5V/V, 5V/V
R2 R1 = R2 / GAIN
1 < GAIN (TYPICAL) < 2
MF
RESR
MCG
M1
MFG
Picking Loop Compensation Components
Figure 16 shows a typical loop associated with a forward
converter, using the LT8311 on the secondary side, and
the LT3752 or LT8310 as the primary-side ICs. Parametric
values specific to the LT3752 are shown in red, while those
specific to the LT8310 are shown in blue. The forward con-
verter loop shown is a peak current mode control system.
The optimum values for loop compensation depend on
the IC used on the primary side and the LT8311, as well
as the operating conditions of the converter (input voltage
range, output voltage, load current, etc.). To compensate
the voltage feedback loop around the LT8311, a series
resistor/capacitor network is usually connected from the
LT8311's COMP pin to GND. For most applications, the
capacitor CC should be in the range of 4.7nF to 47nF, and
the resistor RC should be in the range of 2k to 20k. If the
RC value is too large, the part will be more susceptible to
high frequency noise and jitter. If the RC value is too small,
the transient performance will suffer. The value choice
for CC is somewhat the inverse of the RC choice: if too
small a CC value is used, the loop may be unstable and
if too large a CC value is used, the transient performance
may suffer. A small capacitor, CF, is often connected in
parallel with the RC compensation network to attenuate
the COMP pin voltage ripple induced from the output
voltage ripple (through the internal error amplifier). The
CF capacitor usually ranges in value from 10pF to 100pF.
For certain applications, a phase-lead zero capacitor CPL
(in parallel with RFB1 resistor), or a pole-zero pair (COPTO
and RD) on the OPTO pin may help improve the transient
performance of the loop. A practical approach to design
the compensation network is to start with one of the
circuits in this data sheet that is similar to your applica-
tion, and tune the compensation network to optimize the
performance. Stability should then be checked across all
operating conditions, including load current, input voltage
range and temperature.
LT8311
29
8311f
For more information www.linear.com/LT8311
APPLICATIONS INFORMATION
Picking the Opto-Coupler
The voltage feedback loop, explained earlier, uses an
opto-coupler to convey output voltage information from
the secondary side to the primary side (see Figure 17).
An opto-coupler is used because of its wide prevalence,
relatively low cost, and its ability to convey DC signal
information over an isolation boundary with potential
differences of up to 5000V.
The input of an opto-coupler typically consists of an
infrared light-emitting diode (LED), while the output
is typically a phototransistor. Current flowing into the
opto-coupler’s input LED, called IF, causes photons to
be emitted. These photons cross the opto-coupler’s
isolation barrier and get collected in the base of the output
phototransistor. This photo current, which essentially
forms the phototransistor’s base current, is gained up
by the phototransistor’s ß (current gain) before flowing
out of the opto-coupler, and is called IOPTO_OUT. The key
parameter of interest in an opto-coupler is the current
transfer ratio (CTR). CTR is typically expressed in units
of %, and is calculated as follows:
CTR(%) =
I
OPTO_OUT
I
F
Figure 17. Typical Opto-Coupler Configuration in a Voltage Feedback Loop
8311 F17
IOPTO_OUT
IF
PRIMARY SIDE
OF VOLTAGE
FEEDBACK LOOP
VCC
OPTO
RE
PRIMARY
SIDE
SECONDARY
SIDE
LT8311
OPTO-
COUPLER
ISOLATION
BOUNDARY
RD
where IOPTO_OUT is the output current of the opto-coupler
and IF is the opto-coupler’s input LED current
Opto-couplers have historically been disliked, and jus-
tifiably so, for having CTRs that degrade with operating
lifetime, at higher operating temperatures, and at higher
input currents (IF). Much of this CTR degradation comes
from a reduction in the quantum efficiency of the input
LED, which is a function of the LED’s operating current
(IF), operating temperature and operating lifetime.
Fortunately, LED technology has matured over the last
couple of decades, and has allowed improvements in opto-
coupler performance, a discussion of which is beyond the
scope of this data sheet. Avago Technologies has published
documentation showing 3-sigma CTR degradation of no
more than 10% over 30 field years of operation for their
opto-couplers manufactured with AlGaAs type LEDs run-
ning 5mA of input current (IF) at 100% duty cycle, and at
85°C ambient temperature.
Please refer to the application/design notes from opto-
coupler vendors such as Avago Technologies, CEL and
Vishay, to procure further information on opto-couplers.
A typically recommended opto-coupler is the PS2801 from
California Eastern Laboratories (CEL).
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Opto-Coupler Design Guidance
An opto-coupler’s CTR degradation affects a forward
converter’s voltage feedback loop in two ways:
1. Large Signal Effect: A drop in CTR means that to sus-
tain the same output current from the opto-coupler,
the input current of the opto-coupler will have to increase.
The input current of the opto-coupler is sourced by the
LT8311’s OPTO pin. The opto-feedback loop should
be designed such that, at the lowest CTR possible, the
LT8311’s OPTO pin is not current limited. The maxi-
mum current that the LT8311’s internal opto-driver can
source out of the OPTO pin is 10mA. Design the system
so that, nominally, the OPTO pin is sourcing 2mA to
3mA maximum current into the opto-coupler’s input.
2. Small Signal Effect: A reduction in CTR by 2x will
cause the DC gain and crossover frequency of the for-
ward converter’s voltage feedback loop to drop by 2x,
assuming all other parameters are constant. Likewise,
an increase in CTR by 2x, assuming no change in other
parameters, will cause the DC gain and the crossover
frequency of the voltage feedback loop to increase
by 2x. The voltage feedback loop must be designed
ensuring that at CTR(MAX) (maximum CTR of the opto-
coupler), the crossover frequency of the feedback loop
stays well within the Nyquist frequency of the system
(= switching frequency/2). A good rule of thumb is to
design the voltage feedback loop’s crossover at about
1/10 of the switching frequency for an opto-coupler at
the nominal value of CTR.
As explained earlier, improvements in opto-coupler
technology have allowed CTR changes over the operating
lifetime of an opto-coupler to become significantly smaller
and well controlled. However, the more challenging design
aspect of an opto-coupler is the absolute variation in its
CTR over a large sample size and operating temperature
range. It is this spread in CTR that must be accounted for
when designing an opto-coupler based voltage feedback
loop. Picking an opto-coupler whose CTR variation is no
more than 2x its nominal value, is typically a good starting
point (see Table 1 for a list of opto-couplers with small
CTR spreads at room temperature).
The following guidelines help calculate initial values for
the input and output resistors of the opto-coupler (RD and
RE, respectively) for a generic application. The final values
for RD and RE should be determined after bread-boarding
a system. Use Figure 16 as a reference when reading the
following guidelines:
Step 1:
Pick resistors, R1 and R2, that set the inverting
gain of the primary-side IC’s error amplifier. A typical
starting value for R1 would be 22k on the LT3752, and
100k on the LT8310. A typical starting value for R2 would
be 33k on the LT3752, and 150k on the LT8310.
Step 2:
Calculate the maximum voltage required at the
emitter of the opto-coupler's output transistor (VX_MAX) to
drive the primary-side IC’s COMP or VC pin to the voltage
needed to command zero inductor current (referred to as
VC_LOW in the following equation):
VX _MAX =VREF 1+
R1
R2
VC_LOW
R1
R2
VC_LOW is approximately 0.7V for the LT8310, and 1.25V
for the LT3752. VREF is 1.6V for the LT8310 and 1.25V
for the LT3752.
Step 3:
Pick a maximum opto-coupler output current
(IOPTO_OUT_HIGH) in the range of 1mA to 10mA. A typical
choice for IOPTO_OUT_HIGH might be 2.5mA. Now calculate
RE to be:
RE=
V
XMAX
IOPTO_OUT _HIGH
Step 4:
Estimate the maximum input current (IF_HIGH)
needed to be sourced into opto-coupler by the
LT8311’s OPTO pin, at the opto-coupler’s minimum CTR
(CTRMIN):
IF _HIGH =
I
OPTO_OUT _HIGH
CTR
MIN
Ensure that IF_HIGH is well within the 10mA limit that the
LT8311’s OPTO pin can source.
Step 5:
Estimate the RD value needed for the OPTO pin
to source the IF_HIGH current at the maximum OPTO pin
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voltage (VOPTO(MAX)). The opto-coupler’s input LED has
a turn-on voltage of 1.2V:
RD=
V
OPTO(MAX)
1.2V 0.5V
IF _HIGH
The extra 0.5V in the equation is margin to account for the
OPTO pin's linear range. The maximum OPTO pin voltage
is 6V (minimum guaranteed), when the LT8311’s VIN pin
is at 8V or higher. At lower VIN pin voltages, VOPTO_MAX
is VIN – 1.7V.
The previous equations show how RD and RE ought to
be calculated for large signal characteristics of an opto-
coupler-based voltage feedback loop. The final values
chosen for RD and RE may need to be tweaked from the
values calculated here to achieve a satisfactory compromise
between the large and small signal characteristics of the
voltage feedback loop.
Picking Soft-Start Capacitor (CSS) for Output Soft-Start
The Operation section explained how the LT8311’s SS
pin helps with output soft-start at start-up, with output
overshoot control during short-circuit recovery, and to
prebias the voltage feedback loop during start-up of the
LT8311’s opto-control scheme. The soft-start capacitor,
CSS, is charged by the LT8311’s internally trimmed 10µA
current source at start-up. Since the FB pin voltage tracks
the SS pin voltage when the voltage on SS is below 1.227V,
setting the SS pin’s slew rate will set the FB pin’s slew
rate, setting the time taken by the output to come up to
its regulation voltage. It is important to recognize that the
tracking between the SS pin’s slew rate and the FB’s pin
slew rate is only valid as long as the LT8311’s soft-start of
output voltage is slower than the primary-side IC’s soft-start
of output voltage, as explained in the Operation section.
By observing this criteria, the following equation applies:
V
OUT
t=
V
FB
t=
10µA
C
SS
where CSS is the capacitor from the LT8311’s SS pin to
GND, VOUT is the output voltage of the forward converter,
and VFB is the LT8311’s FB pin voltage.
In steady state, the SS pin voltage is clamped to a maxi-
mum of 2V by an internal clamp.
LT8311 SYNCHRONOUS CONTROL FUNDAMENTALS
Catch and Forward MOSFET Selection
When selecting the secondary-side synchronous MOSFETs,
it is important to choose the following parameters care-
fully to ensure robust operation of the system: maximum
drain-source voltage, maximum drain-source current and
maximum gate-source voltage. Furthermore, to maximize
system efficiency, it is important to lower power dissipation
in the MOSFETs by minimizing their on-resistance (RDS(ON))
and gate charge (Qg). Please use the following guidelines
to choose appropriate catch and forward MOSFETs for a
specific application:
1. Maximum VDS Rating
The maximum voltage seen on the drain of the catch MOS-
FET is a function of the maximum input voltage (VIN(MAX))
of the system, and the transformer turns ratio (NS/NP).
Catch MOSFET VDS(MAX) = VIN(MAX)
N
S
NP
Margin
where Margin is a number from 1 to 3 (typically 1.5 to 2),
allowing a certain safety margin in the catch MOSFET’s
VDS(MAX) equation. This will account for voltage spikes as-
sociated with the leakage inductance of the transformer’s
secondary winding. Using a snubber on the drain of the
catch MOSFET will minimize leakage inductance spikes
and allow Margin to approach the lower end of its range.
The maximum voltage seen on the drain of the forward
MOSFET is a function of the reset mechanism used on
the primary side of the forward converter to reset the
transformer’s magnetic flux.
When using active clamp reset:
Forward MOSFET VDS(MAX)
V
OUT
1VOUT
VIN(MIN) NS
NP
where VIN(MIN) is the minimum input voltage of the system,
and VOUT is the forward converter’s output voltage. Note
that this equation for the forward MOSFET’s VDS(MAX)
assumes that the primary side’s active clamp capacitor
(CCL) is large enough to be treated as a voltage source.
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In reality, the drain voltage of the forward MOSFET will
have somebowing” over and above the voltage calculated
here, associated with the energy shuttled between LMAG
and CCL during the reset process. For most applications,
this bowing can be accounted for by adding a 20% safety
margin on the forward MOSFET’s VDS(MAX) equation.
When using resonant reset:
Forward MOSFET VDS(MAX)
V
OUT
fSW 2 LMAG CRST
where fSW is the forward converter’s switching frequency,
LMAG is the magnetizing inductance of the transformer’s
primary winding, and CRST is the resonant reset capacitor
used on the primary side.
Unlike the catch MOSFET, the VDS(MAX) equation of the
forward MOSFET typically does not need to account for
leakage inductance voltage spikes. This is because the turn-
on and turn-off events of the forward MOSFET, typically,
do not involve the forward MOSFET’s drain having to dis-
sipate large amounts of stored leakage inductance energy.
2. Maximum IDS Rating
Most power MOSFET data sheets have a rating for
continuous-drain current, and pulse-drain current.
Continuous-drain current is the RMS drain current of the
catch and forward MOSFET, which is a function of the
inductor current, and the duty cycle at which the forward
converter is operating. Pulse-drain current is the
instantaneous maximum drain current seen by the MOSFETs,
and is typically the peak of the inductor current waveform.
Prior to calculating the maximum continuous-drain cur-
rent, it is useful to calculate the minimum, maximum and
average duty cycles of the forward converter:
DMIN =
V
OUT
VIN(MAX) NS
NP
DMAX =VOUT
VIN(MIN) NS
NP
DAVG =DMAX +DMIN
2
where VIN(MAX) and VIN(MIN) are the maximum and mini-
mum input voltages of the forward converter.
The catch MOSFET’s maximum continuous drain current,
ICAT_RMS, can be calculated as:
I
CAT _RMS =1DMIN
( )
ILOAD(MAX) 2+IRIPP(PP) 2
12
where DMIN is the minimum duty cycle of the forward
converter, ILOAD(MAX) is the maximum output load current
of the forward converter, and IRIPP(P-P) is the peak-to-
peak ripple current in the output inductor. IRIPP(P-P) is
calculated as follows:
IRIPP(PP) =VOUT
1D
AVG
fSW LOUT
where DAVG is the average duty cycle of the forward con-
verter, fSW is the converter’s switching frequency, and
LOUT is the output inductance value.
The forward MOSFET’s maximum continuous-drain current
(IFWD_RMS) is:
IFWD_RMS =DMAX ILOAD(MAX) 2+IRIPP(PP) 2
12
Both, the forward and catch MOSFET should have a peak
pulse current rating that is higher than the highest pos-
sible peak of the inductor current. This highest possible
peak occurs at the maximum load current, and is equal to:
ILOAD(MAX) +
I
RIPP(PP)
2
3. Maximum VGS Rating
As explained earlier in the INTVCC Bias Supply section,
INTVCC is regulated internally to 7V by the LT8311. By
extension, the catch and forward MOSFET gates can be
driven as high as 7V when using the LT8311’s internal LDO
to regulate INTVCC. For applications using the LT8311’s
internal LDO, picking a maximum VGS greater than 10V
should suffice.
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Alternatively, the INTVCC pin can be overdriven externally
up to 16V. For such applications, picking MOSFETs with
a maximum VGS of ±20V should suffice.
4. Calculating MOSFET Losses Due to RDS(ON)
The conduction/ohmic loss associated with the catch and
forward MOSFET is a function of the MOSFET’s RMS cur-
rent and its on-resistance. For the vast majority of forward
converter applications, which typically have high maximum
load currents on the output (5A or higher), minimizing
losses associated with the MOSFET’s RDS(ON) will be far
more critical than minimizing losses associated with the
MOSFET’s gate charge.
Catch MOSFET Ohmic Loss = (ICAT_RMS)2 • RCAT
where RCAT is the on-resistance (RDS(ON)) of the catch
MOSFET.
Forward MOSFET Ohmic Loss = (IFWD_RMS)2 • RFWD
where RFWD is the on-resistance (RDS(ON)) of the forward
MOSFET.
5. Calculating Qg Based Loss
There are two aspects to the gate charge (Qg) based loss
associated with the secondary synchronous MOSFETs:
A. Qg Based MOSFET Switching Loss:
The catch MOSFET’s turn-on and turn-off timings,
regardless of preactive or SYNC mode, are ZVS (zero
voltage switching) events. The catch MOSFET turns on
after the inductor current is already flowing through its
body diode. Similarly, when the catch MOSFET turns
off, the inductor current subsequently flows through its
body diode. As a result, the voltage across the drain-
source terminals of the catch MOSFET is small during
switching events, resulting in the catch MOSFET having
insignificant switching loss.
The forward MOSFET’s turn-on and turn-off timings,
regardless of preactive or SYNC mode, are ZVS (zero
voltage switching) and ZCS (zero current switching)
events, respectively. The forward MOSFET turns on
after transformer reset is complete. Transformer reset
completion is marked by the transformer’s magnetizing
current flowing through the forward MOSFET’s body
diode, which allows the forward MOSFET to turn on with
a small drain-to-source voltage across it. Similarly, the
forward MOSFET typically turns off after the primary-
side MOSFET has turned off. When the primary-side
MOSFET turns off, the only current flowing through
the forward MOSFET is the transformer magnetizing
current, which for all intents and purposes, can be as-
sumed to be zero. Consequently, the forward MOSFET
has insignificant switching losses.
B. Qg Based Converter Power Loss:
As explained earlier in the INTVCC Bias Supply section,
there is a power loss incurred in turning on/off the catch
and forward MOSFETs, associated with supplying gate
charge (Qg) to the gates of these MOSFETs. This charge
is supplied either by the supply voltage connected to
the LT8311’s VIN pin, when using the internal LDO to
regulate INTVCC, or by the supply voltage connected
to the LT8311’s INTVCC pin, when driving the INTVCC
pin externally. In either case, the total loss associated
with supplying the gate charge is:
Power Loss = VSUPP • (QgCAT + QgFWD) • fSW
where VSUPP is the supply voltage connected to the
LT8311’s VIN pin when INTVCC is internally regulated.
Alternatively VSUPP is the supply voltage connected
to the LT8311’s INTVCC pin when INTVCC is externally
driven. QgCAT and QgFWD is the gate charge (Qg) of the
catch and forward MOSFETs, respectively. fSW is the
forward converter’s switching frequency.
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Setting RTIMER in Preactive Mode
In preactive mode, the TIMER pin resistor, RTIMER, pro-
grams the maximum period that can elapse between two
CSW rising edges before a timeout period is triggered.
Timeout allows the LT8311 to stop all synchronous activ-
ity in the event that the primary-side IC stops switching.
Since CSW rising edges represent primary-side switching
activity, timeout of CSW rising edges is interpreted as
stoppage of switching—at which point the LT8311 ceases
all secondary-side synchronous switching, and starts its
evaluation period. Refer to the Operation section for de-
tails on the evaluation period. Secondary-side switching
resumes when all conditions within the evaluation period
are satisfied. Timeout also ensures that switching activity
within preactive mode occurs at a frequency that is within
preactive mode’s operating frequency range.
As shown in Figure 18, every time the CSW pin voltage
is detected to rise past 1.2V from a voltage level below
–150mV, the LT8311 resets its internal timeout signal.
The gate of the catch MOSFET, CG turns on (after some
propagation delay) when CSW is detected to fall below
–150mV. Upon CG going high, the catch MOSFET turns
on and pulls its drain voltage (CSW) close to its source
voltage, which is tied to GND. CG turns off predictively
in CCM before an anticipated CSW rising edge. If a CSW
rising edge (rising from below –150mV to above 1.2V)
does not come along in time to reset the timeout signal,
the signal eventually charges up to voltage VREF_TIMEOUT
and triggers an internal timeout condition. Consequently,
the LT8311 shuts down all synchronous conduction and
starts the evaluation period. The evaluation period ends only
when the four conditions listed in the Operation section,
including the timely reset of the internal timeout signal,
are satisfied for three consecutive CSW rising edges. Upon
completion of the evaluation period, the LT8311 restarts
synchronous control.
Figure 18. If Timeout Is Triggered in Preactive Mode, LT8311 Shuts Down All Synchronous Conduction and
Starts the Evaluation Period (Note: CSW's ringing waveform is caused by the inductor current getting to 0A.)
0V
8311 F18
LT8311 INTERNAL
TIMEOUT SIGNAL
CG PREDICTIVE
TURN-OFF
TIMEOUT RESETS ONLY WHEN
CSW RISES PAST 1.2V, PRECEDED BY
FALLING BELOW –150mV
TIMEOUT
CSW
(PREACTIVE MODE)
CG
TIME
–150mV
1.2V
CG TURNS ON WHEN CSW < –150mV
EVALUATION PERIOD
VREF_TIMEOUT
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The TIMER resistor is typically picked to set a timeout
period that is 20% higher than the forward converter’s
nominal switching period.
Timeout =
1.20
fSW
where fSW is converter switching frequency in Hz.
Once a timeout period is calculated, the TIMER pin resis-
tor, RTIMER, can be calculated as follows:
RTIMER (kΩ) ~ 22.1E6 • Timeout
where Timeout has units of seconds.
The relationship between RTIMER and timeout is not per-
fectly linear. Table 1 shows RTIMER values (nearest 1%) for
a range of typical forward converter switching frequencies:
Table 1. RTIMER 1% Resistor Values for Different Forward
Converter Switching Frequencies
SWITCHING
FREQUENCY (kHz) TIMEOUT (µs) = 1.2/ fSW RTIMER (kΩ)
100 12 267
150 8 178
200 6 133
250 4.8 107
300 4 88.7
400 3 66.5
500 2.4 53.6
Setting the timeout period at 1.2 • Switching Period will
keep synchronous conduction shut off through frequency
foldback in preactive mode, until the switching frequency
approaches 80% of its final value. For 100kHz switching
applications, this means that the LT8311 is ready for
synchronous conduction in preactive mode, at 80kHz.
Although 80kHz is outside the LT8311’s data sheet specifi-
cations for preactive mode operating frequency range, the
IC is designed to operate down to 80kHz to ride through
such a frequency foldback event. Timeout may also shut
off synchronous conduction during CSW pulse-skipping
events at light output load currents.
Setting RTIMER in SYNC Mode
In SYNC mode, the functionality of the timeout period is
similar to preactive mode, except that the resetting of the
LT8311’s internal timeout signal happens every time the
SYNC pin voltage falls below –1.2V. The goal of the time-
out function in SYNC mode is primarily to limit the catch
MOSFET on-time in the event that the catch MOSFET stays
on too long and conducts an unsafe level of reverse-output
inductor current (current flows from the output capacitor
back towards the drain of the catch MOSFET). Refer to
the section, "Configuring CSP/CSN Inputs of the Current
Sense Comparators in SYNC Mode,” for further informa-
tion on what constitutes an unsafe level of reverse-output
inductor current.
In SYNC mode, set the timeout period to be 20% longer
than the longest switching period of the primary-side IC.
Typically, the longest switching period of the primary-
side IC corresponds to the smallest frequency foldback
frequency (fSW_SMALLEST):
Timeout =
1.2
fSW _SMALLEST
Once a timeout period is calculated, the TIMER pin resis-
tor, RTIMER, can be calculated as follows:
RTIMER(kΩ) ~ 22.1E6 • Timeout
where Timeout has units of seconds, and fSW_SMALLEST
is in units of Hz.
Configuring CSP/CSN Inputs of Current Sense
Comparator in Preactive Mode
The differential input current sense comparator in the
LT8311 is used to provide the IC with information about
the current in the catch MOSFET. Connect the CSP and
CSN pins, through series resistors, to the drain and source
of the catch MOSFET (MCG), to allow the LT8311 to sense
the drain-source voltage of MCG, and make inferences
about its current. Alternatively, CSP and CSN can be tied,
through series resistors, across a sense resistor which
is placed from the source of MCG to ground. As explained
earlier in the Operation section, the CSP and CSN pins
should be configured, in preactive mode, to trip at zero
current in the catch MOSFET. Since the current comparator
internally trips at 66mV, and the CSP pin sources 40µA,
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placing 1%, 1.65k resistors in series with CSP and CSN
should allow the LT8311 to trip with approximately zero
volts across the catch MOSFET. Note that the current
comparator has a propagation delay of 100ns nominally,
so the time taken from the current comparator getting
tripped to the catch MOSFET turning off is about 100ns.
During this 100ns, the current in the output inductor can
reverse and flow from the drain-to-source of the catch
MOSFET. If negative current flow in MCG is not desired, the
CSP pin series resistor can be chosen to trip at a positive
value of source-to-drain catch MOSFET current. The fol-
lowing equation allows calculation of the resistor (RCSP)
to be placed in series with the CSP pin for a desired value
of catch MOSFET trip current (ITRIP):
RCSP =
66mV I
TRIP
R
SNS
40µA
where RSNS is the RDS(ON) of the catch MOSFET when the
CSP and CSN pins are connected directly across the drain-
source terminals of the catch MOSFET. Alternatively, RSNS
is the sense resistor in the source of the catch MOSFET
if the CSP/CSN pins are connected directly across the
sense resistor. Once the resistor in series with the CSP
pin (RCSP) is decided, place an identical resistor in series
with the CSN pin.
Configuring CSP/CSN Inputs of the Current Sense
Comparator in SYNC Mode
The LT8311 is typically operated in SYNC mode when the
forward converter needs to be operated in FCM (forced
continuous mode). In SYNC mode, the LT8311 receives
synchronous control signals on its SYNC pin, through a
pulse transformer, from the primary-side IC’s SOUT pin.
Connecting the LT8311’s CSP/CSN pins across the catch
MOSFET’s drain and source, in SYNC mode, is done to
protect the catch MOSFET from conducting too large a
reverse inductor current at light load.
The following guidelines offered (Steps 1 to 5) may be
used to determine an appropriate catch MOSFET reverse
current trip point (VTRIP):
Step 1:
Determine the worst-case negative inductor
current value during regular FCM operation, which will
likely happen at the smallest frequency foldback frequency,
highest VIN, and at 0A load. An easy way to determine this
is to run the forward converter with the LT8311 working
in SYNC mode and keeping the CSP/CSN pins shorted
to GND. Observing the inductor current waveform on an
oscilloscope at start-up, with VIN at its maximum value,
and the load at 0A, can quickly give the user an idea of the
worst-case negative inductor current value (ICATCH_FET)
during regular start-up operation. This will set a lower
bound on the CSP/CSN trip point (VTRIP minimum):
VTRIP Minimum = |ICATCH_FET| • RDS(ON)
where RDS(ON) is the on-resistance of the catch MOSFET,
and ICATCH_FET is the worst-case magnitude of negative
inductor current (current flowing from drain to source of
catch MOSFET) during FCM operation at startup.
Step 2:
Pick a trip point (VTRIP) that allows some margin
from the value calculated in Step 1. Typical margin might
be 20%, thereby setting a trip point of:
VTRIP = 1.2 • VTRIP Minimum
Step 3:
Determine the selected catch MOSFET’s single
pulse avalanche energy rating (EAS in mJ) from the MOS-
FET’s data sheet and its drain-source break down voltage
(VBR(DSS) in V).
Step 4:
Make sure that the chosen CSP/CSN trip voltage
does not allow so much negative current in the catch
MOSFET, such that when the catch MOSFET turns off, its
avalanche energy rating (based on the following equation)
is violated:
V
TRIP
(in Volts)<R
DS(ON)
2 EAS (1.3 VBR(DSS) VOUT)
(1.3 VBR(DSS) LOUT)
where,
EAS (Joules) = Catch MOSFET’s single-pulse avalanche
energy rating.
VBR(DSS) (V) = Catch MOSFET’s drain-source break down
voltage rating.
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RDS(ON) (Ω) = Catch MOSFET’s on-resistance rating from
the MOSFET’s data sheet.
VOUT (V) = Forward converter’s output voltage in steady-
state.
LOUT (H) = Output inductor.
If the VTRIP voltage is too large, causing the catch MOS-
FET’s avalanche energy rating to be violated, then go
back to Steps 1 and 2, or pick a different MOSFET, until
the avalanche energy experienced by the MOSFET in the
application is within its data sheet specified SOA.
Step 5:
Upon selecting the appropriate trip point, the
series resistors, RCSP and RCSN, may be determined based
on the following equation:
RCSP =RCSN =
66mV V
TRIP
40µA
Connect RCSP between the CSP pin and the catch MOS-
FET’s drain, and RCSN between the CSN pin and the catch
MOSFET’s source.
PREACTIVE MODE SYNCHRONOUS CONTROL
Preactive Mode General Guidelines
The following guidelines are meant to summarize the
connections and operating conditions typically needed
to set up the LT8311’s synchronous control in preactive
mode. While these guidelines are meant to serve as a
starting point, they are not a substitute for bench evalua-
tion. Ultimately, each application that uses the LT8311’s
preactive mode scheme must be evaluated for its specific
requirements, and the IC must be configured accordingly.
1. Bias up VIN and INTVCC as per data sheet recommenda-
tions.
2. Place a minimum of 2.2µF ceramic capacitor from the
VIN pin to GND.
3. Place a minimum of 4.7µF ceramic capacitor from the
INTVCC pin to GND.
4. Tie the PMODE and SYNC pins to 0V.
5. Configure RTIMER to set a timeout period that is 20%
higher than the steady-state switching period of the
forward converter.
6. Connect the CSW and FSW pins, through 2k ceramic
resistors, to the drains of the catch and forward MOS-
FET, respectively. Keep the connection as short in length
as possible.
7. Connect the CSP and CSN pins, each through a 1.65k
resistor, directly across the drain-source terminals of
the catch MOSFET for VDS sensing. A small 10pF filter
capacitor may be required across the CSP and CSN
pins to filter out external noise that couples in.
8. Connect CG and FG to the gates of the catch and for-
ward MOSFET, respectively, with connections that are
as short as possible.
Once synchronous control is up and running:
9. Ensure that the voltage at the CSW and FSW pins does
not exceed the abs max rating of 150V. If the CSW
or FSW pin voltage exceeds 150V, you may need to
use a RC snubber on the drain of the catch and/or the
forward MOSFET.
10.If the catch MOSFET current trip point is causing the
inductor current to reverse (flowing from output back
to the drain of the catch MOSFET) at light loads, re-
configure the CSP/CSN trip point to trip at a slightly
positive value of source-to-drain current in the catch
MOSFET. This typically involves increasing the CSP
and CSN series resistors to a value greater than 1.65k.
11.If the catch MOSFET’s current trip point does not
seem consistent, and the catch MOSFET’s turn-off
edge seems to show jitter at the trip current, the filter
capacitor across the CSP and CSN pins may need to
be adjusted.
Note that typically, the FB pin will be connected through a
resistor divider network to the output voltage, when using
the LT8311 as part of a voltage feedback loop.
LT8311
38
8311f
For more information www.linear.com/LT8311
APPLICATIONS INFORMATION
SYNC MODE SYNCHRONOUS CONTROL
Picking the Pulse Transformer and High Pass Filter
In SYNC Mode, the LT8311 determines the turn-on/off
timings of the catch and forward MOSFETs based on
voltage signals on its SYNC pin. Figure 7 in the Operation
section shows a typical circuit used to communicate syn-
chronous control signals from the primary-side IC’s SOUT
pin to the LT8311’s SYNC pin. This circuit utilizes a pulse
transformer (T2 in Figure 7) to provide isolation between
the primary and secondary sides, and a high pass filter
(RSYNC and CSYNC). CSYNC blocks DC signals from being
applied directly to T2. Eliminating the DC component of the
SOUT signal, through the highpass filter (RSYNC and CSYNC),
allows the SYNC pin signal to go positive or negative at
the rising and falling edges of SOUT, as shown in Figure
19. Positive and negative signals of equal magnitudes and
duration allow equal positive and negative volt-seconds
to be maintained on transformer T2, preventing any net
magnetizing current build-up.
Appropriate values of RSYNC and CSYNC must be chosen
to satisfy all of the following criteria:
1. The RSYNCCSYNC time constant must be large
enough to allow a sufficiently long pulse width to be
generated on the SYNC pin with sufficient overdrive
voltage. This is shown in Figure 19 where t1 must be
at least 50ns at a SYNC voltage of ±2V (or greater
over drive) to trip the SYNC comparators. Using this
constraint, the equation below sets a limit on the
minimum RSYNC • CSYNC product required:
R
SYNC CSYNC
50ns
1 n2V
VMAX
where VMAX is the maximum SOUT voltage, as shown
in Figure 19.
2. RSYNC must be small enough to ensure that the
SYNC signal is sufficiently damped. An underdamped
SYNC signal can cause ringing large enough to cause
false triggering of the SYNC detection comparators,
which may lead to improper secondary-synchronous
control. The equation used to calculate RSYNC for
optimal damping is given by:
RSYNC 1
2 ζ
Lm
CSYNC
where ζ is the damping factor and should typically be
chosen to be about 1. Lm is the magnetizing inductance
of the pulse transformer’s primary winding.
Choosing Lm to be larger allows the damping factor
to increase, so it would be wise to choose a pulse
transformer with a larger primary winding inductance
to increase the damping of the SYNC signal.
Smaller RSYNC values also reduce the sensitivity of
the highpass filter to stray signals (parasitic magnetic
fields) that may couple in.
Figure 19. Positive and Negative SYNC Edges Are Generated on the Rising and Falling Edges of SOUT, Respectively.
The LT8311 Requires Pulse Width Time, t1, to Be at Least 50ns (Typical) with the SYNC Pin Voltage at ±2V (or Greater
Overdrive) to Trigger the Internal SYNC Detect Comparators.
2V
t1
0V
0V
8311 F19
SOUT
SYNC
TIME
VMAX
VMAX
–2V
t1
–VMAX
LT8311
39
8311f
For more information www.linear.com/LT8311
APPLICATIONS INFORMATION
3. RSYNC must be large enough to limit the amount of
source/sink current required each time a positive or
negative SYNC pin voltage signal is generated. The
SOUT pin’s gate drivers offer limited source current
capability; RSYNC must be large enough to ensure
that this constraint in current-drive is not violated.
For instance, the LT3752’s SOUT drivers are rated for
a maximum current of about 100mA. This results in:
R
SYNC
V
MAX
100mA
VMAX is the SOUT gate driver high voltage, which is
typically about 8V to 12V for the LT3752.
The following steps can be used as guidelines to calculate
RSYNC and CSYNC values:
Step 1:
Choose Pulse Transformer. A typically recom-
mended choice is the PE-68386NL from Pulse Electronics.
Step 2:
Determine the primary-side IC’s maximum SOUT
signal magnitude, VMAX (see Figure 19). This sets the maxi-
mum magnitude of the signal on the LT8311’s SYNC pin.
Step 3:
Guess a capacitance value for CSYNC. A good
starting value might be between 220pF and 1nF.
Step 4:
Pick RSYNC based on constraint shown in the
following equation:
1
2Lm
CSYNC
RSYNC MAX
50ns
CSYNC 1 IN(2V / VMAX )
,VMAX
IMAX
where IMAX is the maximum current source/sink capability
of the primary-side IC’s SOUT pin (LT3752’s maximum
capability is about 100mA and LT8310’s maximum current
capability is about 300mA). It is recommended to design
for an IMAX that is lower than the maximum recommended
source current specified, to allow for design margin over
process and temperature.
If the RSYNC calculation in Step 4 yields an unreasonable
resistance value, go back to steps 1 to 3, and change either
Lm, VMAX, or CSYNC. Recalculate RSYNC in Step 4 until all
criteria are satisfied.
Design Example
In a LT3752-LT8311 forward converter design, pulse
transformer PE-68386NL is chosen for communication
of LT3752 SOUT signals, through a highpass filter, to the
LT8311’s SYNC pin.
Step 1:
This transformer has a magnetizing inductance
of Lm = 785µH.
Step 2:
LT3752’s VMAX = 12V.
Step 3:
Choose CSYNC = 220pF
Step 4:
Designing for IMAX = 70mA, Lm = 785µH, CSYNC
= 220pF, VMAX = 12V, results in the following calculation
for RSYNC:
944Ω ≥ RSYNC ≥ Max {127Ω, 171Ω}
Conclusion
In this example, RSYNC = 560Ω is chosen along with CSYNC
= 220pF as the highpass filter to be used along with pulse
transformer, PE-68386NL to communicate the LT3752’s
SOUT signals to the LT8311’s SYNC pin.
LT8311
40
8311f
For more information www.linear.com/LT8311
TYPICAL APPLICATIONS
18V to 72V, 12V/8A Active Clamp Isolated Forward Converter
8311 TA02
LT3753
UVLO_VSEC
OVLO
IVSEC
RT
TOS
TBLNK
TAO
TAS
GND SS1 SS2
INTVCC
AOUT
FB
SYNC
SOUT
R4
71.5k
C4
F
C3
0.47µF
VIN
18V to
72V
VIN
R2
5.9k
R3
1.82k
R5
31.6k
240kHz
R7
34k
COMP
ISENSEN
OC
OUT
ISENSEP
R6
49.9k
C10
2.2µF
100V
C9
100nF
C6
4.7µF
R13, 2k
R12
6mΩ
R11
100Ω
C7
F
1k
R8
100k
R9
100k
R22
154k
LT8311
FSW
CSW
CSP
CG
CSN
OPTO
GND
COMP
SYNC PMODE
SS
FB
VIN
INTVCC
PGOOD
TIMER
VOUT
12V/8A
VOUT
L1
6.8µH
D2
R19, 1.78k
R20, 1.5k
FG
R16, 2k R25
100k
R24
20k
R26
11.3k
C19
22µF
× 2
R17, 2k
R18, 1.78k
C20
470µF
C18
68pF
C12
15nF
R21
2.94k C14
F
C15
4.7µF
C16
2.2µF
C17
2.2nF
R14
10k
C11
100nF
4:4
T1
R23
100k
2.2nF
PS2801-1
C5
10pF
+
C1
4.7µF
× 3 R1
100k
D1
D3
T1: CHAMPS B45R2-0404.04
T2: CEL PS2801
L1: CHAMPS PQR2050-08
M1: INFINEON BSC077N12NS3
M2: IR IRF6217PBF
M3: FAIRCHILD SEMI. FDMS86101DC
M4: INFINEON BSC077N12NS3
D2: CENTRAL SEMI. CMMR1U-02
D3: DIODES INC. SBRIU150
M3
M1
M4
M2
Efficiency and Power Loss at VIN = 48V
LOAD CURRENT (A)
1
EFFICIENCY (%)
90
92
94
88
86
5
37 9
84
82
96
POWER LOSS (W)
8
10
12
6
4
2
0
14
8311 TA02b
EFFICIENCY
POWER LOSS
VIN = 48V
LT8311
41
8311f
For more information www.linear.com/LT8311
TYPICAL APPLICATIONS
18V to 72V, 12V/12.5A, 150W Active Clamp Isolated Forward Converter
R4
49.9k
R5
22.6k
R3
1.82k
R6
7.32k
R7
34k
R8
71.5k
R9
31.6k
R23
100k
R24
100k
R10
2.8k
R11
10k
T1: CHAMPS G45R2_0404.04D
T2: BH ELECTRONICS L00-3250
T3: PULSE PE-68386NL
L1: CHAMPS G45AH2-0404-D4
D1, D2, D3: BAS516
D4: CENTRAL SEMI CMMR1U-02
R13
560Ω
R28
3.16k
R27
100k
VAUX
VAUX
SYNC
VIN
GND
FBLT8311
PGOOD
R14
2k R15
0.006Ω
R16
10k
R18
0.15Ω
R17
499Ω
C10
2.2µF
C9
2.2µF
INTVCC VAUX
M5
ZVN4525E6
Si2325DS
D3
T2
D2
D1
M1
BSC077N12NS3
M2 M3
FDMS86101 BSC077N12NS3
R25
100Ω
R12
1.1k
R26
1k 2.2nF
C2
0.33µF
C3
22nF
PS2801-1
C4
22nF
C5
4.7µF
C11
2.2µF
C13
22µF
16V
×2
C24
2.2nF
250V
VOUT
12V
12.5A
C14
470µF
16V
C12
4.7µF
C17
220nF
8311 TA03a
C18
68pF C19
4.7nF
C6 220pF
T3
C16
1µF
TAO
TAS
TOS
TBLNK
IVSEC
RT
SS1
SS2
HCOMP
FB
COMP
OPTO
INTVCC
TIMER
SS
COMP CSP
PMODE
INTVCC INTVCC
SOUT
ISENSEN
ISENSEP
OUTVIN AOUTHISENSE
HOUT
OC
R2
5.9k
R1
100k
UVLO_VSEC
LT3752
SYNC
C7
100nF
C8
15nF
T1
4:4
M4
R20
499k
R29
13.7k
L1
6.8µH
R30
100k
R31
11.3k
CSN
FG
FSW
CG
CSW
R21
100Ω R22
100Ω
R38
20k
+
C1
4.7µF
100V
×3
VIN
18V TO
72V
GND
OVLO
HFB
D4
C28
68pF
LOAD CURRENT (A)
0
EFFICIENCY (%)
96
94
92
90
88
86 63
8311 TA03b
15129
24VIN
48VIN
72VIN
Efficiency vs Load Current
LT8311
42
8311f
For more information www.linear.com/LT8311
TYPICAL APPLICATIONS
18V to 72V, 12V/12.5A, 150W No-Opto, Active Clamp Isolated Forward Converter
R4
49.9k
R5
22.6k
R3
1.82k
R6
7.32k
R7
34k
R8
60.4k
R9
31.6k R10
2.8k
R11
10k
T1: CHAMPS G45R2_0404.04D
T2: BH ELECTRONICS L00-3250
T3: PULSE PE-68386NL
L1: CHAMPS G45AH2-0404-D4
D1, D2, D3: BAS516
D4: CENTRAL SEMI CMMR1U-02
R13
560Ω
VAUX
VAUX
SYNC
VIN
GND
FBLT8311
PGOOD
R14
2k R15
0.006Ω
R16
10k
R18
0.15Ω
R17
499Ω
C10
2.2µF
C9
2.2µF
INTVCC VAUX
M5 ZVN4525E6
D3
T2
D2
D1
M1
BSC077N12NS3
FDMS86101
R12
1.1k 2.2nF
C2
0.33µF
C3
22nF C4
22nF
C5
4.7µF
C11
2.2µF
C13
22µF
16V
×2
VOUT
12V
12.5A
C14
470µF
16V
C12
4.7µF
8311 TA04a
C6 220pF
T3
TAO
TAS
TOS
TBLNK
IVSEC
RT
SS1
SS2
HCOMP
FB
COMP
OPTO
INTVCC
TIMER
SS
COMP CSP
PMODE
INTVCC INTVCC
SOUT
ISENSEN
ISENSEP
OUTVIN AOUTHISENSE
HOUT
OC
R2
5.9k
R1
100k
UVLO_VSEC
LT3752
SYNC
C7
100nF
C8
15nF
T1
4:4
R20
499k
L1
6.8µH
CSN
FG
FSW
CG
CSW
R21
100Ω R22
100Ω
+
C1
4.7µF
100V
×3
VIN
18V TO 72V
GND
OVLO
HFB
Si2325DS
M3 M4
BSC077N12NS3
M2
C24
2.2nF
250V
R38
20k
D4
LOAD CURRENT (A)
0
VOUT (V)
14.0
13.5
13.0
12.5
12.0
11.0
10.5
11.5
10.0 42
8311 TA04b
128 106
VIN = 70V
VIN = 60V
VIN = 48V
VIN = 36V
VIN = 20V
LOAD CURRENT (A)
0
EFFICIENCY (%)
96
94
92
90
88
86 63
8311 TA04c
15129
24VIN
48VIN
72VIN
VOUT vs Load Current (No-Opto) Efficiency vs Load Current
LT8311
43
8311f
For more information www.linear.com/LT8311
TYPICAL APPLICATIONS
150V to 400V, 12V/16.7A, 200W Active Clamp Isolated Forward Converter
R4
95.3k
R5
40.2k
R3
2.94k
R6
13k
R7
100k
R8
124k
R9
78.7k
R23
22k
R24
22k
R10
22k
R11
10k
T1: CHAMPS LT80R2-12AC-3124005
T2: WÜRTH 750817020
T3: PULSE PE-68386NL
L1: COILCRAFT AGP2923-153
D1: CENTRAL SEMI CMR1U-10
D2, D3, D5: BAS516
D4: CENTRAL SEMI CMMR1U-02
R13
560Ω
R28
3.16k
R27
100k
VAUX
SYNC
VIN
GND FB
LT8311
PGOOD
R14
2k R15
0.022Ω
R18
0.15Ω
R17
499Ω
R35
374k
R36
374k
C10
4.7µFC9
10µF
INTVCC VAUX INTVCC
M5
BSP300
D3
T2
D2
M1
IPD65R25OC6
IPD60R1K4C6
M3
M2
R25
100Ω
R12
806Ω
R26
1.2k 2.2nF
C2
0.47µF
C3
0.22µF
PS2801-1
C4
3.3nF
C5
4.7µF
C11
2.2µF
C13
33µF
16V
×4
C24
10nF
250V
VOUT
12V
16.7A
C14
330µF
16V
C12
4.7µF
C17
1µF
8311 TA05a
C18
100pF
C19
22nF
C6 220pF
T3
C16
1µF
TAO
TAS
TOS
TBLNK
IVSEC
RT
SS1
SS2
HCOMP
FB
COMP
OPTO
INTVCC
VAUX
TIMER
SS
COMP CSP
PMODE
INTVCC INTVCC
SOUT
ISENSEN
ISENSEP
OUTVIN AOUTHISENSE
HOUT
OC
R2
5.76k
R1
499k
R34
499k
UVLO_VSEC
LT3752-1
SYNC
RJK0653DPB
×2
T1
31:5
C20
10µF
D5 M4
FDMS86200
×3
R20
432k
R29
5.11k
L1
15µH
R30
100k
R31
11.3k
CSN
FG
FSW
CG
CSW
R21
100Ω
D4
R22
100Ω
R38
10k
R38
0.002Ω
C27
120pF
+
D1
R16 4.2Ω
C1
2.2µF
630V
VIN
150V TO
400V
GND
OVLO
HFB
CATHODE
ANODE
ACPL-W346
VEE
VOUT
VCC
C21
0.22µF
C8
47nF
630V
C15
10nF
630V
R19
402Ω
C28
68pF
LOAD CURRENT (A)
0
EFFICIENCY (%)
96
95
94
93
92
90
89
91
88
85
87
86
52.5
8311 TA05b
17.510 12.5 157.5
VIN = 150V
VIN = 250V
VIN = 350V
VIN = 400V
Efficiency vs Load Current
LT8311
44
8311f
For more information www.linear.com/LT8311
TYPICAL APPLICATIONS
150V to 400V, 12V/16.7A, 200W No-Opto, Active Clamp Isolated Forward Converter
R4
95.3k
R5
40.2k
R3
2.94k
R6
13k
R7
100k
R8
107k
R9
78.7k R10
22k
R11
10k
T1: CHAMPS LT80R2-12AC-3124005
T2: WÜRTH 750817020
T3: PULSE PE-68386NL
L1: COILCRAFT AGP2923-153
D1: CENTRAL SEMI CMR1U-10
D2, D3, D5: BAS516
D4: CENTRAL SEMI CMMR1U-02
R13
560Ω
VAUX
SYNC
VIN
GND
FBLT8311
PGOOD
R14
2k R15
0.022Ω
R18
0.15Ω
R17
499Ω
R35
374k
R36
374k
C10
4.7µF
C9
10µF
INTVCC VAUX INTVCC
M5
BSP300
D3
T2
D2
M1
IPD65R25OC6
IPD60R1K4C6
M3
M2
R12
806Ω 2.2nF
C2
0.47µF
C3
0.22µF
C4
3.3nF
C5
4.7µF
C11
2.2µF
C13
33µF
16V
×4
VOUT
12V
16.7A
C14
330µF
16V
C12
4.7µF
VAUX
8311 TA06a
C6 220pF
T3
TAO
TAS
TOS
TBLNK
IVSEC
RT
SS1
SS2
HCOMP
FB
COMP
OPTO
INTVCC
TIMER
SS
COMP
CSP
PMODE
INTVCC INTVCC
SOUT
ISENSEN
ISENSEP
OUTVIN AOUTHISENSE
HOUT
OC
R2
5.76k
R1
499k
R34
499k
UVLO_VSEC
LT3752-1
SYNC
RJK0653DPB
×2
T1
31:5
C20
10µF
D5 M4
FDMS86200
×3
R20
432k
L1
15µH
CSN
FG
FSW
CG
CSW
+
D1
ACPL-W346
R16 4.2Ω
C1
2.2µF
630V
VIN
150V TO
400V
GND
OVLO
HFB
CATHODE
ANODE
VEE
VOUT
VCC
C21
0.22µF
C8
47nF
630V
C15
10nF
630V
R19
402Ω
R38
0.002Ω
R21
100Ω R22
100Ω
C27
120pF
C24
10nF
250V
D4 R38
10k
LOAD CURRENT (A)
0
VOUT (V)
14.0
13.5
13.0
12.5
12.0
11.5
10.0
11.0
10.5
42
8311 TA06b
188 1210 14 166
VIN = 150V
VIN = 250V
VIN = 350V
VIN = 400V
LOAD CURRENT (A)
0
EFFICIENCY (%)
96
95
94
93
92
90
89
91
88
85
87
86
52.5
8311 TA06c
17.510 12.5 157.5
VIN = 150V
VIN = 250V
VIN = 350V
VIN = 400V
VOUT vs Load Current (No-Opto) Efficiency vs Load Current
LT8311
45
8311f
For more information www.linear.com/LT8311
TYPICAL APPLICATIONS
R4
95.3k
R5
40.2k
R3
2.94k
R6
13k
R7
100k
R8
124k
R9
78.7k
R23
22k
R24
22k
R10
22k
R11
10k
T1: CHAMPS LT80R2-12AC-3124005
T2: WÜRTH 750817020
T3: PULSE PE-68386NL
T4: ICE GT05-111-100
L1: COILCRAFT AGP2923-153
D1: CENTRAL SEMI CMR1U-10
D2, D3, D5: BAS516
D4: CENTRAL SEMI CMMR1U-02
R13
560Ω
R28
3.16k
R27
100k
VAUX
SYNC
VIN
GND
FBLT8311
PGOOD
R14
2k R15
0.022Ω
R18
0.15Ω
R16
10k
C23 3.3nF
R17
499Ω
R35
374k
C22
220nF
R37
100Ω
R36
374k
C10
4.7µF
C9
10µF
INTVCC VAUX
D1
C21
470pF
M5
BSP300
D3
T2
T4
D2
M1
IPD65R25OC6
IPD60R1K4C6
M3
M2
R25
100Ω
R12
806k
R26
1.2k 2.2nF
C2
0.47µF
C3
0.22µF
PS2801-1
C4
3.3nF
C5
4.7µF
C11
2.2µF
C13
33µF
16V
×4
VOUT
12V
16.7A
C14
330µF
16V
C12
4.7µF
VAUX C17
1µF
8311 TA07
C18
100pF
C19
22nF
C6 220pF
T3
C16
1µF
TAO
TAS
TOS
TBLNK
IVSEC
RT
SS1
SS2
HCOMP
FB
COMP
OPTO
INTVCC
TIMER
SS
COMP CSP
PMODE
INTVCC INTVCC
SOUT
ISENSEN
ISENSEP
OUTVIN AOUTHISENSE
HOUT
OC
R2
5.76k
R1
499k
R34
499k
UVLO_VSEC
LT3752-1
SYNC
RJK0653DPB
×2
T1
31:5
C20
10µF
D5 M4
FDMS86200
×3
R20
432k
R29
5.11k
L1
15µH
R30
100k
R31
11.3k
CSN
FG
FSW
CG
CSW
+
C1
2.2µF
630V
VIN
150V TO
400V
GND
OVLO
HFB
C8
47nF
630V
C15
10nF
630V
R19
402Ω
R21
100Ω R22
100Ω
R38
0.002Ω
C27
120pF
C24
10nF
250V
D4 R38
10k
C28
68pF
LOAD CURRENT (A)
0
EFFICIENCY (%)
96
95
94
93
92
90
89
91
88
85
87
86
52.5
8311 TA07b
17.510 12.5 157.5
VIN = 150V
VIN = 250V
VIN = 350V
VIN = 400V
150V to 400V, 12V/16.7A, 200W, Active Clamp Isolated Forward Converter
(Using Gate Drive Transformer for High Side Active Clamp)
Efficiency vs Load Current
LT8311
46
8311f
For more information www.linear.com/LT8311
TYPICAL APPLICATIONS
75V to 150V, 24V/14A 340W Active Clamp Isolated Forward Converter
(Using Gate Drive Transformer for High Side Active Clamp)
R4
93.1k
R5
53k
R3
5.76k
R6
10k
R7
80.1k
R8
82.5k
R9
52.3k
R23
22k
R24
22k
R10
22k
R11
10k
T1: CHAMPS LT80R2-12AC-1006
T2: WÜRTH 750817020
T3: PULSE PE-68386NL
T4: ICE GT05-111-100
L1: COILCRAFT AGP2923-153
D1: CENTRAL SEMI CMR1U-10
D2, D3, D5: BAS516
D4: CENTRAL SEMI CMMR1U-02
R13
560Ω
R28
3.16k
R27
100k
VAUX
SYNC
VIN
GND
FB
LT8311
PGOOD
R14
2k R15
0.0075Ω
R18
0.15Ω
R16
10k
C23 3.3nF
R17
499Ω
R35
102k
C22
220nF
R37
100Ω
R36
102k
C10
4.7µF
C9
10µF
INTVCC VAUX
D1
C21
470pF
M5
BSP300
D3
T2
T4
D2
M1
IPB200N25N3
IRFL214
M3
M2
R25
100Ω
R12
806Ω
R26
1.2k 2.2nF
C2
0.47µF
C3
0.22µF
PS2801-1
C4
3.3nF
C5
4.7µF
C11
2.2µF
C13
22µF
25V
×4
VOUT
24V
14A
C14
470µF
25V
C12
4.7µF
C17
0.33µF
VAUX
8311 TA08a
C18
100pF
C19
22nF
C6 220pF
T3
C16
1µF
TAO
TAS
TOS
TBLNK
IVSEC
RT
SS1
SS2
HCOMP
FB
COMP
OPTO
INTVCC
TIMER
SS
COMP CSP
PMODE
INTVCC INTVCC
SOUT
ISENSEN
ISENSEP
OUTVIN AOUTHISENSE
HOUT
OC
R2
6.04k
R1
6.98k
R34
698k
UVLO_VSEC
LT3752-1
SYNC
BSC047N08NS3
×2
T1
10:6
C20
10µF
D5 M4
1PB072N15N3G
R20
365k
R29
5.11k
L1
15µF
R30
100k
R31
5.36k
CSN
FG
FSW
CG
CSW
+
C1
2.2µF
250V
VIN
75V TO
150V
GND
OVLO
HFB
C8
15nF
250V
C15
4.7nF
250V
R19
1k
R21
100Ω R22
100Ω
R38
0.003Ω
C27
120pF
C24
10nF
250V
D4 R38
10k
C28
68pF
LOAD CURRENT (A)
0
EFFICIENCY (%)
96
95
94
93
92
91
86
90
89
88
87
2.5
8311 TA08b
157.5 10 12.55
VIN = 75V
VIN = 100V
VIN = 125V
VIN = 150V
Efficiency vs Load Current
LT8311
47
8311f
For more information www.linear.com/LT8311
PACKAGE DESCRIPTION
Please refer to http://www.linear.com/designtools/packaging/ for the most recent package drawings.
FE20(16) (CB) TSSOP REV 0 0512
0.09 – 0.20
(.0035 – .0079)
0° – 8°
0.25
REF
RECOMMENDED SOLDER PAD LAYOUT
0.50 – 0.75
(.020 – .030)
4.30 – 4.50*
(.169 – .177)
1 3 5678 9 10
111214 13
6.40 – 6.60*
(.252 – .260)
3.86
(.152)
2.74
(.108)
20 18 16 15
1.20
(.047)
MAX
0.05 – 0.15
(.002 – .006)
0.65
(.0256)
BSC
0.195 – 0.30
(.0077 – .0118)
TYP
2.74
(.108)
0.45 ±0.05
0.65 BSC
4.50 ±0.10
6.60 ±0.10
1.05 ±0.10
3.86
(.152)
MILLIMETERS
(INCHES) *DIMENSIONS DO NOT INCLUDE MOLD FLASH. MOLD FLASH
SHALL NOT EXCEED 0.150mm (.006") PER SIDE
NOTE:
1. CONTROLLING DIMENSION: MILLIMETERS
2. DIMENSIONS ARE IN
3. DRAWING NOT TO SCALE
SEE NOTE 4
4. RECOMMENDED MINIMUM PCB METAL SIZE
FOR EXPOSED PAD ATTACHMENT
6.40
(.252)
BSC
FE Package
Variation: FE20(16)
20-Lead Plastic TSSOP (4.4mm)
(Reference LTC DWG # 05-08-1924 Rev Ø)
Exposed Pad Variation CB
LT8311
48
8311f
For more information www.linear.com/LT8311
LINEAR TECHNOLOGY CORPORATION 2014
LT 0314 • PRINTED IN USA
Linear Technology Corporation
1630 McCarthy Blvd., Milpitas, CA 95035-7417
(408) 432-1900 FAX: (408) 434-0507 www.linear.com/LT8311
RELATED PARTS
TYPICAL APPLICATION
PART NUMBER DESCRIPTION COMMENTS
LT3752/LT3752-1 Active Clamp Synchronous Forward Controllers with
Internal Housekeeping Controller Ideal for Medium Power 24V, 48V and Up to 400V Input Applications
LT3753 100V Input, Active Clamp Synchronous Forward
Controller Ideal for Medium Power 24V and 48V Input Applications
LTC3765/LTC3766 Isolated Synchronous No-Opto Forward Controller
Chip Set Direct Flux Limit, Multiphase Capable Ideal for Medium Power 24V and
48V Input Applications
LTC3722-1/
LTC3722-2 Synchronous Phase Modulated Full Bridge Controllers Ideal for High Power 24V and 48V Input Applications
LT3748 Isolated Flyback Controller 5V ≤ VIN ≤ 100V, No-Opto Required MSOP-16 (12)
LT8300 100V Micropower Isolated Flyback Converter Monolithic No-Opto with Integrated 260mA Switch, TSOT-23
LT3511/LT3512 100V Isolated Flyback Converters Monolithic No-Opto with Integrated 240mA/420mA Switch, MSOP-16(12)
75V to 150V, 24V/14A 340W No-Opto, Active Clamp Isolated Forward Converter
R4
93.1k
R5
53k
R3
5.76k
R6
10k
R7
80.1k
R8
75k
R9
52.3k R10
22k
R11
10k
T1: CHAMPS LT80R2-12AC-1006
T2: WÜRTH 750817020
T3: PULSE PE-68386NL
T4: ICE GT05-111-100
L1: COILCRAFT AGP2923-153
D1: CENTRAL SEMI CMR1U-10
D2, D3, D5: BAS516
D4: CENTRAL SEMI CMMR1U-02
R13
560Ω
VAUX
SYNC
VIN
GND
FBLT8311
PGOOD
R14
2k R15
0.0075Ω
R18
0.15Ω
R16
10k
C23 3.3nF
R17
499Ω
R35
C22
220nF
R37
100Ω
R36
C10
4.7µF
C9
10µF
INTVCC VAUX
D1
C21
470pF
M5
BSP300
D3
T2
T4
D2
M1
1PB200N25N3
IRFL214
M3
M2
R12
806Ω
2.2nF
C2
0.47µF
C3
0.1µF
C4
3.3nF
C5
4.7µF
C11
2.2µF
C13
22µF
25V
×4
VOUT
24V
14A
C14
470µF
25V
C12
4.7µF
8311 TA08a
C6 220pF
T3
TAO
TAS
TOS
TBLNK
IVSEC
RT
SS1
SS2
HCOMP
FB
COMP
OPTO
INTVCC
TIMER
SS
COMP
CSP
PMODE
INTVCC INTVCC
SOUT
ISENSEN
ISENSEP
OUTVIN AOUTHISENSE
HOUT
OC
R2
6.04k
R1
6.98k
R34
698k
UVLO_VSEC
LT3752-1
SYNC
BSC047N08NS3
×2
T1
10:6
C20
10µF
D5 M4
1PB072N15N3G
R20
432k
L1, 15µH
CSN
FG
FSW
CG
CSW
+
C1
2.2µF
250V
VIN
75V TO
150V
GND
OVLO
HFB
C8
15nF
250V
C15
4.7nF
250V
R19
1k
R21
100Ω
R38
0.003Ω
R22
100Ω
C27
120pF
C24
10nF
250V
D4 R38
10k
LOAD CURRENT (A)
0
VOUT (V)
28
27
26
25
24
20
23
22
21
2
8311 TA08b
1612 146 8 104
VIN = 75V
VIN = 100V
VIN = 125V
VIN = 150V
LOAD CURRENT (A)
0
EFFICIENCY (%)
96
95
94
93
92
91
86
90
89
88
87
2.5
8311 TA08c
157.5 10 12.55
VIN = 75V
VIN = 100V
VIN = 125V
VIN = 150V
VOUT vs Load Current (No-Opto) Efficiency vs Load Current