Balanced Line Receiver ICs THAT 1240, 1243, 1246 FEATURES APPLICATIONS * High CMRR: typ. 90 dB at 60Hz * Balanced Audio Line Receivers * Excellent audio performance - Wide bandwidth: typ. >8.6 MHz - High slew rate: typ. 12 V/s - Low distortion: typ. 0.0006% THD - Low noise: typ. -104 dBu * Instrumentation Amplifiers * Differential Amplifiers * Low current: typ. 2 mA * Precision Summers * Several gains: 0 dB, 3 dB, 6 dB * Industry Standard Pinout * Current Shunt Monitors Description The THAT 1240-series of precision differential amplifiers was designed primarily for use as balanced line receivers for audio applications. Gains of 0 dB, 3 dB, and 6 dB are available to suit various applications requirements. simplicity, reliability, matching, and small size of a fully integrated solution. All three versions of the part typically exhibit 90 dB of common-mode rejection. With 12 V/s slew rate, >8.6 MHz bandwidth, and 0.0006 % THD, these devices are sonically transparent. Moreover, current consumption is typically a low 2 mA. Both surface-mount and DIP packages are available. These devices are laser trimmed in wafer form to obtain the precision resistor matching needed for high CMR performance and precise gain. Manufactured in THAT Corporation's proprietary complementary dielectric isolation (DI) process, the THAT 1240-series provides the sonic benefits of discrete designs with the The THAT 1246 is pin-compatible with the TI INA137 and Analog Devices SSM2143, while the THAT 1240 is pin-compatible with the INA134 and the SSM2141. Vcc In- Sense R2 R1 Vout R4 R3 In+ Ref Pin Name DIP Pin SO Pin Ref 1 1 In- 2 2 In+ 3 3 Vee 4 4 Sense 5 5 Vout 6 6 Vcc 7 7 NC 8 8 Table 1. 1240-series pin assignments Vee Part no. Gain THAT1240 THAT1243 THAT1246 0 dB -3 dB -6 dB NC R 1 , R3 R2 , R4 Figure 1. THAT 1240-series equivalent circuit diagram Gain Plastic DIP Plastic SO 0 dB 1240P08-U 1240S08-U 3 dB 1243P08-U 1243S08-U 6 dB 1246P08-U 1246S08-U Table 2. Ordering information THAT Corporation; 45 Sumner Street; Milford, MA 01757-1656; USA Tel: +1 508 478 9200; Fax: +1 508 478 0990; Web: www.thatcorp.com Copyright (c) 2008, THAT Corporation Document 600035 Rev 04 Document 600035 Rev 04 Page 2 of 8 THAT 1240 Series Balanced Line Receiver ICs SPECIFICATIONS 1 Absolute Maximum Ratings 2,3 Supply Voltages (VCC - VEE) 40V Storage Temperature Range (TST) -40 to +125 C Maximum In- or In+ Voltage -50V + VCC, 50V + VEE Operating Temperature Range (TOP) 0 to +85 C Max/Min Ref or Sense Voltage VCC + 0.5V, VEE - 0.5V Output Short-Circuit Duration (tSH) Continuous Maximum Output Voltage (VOM) VCC + 0.5V, VEE - 0.5V Junction Temperature (TJ) +125 C Electrical Characteristics 2,4 Parameter Symbol Conditions Min Typ Max Units Supply Current ICC No signal -- 2.0 2.8 mA Supply Voltage VCC-VEE 6 -- 36 V Input Voltage Range VIN-DIFF -- -- -- 21.5 24.4 27.5 -- -- -- dBu dBu dBu -- -- -- 27.5 29.1 31 -- -- -- dBu dBu dBu VIN-CM Input Impedance5 ZIN-DIFF Differential -- -- -- 18 21 24 -- -- -- k k k ZIN-CM 1240 (0dB gain) 1243 (-3dB gain) 1246 (-6dB gain) Common Mode All versions -- 18 -- k DC 60Hz 20kHz 70 70 -- 90 90 85 -- -- -- dB dB dB 3V to 18V; VCC = -VEE; all gains -- 90 -- dB 0.0006 -- % Common Mode Rejection Ratio CMRR Power Supply Rejection Ratio6 Total Harmonic Distortion Output Noise Slew Rate Differential (equal and opposite swing) 1240 (0dB gain) 1243 (-3dB gain) 1246 (-6dB gain) Common Mode 1240 (0dB gain) 1243 (-3dB gain) 1246 (-6dB gain) PSRR THD eOUT SR Matched source impedances; V CM = 10V VIN_DIFF = 10dBV, f = 1kHz, BW = 22kHz, RL = 2 k -- 22 Hz to 22kHz bandwidth 1240 (0dB gain) 1243 (-3dB gain) 1246 (-6dB gain) -- -- -- -104 -105 -106 -- -- -- dBu dBu dBu RL = 2k; CL = 300 pF, all gains 7 12 -- V/s 1. All specifications are subject to change without notice. 2. Unless otherwise noted, T A=25C, VCC=+15V, VEE= -15V. 3. Stresses above those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. These are stress ratings only; the functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not impli ed. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. 4. 0 dBu = 0.775 Vrms. 5. While specific resistor ratios are very closely trimmed, absolute resistance values can vary 25% from the typical values show n. Input impedance is monitored by lot sampling. 6. Defined with respect to differential gain. 7. Parameter guaranteed over the entire range of power supply and temperature. THAT Corporation; 45 Sumner Street; Milford, MA 01757-1656; USA Tel: +1 508 478 9200; Fax: +1 508 478 0990; Web: www.thatcorp.com Copyright (c) 2008, THAT Corporation THAT 1240 Series Balanced Line Receiver ICs Page 3 of 8 Document 600035 Rev 04 Electrical Characteristics (con't) 2,4 Parameter Symbol Conditions Small signal bandwidth BW-3dB RL = 2k; CL = 10 pF 1240 (0dB gain) 1243 (-3dB gain) 1246 (-6dB gain) RL = 2k; CL = 300 pF 1240 (0dB gain) 1243 (-3dB gain) 1246 (-6dB gain) Output Gain Error Min Typ Max Units -- -- -- 8.6 12.2 18 -- -- -- MHz MHz MHz -- -- -- 10.3 11.8 13.4 -- -- -- MHz MHz MHz GER-OUT f = 1 kHz -0.05 0 +0.05 dB Output Voltage Swing VO+ VO- RL = 2k RL = 2k VCC-2.5 -- VCC-2 VEE+2 -- VEE+2.5 V V Output Offset Voltage VOFF No signal -7 -- +7 mV Output Short Circuit Current ISC RL = 0 -- 25 -- mA Capacitive Load7 CL -- -- 300 pF VCC In- ~ R 1 b R 2 1/2vIN(DIFF) Sense Vout 1/2vIN(DIFF) ~ In+ R R 4 3 R Ref L C a L VIN(CM) ~ VEE Figure 2. THAT 1240 series test circuit Theory of Operation The THAT 1240-series ICs consist of high performance opamps with integrated, laser-trimmed resistors. These designs take full advantage of THAT's fully complementary dielectric isolation (DI) process to deliver excellent performance with low current consumption. The devices are simple to apply in many applications. Resistor Trimming, Values, and CMRR The 1240-series devices rely upon proprietary, laser-trimmed, silicon-chromium (Si-Cr), thin-film, integrated resistors to deliver the precise matching required to achieve a 90 dB common mode rejection ratio. Trimming is performed in two cycles, both using dc inputs. First, gain is set by trimming the R1/R2 pair. Then, CMRR is set by trimming the other pair (R3/R4). Generally, only one resistor of each pair is trimmed (whichever needs to increase to meet the required specification). To achieve 90 dB CMRR, the R3/R4 ratio is trimmed to within 0.005 % of the R1/R2 ratio. Since the resistors themselves are on the order of 10 k (see Figure 1 for actual values, which change with the specific part), an increase of as little as 0.6 can reduce the CMRR from over 90 dB to only 84 dB. The better the starting CMRR, the more impact (in dB) a given added resistance will have. THAT Corporation; 45 Sumner Street; Milford, MA 01757-1656; USA Tel: +1 508 478 9200; Fax: +1 508 478 0990; Web: www.thatcorp.com Copyright (c) 2008, THAT Corporation Document 600035 Rev 04 Page 4 of 8 Therefore, to achieve this high CMRR in practice, care should be taken to ensure that all source impedances remain balanced. To accomplish this, PCB traces carrying signal should be balanced in length, connector resistance should be minimized, and any input capacitance (including strays) should be balanced between the + and - legs of the input circuitry. Note that the additional contact resistance of some sockets is sufficient to undo the effects of precision trimming. Therefore, socketing the parts is not recommended. THAT's 1200-series InGenius(R) input stages address many of these difficulties through a patented method of increasing commonmode input impedance. A further consideration is that after trimming, the two resistor divider ratios are tightly controlled, but the actual value of any individual resistor is not. In fact, two of the four resistors are normally left without trimming. The initial tolerance of the resistors is quite wide, so it is possible for any given resistor to vary over a surprisingly wide range, Lot-to-lot variations of up to 30 % are to be expected. Input Considerations The 1240-series devices are internally protected against input overload via an unusual arrangement of diodes connecting the + and - Input pins to the power supply pins. The circuit of Figure 3 shows the arrangement used for the R3/R4 side; a similar one applies to the other side. The zener diodes prevent the protection network from conducting until an input pin is raised at least 50 V above VCC or below VEE. Thus, the protection networks protect the devices without constraining the allowable signal swing at the input pins. The reference (and sense) pins are protected via more conventional reversebiased diodes which will conduct if these pins are raised above VCC or below VEE. Because the 1240-series devices are input stages, their input pins are of necessity connected to the outside world. This is likely to expose the parts to ESD when cables are connected and disconnected. Our testing indicates that the 1240-series devices will typically withstand application of up to 1,000 volts under the human body ESD model. To reduce risk of damage from ESD, and to prevent RF from reaching the devices, THAT recommends the circuit of Figure 4. C3 through C5 should be located close to the point where the input signal comes into the chassis, preferably directly on the connector. The unusual circuit design is intended to minimize the unbalancing impact of differences in the values of C4 and C5 by forcing the capacitance from each input to chassis ground to depend primarily on the value of C3. The circuit shown is approximately ten times less sensitive to mismatches between C4 and C5 than the more conventional approach, in which the junction of C4 and C5 is grounded directly. An excellent discussion of input stage grounding can be found in the June 1995 issue of the Journal of the Audio Engineering Society, Vol. 43, No. 6, in articles by Stephen Macatee, Bill Whitlock, and others. Note that, because of the tight matching of the internal resistor ratios, coupled with the uncertainty THAT 1240 Series Balanced Line Receiver ICs in absolute value of any individual resistor, RF bypassing through the addition of R-C networks at the inputs (series resistor followed by a capacitor to ground at each input) is not recommended. The added resistors can interact with the internal ones in unexpected ways. If some impedance for the RF-bypass capacitor to work against is deemed necessary, THAT recommends the use of a ferrite bead or balun instead. If it is necessary to ac-couple the inputs of the 1240-series parts, the coupling capacitors should be sized to present negligible impedance at any frequencies of interest for common mode rejection. Regardless of the type of coupling capacitor chosen, variations in the values of the two capacitors, working against the 1240-series input impedance (itself subject to potential imbalances in absolute value, even when trimmed for perfect ratio match), can unbalance common mode input signals, converting them to balanced signals which will not be rejected by the CMRR of the devices. For this reason, THAT recommends dc-coupling the inputs of the 1240-series devices. Input Voltage Limitations When configured, respectively, for -3 dB and -6 dB gain, the 1243 and 1246 devices are capable of accepting input signals above the power supply rails. This is because the internal opamp's inputs connect to the outside world only through the on-chip resistors R1 through R4 at nodes a and b as shown in Figure 2. Consider the following analysis. Differential Input Signals For differential signals (vIN(DIFF)), the limitation to signal handling will be output clipping. The outputs of all the devices typically clip at within 2V of the supply rails. Therefore, maximum differential input signal levels are directly related to the gain and supply rails. Common Mode Input Signals For common-mode input signals, there is no output signal. The limitation on common-mode handling is the point at which the inputs are overloaded. So, we must consider the inputs of the opamp. For common mode signals (vin(CM)), the common mode input current splits to flow through both R1/R2 and through R3/R4. Because vb is constrained to follow va, we will consider only the voltage at node a. The voltage at a can be calculated as: v a = v IN(CM) R4 R 3 +R 4 Again, solving for vIN(CM), v IN(CM) = v a R 3 +R 4 R4 For the 1240, (R3 + R4) / R4 = 2. For the 1243, (R3 + R4) / R4 = 2.4. For the 1246, (R3 + R4) / R4=3. Furthermore, the same constraints apply to va as in the differential analysis. THAT Corporation; 45 Sumner Street; Milford, MA 01757-1656; USA Tel: +1 508 478 9200; Fax: +1 508 478 0990; Web: www.thatcorp.com Copyright (c) 2008, THAT Corporation THAT 1240 Series Balanced Line Receiver ICs Page 5 of 8 must be kept under 125 C to maintain the devices' specifications. + VCC These devices are stable with up to 300 pF of load capacitance. VCC In+ Power Supply Considerations Ref R3 Document 600035 Rev 04 R4 VEE The 1240-series parts are not particularly sensitive to the power supply, but they do contain wide bandwidth opamps. Accordingly, small local bypass capacitors should be located within a few inches of the supply pins on these parts, as shown in Figure 4. Selecting a Gain Variation VEE Figure 3. Representative input protection circuit Following the same reasoning as above, the maximum common mode input signal for the 1240 is (2VCC - 4) V, and the minimum is (2VEE + 4) V. For the 1243, these figures are (2.4VCC - 4.8) V, and (2.4VEE + 4.8) V. For the 1246, these figures are (3VCC - 6) V, and (3VEE + 6) V. Therefore, for common-mode signals and 15 V rails, the 1240 will accept up to ~26 V in either direction. As an ac signal, this is 52 V peak-peak, 18.4 V rms, or +27.5 dBu. With the same supply rails, the 1243 will accept up to ~31 V in either direction. As an ac signal, this is 62 V peak-peak, 21.9 V rms, or +29 dBu. With the same supply rails, the 1246 will accept up to ~39 V in either direction. As an ac signal, this is 78 V peak-peak, 27.6 V rms, or +31 dBu. Of course, in the real world, differential and common-mode signals combine. The maximum signal that can be accommodated will depend on the superposition of both differential and common-mode limitations. Output Considerations The 1240-series devices are typically capable of supplying 25 mA into a short circuit. While they will survive a short, power dissipation will rise dramatically if the output is shorted. Junction temperature The three different parts offer different gain structures to suit different applications. The 1246 is customarily configured for -6 dB gain, but by reversing the resistor connections, can also be configured for +6 dB. The 1243 is most often configured for -3 dB gain, but can also be configured for +3 dB. The choice of input gain is determined by the input voltage range to be accommodated, and the power supply voltages used within the circuit. To minimize noise and maximize signal-to-noise ratio, the input stage should be selected and configured for the highest possible gain that will ensure that maximum-level input signals will not clip the input stage or succeeding stages. For example, with 18 V supply rails, the 1240-series parts have a maximum output signal swing of +23 dBu. In order to accommodate +24 dBu input signals, the maximum gain for the stage is -1 dB. With 15 V supply rails, the maximum output signal swing is ~+21.1 dBu; here, -3 dB is the maximum gain. In each case, a 1243 configured for -3 dB gain is the ideal choice. The 1240 (0dB gain only) will not provide enough headroom at its output to support a +24 dBu input signal. The 1246 (configured for -6 dB gain) will increase noise, thus reducing dynamic range, by attenuating the input signal more than necessary to support a +24 dBu input. In fact, for most professional audio applications, THAT recommends the -3 dB input configuration possible only with the 1243 in order to preserve dynamic range within a reasonable range of power supply voltages and external headroom limits. U1 1240 VCC C2 In- 7 -In 100n C3 47p C4 470p C5 470p In- VCC 9k 5 Sens 6 Out Ref V EE 3 1 U1 In+ 4 VCC 5 Sense In- 7 2 9k 2 Out 6 Vout THAT1246/1243/1240 In+ +In C1 9k 3 9k 100n 1 Ref In+ VEE VEE Figure 4. RFI and supply bypassing 4 Figure 5. Zero dB line receiver THAT Corporation; 45 Sumner Street; Milford, MA 01757-1656; USA Tel: +1 508 478 9200; Fax: +1 508 478 0990; Web: www.thatcorp.com Copyright (c) 2008, THAT Corporation Output Document 600035 Rev 04 Page 6 of 8 THAT 1240 Series Balanced Line Receiver ICs Applications The THAT 1240, 1243, and 1246 are usually thought of as precision differential amplifiers with gains of zero, -3 and -6 dB respectively. These devices are primarily intended as balanced line receivers for audio applications. However, their topology lends itself to other applications as well. Basic Balanced Receiver Applications Figures 5, 6, and 7, respectively, show the THAT 1240, 1246, and 1243 configured as zero, -6 dB, and -3 dB line receivers. Figures 8 and 9, respectively, show the 1243 and 1246 configured as +3 dB and +6 dB line receivers. The higher gains are achieved by swapping the positions of the resistors within each pair in regard to signal input vs. output. Figure 10 shows a THAT 1240 configured as a precision summing amplifier. This circuit uses both the In+ and Ref pins as inputs. Because of the excellent matching between the laser-trimmed resistor pairs, the output voltage is precisely equal to the sum of the two input voltages. Figure 11 shows a 1240 configured as an instrumentation amplifier. The two opamps preceding the 1240 provide gain equal to 1+(9.998 k / Rg). The 1240 rejects common mode signals while accepting balanced ones. Figure 12 shows a convenient method of driving a typical audio ADC with balanced inputs. This circuit accepts +24 dBu in. By using a pair of THAT 1246 ICs connected in anti-phase, the signal level 10.5k VCC e n line receiver = -127dBu 20 %0.775 20kHz 10 7.5k e n total = (2.45 nV Hz 3.2 ) 2 = 3.2 nV Hz % 20kHz 0.775 nV Hz = -124.7 dBu 10.5k VCC 7.5k 5 Sense In- Output 6 10.5k 3 1 Out Vout +In 7.5k 1 Ref In+ VEE Ref In+ U1 1243 7 2 6 7.5k 4 VEE 4 Figure 6. -3 dB line receiver -In 12k 2 VCC Figure 8. +3 dB line receiver U1 1246 7 6k Vout +In 12k 3 6k VCC 6k In- 1 VEE 5 Sense Output 6 Vout +In Ref In+ 12k 2 -In 6 U1 1246 7 5 Sense In- . Figure 13 shows the recommended method for controlling gain in a balanced system. In such circuits, designers are often tempted to keep the signal balanced and use two Voltage Controlled Amplifiers (VCAs) to independently control the gain on each half of the balanced signal. Unfortunately, this can result in common-mode to differential mode 5 Vout 10.5k nV Hz ) 2 + (2.06 Noise (dBu ) = 20 log -In 3 nV Hz The thermal noise of the 249 resistor is 2.05 nV/Hz. We can assume that the noise contribution of R8 and R19 will be negligible, and therefore, the total noise density going into the input of the ADC will be Sense In- +In = 2.45 U1 1243 7 2 The output noise of a THAT 1246 is -106 dBu, and since there are two of them, the total noise level going into the resistive pad will be -103 dBu. The pad reduces the noise level to -127 dBu at the input to the ADC. The noise density resulting from the line receivers will therefore be The noise floor can then be calculated to be More Complex Applications -In between their respective outputs is +24 dBu. An attenuator network brings this signal down by 24 dB while attenuating the noise of the line receivers as well. 12k 3 6k 1 Ref In+ VEE 4 4 Figure 7. -6 dB line receiver Figure 9. +6 dB line receiver THAT Corporation; 45 Sumner Street; Milford, MA 01757-1656; USA Tel: +1 508 478 9200; Fax: +1 508 478 0990; Web: www.thatcorp.com Copyright (c) 2008, THAT Corporation Output Document 600035 Rev 04 Page 7 of 8 U1 1240 7 9k 2 THAT 1240 Series Balanced Line Receiver ICs VCC In- U2A OP-270B 1 9k VCC C1 2 5 100n Sense In- 6 R2 Output 9k 9k 5 Sens 6 Out Ref VEE 3 1 U1 In+ 4 4k99 Ref In+ In- R3 1 VEE 7 2 4k99 R1 Rg Vout Input 1 3 3 Out THAT1240 C2 6 7 In+ 4 VCC 5 U2B OP-270B Input 2 100n VEE Figure 10. Precision two-input summing circuit Figure 11. Instrumentation amplifier conversion (degrading CMRR) when there are even slight differences in gain between the VCAs. A better approach is to convert the signal to single-ended, alter the gain, and then convert back to balanced. +24 dBu, since the THAT 1243 output stage is capable of accepting 21 dBu without distortion. Reducing R3 to 14 k results in a 3 dB reduction in VCA output noise. This arrangement results in 3 dB greater dynamic range compared to the case where a -6 dB line receiver and a VCA with zero dB static gain are used. After the VCA, the signal is restored to 24 dBu by the THAT 1606. In Figure 13 we use a THAT 1243 -3 dB line receiver to do the balanced-to-single-ended conversion. The VCA section also has a static gain of -3 dB due to the ratio of R2 to R3. This circuit can accept 2 5 InSense R8 6 Vout 2k10 Ref 3 In+ U1 THAT 1 1246 C4 6n8 +24 dBu In Hi +24 dBu In In Lo AIN- to ADC R9 249R Zero dBu Out 2 5 InSense 6 Vout 3 Ref U2 In+ THAT 1 1246 R19 2k10 U3A 1 3 AIN+ to ADC 1/2 Vref of ADC 2 4570 Figure 12. Circuit for audio ADCs with balanced inputs Figure 13. Automated gain control of a balanced signal THAT Corporation; 45 Sumner Street; Milford, MA 01757-1656; USA Tel: +1 508 478 9200; Fax: +1 508 478 0990; Web: www.thatcorp.com Copyright (c) 2008, THAT Corporation Document 600035 Rev 04 Page 8 of 8 THAT 1240 Series Balanced Line Receiver ICs Package Information The THAT 1240 series is available in 8-pin PDIP and 8-pin surface mount (SOIC) packages. Package dimensions are shown below; The 1240 series packages are entirely lead-free. The lead-frames are copper, plated with successive layers of nickel, palladium, and gold. This approach makes it possible to solder these devices using leadfree and lead-bearing solders. Neither the lead-frames nor the plastic mold compounds used in the 1240-series contains any hazardous substances as specified in the European Union's Directive on the Restriction of the Use of Certain Hazardous Substances in Electrical and Electronic Equipment 2002/95/EG of January 27, 2003. The surface-mount package is suitable for use in a 100% tin solder process Package Characteristics Parameter Symbol Conditions Through-hole package JA Thermal Resistance Typ Max See Fig. 14 for dimensions 8 Pin PDIP DIP package soldered to board 100 Environmental Regulation Compliance Units C/W Complies with January 27, 2003 RoHS requirements Surface mount package JA Thermal Resistance Min See Fig. 15 for dimensions 8 Pin SOP SO package soldered to board 150 Soldering Reflow Profile C/W JEDEC JESD22-A113-D (250 C) Moisture Sensitivity Level MSL Above-referenced JEDEC soldering profile Environmental Regulation Compliance 1 Complies with January 27, 2003 RoHS requirements E B C F J 1 B G A C H K F D G H A D ITEM A B C D E F G H J K E MILLIMETERS 9.520.10 6.350.10 7.49/8.13 0.46 2.54 3.68/4.32 0.25 3.180.10 8.13/9.40 3.300.10 INCHES 0.3750.004 0.2500.004 0.295/0.320 0.018 0.100 0.145/0.170 0.010 0.1250.004 0.320/0.370 0.1300.004 Figure 14. -P (DIP) version package outline drawing ITEM A B C D E F G H MILLIMETERS 4.80/4.98 3.81/3.99 5.80/6.20 0.36/0.46 1.27 1.35/1.73 0.19/0.25 0.41/1.27 INCHES 0.189/0.196 0.150/0.157 0.228/0.244 0.014/0.018 0.050 0.053/0.068 0.0075/0.0098 0.016/0.05 Figure 15. -S (SO) version package outline drawing THAT Corporation; 45 Sumner Street; Milford, MA 01757-1656; USA Tel: +1 508 478 9200; Fax: +1 508 478 0990; Web: www.thatcorp.com Copyright (c) 2008, THAT Corporation