1
Features
Multic hip Mod ule Contai ning Field Program mab le System Level Integ ra ted Cir cu it
(FPSLIC) and Secure Configuration EEPROM Memory
512 Kbits to 1 Mbit of Configuration Memory with Security Protection and In-System
Programming (ISP)
Field Programmable System Level Integrated Circuit (FPSLIC)
AT40K SRAM-ba sed FPGA with Embedded High-perform ance RISC AVR® Core and
Extensive Data and Instruction SRAM
5,000 to 40,000 Gates of Patented SRAM-based AT40K FPGA with FreeRAM
2 - 18.4 Kbits of Distributed Single/Dual Port FPGA User SRAM
High-performance DSP Optimized FPGA Core Cell
Dynamically Reconfigurable In-System – FPGA Configuration Access Available
On-ch ip fr om AVR Micr oc ontroller Core to Support Cache Logic® Designs
Very Low Static and Dynamic Power Consumption – Ideal for Portable and
Handheld Applications
Patented AVR Enhanced RISC Architecture
120+ Powerful Instructions – Most Single Clock Cycle Execution
High-performance Hardware Multiplier for DSP-based Systems
Approaching 1 MIPS per MHz Performance
C Code Optimized Architecture with 32 x 8 General-purpose Internal Registers
Low-power Idle, Power-save, and Power-down Modes
100 µA Standby and Typical 2-3 mA per MHz Active
Up to 36 Kbytes of Dynamically Allocated Instruction and Data SRAM
Up to 16 Kbytes x 16 Internal 15 ns Instructions SRAM
Up to 16 Kbytes x 8 Internal 15 ns Data SRAM
JTAG (IEEE Std. 1149.1 Compliant) Interface
Extensive On-chip Debugging Support
Limited Boundary-scan Capabilities According to the JTAG Standards (AVR Ports)
AVR Fixed Peripherals
Industry-standard 2-wire Serial Interface
Two Programmable Serial UARTs
Two 8-bit Timer/Counters with Separate Prescaler and PWM
One 16-bit Timer/Counter with Separate Prescaler, Compare, Capture
Modes and Dual 8-, 9- or 10-bit PWM
Support for FPGA Custom Peripherals
AVR Peripheral Control – Up to 16 Decoded AVR Address Lines Directly
Accessible to FPGA
FPGA Macro Library of Custom Peripherals
Up to 16 FPGA Supplied Internal Interrupts to AVR
Up to Four External Interrupts to AVR
8 Global FPGA Clocks
Two FPGA Clocks Driven from AVR Logic
FPGA Global Clock Access Available from FPGA Core
Multiple Oscill ator Circuits
Programmable Watchdog Timer with On-chip Oscillator
Oscillator to AVR Internal Clock Circuit
Software-selectable Clock Frequency
Oscillator to Timer/Counter for Real-time Clock
VCC: 3.0V - 3.6V
5V Tolerant I/O
3.3V 33 MHz PCI Compliant FPGA I/O
20 mA Sink/Source High-performance I/O Structures
All FPGA I/O Individually Programmable
High-performance, Low-power 0.35µ CMOS Five-layer Metal Process
State-of-the-art Integrated PC-based Software Suite including Co-verification
Rev. 2314D–FPSLI–2/04
Secure
5K - 40K Gates
of AT40K FPGA
with 8-bit
Microcontroller,
up to 36 Kbytes
of SRAM and
On-chip
Program
Storage
EEPROM
AT94S
Secure Series
Programmable
SLI
2 AT94S Secure Family 2314D–FPSLI–2/04
Description The AT94S Series (Secure FPSLIC family) shown in Table 1 is a combination of the
popular Atmel AT40K Series SRAM FPGAs, the AT17 Series Configuration Memories
and the high-performance Atmel AVR 8-bit RISC microcontroller with standard peripher-
als. Ex tensive data an d instruc tion SRAM as well as device contr ol and mana gement
logic are included in this multi-chip module (MCM).
The emb edded AT40K FPGA c ore is a f ully 3.3V PCI-co mpliant, SR AM-based F PGA
with distributed 10 ns programmable synchronous/asynchronous, dual-port/single-port
SRAM, 8 global clocks, Cache Logic ability (partially or fully reconfigurable without loss
of data) and 5,000 to 40,000 usable gates.
Table 1. The AT94S Ser ie s Fami ly
Device AT94S05AL AT94S10AL AT94S40AL
Configuration Memory Size 1 Mbit 1 Mbit 1 Mbit
FPGA Gates 5K 10K 40K
FPGA Core Cells 256 576 2304
FPGA SRAM Bits 2048 4096 18432
FPGA Registers (Total) 436 846 2862
Maximum FPGA User I/O 95 143 287
AVR Programmable I/O Lines 8 16 16
Progr am SRAM Bytes 4K - 16K 20K - 32K 20K - 32K
Data SRAM Bytes 4K - 16K 4K - 16K 4K - 16K
Hardware Multiplier (8-bit) Yes Yes Yes
2-wire Serial Interface Yes Yes Yes
UARTs 222
Watchdog Timer Yes Yes Yes
Timer/Counters 333
Real-time Cl ock Yes Yes Yes
JTAG IC E Yes Yes Yes
Typical AVR
Throughput @ 25 MHz 19 MIPS 19 MIPS 19 MIP S
@ 40 MHz 30 MIPS 30 MIPS 30 MIPS
Operating Voltage 3.0 - 3.6V 3.0 - 3.6V 3.0 - 3.6V
3
AT94S Secure Family
2314D–FPSLI–2/04
Figure 1. AT94S Architecture
The embedded AVR core achieves throughputs approaching 1 MIPS per MHz by exe-
cuting powerful instructions in a single-clock-cycle, and allows system designers to
optimize power consumption vers us processing speed. The AVR c ore is based on an
enhan ced RISC archit ecture tha t combi nes a ri ch ins truction set with 32 gener al-pur-
pose wor king regis ters. All 32 registe rs are di rectly co nnected to the Arithme tic Logic
Unit (ALU), allowing two independent registers to be accessed in one single inst ruction
executed in one clock cycle. The resulting architecture is more code-efficient while
achiev ing throug hpu ts up to ten tim es fas ter tha n co nv entiona l CIS C micr o con trol ler s at
the same clock frequency. The AVR executes out of on-chip SRAM. Both the FPGA
configuration SRAM and AVR instruction code SRAM are automatically loaded at sys-
tem power-up using Atmel’s in-system programmable AT17 Series EEPROM
configuration memories, which are part of the AT94S Multi-chip Module (MCM).
State-of-the-art FPSLIC des ign tools, System Design er, were developed in c onjunc-
tion with the FPSL IC architectu re to help redu ce over all time-to- market by integratin g
microcontroller development and debugging, FPGA development, place and route, and
complete system co-verification in one easy-to-use software tool.
5 - 40K Gates FPGA
Up to
16K x 8
Data
SRAM
Up to 16K x 16
Program
SRAM Memory
PROGRAMMABLE I/O
with
Multiply Two 8-bit
Timer/Counters
16 Prog. I/O
Lines
I/O
I/O
I/O
2-wire Serial
Unit
Up to 16 Interrupt Lines
Up to 16
Decoded
Address Lines
4 Interrupt Lines
Configuration Logic
Configuration
EEPROM
I/O
For ISP
and Chip
Erase
Two Serial
UARTs
4 AT94S Secure Family 2314D–FPSLI–2/04
Internal Ar chitecture For details of the AT94S Secure FPSLIC architecture, please refer to the AT94K
FPSLIC datash eet and th e AT1 7 Series Configur ation Memory d atashe et, avai lable o n
the Atme l web site at http: //www.atmel.co m. This doc ument only describes the diffe r-
ences between the AT94S Secure FPSLIC and the AT94K FPSLIC.
FPSLIC and
Configurator
Interface
Fully In-System Programmable and Re-programmable
When Security Bit Set:
Data Ve r ifi catio n Disabled
Data Transfer to FPSLIC not Externally Visible
Secured EEPROM Will Only Boot the FPSLIC Device or Respond to a Chip
Erase
When Security Bit Cleared:
Entire Chip Erase Performed
In-Sy s tem Pr ogramming Enabled
Data Ve r ifi cation Enabled
Exte rnal Data pi ns allo w for In-Sys tem Progr ammin g of the devi ce and se tting of th e
EEPROM-based security bit. When the security bit is set (active) this programming con-
nection will only respond to a device erase command. Data c annot be read out of the
external programming/data pins when the security bit is set. The part can be re-pro-
grammed, but only after first being erased.
Programming and
Configuration Timing
Characteristics
Atmel’s Configurator Programming Software (CPS), available from the Atmel web site
(http://www.atmel.com/dyn /products/tool s_card.asp?tool_id=3191), creates the pro-
gramming algorithm for the embedded configu rator; however, if you are planning to
write your own software or use other means to program the embedded configurator, the
section below includes the algorithm and other details.
The FPSLIC Configurator The FPSLIC Configurator is a serial EEPROM memory which is used to load program-
mable devices. This document describes the features needed to program the
Configurator from within its programming mode (i.e., when SER_EN is driven Low).
Reference schematics are supplied for ISP applications.
Seri al Bus Overview The serial bus is a two-wire bus; one wire (cSCK) functions as a clock and is provided
by the programmer, the second wire (cSDA) is a bi-directional signal and is used to pro-
vide data and control information.
Information is transmitted on the serial bus in messages. Each MESSAGE is preceded
by a Start Condition and ends with a Stop Condition. The message consists of an inte-
ger number of bytes, each byte consisting of 8 bits of data, followed by a ninth
Acknowledge Bit. This Acknowledge Bit is provided by the recipient of the transmitted
byte. This is possible because devices may only drive the cSDA line Low. The system
must provide a small pull-up current (1 k equivalent) for the cSDA line.
The ME SSAGE FOR MAT for read and write in structi ons c onsist s of th e bytes sho wn in
“Bit Format” on page 5.
While writi ng, th e pr ogr ammer is respon sib le fo r is suin g the ins tructi on a nd d ata . Wh ile
reading, the programmer issues the instruction and acknowledges the data from the
Configurator as necessary.
5
AT94S Secure Family
2314D–FPSLI–2/04
Again, the Acknowledge Bit is asserted on the cSDA line by the receiving device on a
byte-by-byte basis.
The factory blanks devices to all zeros before shipping. The array cannot otherwise be
“initialize d” except by explicitly writin g a known value to each location using the s erial
protocol described herein.
Bit Format Data on the cSDA pin may change only during the cSCK Low time; whereas Start and
Stop Conditions are identified as transitions during the cSCK High time.
Write Instruction Message Format
Current Address Read (Ext ended to Sequential Read) Instruction Message Format
Start and Stop
Conditions The Start Conditi on is indicated by a high- to-low transition of the cSDA line when the
cSCK line i s High. Simil arly, the Sto p Conditio n is generate d by a low-to-hig h transitio n
of the cSDA line when the cSCK line is High, as shown in Figure 2.
The Start Condition will return the device to the state where it is waiting for a Device
Address (its normal quiescent mode).
The Sto p Co ndi tio n i nit iat es an int er nal ly timed wr ite s ign al whos e maxim um dur at ion is
tWR (refer to AC Characteristics table for actual value). During this time, the Configurator
must rema in in prog rammi ng mode (i .e. , SER_EN is dri ven Low) . cS DA and cSCK li nes
are ignored until the cycle is completed. Since the write cycle typically completes in less
than tWR seconds, we recommend the use of “polling” as described in later sections.
Input levels to all other pins should be held constant until the write cycle has been
completed.
Ackno wledge Bit The Acknowledge (ACK) Bit shown in Figure 2 is provided by the Configurator receiving
the byte. The receiving Configurator can accept the byte by asserting a Low value on
the cSDA l in e, or it can refuse the byte b y ass er tin g (al lowi ng the s ig nal to be external ly
pulled up to) a High value on the cSDA line. All bytes from accepted messages must be
terminated by either an Acknowledge Bit or a Stop Condition. Following an ACK Bit,
when the cSDA line is released during an exchange of control between the Configurator
and the programmer, the cSDA line may be pulled High temporarily due to the open-col-
lector output natur e of the line. Cont rol of the l ine mus t resume be fore the n ext rising
edge of the clock.
ACK BIT
(CONFIGURATOR)
DATA
BYTE n STOP
CONDITION
START
CONDITION DEVICE
ADDRESS MS EEPROM
ADDRESS BYTE (NEXT) EEPROM
ADDRESS BYTE LS EEPROM
ADDRESS BYTE DATA
BYTE 1
ACK BIT
(CONFIGURATOR)
DATA
BYTE n STOP
CONDITION
START
CONDITION DEVICE
ADDRESS DATA
BYTE 1
ACK BIT
(PROGRAMMER)
6 AT94S Secure Family 2314D–FPSLI–2/04
Bit Ordering Protocol The most significant bit is the first bit of a byte transmitted on the cSDA line fo r the
Device Address Byte and the EEPROM Address Bytes. It is followed by the lesser sig-
nifican t bits unt il the ei ghth bit, th e lea st sig nif ic ant bit, is trans mi tte d. Howe ve r, for Da ta
Bytes ( both wr iting an d read ing), the first bi t tran smitted is the lea st signi fica nt bit. Th is
protocol is shown in the diagrams below.
De vice Address Byte The contents of the Device Address Byte are shown below, along with the order in which
the bits are clocked into the device.
The CE pin cannot be used for device selection in programming mode (i.e., when
SER_EN is drive Low).
Figure 2. Start and Stop Conditions
Where:R/W = 1 Read
= 0 Write
EEPROM Ad dress
The EEPROM Address consists of three bytes on the 1-Mbit part. Each Address Byte is
followe d by an Ackno wledg e Bit (provid ed by the Con figurat or). These by tes define th e
normal add ress space of the Configurator. T he order in which each by te is clocked in to
the Configura tor is also indicated. Un used bits i n an Address Byte must be set to “0” .
Exceptions to this are when reading Device and Manufacturer Codes.
8th Bit
STOP
Condition
Byte n
cSCK
cSDA
START
Condition
tWR
ACK BIT
Device Address Byte
MSB LSB
1010011R/W
1st 2nd 3rd 4th 5th 6th 7th 8th
MSB LSB MSB LSB MSB LSB
0000000A
E16 ACK AE15 AE14 AE13 AE12 AE11 AE10 AE9 AE8 ACK AE7 AE6 AE5 AE4 AE3 AE2 AE1 AE0 ACK
1st 2nd 3rd 4th 5th 6th 7th 8th 1st 2nd 3rd 4th 5th 6th 7th 8th 1st 2nd 3rd 4th 5th 6th 7th 8th
512-Kbit/1-Mbit Page Length
1-Mbit Address Space
Byte Order
512-Kbit Address Space
7
AT94S Secure Family
2314D–FPSLI–2/04
Notes: 1. The 1-Mbit part requires three EEPROM address
bytes; all three bytes must be individually ACK’d by
the EEPROM.
2. Data byte received/sent LSB to MSB.
EEPROM Address is Defined as:
Note: where Xn ... X0 is (PAGE_COUNT)\b
T_BYTE
T_PAGE
AT17LV010 0000 000x9x8x7x6x5x4x3x2x1x0000 0000
AT17LV010 128
AT17LV010 1024
cSDA
cSCK
cSDA
cSCK
DATA BIT
STOP CONDITION
cSDA
cSCK
ACK BIT
cSDA
cSCK
ACK
START CONDITION
Pr ogrammi ng Summary:
Write to Whole Device
SER_EN Low
PAGE_COUNT 0
START
Send Start Condition
BYTE_COUNT 0
Send Device Address
($A6) ACK?
Send MSB of
EEPROM Address
(1)
ACK?
Send LSB of
EEPROM Address
(1)
Send Data Byte
(2)
BYTE_COUNT
BYTE_COUNT+1
BYTE_COUNT =
T_BYTE?
Send Stop Condition
PAGE_COUNT
PAGE_COUNT+1 PAGE_COUNT =
T_PAGE?
Yes
No
No
No
Yes
No
Send Start Condition
Send Device Address
($A7)
END
ACK?
Yes
No
ACK?
Yes
No
ACK?
Yes
No
Yes
SER_EN High
Low-power (Standby)
Power-Cycle EEPROM
(Latches 1st Byte for
FPGA Download
Operations)
1st Data Byte
Value Changed Due
to Write?
No
Verify Final Write
Cycle Completion
Yes
Middle Byte
EEPROM Address ACK?
No
Yes
8 AT94S Secure Family 2314D–FPSLI–2/04
Pr ogrammi ng Summary:
Read from Whole Device
SER_EN Low
START
Send Start Condition
Send Device Address
($A6) ACK?
Send MSB of
EEPROM Address(1) ACK?
Send LSB of
EEPROM Address(1)
Send Start condition
BYTE_COUNT 0
Send Device Address
($A7)
Yes
No
No
Read Data Byte(2)
BYTE_COUNT
BYTE_COUNT+1
Send ACK
END
BYTE_COUNT=
TT_BYTE?
No
ACK?
Yes
No
Yes
Sent Stop Condition
SER_EN High
Low-power (Standby)
Sequential Read from Current Address
ACK? No
Yes
Yes
Random Access Setup
Middle Byte
EEPROM Address ACK? No
Yes
Notes: 1. The 1-Mbit part requires three EEPROM address
bytes; all three bytes must be individually ACK’d by
the EEPROM.
2. Data byte received/sent LSB to MSB
EEPROM Address is Defined as:
TT_BYTE
AT17LV010 00 00 00 \h
AT17LV010 131072 \d
cSDA
cSCK
cSDA
cSCK
SAMPLE DATA BIT
STOP CONDITION
START CONDITION
cSDA
cSCK
ACK BIT
cSDA
cSCK
ACK
9
AT94S Secure Family
2314D–FPSLI–2/04
The organi za tio n of th e Dat a By te is s ho wn ab ov e. Not e tha t in this c ase , the Data B yte
is clocked into the device LSB first and MSB last.
Writing Writing to the normal address space takes place in pages. A page is 128-bytes long in
the 1-Mbit part. The page boundaries are, respectively, addresses where AE0 down to
AEOS are all zero, and AE6 down to AE0 are all zero. Writing can start at any address
within a page an d the n umber of byt es writte n mus t be 12 8 for the 1-Mbi t par t. The fir st
byte is written at the transm itt ed address . The add ress is in crement ed in the Configura-
tor following the receipt o f each Data Byte. Only the l ower 7 bits of the address are
incremented. Thus, after writing to the last byte add ress within the given page, the
address will roll over to the first byte address of the same page. A Write Instruction con-
sists of:
a Start Condition
a Device Address Byte with R/W = 0
An Acknowledge Bit from the Configurator
MS Byte of the EEPROM Address
An Acknowledge Bit from the Configurator
Next Byte of the EEPROM Address
An Acknowledge Bit from the Configurator
LS Byte of EEPROM Address
An Acknowledge Bit from the Configurator
One or more Data Bytes (sent to the
Configurator)
Each followed by an Acknowledge Bit from the
Configurator
a Stop Condition
WRITE POLLING: On receipt of the Stop Condi tion, the Configurator enters an inte r-
nally-timed write cycle. While the Configurator is busy with this write cycle, it will not
acknowledge any transfers. The programmer can start the next page write by sending
the Start Condition foll owed by the Devic e Address , in effect poll ing the Confi gurator. If
this is not acknowledged, then the programmer should abandon the transfer without
asserting a Stop Condition. The programmer can then repeatedly initiate a write instruc-
tion as above, until an acknowledge is received. When the Acknowledge Bit is received,
the write instruction should continue by sending the first EEPROM Address Byte to the
Configurator.
An alternative to write polling would be to wait a period of tWR before sending the next
page of data or ex iting the programming mod e. All signals must be maintained duri ng
the entire write cycle.
Data Byte
LSB MSB
D0 D1 D2 D3 D4 D5 D6 D7
1st 2nd 3rd 4th 5th 6th 7th 8th
10 AT94S Secure Family 2314D–FPSLI–2/04
Reading Read instructions are initiated similarly to write instructions. However, with the R/W bit in
the Dev ice Addr ess set to one. Ther e are th ree varia nts of th e read ins tructi on: curr ent
address read, random read and sequential read.
For all reads, it is important to understand that the internal Data Byte address counter
mainta ins the l ast addre ss acces sed duri ng the pr evious r ead or writ e operat ion, inc re-
mented by one. This addr ess remains valid between operations a s long as the chip
power is maintained and the device remains in 2-wire access mode (i.e., SER_EN is
driven Low). If the last operation was a read at address n, then the current address
would be n + 1. If the f inal op erati on was a write at addr ess n, then the curren t addre ss
would again be n + 1 with one exception. If address n was the last byte address in the
page, the incr emented address n + 1 would “roll over” to the first byte address on the
next page.
CURRENT ADDRESS READ: Once t he Device Addres s (with the R/W select b it set to
High) is clo cked i n and ackno wle dged by th e Conf igurator , the Data Byte at th e cu rrent
address is serially clocked out by the Configurator in response to the clock from the pro-
grammer. The programmer generates a Stop Condition to accept the single byte of data
and terminate the read instruction.
A Current Address Read instruction consists of
a Start Condition
a Device Address with R/W = 1
An Acknowledge Bit from the Configurator
a Data Byte from the Configurator
a Stop Condition from the programmer.
RANDOM READ: A Ra ndo m Read i s a Curre nt Ad dres s Read p re ce ded by a n abor te d
write instruction. The write instruction is only initiated for the purpose of loading the
EEPROM Address Bytes. Once the Device Address Byte and the EEPROM Address
Bytes are clocked in and acknowledged by the Configurator, the programmer immedi-
ately initiates a Current Address Read.
A Random Address Read instruction consists of :
a Start Condition
a Device Address with R/W = 0
An Acknowledge Bit from the Configurator
MS Byte of the EEPROM Address
An Acknowledge Bit from the Configurator
Next Byte of the EEPROM Address
An Acknowledge Bit from the Configurator
LS Byte of EEPROM Address
An Acknowledge bit from the Configurator
a Start Condition
a Device Address with R/W = 1
An Acknowledge Bit from the Configurator
a Data Byte from the Configurator
a Stop Condition from the programmer.
11
AT94S Secure Family
2314D–FPSLI–2/04
SEQUENTIAL READ: Sequentia l Reads follow eithe r a Current Addres s Read or a
Random Address Read. After the programmer receives a Data Byte, it may respond
with an Acknowledge Bi t. As long as th e Configurator receives an Ack nowledge Bit, it
will con tinue to i ncremen t the Data By te addre ss and seri ally cloc k out sequ ential Data
Bytes until the me mory address limit is reached.(1) The Sequential Read instruction is
terminated when the programmer does not respond with an Acknowledge Bit but
instead generates a Stop Condition following the receipt of a Data Byte.
Note: 1. If an ACK is sent by the prog r am mer a fter the d ata in th e last mem ory address i s sen t
by the configurator, the internal ad dres s co unter will “rol lover” to the fi rst byte address
of the memory array and continue to send data as long as an ACK is sent by the
programmer.
Programmer Functions The following programmer functions are supported while the Configurator is in program-
ming mode (i.e., when SER_EN is driven Low):
1. Read the Manufacturer’s Code and the Device Code (optional for ISP).
2. Pr ogram the device.
3. Verify the device.
In the order given above, they are performed in the following manner.
Rea din g Ma nu f a c t u r e r’s
and Device Codes On AT17LV010 Configurator, the sequential reading of these bytes are accomplished by
performing a Random Read at EEPROM Address 040000H.
The correc t cod es ar e:
Manufacturers Code -Byte 0 1E
Device Code - Byte 1 F7 AT17LV010
Note: The Man u facturer’s Code and D evice Code are read us ing the byte orde ring sp ec ifie d for
Data Bytes; i.e., LSB first, MSB last.
Pr ogramming the Device All the bytes in a given page must be written. The page access order is not important but
it is suggested that the Configur ator be written sequentially from address 0. Writing is
accomplished by using the cSDA and cSCK pins.
Important Note on AT94S Series
Configurators Programming The first byte of data will not be cached for read back during FPGA Configuration (i.e.,
when SER_EN is d riven High) until the Configurator is power-cycled.
Verifying the Device All bytes in the Configurator should be read and compared to their intended values.
Reading is done using the cSDA and cSCK pins.
In-System Programming
Applications The AT94S Series Configurators are in-system (re)programmable (ISP). The example
shown on the following page supports the following programmer functions:
1. Read the Manufacturer’s Code and the Device Code.
2. Pr ogram the device.
3. Verify the device data.
While Atm el’s Se cure FPS LIC C onf igurat ors can be prog ram med f rom vari ous s ourc es
(e.g., on-boa rd microc ontroll ers or PLDs ), the app licatio ns show n here are design ed to
facilitate users of our ATDH2225 Configurator Programming Cable. The typical system
setup is shown in Figure 3.
The pages with in the co nfig ur ati on EE PROM can be selecti v ely rewr itten.
This document is limited to example implementations for Atmel’s AT94S application.
12 AT94S Secure Family 2314D–FPSLI–2/04
Figure 3. Typic al System Setup
The diode connection between the AT94S’ RESET pin and the SER_EN signal allows
the external programmer to force the FPGA into a reset state during ISP. This eliminates
the poten tial for co nten tion on th e cSCK l ine. The pul l-up res isto rs requir ed on the li nes
to RESET, CON and INIT are present on the inputs (internally) to the AT94S FPSLIC,
see Figure 4.
Figure 4. ISP of the AT17LV512/010 in an AT94S FPSLIC Application
Note: 1. Configurato r signal names are shown in pare nthesis.
PC
Secure
FPSLIC
Target System
10-pin
Ribbon
Cable
Programming
Dongle
In-System
Programming
Connector
Header
ATDH2225 10
Secure
FPSLIC
2
4
6
8
10
cSDA 1
cSCK 3
5
7
9
SER_EN
VCC
GND
AT94S
(SER_EN)
DATA0 (cSDA)(1)
CLK (cSCK)(1)
INIT (RESET/OE)(1)
CON (CE)(1)
RESET
GND
RESET
M2
M0
13
AT94S Secure Family
2314D–FPSLI–2/04
Figure 5. Serial Data Timing Diagram
tLOW tHIGH
tHD.STA
tSU.STA
tRtFtSU.DAT
tHD.DAT
tDH
tAA
tSU.STO
tBUF
cSCK
cSDA
cSDA
14 AT94S Secure Family 2314D–FPSLI–2/04
Notes: 1. Specific to programming mode (i.e., when SER_EN is driven Low)
2. Commerc ial temperature range 0°C - 7 0°C
3. Industrial temperature range -40°C - 85°C
4. This parameter is characterized and is not 100% tested.
Notes: 1. Specific to programming mode (i.e., when SER_EN is driven Low)
2. Commerc ial temperature range 0°C - 7 0°C
3. Industrial temperature range -40°C - 85°C
4. This parameter is characterized and is not 100% tested.
DC Characteristic s(1)
VCC = 3.3V ± 10%, TA = -40°C - 85°C(2)(3)(4)
Symbol Parameter Test Condition Min Typ Max Units
VCC Supply Voltage 3.0 3.3 3.6 V
ICC Supply Current VCC = 3.6 2 3 mA
ILL Input Leakage Current VIN = VCC or VSS 0.10 10 µA
ILO Output Lea ka ge Cu rren t V OUT = VCC or VSS 0.05 10 µA
VIH High-l evel Input Voltage VCC x 0.7 VCC + 0.5 V
VIL Low-level Input Voltage -0.5 0.2 V
VOL O utp ut Lo w -l evel Voltage IOL = 2.1 mA 0.4 V
AC Characteristics(1)
VCC = 3.3V ± 10%, TA = -40°C - 85°C(2)(3)(4)
Symbol Parameter Min Max Units
fCLOCK Clock Fre que nc y, Clock 100 KHz
tLOW Clock Pulse Width Low 4 µs
tHIGH Clock Pulse Width High 4 µs
tAA Clock Low to Data Out Valid 0.1 1 µs
tBUF Time the Bus Must Be Free Before a New Transmission Can Star t 4.5 µs
tHD;STA Start Hold Time 2 µs
tSU;STA Star t Setup Time 2 µs
tHD DAT Data In Hold Time 0 µs
tSU DAT Data In Setup Time 0.2 µs
tRInputs Rise Time 0.3 µs
tFInputs Fall Time 0.3 µs
tSU STO Stop Setup Time 2 µs
tDH Data Out Hold Time 0.1 µs
tWR Write Cycle Tim e 20 ms
15
AT94S Secure Family
2314D–FPSLI–2/04
.
Security Bit Once th e security bi t is programm ed, data will no lon ger output from the normal dat a
pad. Once the fuse is set, any attempt to erase the fuse will caus e the configurator to
erase all of it contents.
AT17LV512/010 Security Bit
Programming
Disabling the Security Bit Write 4 bytes “00 00 00 00” to addresses 800000-800003 twice, without a power cycle in
between, using the previously defined 2-wire write algorithm.
Enabling the Security Bit Write 4 byte s “F F FF FF F F” to addres ses 8 00000-80 0003 using t he previ ously def ined
2-wire write algorithm.
Ver i fyi ng the Secu r i ty Bit Read 4 bytes of da ta from addres ses 80000 0-800003 us ing the previ ously de fined 2-
wire Random Read algorithm. If the data is “FF FF FF FF”, the security bit has been
enabled. If the data is “00 00 00 00”, the security bit has been disabled.
Secure FPSLIC Configurator Pin Configurations
144-pin
LQFP 256-pin
CABGA Name I/O Description
105 D16 cSDA I/O Three-state DATA output for configuration.
Open-collector bi-directional pin for
programming.
107 C16 cSC K O CLOCK outp ut. U s ed to i nc rem ent the internal
address and bit counter for reading and
programming.
53 K9
RESET/O
EI RESET/OE input (when SER_EN is High). A
Low level on both the CE and RESET/OE
inputs enables the data output driver. A High
le vel on RESET/OE resets both the add res s
and bi t cou nters . Th e log ic polarity of th is i nput
is programmable as either RESET/OE or
RESET/OE. This document describes the pin
as RESET/OE.
72 N16 CE I Chip Enable input. Used for device selection
only when SER_EN is High. A Low level on
both CE and OE enables the data output
driver. A High level on CE disab l es both the
address and bit counters and f orces the de vic e
into a low-power mode. Note this pin will not
enable/disa ble the devi ce in t he 2-wire Serial
mode (i.e., when SER_EN is driven Low).
81 M5 SER_EN I Serial enable is normally High during FPGA
loading operations. Bringing SER_EN Low
enables the programming mode.
16 AT94S Secure Family 2314D–FPSLI–2/04
Chip Erase Timing The entire devi ce can be eras ed at on ce b y writi ng to a spe cif ic address. T his ope ra tio n
will erase the entire array. See Table 2 for specifics on the write algorithm.
Figure 6. Chip Erase Timing Diagram
Table 2. Chip Erase Cycle Characteristics
Symbol Parameter
Tec Chip Erase Cycle Time (25 ms)
8th BIT
STOP
Condition
SCL
SDA
START
Condition
Tec
ACK
tsu.dat thigh tlow
tnd.dat
17
AT94S Secure Family
2314D–FPSLI–2/04
Packaging and
Pin List information Table 3. Part and Package Combinations Available
Part # Package AT94S05 AT94S10 AT94S40
BG256 DG 93 137 162
LQ144 BQ 84 84
Table 4. AT94K JTAG ICE Pin List
Pin AT94S05
96 FPGA I/O AT94S10
192 FPGA I/O AT94S40
384 FPGA I/O
TDI IO34IO50IO98
TDO IO38 IO54 IO102
TMS IO43 IO63 IO123
TCK IO44 IO64 IO124
Table 5. AT94S Pi n Lis t
AT94S05
96 FPGA I/O AT94S10
144 FPGA I/O AT94S40
288 FPGA I/O
Package
Chip Array 256
CABGA LQ144(1)
FPSLIC Array
I/O1, GCK1 (A16) I/O1, GCK1 (A16) I/O1, GCK1 (A16) A1 2
I/O2 (A17) I/O2 (A17) I/O2 (A17) D4 3
I/O3 I/O3 I/O3 D3 4
I/O4 I/O4 I/O4 B1 5
I/O5 (A18) I/O5 (A18) I/O5 (A18) C2 6
I/O6 (A19) I/O6 (A19) I/O6 (A19) C1 7
I/O7
I/O8
NC NC I/O9 D2
NC NC I/O10 D1
I/O11
I/O12
I/O13
I/O14
I/O7 I/O7 I/O15 E3
I/O8 I/O8 I/O16 E4
NC I/O9 I/O17 E2
18 AT94S Secure Family 2314D–FPSLI–2/04
NC I/O10 I/O18 E1
I/O19
I/O20
NC I/O11 I/O21 F4
NC I/O12 I/O22 F3
I/O23
I/O24
I/O9, FCK1 I/O13, FCK1 I/O25, FCK1 F1 9
I/O10 I/O14 I/O26 G7 10
I/O11 (A20) I/O15 (A20) I/O27 (A20) G6 11
I/O12 (A21) I/O16 (A21) I/O28 (A21) G4 12
NC I/O17 I/O29 G5
NC I/O18 I/O30 G2
I/O31
I/O32
I/O33
I/O34
NC NC I/O35 G1
NC NC I/O36 H7
I/O37
I/O38
NC NC I/O39 H6
NC NC I/O40 H5
NC I/O19 I/O41 H3
NC I/O20 I/O42 H4
I/O13 I/O21 I/O43 H2 13
I/O14 I/O22 I/O44 H1 14
I/O45
I/O46
I/O15 (A22) I/O23 (A22) I/O47 (A22) J7 15
I/O16 (A23) I/O24 (A23) I/O48 (A23) J1 16
I/O17 (A24) I/O25 (A24) I/O49 (A24) J4 19
I/O18 (A25) I/O26 (A25) I/O50 (A25) J5 20
I/O51
Table 5. AT94S Pin List (Continued)
AT94S05
96 FPGA I/O AT94S10
144 FPGA I/O AT94S40
288 FPGA I/O
Package
Chip Array 256
CABGA LQ144(1)
19
AT94S Secure Family
2314D–FPSLI–2/04
I/O52
I/O19 I/O27 I/O53 J6 21
I/O20 I/O28 I/O54 J8 22
NC I/O29 I/O55 K1
NC I/O30 I/O56 K2
I/O57
I/O58
I/O59
I/O60
NC NC I/O61 K4
NC NC I/O62 K5
I/O63
I/O64
NC NC I/O65 K6
NC NC I/O66 L1
NC I/O31 I/O67 L2
NC I/O32 I/O68 L5
I/O21 (A26) I/O33 (A26) I/O69 (A26) L4 23
I/O22 (A27) I/O34 (A27) I/O70 (A27) M1 24
I/O23 I/O35 I/O71 M2 25
I/O24, FCK2 I/O36, FCK2 I/O72, FCK2 N1 26
I/O73
I/O74
I/O37 I/O75
I/O38 I/O76
I/O77
I/O78
I/O79
I/O80
I/O25 I/O39 I/O81 M3
I/O26 I/O40 I/O82 N2
I/O41 I/O83
I/O42 I/O84
I/O85
Table 5. AT94S Pin List (Continued)
AT94S05
96 FPGA I/O AT94S10
144 FPGA I/O AT94S40
288 FPGA I/O
Package
Chip Array 256
CABGA LQ144(1)
20 AT94S Secure Family 2314D–FPSLI–2/04
I/O86
I/O87
I/O88
I/O27 (A28) I/O43 (A28) I/O89 (A28) P1 28
I/O28 I/O44 I/O90 P2 29
I/O91
I/O92
I/O29 I/O45 I/O93 R1 30
I/O30 I/O46 I/O94 N3 31
I/O31 (OTS) I/O47 (OTS) I/O95 (OTS)T132
I/O32, GCK2 (A29) I/O48, GCK2 (A29) I/O96, GCK2 (A29) P3 33
AVRRESET AVRRESET AVRRESET R2 34
M0 M0 M0 R3 36
FPSLIC Array
M2 M2 M2 T3 38
I/O33, GCK3 I/O49, GCK3 I/O97, GCK3 R4 39
I/O34 (HDC/TDI) I/O50 (HDC/TDI) I/O98 (HDC/TDI) T4 40
I/O35 I/O51 I/O99 N5 41
I/O36 I/O52 I/O100 P5 42
I/O53 I/O101 43
SER_EN SER_EN SER_EN M5 81
I/O38 (LDC/TDO) I/O54 (LDC/TDO) I/O102 (LDC/TDO) R5 44
I/O103
I/O104
I/O105
I/O106
NC NC I/O107 T5
NC NC I/O108 M6
I/O39 I/O55 I/O109 P6
I/O40 I/O56 I/O110 R6
NC I/O57 I/O111 L6
NC I/O58 I/O112 T6
I/O113
I/O114
Table 5. AT94S Pin List (Continued)
AT94S05
96 FPGA I/O AT94S10
144 FPGA I/O AT94S40
288 FPGA I/O
Package
Chip Array 256
CABGA LQ144(1)
21
AT94S Secure Family
2314D–FPSLI–2/04
I/O115
I/O116
I/O59 I/O117
I/O60 I/O118
I/O119
I/O120
I/O41 I/O61 I/O121 M7 46
I/O42 I/O62 I/O122 N7 47
I/O43 (TMS) I/O63 (TMS ) I/O123 (TMS) P7 48
I/O44 (TCK) I/O64 (TCK) I/O124 (TCK) R7 49
NC I/O65 I/O125 K7
NC I/O66 I/O126 K8
I/O127
I/O128
I/O129
I/O130
I/O131
I/O132
I/O133
I/O134
NC I/O67 I/O135 M8
NC I/O68 I/O136 R8
I/O45 I/O69 I/O137 P8 50
I/O46 I/O70 I/O138 N8 51
I/O139
I/O140
I/O141
I/O142
I/O47 (TD7) I/O71 (TD7) I/O143 (TD7) L8 52
I/O48 (InitErr) RESET/OE I/O72 (InitErr) RESET/OE I/O144 (InitErr) RESET/OE K9 53
I/O49 (TD6) I/O73 (TD6) I/O145 (TD6) P9 56
I/O50 (TD5) I/O74 (TD5) I/O146 (TD5) N9 57
I/O147
I/O148
Table 5. AT94S Pin List (Continued)
AT94S05
96 FPGA I/O AT94S10
144 FPGA I/O AT94S40
288 FPGA I/O
Package
Chip Array 256
CABGA LQ144(1)
22 AT94S Secure Family 2314D–FPSLI–2/04
I/O149
I/O150
I/O51 I/O75 I/O151 M9 58
I/O52 I/O76 I/O152 L9 59
NC I/O77 I/O153 J9
NC I/O78 I/O154 T10
I/O155
I/O156
I/O157
I/O158
I/O159
I/O160
I/O161
I/O162
NC I/O79 I/O163 P10
NC I/O80 I/O164 N10
I/O53 (TD4) I/O81 (TD4) I/O165 (TD4) L10 60
I/O54 (TD3) I/O82 (TD3) I/O166 (TD3) T11 61
I/O55 I/O83 I/O167 R11 62
I/O56 I/O84 I/O168 M11 63
NC NC I/O169 N11
NC NC I/O170 T12
NC I/O85 I/O171 R12
NC I/O86 I/O172 T13
I/O173
I/O174
I/O175
I/O176
NC I/O87 I/O177 N12
NC I/O88 I/O178 P12
I/O57 I/O89 I/O179 R13
I/O58 I/O90 I/O180 T14
NC NC I/O181 N13
NC NC I/O182 P13
Table 5. AT94S Pin List (Continued)
AT94S05
96 FPGA I/O AT94S10
144 FPGA I/O AT94S40
288 FPGA I/O
Package
Chip Array 256
CABGA LQ144(1)
23
AT94S Secure Family
2314D–FPSLI–2/04
I/O59 (TD2) I/O91 (TD2) I/O183 (TD2) T16 65
I/O60 (TD1) I/O92 (TD1) I/O184 (TD1) P14 66
I/O185
I/O186
I/O187
I/O188
I/O61 I/O93 I/O189 R16 67
I/O62 I/O94 I/O190 P15 68
I/O63 (TD0) I/O95 (TD0) I/O191 (TD0) N14 69
I/O64, GCK4 I/O96, GCK4 I/O192, GCK4 P16 70
CON/CE CON/CE CON/CE N16 72
FPSLIC Array
RESET RESET RESET M14 74
PE0 PE0 PE0 M12 75
PE1 PE1 PE1 M15 76
PD0 PD0 PD0 M16 77
PD1 PD1 PD1 L12 78
PE2 PE2 PE2 L15 79
PD2 PD2 PD2 L11 80
NC NC NC E12
SER_EN SER_EN SER_EN M5 81
PD3 PD3 PD3 K11 82
PD4 PD4 PD4 K12 83
PE3 PE3 PE3 K14 84
CS0 CS0 CS0 K15 85
SDA SDA SDA J10
SCL SCL SCL J12
PD5 PD5 PD5 J14 86
PD6 PD6 PD6 J13 87
PE4 PE4 PE4 J16 88
PE5 PE5 PE5 J11 89
PE6 PE6 PE6 H15 92
PE7 (CHECK) PE7 (CHECK) PE7 (CHECK) H14 93
PD7 PD7 PD7 H13 94
Table 5. AT94S Pin List (Continued)
AT94S05
96 FPGA I/O AT94S10
144 FPGA I/O AT94S40
288 FPGA I/O
Package
Chip Array 256
CABGA LQ144(1)
24 AT94S Secure Family 2314D–FPSLI–2/04
INTP0 INTP0 INTP0 H12 95
XTAL1 XTAL1 XTAL1 G15 96
XTAL2 XTAL2 XTAL2 G14 97
RX0 RX0 RX0 G12 98
TX0 TX0 TX0 G11 99
INTP1 INTP1 INTP1 F15
INTP2 INTP2 INTP2 F14
TOSC1 TOSC1 TOSC1 E16 101
TOSC2 TOSC2 TOSC2 E15 102
RX1 RX1 RX1 E14 103
TX1 TX1 TX1 E13 104
DATA0/cSDA DATA0/cSDA DATA0/cSDA D16 105
INTP3 (CSOUT) INTP3 (CSOUT) INTP3 (CSOUT) D15 106
CCLK/cSCK CCLK/cSCK CCLK/cSCK C16 107
I/O65:96 Are Unbonded I/O97:144 Are Unbonded I/O193:288 Are Unbonded
FPSLIC Array
Testclock Testclock Testclock C15 109
I/O97 (A0) I/O145 (A0) I/O289 (A0) C14 111
I/O98, GCK7 (A1) I/O146, GCK7 (A1) I/O290, GCK7 (A1) B15 112
I/O99 I/O147 I/O291 A16 113
I/O100 I/O148 I/O292 D13 114
I/O293
I/O294
NC NC I/O295 C13
NC NC I/O296 B14
I/O101 (CS1, A2) I/O149 (CS1, A2) I/O297 (CS1, A2) A15 115
I/O102 (A3) I/O150 (A3) I/O 298 (A3) A14 116
I/O299
I/O300
I/O104 I/O151 I/O301 Shared with Test
clock
NC I/O152 I/O302 D12
I/O103 I/O153 I/O303 C12 117
NC I/O154 I/O304 A13
NC NC I/O305 B12
Table 5. AT94S Pin List (Continued)
AT94S05
96 FPGA I/O AT94S10
144 FPGA I/O AT94S40
288 FPGA I/O
Package
Chip Array 256
CABGA LQ144(1)
25
AT94S Secure Family
2314D–FPSLI–2/04
I/O306
I/O307
I/O308
NC I/O155 I/O309 A12
NC I/O156 I/O310 E11
NC NC I/O311 C11
NC NC I/O312 D11
I/O105 I/O157 I/O313 A11 119
I/O106 I/O158 I/O314 F10 120
NC I/O159 I/O315 E10
NC I/O160 I/O316 D10
NC NC I/O317 C10
NC NC I/O318 B10
I/O319
I/O320
I/O321
I/O322
I/O323
I/O324
I/O107 (A4) I/O161 (A4) I/O 325 (A4) A10 121
I/O108 (A5) I/O162 (A5) I/O 326 (A5) G10 122
NC I/O163 I/O327 G9
NC I/O164 I/O328 F9
I/O109 I/O165 I/O329 E9 123
I/O110 I/O166 I/O330 C9 124
I/O331
I/O332
I/O333
I/O334
I/O111 (A6) I/O167 (A6) I/O 335 (A6) B9 125
I/O112 (A7) I/O168 (A7) I/O 336 (A7) A9 126
I/O113 (A8) I/O169 (A8) I/O 337 (A8) A8 129
I/O114 (A9) I/O170 (A9) I/O 338 (A9) B8 130
I/O339
Table 5. AT94S Pin List (Continued)
AT94S05
96 FPGA I/O AT94S10
144 FPGA I/O AT94S40
288 FPGA I/O
Package
Chip Array 256
CABGA LQ144(1)
26 AT94S Secure Family 2314D–FPSLI–2/04
I/O340
I/O341
I/O342
I/O115 I/O171 I/O343 C8 131
I/O116 I/O172 I/O344 D8 132
NC I/O173 I/O345 E8
NC I/O174 I/O346 F8
I/O117 (A10) I/O175 (A10) I/O347 (A10) H8 133
I/O118 (A11) I/O176 (A11) I/O348 (A11) A7 134
NC NC I/O349 C7
NC NC I/O350 D7
I/O351
I/O352
I/O353
I/O354
I/O355
I/O356
NC I/O177 I/O357 F7
NC I/O178 I/O358 A6
I/O119 I/O179 I/O359 F6 135
I/O120 I/O180 I/O360 B6 136
I/O361
I/O362
NC I/O181 I/O363 D6
NC I/O182 I/O364 E6
I/O365
I/O366
I/O367
I/O368
I/O121 I/O183 I/O369 A5
I/O122 I/O184 I/O370 B5
I/O123 (A12) I/O185 (A12) I/O371 (A12) E5 138
I/O124 (A13) I/O186 (A13) I/O372 (A13) C5 139
I/O373
Table 5. AT94S Pin List (Continued)
AT94S05
96 FPGA I/O AT94S10
144 FPGA I/O AT94S40
288 FPGA I/O
Package
Chip Array 256
CABGA LQ144(1)
27
AT94S Secure Family
2314D–FPSLI–2/04
Note: 1. LQ144 is only offered in the AT94S10 and AT94S40.
Note: 1. Fo r pow er r ail support for produ ct mig rati on to lo we r-po wer devices , ref er to the “Desig ning in Spl it P o w er Supp ly Support for
AT94KAL/AX and AT94SAL/AX Devices” application note (doc2308.pdf), available on the Atmel web site, at
http://www.atmel.com/dyn/products/app_notes.asp?family_id=627.
Thermal Coefficient Table
I/O374
I/O375
I/O376
I/O377
I/O378
NC I/O187 I/O379 A4
NC I/O188 I/O380 B4
I/O125 I/O189 I/O381 A3 140
I/O126 I/O190 I/O382 C4 141
I/O127 (A14) I/O191 (A14) I/O383 (A14) B3 142
I/O128, GCK8 (A15) I/O192, GCK8 (A15) I/O384, GC K8 (A15) A2 143
Table 5. AT94S Pin List (Continued)
AT94S05
96 FPGA I/O AT94S10
144 FPGA I/O AT94S40
288 FPGA I/O
Package
Chip Array 256
CABGA LQ144(1)
Table 6. 256 CABGA and LQ144 VDD, VCC and GND Pins(1)
Package VDD VCC GND
256
CABGA B2, G13, R14, G8, H10, J3,
K13, L3, M10, T7 D14, F12, P4, G3, H9, E7,
K10, L13, M13, T9
B11, B13, B16, B7, C3, C6, D5, D9, F11 , F13, T15, F16,
F2, F5, G16, H11, H16 , J15, J2, K16, K3, T2, L14, L16 ,
L7, M4, N15, N4, N6, P11, R9, R10, R15, T8
LQ144 90 18, 37, 54, 73, 108, 128, 144 1, 8, 17, 27, 35, 45, 55, 64, 71, 91, 100, 110, 118, 127,
137
Package Style Lead Count Theta J-A [°C/W]
0 LFPM Theta J-A [°C/W]
225 LFPM Theta J-A [°C/W]
500 LPFM
CABGA 256 27 23 20
LQFP 144 35
28 AT94S Secure Family 2314D–FPSLI–2/04
Ordering Information
Usable Ga tes Speed Grade O r d ering Code Pac kage Operation Range
5,000 25 MHz AT94S05AL-25DGC 256ZA Commercial
(0°C - 70°C)
AT94S05AL-25DGI 256ZA Industrial
(-40°C - 85°C)
10,000 25 MHz
AT94S10AL-25DGC 256ZA Commercial
(0°C - 70°C)
AT94S10AL-25BQC 144L1
AT94S10AL-25DGI 256ZA Industrial
(-40°C - 85°C)
AT94S10AL-25BQI 144L1
40,000 16 MHz
AT94S40AL-25DGC 256ZA Commercial
(0°C - 70°C)
AT94S40AL-25BQC 144L1
AT94S40AL-25DGI 256ZA Industrial
(-40°C - 85°C)
AT94S40AL-25BQI 144L1
Package Type
256ZA 256-ball, Chip Array Ball Grid Array Package (CABGA)
144L1 144-lead, Low Profile Plastic Gull Wing Quad Flat Package (LQFP)
29
AT94S Secure Family
2314D–FPSLI–2/04
Pa ckaging Information
256ZA – CABGA
2325 Orchard Parkway
San Jose, CA 95131
TITLE DRAWING NO.
R
REV.
256ZA, 256-ball (16 x 16 Array), 17 x 17 mm Body,
Chip Array Ball Grid Array (CABGA) Package A
256ZA
11/07/01
Top View
123
A1
Ball Pad Corner
45678
A
B
D
C
E
910111214131516
G
J
H
K
M
L
N
P
R
T
1.00 REF
1.00 REF
Bottom View
(256 SOLDER BALLS)
F
D
A1
Ball Pad Corner
E
Side View
A2
b
A1
A3
A
e
e
COMMON DIMENSIONS
(Unit of Measure = mm)
SYMBOL MIN NOM MAX NOTE
D 17 BSC
E 17 BSC
A 1.30 1.40 1.50
A1 0.31 0.36 0.41
A2 0.29 0.34 0.39
A3 0.65 0.70 0.75
e 1.00 BSC
b 0.46 REF
Notes: 1. This drawing is for general information only. Refer to JEDEC Drawing MO-205 for proper dimensions, tolerances, datums, etc.
2. Array as seen from the bottom of the package.
30 AT94S Secure Family 2314D–FPSLI–2/04
144L1 – LQFP
2325 Orchard Parkway
San Jose, CA 95131
TITLE DRAWING NO.
R
REV.
144L1 A
11/30/01
144L1, 144-lead (20 x 20 x 1.4 mm Body), Low Profile
Plastic Quad Flat Pack (LQFP)
A1
A2
Bottom View
Side View
Top View
N
T
Y
R
U
C
O
L1
XX
E1
D1
e
D
E
b
COMMON DIMENSIONS
(Unit of Measure = mm)
SYMBOL MIN NOM MAX NOTE
1. This drawing is for general information only; refer to JEDEC Drawing MS-026 for additional information.
2. The top package body size may be smaller than the bottom package size by as much as 0.15 mm.
3. Dimensions D1 and E1 do not include mold protrusions. Allowable protrusion is 0.25 mm per side. D1 and E1 are maximum plastic
body size dimensions including mold mismatch.
4. Dimension b does not include Dambar protrusion. Allowable Dambar protrusion shall not cause the lead width to exceed the maximum
b dimension by more than 0.08 mm. Dambar cannot be located on the lower radius or the foot. Minimum space between protrusion and
an adjacent lead is 0.07 mm for 0.4 and 0.5 mm pitch packages.
5. These dimensions apply to the flat section of the lead between 0.10 mm and 0.25 mm from the lead tip.
6. A1 is defined as the distance from the seating place to the lowest point on the package body.
A1 0.05 0.15 6
A2 1.35 1.40 1.45
D 22.00 BSC
D1 20.00 BSC 2, 3
E 22.00 BSC
E1 20.00 BSC 2, 3
e 0.50 BSC
b 0.17 0.22 0.27 4, 5
L1 1.00 REF
Notes:
Printed on recycled paper.
2314D–FPSLI–2/04 xM
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