This is information on a product in full production.
June 2017 DocID15701 Rev 11 1/38
VNH5019A-E
Automotive fully integrated H-bridge motor driver
Datasheet - production data
Features
AEC-Q100 qualified
ECOPACK®: lead free and RoHS
compliant
Output current: 30 A
3 V CMOS compatible inputs
Undervoltage and overvoltage shutdown
High-side and low-side thermal shutdown
Cross-conduction protection
Current limitation
Very low standby power consumption
PWM operation up to 20 kHz
Protection against:
Loss of ground and loss of VCC
Current sense output proportional to motor
current
Charge pump output for reverse polarity
protection
Output protected against short to ground and
short to VCC
Description
The VHN5019A-E is a full bridge motor driver
intended for a wide range of automotive
applications. The device incorporates a dual
monolithic high-side drivers and two low-side
switches. The high-side driver switch is designed
using STMicroelectronics’ well known and proven
proprietary VIPower®M0 technology that allows
to efficiently integrate on the same die a true
Power MOSFET with an intelligent
signal/protection circuit.
The three dice are assembled in a
MultiPowerSO-30 package on electrically isolated
lead-frames. This package, specifically designed
for harsh automotive environments offers
improved thermal performance thanks to exposed
die pads. The input signals INAand INBcan
directly interface the microcontroller to select the
motor direction and the brake condition.
The DIAGA/ENAor DIAGB/ENB, when connected
to an external pull-up resistor, enables one leg of
the bridge. It also provides a feedback digital
diagnostic signal. The CS pin allows to monitor
the motor current by delivering a current
proportional to its value when CS_DIS pin is
driven low or left open. The PWM, up to 20 KHz,
lets us control the speed of the motor in all
possible conditions. In all cases, a low-level state
on the PWM pin turns off both the LSAand LSB
switches. When PWM rises to a high-level, LSAor
LSBturns on again depending on the input pin
state. Output current limitation and thermal
shutdown protect the concerned high-side in
short to ground condition.
The short to battery condition is revealed by the
overload detector or by thermal shutdown that
latches off the relevant low-side.
Active VCC pin voltage clamp protects the device
against low energy spikes in all configurations for
the motor. The CP pin provides the necessary
gate drive for an external N-channel PowerMOS
used for reverse polarity protection.
Type RDS(on) Iout Vccmax
VNH5019A-E 18 mtyp
per leg) 30 A 41 V
MultiPowerSO-30™
www.st.com
Contents VNH5019A-E
2/38 DocID15701 Rev 11
Contents
1 Block diagram and pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
2 Electrical specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
2.1 Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
2.2 Thermal data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
2.3 Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
2.4 Waveforms and truth table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
2.5 Reverse battery protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
3 Package and PCB thermal data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
3.1 MultiPowerSO-30 thermal data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
3.1.1 Thermal calculation in clockwise and anti-clockwise operation in
steady-state mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
3.1.2 Thermal calculation in transient mode . . . . . . . . . . . . . . . . . . . . . . . . . . 27
4 Package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
4.1 MultiPowerSO-30 package information . . . . . . . . . . . . . . . . . . . . . . . . . . 31
4.2 MultiPowerSO-30 suggested land pattern . . . . . . . . . . . . . . . . . . . . . . . . 33
4.3 MultiPowerSO-30 packing information . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
5 Order codes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
6 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
DocID15701 Rev 11 3/38
VNH5019A-E List of tables
38
List of tables
Table 1. Suggested connections for unused and non connected pins . . . . . . . . . . . . . . . . . . . . . . . . 6
Table 2. Pin definitions and functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Table 3. Block descriptions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Table 4. Absolute maximum rating . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Table 5. Thermal data. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Table 6. Power section . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Table 7. Logic inputs (INA, INB, ENA, ENB,PWM, CS_DIS) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Table 8. Switching (VCC = 13 V, RLOAD = 0.87 W, Tj = 25 °C) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Table 9. Protection and diagnostic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Table 10. Current sense (8 V < VCC < 21 V). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Table 11. Charge pump . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Table 12. Truth table in normal operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Table 13. Truth table in fault conditions (detected on OUTA). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Table 14. Electrical transient requirements (part 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Table 15. Electrical transient requirements (part 2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Table 16. Electrical transient requirements (part 3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Table 17. Thermal calculation in clockwise and anti-clockwise operation in steady-state mode . . . . 27
Table 18. Thermal parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
Table 19. MultiPowerSO-30 mechanical data. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
Table 20. Device summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
Table 21. Document revision history. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
List of figures VNH5019A-E
4/38 DocID15701 Rev 11
List of figures
Figure 1. Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
Figure 2. Configuration diagram (top view) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Figure 3. Current and voltage conventions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Figure 4. Typical application circuit for DC to 20 kHz PWM operation with reverse battery
protection (option A) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15
Figure 5. Typical application circuit for DC to 20 kHz PWM operation with reverse battery
protection (option B) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .16
Figure 6. Behavior in fault condition (how a fault can be cleared) . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Figure 7. Definition of the delay time measurement . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Figure 8. Definition of the low-side switching times . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Figure 9. Definition of the high-side switching times . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Figure 10. Definition of dynamic cross conduction current during a PWM operation. . . . . . . . . . . . . . 21
Figure 11. Waveforms in full bridge operation (part 1). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
Figure 12. Waveforms in full bridge operation (part 2). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
Figure 13. Definition of delay response time of sense current. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
Figure 14. Half-bridge configuration. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
Figure 15. Multi-motor configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
Figure 16. MultiPowerSO-30™ PC board . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
Figure 17. Chipset configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
Figure 18. Auto and mutual Rthj-amb vs PCB copper area in open box free air condition . . . . . . . . . 26
Figure 19. Chipset configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
Figure 20. MultiPowerSO-30 HSD thermal impedance junction ambient single pulse . . . . . . . . . . . . 28
Figure 21. MultiPowerSO-30 LSD thermal impedance junction ambient single pulse . . . . . . . . . . . . . 28
Figure 22. Thermal fitting model of an H-bridge in MultiPowerSO-30 . . . . . . . . . . . . . . . . . . . . . . . . . 29
Figure 23. MultiPowerSO-30 package outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
Figure 24. MultiPowerSO-30 suggested pad layout. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
Figure 25. MultiPowerSO-30 tape and reel shipment (suffix “TR”) . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
DocID15701 Rev 11 5/38
VNH5019A-E Block diagram and pin description
38
1 Block diagram and pin description
Figure 1. Block diagram
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Block diagram and pin description VNH5019A-E
6/38 DocID15701 Rev 11
Figure 2. Configuration diagram (top view)
Table 1. Suggested connections for unused and non connected pins
Connection / pin Current sense N.C. OUTx
INPUTx, PWM
DIAGx/ENx
CS_DIS
Floating Not allowed X X X
To ground Through 1 k resistor X Not allowed Through 10 k
resistor
Table 2. Pin definitions and functions
Pin Symbol Function
1, 25, 30 OUTA,
Heat Slug2
Source of high-side switch A / drain of low-side switch A, power
connection to the motor
2,14,17, 22,
24,29 N.C. Not connected
3, 13, 23 VCC,
Heat Slug1
Drain of high-side switches and connection to the drain of the
external PowerMOS used for the reverse battery protection
12 VBAT
Battery connection and connection to the source of the external
PowerMOS used for the reverse battery protection
5EN
A/DIAGA
Status of high-side and low-side switches A; open drain output.
This pin must be connected to an external pull-up resistor. When
externally pulled low, it disables half-bridge A. In case of fault
detection (thermal shutdown of a high-side FET or excessive
ON-state voltage drop across a low-side FET), this pin is pulled
low by the device (see Table 13: Truth table in fault conditions
(detected on OUTA).
OUT
A
OUT
A
OUT
A
OUT
B
OUT
B
N.C.
V
CC
IN
A
EN
A
/DIAG
A
CS_DIS
PWM
CS
EN
B
/DIAG
B
IN
B
CP
V
BAT
V
CC
OUT
B
N.C.
N.C.
GND
A
GND
A
GND
A
N.C.
V
CC
N.C.
GND
B
GND
B
GND
B
1
15 16
30
V
CC
Heat Slug1
OUT
B
Heat Slug3
OUT
A
Heat Slug2
N.C.
DocID15701 Rev 11 7/38
VNH5019A-E Block diagram and pin description
38
)
6 CS_DIS Active high CMOS compatible pin to disable the current sense
pin
4IN
AClockwise input. CMOS compatible
7 PWM PWM input. CMOS compatible.
8CS
Output of current sense. This output delivers a current
proportional to the motor current, if CS_DIS is low or left open.
The information can be read back as an analog voltage across
an external resistor.
9EN
B/DIAGB
Status of high-side and low-side switches B; Open drain output.
This pin must be connected to an external pull up resistor. When
externally pulled low, it disables half-bridge B. In case of fault
detection (thermal shutdown of a high-side FET or excessive
ON-state voltage drop across a low-side FET), this pin is pulled
low by the device (see Table 13: Truth table in fault conditions
(detected on OUTA).
10 INBCounter clockwise input. CMOS compatible
11 CP Connection to the gate of the external MOS used for the reverse
battery protection
15, 16, 21 OUTB,
Heat Slug3
Source of high-side switch B / drain of low-side switch B, power
connection to the motor
26, 27, 28 GNDASource of low-side switch A and power ground(1)
18, 19, 20 GNDBSource of low-side switch B and power ground(1)
1. GNDA and GNDB must be externally connected together
Table 3. Block descriptions(1)
Name Description
Logic control Allows the turn-on and the turn-off of the high-side and the
low-side switches according to the Table 12.
Overvoltage + undervoltage Shut down the device outside the range [4.5 V to 24 V] for the
battery voltage.
High-side, low-side and clamp
voltage
Protect the high-side and the low-side switches from the
high-voltage on the battery line in all configuration for the motor.
High-side and low-side driver Drive the gate of the concerned switch to allow a proper RDS(on)
for the leg of the bridge.
Linear current limiter Limits the motor current, by reducing the high-side switch
gate-source voltage when short-circuit to ground occurs.
High-side and low-side
overtemperature protection
In case of short-circuit with the increase of the junction
temperature, it shuts down the concerned driver to prevent its
degradation and to protect the die.
Low-side overload detector Detects when low-side current exceeds shutdown current and
latches off the concerned low-side.
Table 2. Pin definitions and functions (continued)
Pin Symbol Function
Block diagram and pin description VNH5019A-E
8/38 DocID15701 Rev 11
Charge pump Provides the voltage necessary to drive the gate of the external
PowerMOS used for the reverse polarity protection
Fault detection
Signalizes an abnormal condition of the switch (output
shorted to ground or output shorted to battery) by pulling
down the concerned ENx/DIAGx pin.
Power limitation Limits the power dissipation of the high-side driver inside
safe range in case of short to ground condition.
1. See Figure 1
Table 3. Block descriptions(1) (continued)
Name Description
DocID15701 Rev 11 9/38
VNH5019A-E Electrical specifications
38
2 Electrical specifications
Figure 3. Current and voltage conventions
2.1 Absolute maximum ratings
Stressing the device above the rating listed in the “absolute maximum ratings” table may
cause permanent damage to the device. These are stress ratings only and operation of the
device at these or any other conditions above those indicated in the operating sections of
this specification is not implied. Exposure to absolute maximum rating conditions for
extended periods may affect device reliability. Refer also to the STMicroelectronics SURE
program and other relevant quality document.
VCC
INA
GNDB
IS
IOUTA
IINA
VINA
VCC
VOUTA
ISENSE
VOUTB
DIAGA/ENA
IENA
IGND
IOUTB
INB
IINB
DIAGB/ENB
IENB
VENB
VENA
VINB
VSENSE
OUTA
OUTB
PWM
CS
Ipw
Vpw
GNDA
GND
CP VBAT
IBAT
VBAT
VCP
ICP
CS_DIS ICSD
VCSD
Table 4. Absolute maximum rating
Symbol Parameter Value Unit
VBAT Maximum battery voltage(1) -16
+41
V
V
VCC Maximum bridge supply voltage + 41 V
Imax Maximum output current (continuous) 30 A
IR Reverse output current (continuous) -30 A
IIN Input current (INA and INB pins) +/- 10 mA
IEN Enable input current (DIAGA/ENA and DIAGB/ENB pins) +/- 10 mA
Ipw PWM input current +/- 10 mA
ICP CP output current +/- 10 mA
ICS_DIS CS_DIS input current +/- 10 mA
Electrical specifications VNH5019A-E
10/38 DocID15701 Rev 11
2.2 Thermal data
VCS Current sense maximum voltage VCC - 41
+VCC
V
V
VESD
Electrostatic discharge (human body model: R = 1.5 k,
C = 100 pF) 2kV
TcCase operating temperature -40 to 150 °C
TSTG Storage temperature -55 to 150 °C
1. This applies with the n-channel MOSFET used for the reverse battery protection. Otherwise VBAT has to be
shorted to VCC.
Table 4. Absolute maximum rating (continued)
Symbol Parameter Value Unit
Table 5. Thermal data
Symbol Parameter Max. value Unit
Rthj-case
Thermal resistance junction-case HSD 1.7 °C/W
Thermal resistance junction-case LSD 3.2 °C/W
Rthj-amb Thermal resistance junction-ambient See Figure 18 °C/W
DocID15701 Rev 11 11/38
VNH5019A-E Electrical specifications
38
2.3 Electrical characteristics
Values specified in this section are for 8 V < VCC < 21 V, -40 °C < Tj < 150 °C, unless
otherwise specified.
Table 6. Power section
Symbol Parameter Test conditions Min. Typ. Max. Unit
VCC
Operating bridge supply
voltage 5.5 24 V
ISSupply current
OFF-state with all fault cleared and ENx = 0 V
(standby):
INA = INB = PWM = 0; Tj = 25 °C; VCC = 13 V
INA = INB = PWM = 0
OFF-state (no standby):
INA = INB = PWM = 0; ENx = 5 V
10 15
60
6
μA
μA
mA
ON-state:
INA or INB = 5 V, no PWM
INA or INB = 5 V, PWM = 20 kHz
48
8
mA
mA
RONHS
Static high-side
resistance
IOUT = 15 A; Tj = 25 °C 12.0
m
IOUT = 15 A; Tj = - 40 °C to 150 °C 26.5
RONLS
Static low-side
resistance
IOUT = 15 A; Tj = 25 °C 6.0
m
IOUT = 15 A; Tj = - 40 °C to 150 °C 11.5
Vf
High-side
free-wheeling diode
forward voltage
If = 15 A,
Tj = 150 °C 0.6 0.8 V
IL(off)
High-side OFF-state
output current (per
channel)
Tj = 25 °C; VOUTX = ENX = 0 V; VCC = 13 V 3
μA
Tj = 125 °C; VOUTX = ENX = 0 V; VCC = 13 V 5
Table 7. Logic inputs (INA, INB, ENA, ENB,PWM, CS_DIS)
Symbol Parameter Test conditions Min. Typ. Max. Unit
VIL
Low-level input
voltage
Normal operation (DIAGX/ENX pin
acts as an input pin) 0.9 V
VIH
High-level input
voltage
Normal operation (DIAGX/ENX pin
acts as an input pin) 2.1 V
IINL Low-level input current VIN = 0.9 V 1 μA
IINH
High-level input
current VIN = 2.1 V 10 μA
VIHYST
Input hysteresis
voltage
Normal operation (DIAGX/ENX pin
acts as an input pin) 0.15 V
Electrical specifications VNH5019A-E
12/38 DocID15701 Rev 11
VICL Input clamp voltage
IIN = 1 mA 5.5 6.3 7.5
V
IIN = -1 mA -1.0 -0.7 -0.3
VDIAG
Enable low-level
output voltage
Fault operation (DIAGX/ENX pin
acts as an output pin); IEN = 1 mA 0.4 V
Table 8. Switching (VCC = 13 V, RLOAD = 0.87 , Tj = 25 °C)
Symbol Parameter Test conditions Min Typ Max Unit
f PWM frequency 0 20 kHz
td(on) HSD rise time Input rise time < 1μs
(see Figure 9)250 μs
td(off) HSD fall time Input rise time < 1μs
(see Figure 9)250 μs
trLSD rise time (see Figure 8)12μs
tfLSD fall time (see Figure 8)12μs
tDEL
Delay time during change of
operating mode (see Figure 7) 200 400 1600 μs
trr
High-side free wheeling
diode reverse recovery time (see Figure 10) 110 ns
IRM
Dynamic cross-conduction
current
IOUT = 15 A
(see Figure 10)2A
Table 9. Protection and diagnostic
Symbol Parameter Test conditions Min Typ Max Unit
VUSD
VCC undervoltage
shutdown 4.5 5.5 V
VUSDhyst
VCC undervoltage
shutdown hysteresis 0.5 V
VOV VCC overvoltage shutdown 24 27 30 V
ILIM_H High-side current limitation 30 50 70 A
ISD_LS Low-side shutdown current 70 115 160 A
VCLPHS(1)
High-side clamp voltage
(VCC to OUTA = 0 or
OUTB = 0)
IOUT = 15 A 43 48 54 V
VCLPLS(1)
Low-side clamp voltage
(OUTA = VCC or
OUTB = VCC to GND)
IOUT = 15 A 27 30 33 V
TTSD(2) Thermal shutdown
temperature VIN = 2.1 V 150 175 200 °C
Table 7. Logic inputs (INA, INB, ENA, ENB,PWM, CS_DIS) (continued)
Symbol Parameter Test conditions Min. Typ. Max. Unit
DocID15701 Rev 11 13/38
VNH5019A-E Electrical specifications
38
TTSD_LS
Low-side thermal
shutdown temperature VIN = 0 V 150 175 200 °C
TTR(3) Thermal reset temperature 135 °C
THYST(3) Thermal hysteresis 7 15 °C
1. The device is able to pass the ESD and ISO pulse requirements as specified in the Table 15.
2. TTSD is the minimum threshold temperature between HS and LS
3. Valid for both HSD and LSD
Table 9. Protection and diagnostic (continued)
Symbol Parameter Test conditions Min Typ Max Unit
Table 10. Current sense (8 V < VCC < 21 V)
Symbol Parameter Test conditions Min Typ Max Unit
K0IOUT/ISENSE
IOUT = 3 A, VSENSE = 0.5 V,
Tj = - 40 °C to 150°C 4670 7110 10110
dK0/K0
Analog current sense ratio
drift
IOUT = 3 A; VSENSE = 0.5 V,
Tj = -40 °C to 150 °C -19 19 %
K1IOUT/ISENSE
IOUT = 8 A,VSENSE = 1.3V,
Tj = - 40 °C to 150°C 6060 7030 8330
dK1/K1
Analog current sense ratio
drift
IOUT = 8 A; VSENSE = 1.3V,
Tj = -40 °C to 150 °C -14 14 %
K2IOUT/ISENSE
IOUT = 15 AVSENSE = 2.4 V,
Tj = - 40 °C to 150°C 6070 6990 7810
dK2/K2
Analog current sense ratio
drift
IOUT = 15 A; VSENSE = 2.4 V,
Tj = -40 °C to 150 °C -12 12 %
K3IOUT/ISENSE
IOUT = 25 AVSENSE = 4 V,
Tj = - 40 °C to 150°C 6000 6940 7650
dK3/K3
Analog current sense ratio
drift
IOUT =25 A; VSENSE = 4 V,
Tj = -40 °C to 150 °C -12 12 %
VSENSE
Max analog sense output
voltage IOUT = 15 A, RSENSE = 1.1 k5V
ISENSEO Analog sense leakage current
IOUT = 0 A, VSENSE = 0 V, VCSD = 5 V,
VIN = 0 V,
Tj = - 40 to 150°C
05
μA
IOUT = 0 A, VSENSE = 0 V, VCSD = 0 V,
VIN = 5 V,
Tj = - 40 to 150°C
0 100
tDSENSEH
Delay response time from
falling edge of CS_DIS pin
VIN = 5 V, VSENSE < 4 V, IOUT = 8 A,
ISENSE = 90% of ISENSEmax
(see fig Figure 13)
50 μs
tDSENSEL
Delay response time from
rising edge of CS_DIS pin
VIN = 5 V, VSENSE < 4 V, IOUT = 8 A,
ISENSE = 10% of ISENSEmax
(see fig Figure 13)
20 μs
Electrical specifications VNH5019A-E
14/38 DocID15701 Rev 11
2.4 Waveforms and truth table
In normal operating conditions the DIAGX/ENX pin is considered as an input pin by the
device. This pin must be externally pulled-high.
PWM pin usage: in all cases, a “0” on the PWM pin turns off both LSA and LSB switches.
When PWM rises back to “1”, LSA or LSB turns on again depending on the input pin state.
Table 11. Charge pump
Symbol Parameter Test conditions Min Typ Max Unit
VCP
Charge pump output
voltage
ENX = 5 V VCC + 5 VCC + 10
V
ENX = 5 V, VCC = 4.5 V 10.5
IBAT
Charge pump standby
current ENA = ENB = 0 V 200 nA
Table 12. Truth table in normal operating conditions
INAINBDIAGA/ENADIAGB/ENBOUTAOUTBCS (VCSD = 0 V) Operating mode
1 1 1 1 H H High imp. Brake to VCC
10 1 1 H LI
SENSE = IOUT/K Clockwise (CW)
01 1 1 L HI
SENSE = IOUT/K Counterclockwise
(CCW)
0 0 1 1 L L High imp. Brake to GND
DocID15701 Rev 11 15/38
VNH5019A-E Electrical specifications
38
Figure 4. Typical application circuit for DC to 20 kHz PWM operation with reverse battery
protection (option A)
DIAGB/ENB
+5V
1K
3.3K
INB
1K
GND
A
GND
B
C
Note:
The external N-channel Power MOSFET used for the reverse battery protection should have the following characteristics:
- BVdss > 20 V (for a reverse battery of -16 V);
- RDS(on) < 1/3 of H-bridge total RDS(on)
- Standard Logic Gate Driving
Electrical specifications VNH5019A-E
16/38 DocID15701 Rev 11
Figure 5. Typical application circuit for DC to 20 kHz PWM operation with reverse battery
protection (option B)
Note: In normal operating conditions the DIAGX/ENX pin is considered an input pin by the device.
This pin must be externally pulled high.
In case of a fault condition the DIAGX/ENX pin is considered an output pin by the device.
DIAG
B
/EN
B
+5V
1K
3.3K
INB
1K
GND
A
GND
B
C
Note:
The value of the blocking capacitor (C) depends on the application conditions and defines voltage and current ripple onto supply line at PWM
operation. Stored energy of the motor inductance may flyback into the blocking capacitor, if the bridge driver goes into 3-state. This causes a
hazardous overvoltage if the capacitor is not big enough. As basic orientation, 500 μF per 10 A load current is recommended.
Table 13. Truth table in fault conditions (detected on OUTA)
INAINBDIAGA/ENADIAGB/ENBOUTAOUTBCS (VCSD=0V)
1
1
0
1
OPEN
HHigh
impedance
0L
0
1HI
OUTB/K
0L
High
impedance
X X 0 OPEN
Fault Information Protection Action
DocID15701 Rev 11 17/38
VNH5019A-E Electrical specifications
38
The fault conditions are:
overtemperature on one or both high-sides (for example, if a short to ground occurs as
it could be the case described in line 1 and 2 in the Table 14);
Short to battery condition on the output (saturation detection on the low-side
Power MOSFET).
Possible origins of fault conditions may be:
OUTA is shorted to ground. It follows that, high-side A is in overtemperature state.
OUTA is shorted to VCC. It means that, low-side Power MOSFET is in saturation state.
When a fault condition is detected, the user knows which power element is in fault by
monitoring the INA, INB, DIAGA/ENA and DIAGB/ENB pins.
In any case, when a fault is detected, the faulty leg of the bridge is latched off. To turn on the
respective output (OUTX) again, the input signal must rise from low-level to high-level.
Figure 6. Behavior in fault condition (how a fault can be cleared)
Note: In case the fault condition is not removed, the procedure for unlatching and sending the
device in Stby mode is:
- Clear the fault in the device (toggle: INA if ENA=0 or INB if ENB=0)
- Pull low all inputs, PWM and Diag/EN pins within tDEL.
If the Diag/En pins are already low, PWM=0, the fault can be cleared by simply toggling the
input. The device enters in stby mode as soon as the fault is cleared.
Electrical specifications VNH5019A-E
18/38 DocID15701 Rev 11
Table 14. Electrical transient requirements (part 1)
ISO T/R
7637/1
Test pulse
Test level
I II III IV Delay and impedance
1 -25 V -50 V -75 V -100 V 2 ms, 10
2 +25 V +50 V +75 V +100 V 0.2 ms, 10
3a -25 V -50 V -100 V -150 V 0.1 s, 50
3b +25 V +50 V +75 V +100 V 0.1 s, 50
4 -4 V -5 V -6 V -7 V 100 ms, 0.01
5 +26.5 V +46.5 V +66.5 V +86.5 V 400 ms, 2
Table 15. Electrical transient requirements (part 2)
ISO T/R
7637/1
Test pulse
Test levels
I II III IV
1C C C C
2C C C C
3a C C C C
3b C C C C
4C C C C
5C E E E
Table 16. Electrical transient requirements (part 3)
Class Contents
CAll functions of the device are performed as designed after exposure to
disturbance.
E
One or more functions of the device are not performed as designed after
exposure to disturbance and cannot be returned to proper operation without
replacing the device.
DocID15701 Rev 11 19/38
VNH5019A-E Electrical specifications
38
2.5 Reverse battery protection
Against reverse battery condition the charge pump feature allows to use an external
N-channel MOSFET connected as shown in the typical application circuit (see Figure 4).
As alternative option, a N-channel MOSFET connected to GND pin can be used (see typical
application circuit in figure Figure 5).
With this configuration we recommend to short VBAT pin to VCC.
The device sustains no more than -30 A in reverse battery conditions because of the two
body diodes of the power MOSFETs. Additionally, in reverse battery condition the I/Os of
VNH5019A-E is pulled down to the VCC line (approximately -1.5 V). Series resistor must be
inserted to limit the current sunk from the microcontroller I/Os. If IRmax is the maximum
target reverse current through microcontroller I/Os, series resistor is:
Figure 7. Definition of the delay time measurement
R
V
IOs
V
CC
–
IRmax
------------------------------=
t
t
V
INB
V
INA,
t
PWM
t
I
LOAD
t
DEL
t
DEL
Electrical specifications VNH5019A-E
20/38 DocID15701 Rev 11
Figure 8. Definition of the low-side switching times
Figure 9. Definition of the high-side switching times
t
f
PWM
t
t
V
OUTA, B
20%
90% 80%
10%
t
r
t
t
V
OUTA
V
INA,
90%
10%
t
d(on)
t
d(off)
DocID15701 Rev 11 21/38
VNH5019A-E Electrical specifications
38
Figure 10. Definition of dynamic cross conduction current during a PWM operation
t
t
I
MOTOR
PWM
t
V
OUTB
t
I
CC
t
rr
I
RM
IN
A
=1, IN
B
=0
Electrical specifications VNH5019A-E
22/38 DocID15701 Rev 11
Figure 11. Waveforms in full bridge operation (part 1)
NORMAL OPERATION (DIAGA/ENA=1, DIAGB/ENB=1)
INA
INB
PWM
OUTA
OUTB
IOUTA->OUTB
DIAGA/ENA
DIAGB/ENB
DIAGB/ENB
INA
INB
PWM
OUTA
OUTB
DIAGA/ENA
NORMAL OPERATION (DIAGA/ENA=1, DIAGB/ENB=0 and DIAGA/ENA=0, DIAGB/ENB=1)
CS (*)
CS
IOUTA->OUTB
tDEL tDEL
LOAD CONNECTED BETWEEN OUTA, OUTB
LOAD CONNECTED BETWEEN OUTA, OUTB
(*) CS BEHAVIOUR DURING PWM MODE DEPENDS ON PWM FREQUENCY AND DUTY CYCLE
CS_DIS
CS_DIS
INA
INB
TjHSA
DIAGA/ENA
DIAGB/ENB
ILIM
TTSD_HSA
TTR_HSA
Tj>T
TR
CURRENT LIMITATION/THERMAL SHUTDOWN or OUTASHORTED TO GROUND
CS
IOUTA->OUTB
normal operation OUTAshorted to ground normal operation
CS_DIS
Tj<T
TSD
Tj=TTSD
power limitation
limitation
current
DocID15701 Rev 11 23/38
VNH5019A-E Electrical specifications
38
Figure 12. Waveforms in full bridge operation (part 2)
normal operation OUTAsoftly shorted to VCC normal operation undervoltage shutdown
INA
INB
OUTA
OUTB
DIAGB/ENB
DIAGA/ENA
OUTAshorted to VCC (resistive short) and undervoltage shutdown
CS V<nominal
IOUTA->OUTB
CS_DIS
Tj_LSA
TTSD_LS
normal operation OUTAhardly shorted to VCC normal operation undervoltage shutdown
INA
INB
OUTA
OUTB
DIAGB/ENB
DIAGA/ENA
OUTAshorted to VCC (pure short) and undervoltage shutdown
CS V<nominal
IOUTA->OUTB
CS_DIS
ILSA
ISD_LS
ILSA
ISD_LS
Tj_LSA
TTSD_LS
Electrical specifications VNH5019A-E
24/38 DocID15701 Rev 11
Figure 13. Definition of delay response time of sense current
The VNH5019A-E can be used as a high power half-bridge driver achieving an
on-resistance per leg of 9.5 m. The figure below shows the suggested configuration:
Figure 14. Half-bridge configuration
The VNH5019A-E can easily be designed in multi-motor driving applications such as seat
positioning systems where only one motor must be driven at a time. The DIAGX/ENX pins
allow the unused half-bridges to be put into high-impedance. The diagram that follows
shows the suggested configuration:
CURRENT SENSE
INPUT
LOAD CURRENT
CS_DIS
t
DSENSEH
t
DSENSEL
M
OUT
A
OUT
A
OUT
B
OUT
B
PWM
DIAG
A
/EN
A
IN
A
DIAG
B
/EN
B
IN
B
GND
B
GND
A
GND
B
GND
A
PWM
DIAG
A
/EN
A
IN
A
DIAG
B
/EN
B
IN
B
V
CC
V
CC
CP
CP
V
BAT
V
BAT
CS_DIS CS_DIS
DocID15701 Rev 11 25/38
VNH5019A-E Electrical specifications
38
Figure 15. Multi-motor configuration
M
2
OUT
A
OUT
A
OUT
B
OUT
B
V
CC
PWM
DIAG
A
/EN
A
IN
A
DIAG
B
/EN
B
IN
B
GND
B
GND
A
GND
B
GND
A
PWM
DIAG
A
/EN
A
IN
A
DIAG
B
/EN
B
IN
B
M
1
M
3
CS_DISCS_DIS
V
CC
CP
CP
V
BAT
V
BAT
Package and PCB thermal data VNH5019A-E
26/38 DocID15701 Rev 11
3 Package and PCB thermal data
3.1 MultiPowerSO-30 thermal data
Figure 16. MultiPowerSO-30™ PC board
Figure 17. Chipset configuration
Figure 18. Auto and mutual Rthj-amb vs PCB copper area in open box free air condition
Note: Layout condition of Rth and Zth measurements (PCB FR4 area = 58 mm x 58 mm, PCB
thickness = 2 mm, Cu thickness = 35 mm, Copper areas: from minimum pad lay-out to 16 cm2).
CHIP 1
RthA
CHIP 2 CHIP 3
RthB RthC
RthAB RthAC
RthBC
DocID15701 Rev 11 27/38
VNH5019A-E Package and PCB thermal data
38
3.1.1 Thermal calculation in clockwise and anti-clockwise operation in
steady-state mode
3.1.2 Thermal calculation in transient mode
Ths= Pdhs • Zhs + Zhsls • (PdlsA + PdlsB) + Tamb
TlsA= PdlsA • Zls + Pdhs • Zhsls + PdlsB • Zhsls + Tamb
TlsB= PdlsB • Zls + Pdhs • Zhsls + PdlsA • Zhsls + Tamb
Figure 19. Chipset configuration
Equation 1: pulse calculation formula
Table 17. Thermal calculation in clockwise and anti-clockwise operation in steady-state mode
Chip 1 Chip 2 Chip 3 Tjchip1 Tjchip2 Tjchip3
ON OFF ON Pdchip1 • RthA + Pdchip3 •
RthAC + Tamb
Pdchip1 • RthAB + Pdchip3 •
RthBC + Tamb
Pdchip1 • RthAC + Pdchip3 •
RthC + Tamb
ON ON OFF Pdchip1 • RthA + Pdchip2 •
RthAB + Tamb
Pdchip1 • RthAB + Pdchip2 • RthB
+ Tamb
Pdchip1 • RthAC + Pdchip2 •
RthBC + Tamb
ON OFF OFF Pdchip1 • RthA+ Tamb Pdchip1 • RthAB + Tamb Pdchip1 • RthAC + Tamb
ON ON ON Pdchip1 • RthA + (Pdchip2 +
Pdchip3) • RthAB + Tamb
Pdchip2 • RthB + Pdchip1 •
RthAB + Pdchip3 • RthBC + Tamb
Pdchip1 • RthAB + Pdchip2 •
RthBC + Pdchip3 • RthC + Tamb
CHIP 1
Zls
CHIP 2 CHIP 3
Zls Zls
Zhsls Zhsls
Zlsls
ZTHRTH ZTHtp 1–+=
where tpT=
Package and PCB thermal data VNH5019A-E
28/38 DocID15701 Rev 11
Figure 20. MultiPowerSO-30 HSD thermal impedance junction ambient single pulse
Figure 21. MultiPowerSO-30 LSD thermal impedance junction ambient single pulse
DocID15701 Rev 11 29/38
VNH5019A-E Package and PCB thermal data
38
Figure 22. Thermal fitting model of an H-bridge in MultiPowerSO-30
Table 18. Thermal parameters(1)
Area/island (cm2) Footprint 4 8 16
R1 = R7 (°C/W) 0.1
R2 = R8 (°C/W) 0.3
R3 = R10 = R16 (°C/W) 0.5
R4 (°C/W) 6
R5 (°C/W) 30 24 24 24
R6 (°C/W) 56 52 42 32
R9 = R15 (°C/W) 0.05
R11 = R17 (°C/W) 0.7
R12 = R18 (°C/W) 10
R13 = R19 (°C/W) 36 26 26 26
R14 = R20 (°C/W) 56 42 36 28
R21 = R22 (°C/W) 35 25 25 25
R23 (°C/W) 160 150 150 150
C1 = C7 = C9 = C15 (W.s/°C) 0.005
C2 = C8 (W.s/°C) 0.01
C3 (W.s/°C) 0.03
C4 (W.s/°C) 0.4
C5 (W.s/°C) 1.5 2 2 2
C6 (W.s/°C) 3456
C10 = C16 (W.s/°C) 0.015
C11 = C17 (W.s/°C) 0.05
Package and PCB thermal data VNH5019A-E
30/38 DocID15701 Rev 11
C12 = C18 (W.s/°C) 0.3
C13 = C19 (W.s/°C) 1.2 2 2 2
C14 = C20 (W.s/°C) 2.5 3 4 5
C21 = C22 = C23 (W.s/°C) 0.01 0.008 0.008 0.008
1. A blank space means that the value is the same as the previous one.
Table 18. Thermal parameters(1) (continued)
Area/island (cm2) Footprint 4 8 16
DocID15701 Rev 11 31/38
VNH5019A-E Package information
38
4 Package information
In order to meet environmental requirements, ST offers these devices in different grades of
ECOPACK® packages, depending on their level of environmental compliance. ECOPACK®
specifications, grade definitions and product status are available at: www.st.com.
ECOPACK® is an ST trademark.
4.1 MultiPowerSO-30 package information
Figure 23. MultiPowerSO-30 package outline
N
A2
0.35
A3
L
S
h x 45° BeA
F1 F1
E
30
1
E1
DF3
F2 F2
BOTTOM VIEW
C
Package information VNH5019A-E
32/38 DocID15701 Rev 11
Table 19. MultiPowerSO-30 mechanical data
Symbol
Data book mm
Min. Typ. Max.
A 2.35
A2 1.85 2.25
A3 0 0.1
B 0.42 0.58
C 0.23 0.32
D 17.1 17.2 17.3
E 18.85 19.15
E1 15.9 16 16.1
e1
F1 5.55 6.05
F2 4.6 5.1
F3 9.6 10.1
L 0.8 1.15
N 10°
S0° 7°
DocID15701 Rev 11 33/38
VNH5019A-E Package information
38
4.2 MultiPowerSO-30 suggested land pattern
Figure 24. MultiPowerSO-30 suggested pad layout
Package information VNH5019A-E
34/38 DocID15701 Rev 11
4.3 MultiPowerSO-30 packing information
The devices are packed in tape and reel shipments (see Figure 20: Device summary on
page 35).
Figure 25. MultiPowerSO-30 tape and reel shipment (suffix “TR”)
Reel dimensions
Dimension mm
Base q.ty 1000
Bulk q.ty 1000
A (max) 330
B (min) 1.5
C (± 0.2) 13
D (min) 20.2
G (+ 2 / -0) 32
N (min) 100
T (max) 38.4
To p
cover
tape
Start
No componentsNo components Components
500 mm min
500 mm min
Empty components pockets
User direction of feed
Tape dimensions
According to Electronic Industries Association (EIA)
Standard 481 rev. A, Feb 1986
Description Dimension mm
Tape width W 32
Tape hole spacing P0 (± 0.1) 4
Component spacing P 24
Hole diameter D (± 0.1/-0) 1.5
Hole diameter D1 (min) 2
Hole position F (± 0.1) 14.2
Compartment Depth K (max) 2.2
Hole Spacing P1 (± 0.1) 2
End
DocID15701 Rev 11 35/38
VNH5019A-E Order codes
38
5 Order codes
Table 20. Device summary
Package
Order codes
Tape and reel
MultiPowerSO-30 VNH5019ATR-E
Revision history VNH5019A-E
36/38 DocID15701 Rev 11
6 Revision history
Table 21. Document revision history
Date Revision Changes
22-Jan-2008 1 Initial release.
04-Nov-2009 2
Uploaded corporate template by using V3 version
Added Table 5: Thermal data
Section 2.1: Absolute maximum ratings
– Added text
Table 6: Power section
–I
S: added max value for INA = INB = PWM = 0; Tj = 25 °C;
VCC=13V in Test conditions, deleted INA = INB = PWM = 0
–V
f: changed Test conditions, changed typ/max value
–I
RM: deleted and copied in Table 8: Switching (VCC = 13 V,
RLOAD = 0.87 W, Tj = 25 °C) whole row
Table 8: Switching (VCC = 13 V, RLOAD = 0.87 W, Tj = 25 °C)
–t
DEL: changed min/typ/max value
– Copied IRM row by Table 6: Power section
Updated Table 10: Current sense (8 V < VCC < 21 V)
Table 11: Charge pump
–V
CP: changed min/max value for ENX = 5 V, changed typ
value for ENX = 5 V, VCC = 4.5 V
Updated Figure 11: Waveforms in full bridge operation (part 1)
Updated Figure 12: Waveforms in full bridge operation (part 2)
Added Chapter 4
16-Dec-2009 3
Updated following tables:
– Table 6: Power section
– Table 9: Protection and diagnostic
– Table 10: Current sense (8 V < VCC < 21 V)
Added Figure 6: Behavior in fault condition (how a fault can be
cleared)
Added Chapter 3: Package and PCB thermal data
06-Apr-2010 4
Updated Table 5: Thermal data.
Table 6: Power section:
–I
S: updated test condition and max value
Updated table notes on Table 9: Protection and diagnostic.
Table 10: Current sense (8 V < VCC < 21 V):
–dK
0/k0, dK1/k1, dK3/k3: updated minimum end maximum
values.
19-Apr-2010 5 Updated Table 10: Current sense (8 V < VCC < 21 V).
25-May-2010 6 Updated Features list.
Updated Table 6: Power section.
02-Sep-2010 7 Updated Table 5: Thermal data.
DocID15701 Rev 11 37/38
VNH5019A-E Revision history
38
22-Dec-2011 8
Updated Figure 1: Block diagram
Added Table 1: Suggested connections for unused and not
connected pins
Updated Table 3: Block descriptions
Table 8: Switching (VCC = 13 V, RLOAD = 0.87 W, Tj = 25 °C):
–T
TSD, TTR, THYST
: added note
–T
TSD_LS: added row
Updated Table 13: Truth table in fault conditions (detected on
OUTA)
Updated Figure 11: Waveforms in full bridge operation (part 1)
and Figure 12: Waveforms in full bridge operation (part 2)
19-Sep-2013 9 Updated Disclaimer.
11-Jan-2017 10
– Removed all information relative to tube packing of the
product
– Modified Section 4: Package information.
– Added AEC-Q100 qualified in the Features section
– Minor text edits throughout the document
26-Jun-2017 11 Updated Table 20: Device summary on page 35.
Table 21. Document revision history (continued)
Date Revision Changes
VNH5019A-E
38/38 DocID15701 Rev 11
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