SMT4004 QUAD TRACKING POWER SUPPLY MANAGER FEATURES & APPLICATIONS INTRODUCTION * Programmable Softstart, Tracking and Voltage Monitoring Functions * Controls 4 Independent Supplies Down to 0.9V * Programmable Bus-Side and Card-Side UV and OV Thresholds * Guarantees Differential Supply Tracking * Operates From Any One of Four Supply Voltages down to 2.7V * Four independent RST#s, two IRQ#s, CROWBAR and Circuit breaker functions * I2C 2-Wire Serial Bus Interface for Programming, Power On/Off and Operational Status * 256X8 Nonvolatile EEPROM Memory Array The SMT4004 is a fully integrated programmable voltage manager IC, providing supervisory functions and tracking control for up to four independent power supplies. The four internal managers perform the following functions: monitor source (bus-side) voltages for under-voltage and over-voltage conditions, monitor back end (card-side) voltages for under-voltage conditions, ensure voltages to the card-side track within specified parametric limits, and provide status information to a host processor. The SMT4004 incorporates nonvolatile programmable circuits for setting all monitored thresholds for each manager. Individual functions are also programmable allowing Interrupts or Reset conditions to be generated by many combinations of events. Also included are nonvolatile fault status registers and a 2K-bit (256 byte) nonvolatile memory. Applications * Power Supply Management * Telecom/Datacom Motherboards/Servers * Mezzanine Line Cards * Compact PCITM Hot Swap Control * Network Processors, DSPs, ASICs User programming of configuration and control values is simplified with the interface adapter (SMX3200) and Windows GUI software obtainable from Summit Microelectronics. SIMPLIFIED APPLICATIONS DRAWING 1.5V RS4 2.5V RS1 RS3 10 37 32 20 39 35 30 22 38 34 29 23 VI1 CB1 VGATE1 VO1 VI3 CB3 VGATE3 VO3 VI4 CB4 VGATE4 VO4 10 S E ATE D 1# 11 S E ATE D 2# 47 SCL 46 SDA 24 E N AB LE 31 21 VDD_CAP 36 VGG_CAP 40 P W R_O N GND VO2 IRQ _C LR # VGATE2 6 33 M R# 5 LD O # 1 W DO# 2 IRQ # 7 TRK R _IRQ # H E ALTHY# CB2 26 SM T4004 VI2 Bus-Side Connector 41 18 28 42 10 1uF 9 R S T1# 13 R S T2# 14 R S T3# 15 R S T4# 16 Card-Side Application Circuits 10 10 10F RS2 Note: This is an applications example only. Some pins, components and values are not shown. (c) SUMMIT Microelectronics, Inc. 2001 * 300 Orchard City Drive, #131 * Campbell CA 95006 * Phone 408 378-6461 * FAX 408 378-6596 www.summitmicro.com 2049 4.0 3/04/02 1 SMT4004 DETAILED DEVICE DESCRIPTION SUPPLY MANAGERS The SMT4004 has four distinct programmable power supply managers and associated circuitry. The managers are individually programmable and can operate independently or together with the other managers. Each manager monitors the bus and cardside voltages and current for that supply (Figure 1). The VI pin is the bus-side input that connects to two comparators to monitor under-voltage (UV) and overvoltage conditions (OV). The threshold for the UV detector is programmable in 20mV increments, from 0.9V to 6.0V. The OV detector is programmable in 4% increments of the UV settings, from 120% to 244% of the UV settings. The OV threshold is an offset from the UV sensor and the offset varies as the UV threshold; if UV is set to 0.9V then OV can be set from 1.08 to 2.2V. The OV setting is related to the UV setting according to: OV = UV X [(0.04 X DecVal) + 1.2] Where: UV1 = Card-side primary Under-voltage setting. UV2 = Card-side secondary Under-voltage setting. DecVal = Decimal value of UV2 Register contents. If the VO input is below the UV2 threshold the manager generates an UV2 fault status on the internal bus. Generally the first threshold, UV1, is used to provide a warning that the supply is deteriorating while the second threshold, UV2, is set lower to indicate the supply is out of the operating range. The UV1 and UV2 status outputs from the manager can be programmed to generate a Reset or an Interrupt. Programmable Offset VI - Where: OV = Bus-side Over-voltage setting. UV = Bus-side Under-voltage setting. DecVal = Decimal value of OV Register contents. OV + Programmable Threshold + The VO pin is the card-side input that connects to two comparators to monitor two under-voltage threshold conditions. The threshold for the first undervoltage monitor (UV1) is programmable in 20mV increments, from 0.9V to 6.0V. If the VO input is below the UV1 threshold the manager generates an UV1 fault status on the internal bus. VREF UV_OVERRIDE CB Programmable Delay 25mV 50mV Programmable QuickTrip Threshold VO + - QT-CB + - Programmable Threshold + VO UV1 - The threshold for the second under-voltage monitor can be set equal to the UV1 threshold or to one of 31 values less than UV1. The UV2 setting is related to the UV1 setting according to: UV2 = UV1 X [1-(0.01 X DecVal)] UV - Internal Bus If the VI input is below the UV threshold the manager generates a UV fault status on the internal bus. If the VI input is above the OV threshold the manager generates an OV fault status on the internal bus. The UV and OV status information can be selected to generate an IRQ# output. Refer to Figure 3 for an illustration of the IRQ# function and the relation of the UV and OV status of the four managers. Programmable Offset + VREF UV2 - Figure 1. Supply Manager Schematic. Summit Microelectronics, Inc 2049 4.0 3/04/02 2 SMT4004 DETAILED DEVICE DESCRIPTION (CONTINUED) The UV_OVERRIDE input is used to mask undervoltage conditions. When asserted (high) all undervoltage conditions are ignored. This function is used either during system test or when performing voltage margin tests. During normal operation this pin must be connected to ground. CB is the circuit breaker input. A series resistor placed between VI and CB causes the circuit breaker to trip when the voltage across the resistor exceeds the programmed value of 25mV or 50mV (VCB). A programmable filter is provided to allow voltage drops greater than VCB for selected delays of 25s, 50s, 100s or 200s. If the filter time is exceeded; an overcurrent condition (QT-CB) is generated from the manager. The CB pin is also connected to the QuickTrip comparator. It is used in conjunction with the circuit breaker function or may be disabled. When enabled, a voltage across the series resistor exceeding the QuickTrip threshold (VQT) instantly generates a QT-CB signal from the manager. VQT can be set to different levels depending on the CB selection; see VQT page 13. The QT-OC output from the manager can generate a RST# (Figure 2), an IRQ#, (Figure 3) or an internal force shutdown (FSD) and crowbar output (Figure 5). MR# is low, returning high tPRTO seconds after MR# is de-asserted. INTERRUPT (IRQ#) CIRCUIT The SMT4004 has an active-low open-drain IRQ# output. The sources for triggering an interrupt are selected from the UV, OV, UV1 and UV2 status outputs of each manager. When asserted, IRQ# is latched and can only be cleared by a high to low transition on the IRQ_CLR# pin (Figure 3). RESET & TRKR_IRQ SELECT REG 7 6 5 4 3 2 1 0 QT-CB2 RST2# PRT UV22 UV12 MR# QT-CB1 RST1# PRT UV21 DEVICE POWER SUPPLY The VI inputs also provide the operating supply voltage for the SMT4004. Internally they are diodeOR'ed, so the highest potential VI input becomes the VDD supply. Refer to the functional Block Diagram on page 8. UV11 UV13 RST3# UV23 PRT QT-CB3 UV14 RESET CIRCUIT RST4# The SMT4004 has four active-low, open-drain Reset pins (RST1# - RST4#). All RST# outputs are asserted once power is applied; remaining asserted for tPRTO (programmable reset timeout period, Figure 10) after all Reset generating conditions are removed. UV24 PRT QT-CB4 7 6 5 4 3 2 1 0 RESET & TRKR_IRQ SELECT REG PRT Programmable Reset Timer reset circuit Individual RST# outputs can be programmed to become active from three manager status conditions: UV1, UV2 or QT-CB. The RST# output remains active for tPRTO after the fault condition is removed (Figure 2). Asserting the Manual Reset input (MR# low) forces all RST# outputs low. The RST# outputs remain low while Summit Microelectronics, Inc Figure 2. Programmable and hard-wired sources for generating resets. 2049 4.0 3/04/02 3 SMT4004 DETAILED DEVICE DESCRIPTION (CONTINUED) IRQ# SELECT REGISTER 7 6 5 4 3 2 1 0 UV22 UV12 UV2 OV2 UV21 UV11 UV1 OV1 OV3 IRQ# UV3 SET Q UV13 Q RESET UV23 VDD_CAP OV4 IRQ_CLR# UV4 UV14 UV24 7 6 5 4 3 2 1 0 IRQ# SELECT REGISTER IRQ# SELECT REGISTER 3 2 1 0 QT_CB4 QT_CB3 QT_CB2 QT_CB1 Figure 3. Interrupt sources from the SMT4004 supply managers. Summit Microelectronics, Inc 2049 4.0 3/04/02 4 SMT4004 DETAILED DEVICE DESCRIPTION (CONTINUED) CHARGE PUMP AND VGATE CONTROL VGATE output. The VGATE outputs control the gate voltages of external N-channel MOSFETs. Each MOSFET separates the bus and card-side voltages. The VGATE outputs control the card-side slew rates during the power-on/off interval. The VGATEs are turned on when their controlling inputs meet either softstart conditions or when tracking conditions are met so the MOSFET card-side voltages track. The manager inputs (Figure 1) and the control inputs (Figure 4) control the VGATE outputs. The VGATE control blocks (Figure 4) are the logic functions controlling the VGATE outputs. All inputs to these blocks are used to enable the VGATE outputs to drive the external MOSFETs. The ENABLE input only affects the charge pump (VGG_CAP voltage). Its active state is programmable and must be true to turn-on the charge pump. The charge pump provides the high-side drive voltage to the VGATE pins. The PWR_ON and FORCE_SD inputs active states are programmable. PWR_ON, SEATED1# and SEATED2# must be true and FORCE_SD false to enable a power-on sequence. Certain conditions must be met for the VGATE outputs to become active. The conditions are defined by the sequence enable logic, the manager inputs and the user selected function (softstart or track) for each VD D _ C A P SEQUENCE E N AB LE LO G IC 1 00 K 4 p lcs Ac tive H ig h P W R _O N Ac tive L o w S E ATE D 1# S E ATE D 2# Ac tive H ig h FO R C E _S D Ac tive L o w Ac tive H ig h E N AB LE Ac tive L o w C harg e Pu m p Tracker S elect R egs VG 4 VG 3 VG 2 VG 1 OV1 UV1 OV2 UV2 OV3 UV3 OV4 UV4 V G ATE C O N TR O L VG AT E C ircu it V G ATE 1 VG AT E C ircu it V G ATE 2 VG AT E C ircu it V G ATE 3 VG AT E C ircu it V G ATE 4 S O F TS TAR T DONE F SD OV1 UV1 OV2 UV2 V G ATE C O N TR O L OV3 UV3 TR AC K IN G TRKR1 TRKR2 TR K R _IR Q # TRKR3 OV4 UV4 TRKR4 VO1 VO2 VO3 VO4 TR K R _IR Q S E LE C T Figure 4. Charge Pump and VGATE Control Summit Microelectronics, Inc 2049 4.0 3/04/02 5 SMT4004 DETAILED DEVICE DESCRIPTION (CONTINUED) If both softstart and tracking are enabled, the softstart VGATE outputs must be fully on (VGATE = VGG_CAP) before the tracking VGATEs are enabled. The VO inputs are monitored and compared by the tracking logic to control the VGATEs of the tracked voltages. They are also used by the VGATE tracking control logic to generate a TRKR_IRQ# output if a differential of >300mV between any tracked VO input occurs during the tracking interval. The CBFAULT is programmable as an active high or active low output. It is asserted when an overcurrent condition (QT-CB) occurs (Figure 6). T R K R _IR Q IR Q 1 R ST 1 FORCE SHUTDOWN AND CROWBAR The VGATE outputs can be rapidly shutdown by asserting the FORCE_SD input or when an internally generated force shutdown (FSD) occurs. IR Q 2 Q Q QT-CB1 RESET QT-CB2 VDD_CAP QT-CB3 QT-CB4 FORCE_SD CROWBAR IRQ CROWBAR FUNCTION SELECT TRKR_IRQ FSD T ypical of All Channels R ST 2 IR Q 3 SET R ST X C ard-S ide U V2 X Q T -C B X HEALTHY# AND CBFAULT BEGIN_TRK IR Q X C ard-S ide U V1 X Internal sources that generate a force shutdown are programmable and are: a TRKR_IRQ#, a general IRQ# or an over-current condition (QT-CB) (Figure 5). The SMT4004 has two status output pins, HEALTHY# and CBFAULT (Figure 6). HEALTHY# is an active-low open-drain output that is asserted when all bus and card-side conditions are within the programmed settings, i.e., there must be no bus or card-side fault conditions (programmed RST#s, IRQ#s, or TRKR_IRQ#s) from the bus-side UV, OV and card-side UV1, UV2 and QT-CB outputs from the managers. If no RST#s, IRQ#s, or TRKR_IRQ#s are enabled, HEALTHY# will stay asserted even if fault conditions exist. HEALTHY# is an instantaneous indication of the status of the signals RST#s, IRQ#, and TRKR_IRQ# and is derived from the unlatched versions of these signals. C ard-S ide U V1 X C ard-S ide U V2 X B us-S ide U V X B us-S ide O V X H EALT H R ST 3 IR Q 4 R ST 4 Q T -C B 1 Q T -C B 2 Q T -C B 3 Q T -C B 4 C B FAU LT Figure 6. HEALTHY# and CBFAULT circuitry. FAULT STATUS REGISTERS The SMT4004 has three nonvolatile fault status registers. When an IRQ# is generated the cause of the interrupt is recorded in the fault register. The fault source is indicated as a `1' in the assigned bit location (Figure 7). The fault status registers are overwritten each time an IRQ# is generated. The fault status registers are always available for reading except for when a nonvolatile write is in progress. The conditions for overwriting (clearing) the fault condition is dependent upon the device configuration with regard to the programmable `active writing state' of the MR# input. Clearing the fault status registers is not necessary as the last fault condition overwrites any information previously stored. If clearing the registers is desired, it is accomplished by forcing a write to those registers while no fault conditions exist. FORCE_SD REG Figure 5. Force Shutdown (FSD) and CROWBAR circuitry. Summit Microelectronics, Inc 2049 4.0 3/04/02 6 SMT4004 DETAILED DEVICE DESCRIPTION (CONTINUED) For prototyping purposes, the Windows GUI (described in the Serial Interface section) has an option to clear the fault status registers. Fault recording is disabled when the PWR_ON input is de-asserted. F ault Status R eg ister Ad d ress 1D 0 The SMT4004 uses the industry standard I2C, 2wire serial data interface. This interface provides access to the configuration registers, the nonvolatile fault registers and a 2K-bit (256 byte) nonvolatile memory. The interface has three address inputs (A0 A2) allowing up to eight devices on the same bus. This allows multiple devices on the same board or multiple boards in a system to be controlled with two signals; SDA and SCL. 6 5 4 3 2 1 0 UV1 1 UV1 2 UV1 3 UV1 4 UV2 1 UV2 2 UV2 3 UV2 4 F ault Status R eg ister Ad d ress 1E 7 The configuration and nonvolatile fault registers share the same device type identifier, 1001[bin], which is distinct from the 2K memory device type identifier, optionally 1010[bin] or 1011[bin]. The separation of address space allows full utilization of the memory array. The memory is functionally identical to the industry standard 24C02. 4 3 2 1 0 QT -CB 1 QT -CB 2 QT -CB 3 QT -CB 4 5 T RKR 3 T RKR 2 T RKR 1 6 T RKR 4 F ault Status R eg ister Ad d ress 1F 7 The memory array can be read with MR# low. The memory array cannot be written when the part is in reset whether from MR# being low or from any other reset source. The configuration and fault registers may be read regardless of the state of MR#. A user option selects the active state of the MR# input for writing to the configuration and fault registers. Figure 7. Fault Status register bit allocation WATCHDOG AND LONGDOG TIMERS The SMT4004's internal timer triggers the activation of the LDO# and WDO# outputs. LDO# and WDO# are active-low open-drain outputs that can be wire-OR'ed with other open-drain signals. During a power-on sequence the timers are disabled until all four Resets are released. At this time both timers, if enabled, begin clocking at t0. If either times out, it asserts its respective output. The timers work in tandem, so any high to low transition on the WLDI input Resets both timers to t0. The longdog timer must be programmed to timeout sometime after the watchdog timer. The WDO# could Summit Microelectronics, Inc Both timers can be programmed off, facilitating system debug. This feature can also be used to allow an operating system to boot-up and configure itself without Interrupts or Resets. SERIAL INTERFACE OV 4 1 OV 3 2 OV 2 3 OV 1 4 UV 4 5 UV 3 6 UV 2 UV 1 7 then be wire-OR'ed with the IRQ# output to provide an alert that action needs to be taken. The LDO# output could be wire-OR'ed with a system RST# signal to indicate a shutdown condition exists. Device configuration utilizing the Windows based SMT4004 graphical user interface (GUI) is highly recommended. The software is available from the Summit website (www.summitmicro.com). Using the GUI in conjunction with this datasheet and Application Note 22, simplifies the process of device prototyping and the interaction of the various functional blocks. A programming Dongle (SMX3200) is available from Summit to communicate with the SMT4004. The Dongle connects directly to the parallel port of a PC and programs the device through a cable using the I2C bus protocol. 2049 4.0 3/04/02 7 SMT4004 SEATED1# SEATED2# ENABLE 33 10 11 24 V DD _C AP IRQ_CLR# PW R_ON 27 M R# FORCE_S D INTERNAL BLOCK DIAGRAM 5 6 13 V I1 41 VO1 20 CB1 37 SUP P LY M ANAG E R #1 RES E T INTE R RUPT CO N TRO L & FAULT STATUS REG ISTE RS 12 UV_ O VER RIDE RST2# 15 RST3# 16 7 9 25 3 SEQ U E NCE ENABLE LO G IC V I2 40 VO2 21 CB2 36 39 VO3 22 CB3 35 1.25V R EF RST4# IRQ # TRKR_IRQ # CBFAULT CRO W BAR 26 HEALTHY# 32 V G ATE 1 SUP P LY M ANAG E R #2 CHARG E PUM P & VG ATE CO N TRO L V I3 RST1# 14 SUP P LY M ANAG E R #3 All R esistors are 100K TIM E R LO G IC 31 V G ATE 2 30 V G ATE 3 29 V G ATE 4 28 V G G _CAP 48 W LD I 1 LD O # 2 W DO # 4 P O W E R S U P PL Y AR B IT R AT IO N 34 8 17 18 19 42 VDD_CAP CB4 S E R IAL INTE R FACE & M E M O RY ARR AY SUP P LY M ANAG E R #4 AGND 23 DGND VO4 PGND 38 PGND V I4 47 SCL 46 SDA 43 A0 44 A1 45 A2 Figure 7A. SMT4004 Internal Block Diagram. Summit Microelectronics, Inc 2049 4.0 3/04/02 8 SMT4004 PIN D PIN DESCRIPTIONS Pin Number Pin Type Pin Name 1 O LDO# 2 O WDO# P 3 O 4 PWR (out) CROWBAR 1.25VREF 5 I MR# 6 I IRQ_CLR# 7 O IRQ# 8 PWR PGND 9 O TRKR_IRQ# 10 I SEATED1# 11 I SEATED2# Description The longdog timer output is an active low open-drain output. It is driven low when the longdog timer has timed out. The watchdog timer output is an active low open-drain output. It is driven low when the watchdog timer has timed out. CROWBAR is an active high totem pole output. It is a programmable output; it can act as a CROWBAR output or as an Early-Voltage-Drive (EVD) output. As a CROWBAR it generates a short duration (20s) positive pulse generally used to trigger an external SCR. The sources for initiating the pulse are user selectable and are illustrated in Figure 5. As an EVD output, the pin is held high until the SMT4004 begins tracking, allowing an external MOSFET to discharge any residual voltages on the cardside power rails. The 1.25VREF pin provides a 1.25V reference output voltage. It requires a 0.1F bypass capacitor to AGND (pin 19). The MR# (manual Reset) pin is an active low input. When MR# is driven low, the RST1#-RST4# pins are driven low and stay low while MR# is asserted. After MR# returns high, the Reset outputs remain low for tPRTO. Asserting MR# also resets the watchdog and longdog timers to t0 after the expiration of tPRTO. The MR# pin is internally pulled-up to VDD_CAP with a 100K resistor. The IRQ_CLR# pin is an active low input. A low on IRQ_CLR# clears any active IRQ#. As long as IRQ_CLR# is held low, IRQ#s are blocked. The IRQ_CLR# pin is internally pulled-up to VDD_CAP with a 100K resistor. The IRQ# is an active low open-drain output. It is driven low when one or more of its programmable triggers are active. The programmable trigger sources are illustrated in Figure 3. PGND is the ground for the power portion of the internal circuitry. It is internally tied to pin 17. Both pins must be tied to system ground. TRKR_IRQ# is an active low open-drain output. It is driven low when one or more of its programmable triggers are active. The programmable trigger sources are tracking errors detected by the managers and are illustrated in Figure 4. The SEATED# inputs are effectively enable inputs. Both must be low for the power-on sequence to proceed. In applications utilizing staggered pin lengths the SEATED# inputs should be tied to the short pins. Internally these pins are pulled-up to VDD_CAP with 100K resistors. The UV_OVERRIDE pin is an active high input. When asserted, the UV comparators are disabled (Figure 1). Internally this pin is pulled-up to VDD_CAP with a 100K resistor. This pin must be low for normal operation. Note: P indicates the pin's function or the active state of the pin is programmable. 12 I UV_OVERRIDE Summit Microelectronics, Inc 2049 4.0 3/04/02 9 SMT4004 PIN DESCRIPTIONS (CONTINUED) Pin Number Pin Type Pin Name 13 O RST1# 14 O RST2# 15 O RST3# 16 O RST4# 17 PWR PGND 18 PWR DGND 19 PWR AGND 20 21 22 23 I I I I VO1 VO2 VO3 VO4 24 I 25 O P P 26 O 27 I 28 ENABLE P CBFAULT HEALTHY# FORCE_SD PWR VGG_CAP Description The RST# outputs are active low open-drain outputs. The supply manager trigger source for each Reset output is individually programmable and is illustrated in Figure 2. Each output remains low until the fault is removed and tPRTO has expired. All Reset outputs are driven low when the MR# input is asserted; remaining low while MR# is asserted and for tPRTO after MR# is released. PGND is the ground for the power portion of the internal circuitry. It is internally tied to pin 8. Both pins must be tied to system ground. DGND is the ground for the digital portion of the internal circuitry. It must be tied to system ground. AGND is the ground for the analog portion of the internal circuitry. It must be tied to system ground. The VO inputs are used to monitor the card-side voltages for the individual managers. ENABLE is an input with a programmable active true state. When the input is true, the charge pump that supplies the high side drive voltage for the VGATE outputs is turned on. The ENABLE input is internally tied to VDD_CAP with a 100K resistor. CBFAULT is an output with a programmable true state. CBFAULT is asserted when there is an over-current condition (QT-CB). HEALTHY# is an unlatched active-low open-drain output. It is asserted when all four managers report no bus-side over-voltages (OV), under-voltages (UV) or card-side under-voltages (UV1 or UV2) or over-current (QT-CB) conditions. See Figure 6. FORCE_SD is an input with a programmable active true state. When the input is true, the VGATE outputs are immediately turned off and clamped to ground. The FORCE_SD input is internally tied to VDD_CAP with a 100K resistor. VGG_CAP is a charge storage connection for the SMT4004 internal charge pump. A 1F capacitor rated above 16V is recommended for most applications. 29 O VGATE4 The VGATE outputs are used to control the turn-on of the card-side voltages 30 O VGATE3 by providing a high side voltage to a power MOSFET. The fully on output 31 O VGATE2 voltage is 14.5V. 32 O VGATE1 Note: P indicates the pin's function or the active state of the pin is programmable. Summit Microelectronics, Inc 2049 4.0 3/04/02 10 SMT4004 PIN DESCRIPTIONS (CONTINUED) Pin Number Pin Type Pin Name Description PWR_ON is an input with a programmable active true state. It must be true for the SMT4004 to begin turning on the VGATE outputs. The PWR_ON input is internally tied to VDD_CAP with a 100K resistor. Once the power-on operation is complete, de-asserting the PWR_ON input forces the tracked channels to track down. The channels programmed for softstart are unaffected and their respective VGATE outputs remain active. 33 I PWR_ON 34 35 36 37 I I I I CB4 CB3 CB2 CB1 38 I/PWR VI4 39 I/PWR VI3 40 I/PWR VI2 41 I/PWR VI1 42 PWR VDD_CAP 43 44 45 I I I A0 A1 A2 46 I/O SDA 47 I SCL 48 I WLDI Summit Microelectronics, Inc CBX are inputs monitoring a voltage drop across an external sense resistor placed between the respective VI and CB inputs. The VI inputs provide two functions. They are primarily the bus-side (unswitched) voltage monitoring inputs for the individual supply managers. In addition, they are internally diode-OR'ed to provide the SMT4004's VDD_CAP supply. VDD_CAP is a charge storage connection to the SMT4004's internal power supply. For most applications this pin is tied to a 10F capacitor. The address pins are biased either to VDD_CAP or GND and provide a mechanism for assigning a unique I2C serial bus address to the SMT4004. These pins are internally pulled-up to VDD_CAP with 100K resistors. SDA is the bidirectional serial data pin. This pin is internally pulled-up to VDD_CAP with 100K resistor. SDA is configured as an open-drain output and requires a pull-up resistor to the highest VDD of the I2C system for proper operation. SCL is the serial clock input, used for clocking data into or out of the SMT4004. This pin is internally pulled-up to VDD_CAP with 100K resistor. SCL is configured as an open-drain output and requires a pull-up resistor to the highest VDD of the I2C system for proper operation. WLDI is an input. A low-to-high transition on this pin resets both the watchdog and longdog timers to t0. If the WLDI input is held high, WDO# is disabled while the LDO# output remains active. The WLDI input is internally tied to VDD_CAP through a 100K resistor. 2049 4.0 3/04/02 11 SMT4004 PACKAGE AND PIN CONFIGURATION A2 A1 A0 VDD_CAP VI1 VI2 VI3 VI4 CB1 43 42 41 40 39 38 37 SDA 46 44 SCL 47 45 W LDI 48 48 Lead TQFP S E ATE D 1# 10 27 FO R C E _S D S E ATE D 2# 11 26 H E AL TH Y # U V _O V E R R ID E 12 25 C B F AU L T ENABLE V G G _C AP 24 V G ATE 4 28 23 29 9 VO4 8 VO3 PGND TR K R _IR Q # 22 V G ATE 3 21 30 VO2 7 20 V G ATE 2 IR Q # 19 IR Q _C LR # VO1 V G ATE 1 31 AGND 32 6 18 5 DGND M R# 17 P W R _O N 16 CB4 33 PGND 34 4 RST4# 3 1.25V R E F 15 C R O W B AR 14 CB3 RST3# CB2 35 RST2# 36 2 13 1 W DO# RST1# LD O # ABSOLUTE MAXIMUM RATINGS RECOMMENDED OPERATING CONDITIONS Temperature Under Bias .................... -55C to +125C Storage Temperature.......................... -65C to +150C Terminal Voltage with Respect to GND: VI & VO Inputs ..............................-0.3V to 7.0V VGATE Outputs..........................................16V All Others......................................-0.3V to 7.0V Output Short Circuit Current............................100mA Lead Solder Temperature (10 secs)...................300C Junction Temperature............................................150C ESD Rating per JEDEC...................................2000V Latch-Up testing per JEDEC........................+/- 100mA Temperature Range(Ambient)............-40 C to +85C Supply Voltage..................................2.7V to 6.0V 1/ EEPROM Write Supply Voltage............3.0V to 6.0V 2/ Package Thermal Resistance ( JA) 48 Lead TQFP.......................................80oC/W Stresses listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only and functional operation of the device at these or any other conditions outside those listed in the operational sections of the specification is not implied. Exposure to any absolute maximum rating for extended periods may affect device performance and reliability. Devices are ESD sensitive. Handling precautions are recommended. Summit Microelectronics, Inc Moisture Classification Level 1 (MSL 1) per J-STD- 020 Notes: 1/ For reliable operation the VDD_CAP node voltage must be equal to or greater than 2.7V (voltage level measured on pin 42). 2/ During an EEPROM memory array or Configuration Register Write, the supply voltage minimum is 3.0V. RELIABILITY CHARACTERISTICS Data Retention........................................100 Years Endurance......................................100,000 Cycles 2049 4.0 3/04/02 12 SMT4004 DC OPERATING CHARACTERISTICS (Over recommended operating conditions, unless otherwise noted. All voltages are relative to GND.) Symbol Parameter Conditions Min. Typ. Max Device supply voltage Power Supply Voltage 2.7 6.0 VSUPPLY provided by the highest VIX input. VX Monitoring Voltage VI1-VI4, VO1-VO4 0 PVITHYS VGATE Outputs enabled, write to EE memory array - Note 1/ Programmable VI See explanation on Threshold for UV condition page 2 Programmable VI See explanation on Threshold for OV condition page 2 OV/UV trip hysteresis PVITUVACC Programmable UV Threshold Accuracy IDD PVITUV PVITOV PVITOVACC PVOTUV1 PVOTUV2 PVOTUV1ACC PVOTUV2ACC VCB VQT Programmable OV Threshold Accuracy Programmable VO Threshold for UV1 condition Programmable VO Threshold for UV2 condition Programmable UV1 Threshold Accuracy Programmable UV2 Threshold Accuracy Write In Progress V 5 mA 0.9 6.0 V 1.08 6.6 V 10 0.97xPVITUV 0.97xPVITUV PVITUV PVITUV mV 1.03xPVITUV 1.06xPVITUV V V No Write in Progress 0.95xPVITOV PVITOV 1.05xPVITOV V Write In Progress 0.92xPVITOV PVITOV 1.05xPVITOV V See explanation on page 2 0.9 6.0 V See explanation on page 2 0.69xPVOTUV1 PVOTUV1 V No Write in Progress 0.97xPVOTUV1 1.03xPVOTUV1 V Write In Progress No Write in Progress Write in Progress Programmable circuit breaker trip voltage CB Trip Point = 25mV CB Trip Point = 50mV Programmable Quick Trip Threshold Voltage CB=25mV CB=50mV CB=25mV CB=50mV CB=25mV CB=50mV Summit Microelectronics, Inc V 6.6 Power Supply Current No Write in Progress Unit QT=55mV QT=80mV QT=85mV QT=110mV QT=135mV QT=160mV 2049 4.0 3/04/02 0.97xPVOTUV1 0.95xPVOTUV2 0.95xPVOTUV2 19 37 40 60 65 80 100 120 PVOTUV1 PVOTUV1 PVOTUV2 PVOTUV2 25 50 55 80 85 110 135 160 1.06xPVOTUV1 1.05xPVOTUV2 1.08xPVOTUV2 31 62 70 100 105 140 170 200 V V V mV mV mV mV mV mV mV mV 13 SMT4004 DC OPERATING CHARACTERISTICS (CONTINUED) (Over recommended operating conditions, unless otherwise noted. All voltages are relative to GND.) Symbol Parameter Conditions Min. Typ. Max ON ( IVGATE = 4A) 12 16 VGATE drive output VVGATE - Note 2/ OFF (IVGATE = -8mA) - Note 2/ Total VGATE output drive current IVGATE All VGATEs forced to 10V - Note 2/ All VGATEs forced to 1V - Note 2/ SRVOX VTRKR VTRKR_IRQ# VREF VIH VIL VOL VCSWFZ RPull-Up VCROW Notes: SRVOX = 100V/s SRVOX = 250V/s Tracking VOX Slew Rate SRVOX = 500V/s SRVOX = 1000V/s Differential between Tracking Differential Voltage Tracking VOX pins - Note 3/ Tracking Differential Voltage Differential between Causes TRKR_IRQ# Tracking VOX pins 1.25VREF Output Voltage RLOAD = 2K to gnd VDD_CAP = 2.7V to 4.5V Input High Voltage VDD_CAP = 4.5V to 6.0V VDD_CAP = 2.7V to 4.5V Input Low Voltage VDD_CAP = 4.5V to 6.0V Open-drain Outputs, IOL Output Low Voltage = -2mA Card-Side Wait-For-Zero Note 4/ Threshold Input Pull-Up Resistors See Pin Descriptions CROWBAR Output Voltage RLOAD=10k to gnd 0 0.4 Unit V V 10 A 30 A 60 150 400 800 100 250 500 1000 140 350 600 1200 V/s V/s V/s V/s 100 250 mV 300 1.23 mV 1.27 V 0.9xVDD_CAP 6.0 V 0.7xVDD_CAP 6.0 V -0.1 0.1xVDD_CAP V -0.1 0.2xVDD_CAP V 0 0.4 V 0.5 1.2 V 165 VDD_CAP k V 50 VDD_CAP-0.5 1.25 100 1/ - Does not include external load on VDD_CAP. Any external pull-up resistors tied to VDD_CAP will increase IDD. Maximum allowable external current sourced from VDD_CAP is 1mA with VDD_CAP=10F. 2/ - IVGATE is the sum of all VGATE output currents. 3/ - The SMT4004 adjusts the VGATE outputs to control the differential of the VOX outputs to within 100mV nominally. External influences may increase the differential until the VGATE outputs adjust to minimize the differential. 4/ - Guaranteed by Design. Summit Microelectronics, Inc 2049 4.0 3/04/02 14 SMT4004 AC OPERATING CHARACTERISTICS (Over recommended operating conditions, unless otherwise noted. All voltages are relative to GND.) Symbol Description Conditions Min. Typ. Max. CBDELAY = 25s 20 25 40 CBDELAY = 50s 40 50 80 CBDELAY Programmable Circuit Breaker Filter CBDELAY = 100s 80 100 140 160 200 280 CBDELAY = 200s tPWDTO = 400ms Programmable Watchdog Timer tPWDTO = 800ms -25 tPWDTO tPWDTO +25 Time-Out Period tPWDTO = 1600ms tPWDTO = 3200ms tPLDTO = 800ms Programmable Longdog Timer Time- tPLDTO = 1600ms -25 tPLDTO tPLDTO +25 Out Period tPLDTO = 3200ms tPLDTO = 6400ms tPRTO = 25ms Programmable Reset Time-Out tPRTO = 50ms -25 tPRTO tPRTO +25 Period tPRTO = 100ms tPRTO = 200ms tCROW CROWBAR output pulse width 16 28 SCR Mode, RLOAD=10k tDFIRQ Delay from fault detection to IRQ# 1 tDFRST Delay from fault detection to RST# 1 Delay from fault detection to tDFHEALTHY# 1 HEALTHY# Delay from tracking fault detection to tDTKRIRQ 1 TRKR_IRQ# Delay from fault detection to tDFCR 1 CROWBAR Delay from assertion of MR# to tDMRRST 100 RST# Active Delay from VIX valid to VGATEX VGG_CAP=14V 0 tDVIVG activated Delay from assertion of FORCE_SD tDFSVG 10 to VGATE clamped to ground. Summit Microelectronics, Inc 2049 4.0 3/04/02 Unit s s s s % % % s s s s s s ns s s 15 SMT4004 I2C 2-WIRE SERIAL INTERFACE AC OPERATING CHARACTERISTICS - 100kHz (Over recommended operating conditions, unless otherwise noted. All voltages are relative to GND.) Symbol Description Conditions Min Typ Max Units fSCL SCL Clock Frequency KHz tLOW Clock Low Period 4.7 s tHIGH Clock High Period 4.0 s 4.7 s 0 Before New Transmission 100 tBUF Bus Free Time tSU:STA Start Condition Setup Time 4.7 s tHD:STA Start Condition Hold Time 4.0 s tSU:STO Stop Condition Setup Time 4.7 tAA Clock Edge to Data Valid SCL low to valid SDA (cycle n) 0.2 tDH Data Output Hold Time SCL low (cycle n+1) to SDA change 0.2 tR SCL and SDA Rise Time Note 1/ 1000 ns tF SCL and SDA Fall Time Note 1/ 300 ns tSU:DAT Data In Setup Time 250 ns tHD:DAT Data In Hold Time 0 ns TI Noise Filter SCL and SDA tWR Write Cycle Time Note 1/ Noise suppression s 3.5 s s 100 ns 5 ms Note: 1/ - Guaranteed by Design. TIMING DIAGRAMS tR tF tSU:SDA tHD:SDA tHIGH tLOW SCL tHD:DAT tSU:DAT tSU:STO tBUF SDA (IN) tAA tDH SDA (OUT) Figure 8 . Basic I2C Serial Interface Timing Summit Microelectronics, Inc 2049 4.0 3/04/02 16 SMT4004 TIMING DIAGRAMS (CONTINUED) FO R C E _S D E N AB LE P W R _O N S E ATE D 1&2# S oft S tart V G ATE s Tracking V G ATE s Figure 9. Relationship of de-asserting the enabling inputs on the VGATE outputs. t0 t0 t0 t0 t0 t PR T O t0 t0 t PR T O C om posite R ST # M R# t PW D T O t PW D T O t PW D T O W DO# t PL DT O LDO # t PL DT O t PL DT O <t PL DT O t PR T O <t PW D T O W LD I Figure 10. Relation of LDO# and WDO# with WLDI, RST# and MR# Summit Microelectronics, Inc 2049 4.0 3/04/02 17 SMT4004 APPLICATIONS INFORMATION APPLICATIONS EXAMPLE The timing diagram in Figure 11 illustrates a full power-on and power-off sequence and the relationship between many of the signals. This is based on the simplified applications diagram on Page 1. Manager 1 is programmed to softstart. Its' supply feeds two power supplies that are monitored by managers 3 and 4 that, along with manager 2, are programmed for tracking. The flow chart in Figure 12A and B are a further illustration for the same application. E NAB LE P W R _O N P V IT 1 V I1 V G ATE 1 P VO T1 VO1 P V IT 2 V I2 + V I3 + P V IT 3 V I4 P V IT 4 = V G ATE 2 V G ATE 3 V G ATE 4 P VO T2 VO2 P VO T3 VO3 P VO T4 VO4 VO 2 C om posite V O 2,3 & 4 VO 3 VO 4 tP R T O R S T#s H E ALTH Y# Figure 11 - Timing relationship of events during a Power-On and Power-Off sequence. Summit Microelectronics, Inc 2049 4.0 3/04/02 18 Summit Microelectronics, Inc 2049 4.0 3/04/02 GO TO SHUTDOW N ROUTINE NO CB1 O K? YES VI1 PVIT OV1 ? YES T urn ON VGAT E1 YES IS VGG Voltage Fully ON ? YES SEAT ED1# and SEAT ED2# TRUE? YES VI1 PVIT UV1 & VI1 < PVIT OV1 ? YES FO RCE_SD FALSE ? YES ENABLE ASSERT ED? YES PW R_O N T RUE? YES Manager 1 = Softstart M anagers 2, 3 and 4 = Tracking VI2 > VI3 > VI4 GO TO TRACKING ROUTINE YES NO NO NO NO NO NO NO NO NO > 100m V? COM PARE VO INPUT S ADJUST VGAT E OUT PUT S NO > 300m V? YES > 100m V? COM PARE VO INPUT S NO VI4>PVIT OV 4? ADJUST VGAT E OUT PUT S YES TURN O N VG AT E O UT PUT S YES VI2,VI3,VI4 PVIT UV1 & VI2,VI3,VI4 < PVIT OV1? TRACKING ROUTINE YES YES G O T O SHUT DO W N ROUT INE YES NO NO NO > 100m V? COM PARE VO INPUT S ADJUST VGAT E OUT PUTS NO > 300m V? YES > 100m V? COM PARE VO INPUT S NO VI3>PVIT OV 3? REMO VE VO 4 FRO M T RACKING YES G O T O SHUT DO W N ROUT INE YES YES G O T O G ENERAL MO NIT OR RO UT INE ST ART LONG DO G ST ART W AT CHDOG YES RESET T IMED O UT ? START RESET T IMER ASSERT HEALT HY# O UT PUT YES VI2 > PVIT OV 2? YES REMO VE VO 3 FRO M T RACKING NO NO SMT4004 APPLICATIONS INFORMATION (CONTINUED) Figure 12A - Power-On Sequence of Events 19 SMT4004 APPLICATIONS INFORMATION (CONTINUED) GENERAL MONITORING OPERATION PWR_ON REMOVED ROUTINE ENABLE REMOVED ROUTINE ADJUST VGATE4 SHUTDOWN ALL ACTIVE VGATE OUTPUTS NO ALL VOLTAGES WITHIN LIMITS? GO TO SHUTDOWN ROUTINE YES ALL CONTROL INPUTS VALID? VO4 <PVOT4? YES NO IF ON DE-ASSERT HEALTHY# & IF OFF ASSERT ALL RST# OUTPUTS YES NO DE-ASSERT HEALTHY# ASSERT ENABLED RST#S YES DID SEATED# GO HIGH? SEATED# REMOVED ROUTINE GO TO SEATED# REMOVED ROUTINE YES NO WAS ENABLE DEASSERTED? GO TO ENABLE REMOVED ROUTINE YES ADJUST VGATE4 SHUTDOWN ALL ACTIVE VGATE OUTPUTS NO VO4 = VO3? WAS PWR_ON DEASSERTED? NO NO IF ON DE-ASSERT HEALTHY# & IF OFF ASSERT ALL RST# OUTPUTS YES ADJUST VGATE4 & VGATE3 GO TO PWR_ON REMOVED ROUTINE VO4&VO3 = VO2? NO SHUTDOWN ROUTINE YES ADJUST VGATE4, VGATE3 & VGATE2 NO IS VOX HIGH? YES VO4&VO3&VO2 = 0V? NO SHUTDOWN ALL ACTIVE VGATE OUTPUTS YES IF ON DE-ASSERT HEALTHY# & IF OFF ASSERT ALL RST# OUTPUTS YES IS ENABLE DEASSERTED? NO GO TO ENABLE REMOVED ROUTINE Figure 12B - Power-Off Sequence of Events Summit Microelectronics, Inc 2049 4.0 3/04/02 20 SMT4004 APPLICATIONS INFORMATION (CONTINUED) SOFTSTART VS TRACKING As a power supply manager the SMT4004 separates two power domains; the bus-side, or source power supplies, and the card-side that contain the application circuitry. Its primary tasks are to monitor the voltages and control the switching of the bus-side voltages to the card-side circuits. The switching is accomplished by providing a high-side drive output on the VGATE pins. The VGATE output is applied to the gates of the power MOSFET. During tracking, the card-side voltages are monitored to minimize the differential voltage between each tracked voltage until they reach their respective undervoltage thresholds (UV1). In tracking mode, the ramp rates are constant but can stop and wait. That is, if during the tracking interval there is any difference between the VO inputs, the VGATE outputs will stop and wait for the slow channel to catch up. Softstart The supply managers can act as either tracking managers or as softstart managers. Individual managers turn on their VGATE outputs once all enabling conditions for that class of manager (softstart or tracking) are met. If a manager is set to soft start, its VGATE output ramps at a programmable constant slew rate until it reaches its maximum value. This operation is commonly used when a voltage (e.g., 5V) is first switched into a DC-to-DC converter or group of LDOs. These outputs may then be tracked to the cardside logic. Scope Shot 2. Power-On with all four managers set to track. POWER-ON Initial Conditions At least one of the VI pins must be equal to or greater than 2.85V before the power-on operation can proceed. For reliable operation the VDD_CAP node voltage must be equal to or greater than 2.7V (voltage level measured on pin 42). This requires that at least one of the VI inputs needs to be at or above 2.85V for proper device operation. There is internal arbitration circuitry which chooses the highest VIX to power the SMT4004 and causes an internal voltage drop from VIX to VDD_CAP. Scope Shot 1. Typical softstart Power-On by two managers and tracking by two managers. Tracking When a manager is programmed for tracking all enabling conditions for that class of manager (tracking) must be met before the VGATE outputs are turned on. The enabling conditions also include all softstart managers having their VGATE outputs fully on with no existing fault conditions for the softstart managers. Summit Microelectronics, Inc Both SEATED# inputs must be low. The SEATED# inputs are generally used with staggered-pin applications where the connector for the application card has two or three levels of pin lengths. This allows `early-power' to be applied to the SMT4004 so it can begin to monitor bus side supplies as they come up, and also a method to indicate the application board is fully seated and ready for operation. Removal of a powered board is first recognized by the SEATED# pins going high, causing power-off of the board by shutting down the charge-pump, not ensuring a track 2049 4.0 3/04/02 21 SMT4004 APPLICATIONS INFORMATION (CONTINUED) down. In this application the SEATED# pins are routed to the board's short pins and grounded when the board is fully inserted. The SEATED# pins can be tied to card insertion switches or they actively driven and used as device enable inputs. FORCE_SD can be programmed as a true high or true low input. When asserted, the VGATE outputs are turned off and clamped to ground. Therefore, this input must be false for power-on to proceed. This pin is internally pulled up to the VDD_CAP node with a 100K resistor. The PWR_ON input can be programmed as a true high or true low input. It must be true for both soft start and tracking managers to turn on their VGATE outputs. If the SMT4004 has already activated the VGATE outputs and PWR_ON is turned off, only the VGATE outputs for the tracking managers are turned off. VGATE outputs programmed for soft start remain active. Assum ptio ns: m anagers 1 & 2 are softstart, m anagers 3 & 4 are tracking and are not shown; Staggered pin application; ENABLE true low and FORCE_SD true high, both tied to ground; PW R_ON active high, tied to +5V thru pull up; only RST1# and RST2# enabled. E N AB LE The ENABLE input can be programmed to a true high or true low input. The ENABLE input activates the high-side driver charge pump and must be true for the VGATE outputs to be able to drive the gates of the external MOSFETs. Managers programmed for soft start enable their VGATE outputs once all softstarted VI inputs are within their programmed threshold limits (UV and OV) (Figure 13). Managers programmed for tracking enable their VGATE output once softstarting is successful conditions and all tracking manager's VI inputs are within their programmed threshold limits (Figure 14). POWER-ON OPTIONS Bus-side Over-voltage If OV detection is selected and is programmed to be a trigger source for IRQ# and if IRQ# is a trigger source for force shutdown (FSD), the user has several options as to how the part reacts to an OV. Different options can be chosen for how the SMT4004 will respond during the time periods during power-on, after power-on has completed, or when normal monitoring Summit Microelectronics, Inc GND VI1 O V V I1 VI1 UV P W R _O N S E ATE D 1& 2# V G ATE 1 VO 1 U V 1 VO 1 UV 2 VO1 VI2 O V An I2C power-on function is available. This allows the tracking power-on/off operations to be initiated by the 2-wire serial interface. If the SMT4004 is configured for I2C power-on, the PWR_ON pin must be in its true state. GND FO R C E _S D V I2 VI2 UV V G ATE 2 VO 2 UV 1 VO2 VO 2 UV 2 t P R TO R S T1# & R S T2# Figure 13. Typical Soft Start Sequence is underway. OV detection must not be enabled on disabled manager channels. If an OV occurs after softstart has completed and before tracking has begun, the SMT4004 can be programmed to ignore the OV. A case where this would be selected might be as illustrated in the Simplified Applications drawing on Page 1. Assume the +5V softstarts as planned and the LDO's are energized. The LDO's might cause a temporary OV condition before full regulation on the 1.5V or 2.5V supplies occurs. If the ignore option is selected the following are true: 1. Only managers with OV detection are affected. 2. If OV occurs during softstart, the VGATE outputs are turned off and remain off until the OV condition is cleared. 3. If tracking has started and OV is detected, a FORCE_SD is initiated. 2049 4.0 3/04/02 22 SMT4004 APPLICATIONS INFORMATION (CONTINUED) NOTE: If the starting VO potentials are too high, tracking of low voltage supplies may not meet some system specifications. Assu m ption s: m anagers 1 and 2 are tracking m anagers; Managers 3 & 4 are turned off; FORCE_SD is active high and ENABLE is active low, both tied to ground; PW R_ON is active high tied to VDD thru a pull-up resistor; the SEATED# inputs are tied to ground. 2. The CROWBAR pin is normally configured to output a short positive pulse to trigger an SCR. Optionally it can be configured as a normally active high output during the power-on phase prior to tracking. Configured as such, it can be used to drive the gate of an N-channel MOSFET to actively discharge any `early voltages.' Once tracking is initiated, the CROWBAR output goes low allowing the card-side voltages to turn-on. Refer to Figure 15 for a schematic illustration. GND F O R C E _S D GND E N AB L E P W R _O N S E ATE D 1& 2# gnd VI1 O V V I1 NOTE: This feature can be used independently or in conjunction with the DWFZ option. VI1 UV VI2 O V VI2 UV Q1 RS VIN VOUT to Application Circuit VO1 SMT4004 PGND VO 1 UV 1 VO 1 UV 2 VO 2 U V 1 CROWBAR Common GND VO 2 UV 2 VO2 VGATE1 V G ATE 2 CB1 VI1 V G ATE 1 VO1 RG1 10 PGND V I2 VO 1 VO 1 UV 1 C om p osite V O 1 an d V O 2 R S T1# & R S T2# Figure 15 - Example implementation of the `Early Drive Function.' VO 2 t P R TO Tracking Failure Options Figure 14 - Typical tracking sequence of operation. Card-side Voltage When tracking is selected the SMT4004 monitors the VO inputs prior to initiating the tracking function. The SMT4004 will not start tracking until the VO inputs are below 0.5V (VCSWFZ). However, some systems may partially charge one or more of the power busses if a softstart voltage has energized some of the application circuitry. If the charge is excessive (>VCSWFZ), tracking will not start. The SMT4004 has two options that can be selected to accommodate this situation. 1. The "Don't-Wait-For-Zero" (DWFZ) option can be enabled. As the name implies the SMT4004 will not monitor the VO inputs and tracking starts once all UV, OV and enabling inputs are valid. Summit Microelectronics, Inc During tracking, differentials greater than 300mV between VO inputs can be reported through the assertion of the TRKR_IRQ# output. Any tracking manager detecting a failure can generate an interrupt; and any tracking manager can be assigned to track but not generate an interrupt. If a manager is assigned to track and a tracking error is detected the SMT4004 can be programmed to take one of the following actions. * Ignore the condition and proceed with the power-on operation. * Shutdown all supplies and generate a TRKR_IRQ#. * Generate a TRKR_IRQ# and proceed with the power-on operation. 2049 4.0 3/04/02 23 SMT4004 APPLICATIONS INFORMATION (CONTINUED) POWER-OFF Power-off of the application circuit is affected by turning off the VGATE outputs. This can be done by de-asserting one of the enabling signals or the detection of a fault condition. When the SMT4004 Scope Shot 4. Power-Off of all managers using the FORCE_SD pin. SOFTWARE POWER-ON/POWER-OFF Scope Shot 3. Power-Off caused by de-assertion of PWR_ON( all managers selected for tracking). receives a power-off command whether it be from the PWR_ON pin, an I2C command or from the latching of a fault, there will be a delay of approximately VIMAX/Tracking Slew Rate (where VIMAX is the VI with the highest voltage level) before the first tracked VGATE begins to discharge. Enabling Inputs RESET OPERATION If the PWR_ON input is de-asserted tracking managers will `track down' their voltages. The softstart managers are unaffected and their VGATE outputs remain active. If either or both SEATED# inputs are de-asserted the SMT4004 immediately powers-off the VGATE outputs. If the FORCE_SD input is asserted, the managers immediately shut off the VGATE drivers by clamping these outputs to ground (Scope Shot 4). If the ENABLE input is de-asserted, the VGATE outputs are shutoff. Refer to Figure 9 for an illustration of de-asserting the various enabling inputs. Summit Microelectronics, Inc The SMT4004 has an option allowing a commanded power-on and power-off via the I2C serial interface of tracked channels. If the device is configured for this option, the PWR_ON pin must be in the true state. Once all enabling conditions are met and all voltages are within their thresholds the SMT4004 can be tracked-up by writing to register 16. Once the application circuit is tracked-up, a subsequent write to register 17 initiates a track down. Refer to the applications circuits and descriptions for a system level description. Once power is applied to the SMT4004 the four RST# outputs are driven low. Because they are meant to be used by the application circuitry, the RST# outputs remain low until all Reset trigger sources (for any manager's UV1, UV2 or QT-CB output) are removed. The RST# outputs remain low for the duration of the programmable reset time-out period (tPRTO) after the triggers are cleared. After the circuitry is `powered-on' and the SMT4004 is in the steady-state monitoring mode, the RST# outputs remain high unless one of the enabled fault conditions is detected by a manager. When this occurs only the RST# output affected by that manager is asserted. All RST# outputs that have gone low to indicate a problem on their corresponding channel will remain low until all reset conditions have been removed and tPRTO has expired. 2049 4.0 3/04/02 24 SMT4004 APPLICATIONS INFORMATION (CONTINUED) All four RST# outputs are driven low when the MR# input is taken low. They continue to assert their outputs after MR# returns high for tPRTO seconds. INTERRUPTS, FORCE SHUTDOWN AND CROWBAR The SMT4004 has two interrupt outputs: IRQ# and TRKR_IRQ#. The CROWBAR output is configurable to operate in conjunction with the IRQ# outputs. The IRQ# output has a large number of programmable sources for latching its output. Any combination of supply manager fault condition outputs (UV, OV, UV1, UV2 and QT-CB) can be enabled as a trigger for the IRQ# latched output. Once triggered the IRQ# output is latched and remains asserted even if the fault condition is removed. IRQ# can only be cleared by asserting the IRQ_CLR# input. IRQ# can also trigger a force shutdown (FSD) and/or a CROWBAR pulse. Refer to Figure 3 and the graphical user interface (GUI) for the SMT4004. During initial power-on of the SMT4004 the IRQ# output is disabled until the SMT4004 comes out of Reset. The hold off can be extended from the end of the Reset timeout period for 0ms, 200ms, 400ms, 800ms or 1600ms. This allows the application circuit and all of the supplies time to stabilize after the initial power-on. The VGATE control circuitry monitors VO inputs for those managers selected for tracking. If a VO input is found to not be tracking or deviates from the other voltages by more than 300mV, the control circuitry generates a tracker error. If that output is AND'ed with an enable bit it forces the TRKR_IRQ# output low. No other fault conditions can generate a TRKR_IRQ#: Like the IRQ# output TRKR_IRQ# can trigger an internal force shutdown and/or a CROWBAR pulse. If the fault latch feature is enabled the fault condition is captured. The fault sources are a force shutdown, CROWBAR, or IRQ#. When a fault is detected a volatile latch is set to keep the SMT4004 from being powered-up again until IRQ_CLR# is toggled. The CROWBAR pin is designed to deliver an active high pulse to an external SCR to shutdown the cardside voltages as quickly as possible. A CROWBAR pulse can be triggered by one of seven inputs: a QTCB fault, an IRQ#, a TRKR_IRQ# and/or assertion of the FORCE_SD input. These trigger sources are Summit Microelectronics, Inc optional and any combination can be selected. Note: Because an over-current condition is potentially catastrophic, each manager has a unique source input to the CROWBAR logic even though they are included in the trigger sources for an IRQ#. This allows less harmful fault triggers to be used as inputs for the IRQ#, without generating a CROWBAR. There is also an option to change the CROWBAR pin output from an SCR pulse to a voltage level to discharge Cardside early voltages prior to tracking (see Figure 15). WATCHDOG AND LONGDOG TIMERS The SMT4004 has two timers that generate independent outputs: the WDO#, output, or watchdog timer output and the LDO# or longdog timer output. Both timers use the same clock circuitry; however, the time out period for both timers is independently programmable. When the timer has timed out for either the watchdog or the longdog, their respective outputs are driven low. The timers are Reset to t0 by a low-to-high transition on the WLDI input. Note: If WLDI is held high the WDO# output is disabled and the LDO# transitions low after its programmed time out period tPLDTO. It remains low for tPLDTO returning high for tPLDTO seconds, repeating the pulse output until the next low-to-high transition on the WLDI input. Both timers are disabled during the initial power-on operation and will not start until all RST# outputs have been released. The end of the initial programmable reset time-out period, tPRTO, is effectively t0 for both timers. Asserting MR# or the occurrence of a fault condition causing any Reset disables the timers until the RST# outputs are released. Refer to Figure 10 for an illustration of the relation between the timer outputs, WLDI and the Reset functions. SERIAL INTERFACE Access to the configuration registers and memory array is carried out over an industry standard 2-wire serial interface (I2C). SDA is a bi-directional data line and SCL is the clock input. Data is clocked in on the rising edge of SCL and clocked out by the falling edge of SCL. All data transfers begin with the MSB. During data transfers SDA must remain stable while SCL is high. Data are transferred in 8-bit packets with an intervening clock period in which an acknowledge is provided by the device receiving data. The SCL high period (tHIGH) is used for generating start and stop conditions that precede and 2049 4.0 3/04/02 25 SMT4004 APPLICATIONS INFORMATION (CONTINUED) end most transactions on the serial bus. A high-to-low transition of SDA during tHIGH is a start condition and a low-to-high transition of SDA during tHIGH is a stop condition. The interface protocol allows operation of multiple devices and types of devices on a single bus through the use of unique device addressing. The address byte is comprised of a 4-bit device type identifier, a 3-bit bus address and a single bit indicating that the operation is a read or a write. Refer to Table 1 for an illustration of the configuration of the address as defined for the SMT4004. The device type identifier for the memory array is generally set to 1010[bin] following the industry standard for a typical nonvolatile memory. There is an option to change the identifier to 1011[bin] allowing it to be used on a bus that may be occupied by other memory devices. The configuration and fault status registers are accessible with a separate device type identifier of 1001[bin]. The bus address is defined by the state (`0' or `1') of the A0, A1 and A2 pins. The serial data stream must match the state of these pins. Writing to the memory or a configuration register is illustrated in Figures 16 and 18. A start condition followed by the address byte is provided by the host; the SMT4004 responds with an acknowledge; the host then responds by sending the memory address pointer or configuration register address pointer; the SMT4004 responds with an acknowledge; the host then clocks in the data. For memory writes an additional 15 bytes of data can be written. Only one configuration register can be written per data transfer. After the last byte is clocked in, a stop condition must be issued for the nonvolatile write operation to proceed. Device Identifier D6 D5 0 1 0 1 0 1 0 1 0 0 0 0 The address pointer for the registers and the memory can only be changed by a write command. If a read command is issued without address conditioning, the data that is clocked out will be from a location pointed to by the last written (or read) address incremented by 1. In order to read data from a specific location a false write command is issued. The sequence is: issue a start and a device address with a write command; wait for an acknowledge; send the array or register address; wait for an acknowledge; issue a new start and device address with a read command; wait for an acknowledge then proceed to clock out data. For memory reads, the host can acknowledge receipt of data and then continue clocking out data and acknowledging without restriction. For register reads, only a single location can be read with each command sequence. All read operations are concluded by issuing a stop condition. Refer to Figures 17 and 19 for an illustration of the read sequence. MR# AND THE SERIAL INTERFACE WRITE D7 1 1 1 1 1 1 READ D4 0 0 1 1 1 1 D3 A2 A2 A2 A2 A2 A2 Bus Address D2 D1 A1 A0 A1 A0 A1 A0 A1 A0 A1 A0 A1 A0 When writing the memory array the MR# input must be high. When writing the memory array the SMT4004 cannot be in reset. When reading the status registers or memory array, the state of the MR# input is ignored. When writing the configuration registers the default requirement for MR# is for it to be asserted or low. There is an option that allows this to be a `don't care' input; that is, the pin can be high or low and the configuration registers can be written. [This option is chosen on the Miscellaneous Settings tab of the Windows GUI] R/W D0 1 0 1 0 1 0 Action Read Memory Write Memory Read Memory (alternate address) Write Memory (alternate address) Read Registers Write Registers Table 1. Illustration of serial address bytes. Summit Microelectronics, Inc 2049 4.0 3/04/02 26 SMT4004 APPLICATIONS INFORMATION (CONTINUED) O ptional Device Type Identifier S T A R T M aster 1 0 1 Bus Address = Address Pins 1 SD A 0 S T O P 1 1 A 2 0 A 1 A 0 M emory Address Location A 7 W A 5 A 6 A 3 A 4 A 1 A 2 A 0 A C K SM T 4004 D 6 D 7 D 5 D 4 D 3 D 2 D 1 D 0 A C K A C K Figure 16. Memory write sequence. Optional Device Type Identifier M aster S T A R T 1 1 1 Bus Address = Address Pins 1 SD A 0 0 1 A 2 0 A 1 A 0 Memory Address Location A 7 W A 5 A 6 A 4 A 3 A 2 A 1 A 0 A C K SM T 4004 Optional Device Type Identifier S T A R T 1 0 1 1 1 0 1 0 N A C K A C K A 2 A 1 A 0 A C K D 6 D 7 R D 5 D 4 D 3 D 2 D 1 S T O P D 0 A C K Figure 17. Memory read sequence. S T A R T M aster Bus A ddress = Address Pins 1 SD A 0 0 1 A 2 A 1 A 0 S T O P Configuration Register Address 1 W 1 1 1 C 2 1 C 1 C 0 A C K SM T 4004 D 6 D 7 D 5 D 4 D 3 D 2 D 1 D 0 A C K A C K Figure 18. Write configuration register sequence. M aster SD A S T A R T Bus Address = Address Pins 1 0 0 1 SM T 4004 A 2 A 1 A 0 S T A R T Configuration Register Address 1 W A C K 1 1 1 1 C 2 C 1 C 0 Bus Address = Address Pins 1 A C K N A C K 0 0 1 A 2 A 1 A 0 D 7 R D 6 D 5 D 4 D 3 D 2 D 1 S T O P D 0 A C K Figure 19. Read Configuration register or status register sequence. Summit Microelectronics, Inc 2049 4.0 3/04/02 27 SMT4004 APPLICATIONS INFORMATION (CONTINUED) Crowbar and Pin Polarity PROTOTYPING WITH THE SMT4004 WINDOWS GUI SOFTWARE Select one or more Crowbar Source Enables. For prototyping and device evaluation, use the Windows Graphical User Interface (GUI) and SMX3200 device programmer with the SMT4004. The programming system is available from the Summit website (www.summitmicro.com). Further explanation of the 32 individual configuration registers and associated GUI settings are included in Application Note 22. Select Crowbar pin function. Select "Active" pin polarity. IRQ#, Circuit Breaker, OV Settings These are important house keeping chores that need to be selected. Starting at the bottom: After installing and starting the interface, the screen will display six different tabs. (Before proceeding, click on the Read Config button or Load Defaults). Each tab represents a group of functions and features that need to be selected for the end application. Power Managers, Resets and IRQ#s TAB This screen allows the user to select any one of the four managers and then configure its operation. The required information for each manager is: Enable or disable the manager. If a manager is disabled, OV must be disabled on that manager. Tracking Mode or Soft Start. Bus-Side Operation: adjust the UV and OV thresholds enable their use individually. Card-Side Operation: adjust the UV1 and UV2 thresholds and enable the use of UV2. Turn off or select a QT threshold. Select the sources that can trigger an interrupt. Select the sources that can trigger a Reset. Slew Rate, Timer and Circuit Breaker Select the VGATE slew rate for both power-on and power-off. The Circuit breaker delay is the programmable filter. Configure the IRQ# options. Next: The circuit breaker trip point is the voltage drop across the sense resistor that will be used to determine an over-current condition. The last two boxes determine the action that is taken if an over-current condition exists. Miscellaneous Settings MRB (MR#), I2C power-On/Off Memory Address Select and Bus Address Response all configure the operation of the serial interface. Select Fault Latching Capability. Select whether the VO inputs need to be near 0V before tracking commences. (Disable option) Memory Array and Status Regs The memory array function allows reading and writing the array. The GUI screen displays an `address-relative' bit map of the contents of the array. This TAB provides access to the fault status registers and the ability to clear them during debug. The 300mV Trakker Action refers to the optional actions that can be taken if a differential of more than 300mV is detected by tracking managers. Select which manager can generate a TRKR_IRQ#. Select the reset timeout period. Select both the LDO# and WDO# timer values. Summit Microelectronics, Inc 2049 4.0 3/04/02 28 SMT4004 APPLICATIONS INFORMATION (CONTINUED) USE A KELVIN CONNECTION FOR ACCURATE CURRENT MEASUREMENT High current measurements using a series resistor can be very accurate when a Kelvin connection is used between the resistor and the VI and CB inputs. A Kelvin connection is a 4-terminal connection, usually made to a 2-terminal device, separating the current path through the resistor from the voltage drop across the resistor. The sense points are located as physically close to the resistor terminals as possible. This eliminates inaccuracies that may be caused by randomly placing the sense connection along the power trace on the printed circuit board. Figure 20 illustrates the 4-wire Kelvin principle applied to a 2terminal surface mount sense resistor. Current sense resistors are available from a number of manufacturers in two basic styles: open air and resistor chips. Open air resistors are metal strips and are available in both leaded and surface mount packages. Resistor chips are surface mount packages and offer excellent thermal characteristics. Both styles are available in resistance ranges from <1m to 1. True 4-terminal sense resistors are available, but are generally more expensive. Unless extreme precision is required, the 2-terminal resistor is the economical choice with PCB traces tapping off the trace at the resistor ends to provide the 4-terminal Kelvin connection. High Current Path Sense Resistor Supply r ppe Co ce T ra r ppe Co ce T ra To MOSFET Drain CB VI Kelvin Connections SMT4004 voltage drop. For optimal performance the other three RS/VI & RS/CB traces should be near equal length and the sense resistor(s) should be as close to the SMT4004 as possible. POWER MOSFETS Selection of MOSFET switches for the SMT4004 Tracker is a compromise between load regulation, board area, and MOSFET cost. To obtain good load regulation with low supply voltages, the MOSFET must have a very low ON resistance (RDS(ON)). SELECTING A MOSFET AND THE SENSE RESISTOR VALUES FOR THE SMT4004. The following is an example of how to determine the MOSFET and Sense resistor values for a given power supply. For a 1.8V supply with a 10A maximum load current, the load resistance is equivalent to 180m. If the total resistance of the sense resistor plus trace resistance plus MOSFET ON (RDS(ON)) resistance is 9m, the load regulation is approximately 5% for a load change from 0A to 10A. Assume the selected circuit breaker trip voltage is 25mV. If the voltage drop across the MOSFET is kept below 25mV at maximum current, then a total drop of 50mV yields a load regulation of less than 3% with a 1.8V supply, and 1% with a 5V supply. Choosing a suitable MOSFET is simply a matter of applying Ohm's law once the supply voltage, load current, and load regulation requirements are known. For the 1.8V & 10A example, first choose the current sense resistor. A margin should be allowed; therefore, set the trip current higher than the operating current. For example, choosing 12.5A yields 25% over-current and allows for the tolerances of the resistor and trip voltage. With a nominal trip voltage of 25mV and a trip current of 12.5A, the current sense resistor is 2m. Therefore, the MOSFET RDS(ON) must be below 7m. Some low RDS(ON) MOSFETs are shown in Table 2. Figure 20. Typical Kelvin Connection The VI input with highest potential is effectively the power supply pin for the SMT4004. This means there will be additional current (max. 3mA) on this PCB trace. Therefore, this sense resistor (RS) to VI trace should be of sufficient size to eliminate any unwanted Summit Microelectronics, Inc 2049 4.0 3/04/02 29 SMT4004 APPLICATIONS INFORMATION (CONTINUED) PARALLELING MOSFETS REDUCES VOLTAGE DROPS AND POWER DISSIPATION When supply regulation is unacceptable due to high RDS(ON), two or more MOSFETs may be wired in parallel to lower the RDS(ON). For lower voltage supplies with high current, such as a 1V supply delivering 15A of load current, load regulation is improved by using two or more MOSFETs in parallel. The RDS(ON) is halved when two identical MOSFETs are connected as in Figure 21. The MOSFET gates must be connected with identical gate resistors (RGx) as shown. Q1 RS VIN VOUT to Application Circuit Q2 RG1 10 SMT4004 REMOTE SENSING VO1 VGATE1 CB1 VI1 RG2 10 Figure 21. Parallel MOSFET connections This technique can be used with power supplies that have Sense inputs. Remote sensing eliminates the effect of the current sense resistor voltage drop. With this arrangement (Figure 22) only the MOSFET RDS(ON) must be considered and a wider selection of devices can be used. +V S EN S E Q1 RS +V F O R C E VOUT to App licatio n C ircu it 100F VO1 VGATE1 DC-to-DC Converter CB1 VI1 RG1 10 5x 220F PGND -V S EN S E PGND SM T4004 -V F O R C E Figure 22. Remote sense connections Part Number IRF3703 IRF1404S IRF6603 IRL3803S HUF76145S3S HUF76145S3S STV160NF03L STB80NF03L-04 SUB75N03-04 SUB75N04-05L Table 2. Available low RDS(ON) power MOSFETs RDS(ON) @ VGS = 10V Manufacturer V(BR)DSS International Rectifier 30V 2.8m max. International Rectifier 40V 4m max. International Rectifier 30V 3.9m max. International Rectifier 30V 6m max. Fairchild Semiconductor 30V 4.5m max. Fairchild Semiconductor 30V 5.5m max. ST Microelectronics 30V 2.8m max. ST Microelectronics 30V 4m max. Vishay Siliconix 30V 4m max. Vishay Siliconix 40V 5.5m max. Summit Microelectronics, Inc 2049 4.0 3/04/02 ID@100C 180A 162A 22A 140A 75A 75A 113A 56A 75A 55A Package Super D2 D2PAK DirectFETTM D2PAK D2PAK D2PAK Power SO-10 D2PAK TO-263 TO-263 30 Figure 23 - IBMTM PowerNP NP4GS3 network processor reference platform. (Not all connections are shown. Please forDrive, further Orchard City #131 *information). Campbell CA 95006 * Phone 408 378-6461 * FAX 408 378-6596 www.summitmicro.com (c) SUMMIT Microelectronics, Inc. contact 2001 * 300 IBM 31 2049 4.0 3/04/02 out in in W atch_Long_Dog_In Force_Shutdown_ In 1.8V 330 SDA SCL in SCL 13 330 7 47 17 18 19 8 24 12 33 35 9 VREFL1 10 VO UT1 22 6.81K 2.21K FORCE_SD PW R_ON UV_OVERRIDE ENABLE PGND AGND DGND PGND W DO# LDO# W LDI 39 27 48 1 2 11 10 45 44 43 37 32 1 D D D 2 S 8 7 1 30 20 S S D 3 2 RTOP 4 CO MP LT1431 V+ GND-S GND-F 5 6 REF RMID 40 G 1 IRL3803S CO LLECTOR 3 2 3 S IRF7805 7 8 VDD_CAP SDA SCL A0 M em ory Address = A2 A1 Register Address = 92 A2 SEATED1# SEATED2# 41 VI1 RS3 0.002 adjust value for current trip SM P9210 GND 42 46 10uF VDD 12 VREFH1 Vcc 14 SDA 3 A0 2 A1 1 A2 11 SCL SDA 10K G 10 4 VGATE1 6 VI2 D 36 31 G 10 4 5 1 D D D 2 S 3 S 21 S IRF7805 7 8 6 D 10 3 2 360 0.1F S D G 1 IRL3803S SMT4004 CB2 5 VO1 adjust value for current trip RS2 0.002 VGATE2 +5.1V or VDD_CAP 10K 2plcs in out W atch_Dog_O ut Long_Dog_Out 3.7V in SEAT_2 in in bi 2_W ire_Data 2_W ire_Clock SEAT_1 in VI3 5.1V CB1 CB3 10 VO2 adjust value for current trip RS1 0.002 VO3 in VGATE3 TM VI4 CB4 34 29 4 6 D 1 23 5 G 10 VGATE4 RS4 0.002 adjust value for current trip 38 RST4# RST3# RST2# RST1# S 3 S 7 8 D D D IRF7805 S 2 VGG_CAP 1.25V REF IRQ# TRKR_IRQ# HEALTHY# CBFAULT M R# IRQ_CLR# 28 4 7 9 1uF NC Out In Out 1.8V_RST 3.3V_RST 2.5V_RST 5V_RST +5V (Vcc) +2.5V +3.3V 10K +1.8V PW R_IRQ TRKR_IRQ Pwr_Sys_OK Current_Trip Manual_Reset Interrupt_Clear 0.1F Out Out Out Out In Out Out Out Out Out Out +5.1V or VDD_CAP +5.1V or VDD_CAP 26 25 5 6 3 16 15 14 13 10K CROW BAR VO4 2.5V SMT4004 APPLICATIONS INFORMATION (CONTINUED) SMT4004 DEVELOPMENT HARDWARE AND SOFTWARE directly downloaded to the SMT4004 via the programming Dongle and cable. An example of the connection interface is shown in Figure 24. The end user can obtain the Summit SMX3200 programming system for device prototype development. The SMX3200 system consists of a programming Dongle, cable and Windows GUI software. It can be ordered on the website or from a local Summit representative. The latest revisions of all software and an Application Brief describing the SMX3200 is available from the website (www.summitmicro.com). When design prototyping is complete, the software can generate a HEX data file that should be transmitted to Summit for design verification and approval. Summit will then assign a unique customer ID to the HEX code and program production devices. The devices are marked with the customer ID as a part number suffix per the marking specification shown at the end of the data sheet. The SMX3200 programming Dongle/cable interfaces directly between a PC's parallel port and the target application. The SMT4004 is then configured on-screen via an intuitive graphical user interface employing drop-down menus. Please be aware that the end user can always reconfigure a product that has been programmed by Summit, however, doing so does not allow the part to be fully tested with the new configuration register settings. The Windows GUI software will generate the data and send it in I2C serial bus format so that it can be Top view of straight 0.1" x 0.1 closed-side connector. SMX3200 interface cable connector. Pin 10, Reserved Pin 8, Reserved Pin 6, MR# Pin 4, SDA Pin 2, SCL Positive Supply V D D _C AP SM T4004 MR# SD A SC L 10 8 6 4 2 9 7 5 3 1 Pin 9, 5V Pin 7, 10V Pin 5, Reserved Pin 3, GND Pin 1, GND 0.1 F GND Com mon Ground Figure 24 SMX3200 Programmer I2C serial bus connections to program the SMT4004. Summit Microelectronics, Inc 2049 4.0 3/04/02 32 SMT4004 DEFAULT CONFIGURATION REGISTER SETTINGS - SMT4004F-017 Register Hex Contents Configured as: R00 B4 Bus-Side VI1 UV Threshold set to 4.5V - PVITUV R01 69 Bus-Side VI2 UV Threshold set to 3.0V - PVITUV R02 41 Bus-Side VI3 UV Threshold set to 2.2V - PVITUV R03 28 Bus-Side VI4 UV Threshold set to 1.7V - PVITUV R04 60 Bus-Side VI1 UV and OV enabled, OV Threshold set to 5.5V - PVITOV R05 60 Bus-Side VI2 UV and OV enabled, OV Threshold set at 3.6V - PVITOV R06 62 Bus-Side VI3 UV and OV enabled, OV Threshold set at 2.8V - PVITOV R07 67 Bus-Side VI4 UV and OV enabled, OV Threshold set at 2.5V - PVITOV R08 B9 Card-Side VO1 Threshold set to 4.6V - PVOTUV1 R09 6E Card-Side VO2 Threshold set to 3.1 V - PVOTUV1 R0A 46 Card-Side VO3 Threshold set to 2.3V - PVOTUV1 R0B 2D Card-Side VO4 Threshold set to 1.8V - PVOTUV1 R0C A2 Card-Side VO1 Threshold 2 set to 4.5V - PVOTUV2 R0D A3 Card-Side VO2 Threshold 2 set to 3.0V - PVOTUV2 R0E A4 Card-Side VO3 Threshold 2 set to 2.2V - PVOTUV2 R0F A6 Card-Side VO4 Threshold 2 set to 1.7V - PVOTUV2 R10 05 Responds to pin biased addresses, 1010BIN, 250V/s slew rate on and off R11 DD Enable all RST# sources Except for CB R12 DD Enable all RST# sources Except for CB R13 FF Enable all IRQ# sources R14 FF Enable all IRQ# sources R15 6F 800 ms POR to IRQ# delay, enable all sources, CB Trip point set to 25mV R18 00 - Note 1/ R19 81 Enable Crowbar on manual input and Quicktrip only R1A AA Enable 100mV Quicktrip all manager circuits R1B 02 All outputs active low, over current delay 100s R1C F6 Reset 200ms, Longdog 3200ms, Watchdog 1600ms MR# Required to Program, Fault Latching disabled, I2C Power On/Off Disabled, OV Causes a Forced ShutDown Note 1/ - Bits D5, D6 and D7 are reserved bits; therefore the contents of R18 may not be 00h. Application Note 22 contains a complete description of the default settings and each of the 32 individual Configuration Registers. The default configuration does not include Registers R16 and R17 (virtual addresses) or R1D, R1E and R1F (Fault Status Registers). Summit Microelectronics, Inc 2049 4.0 3/04/02 33 SMT4004 PACKAGE 48 P IN TQ FP P AC K AG E 0 .3 54 (9.00 ) BSC 0 .2 76 (7.00 ) B S C (B ) Inc he s (M illim e te rs ) (A) 0 .0 2 (0.5) BSC 0.0 0 7 - 0 .0 1 1 (0.17 - 0 .2 7) D E T A IL " A " (B ) (A) R ef Jed ec M S-026 0 .0 37 - 0 .04 1 0 .9 5 - 1.05 Pin1 Indicator 0 .0 39 (1.00 ) 0 .0 47 M A X. (1.2) A B Ref 0 o M in to 7o Max 0.0 0 2 - 0 .0 0 6 (0.05 -0.15 ) 0 .0 18 - 0 .03 0 (0.45 - 0 .75 ) D ET AIL "B " Summit Microelectronics, Inc 2049 4.0 3/04/02 34 SMT4004 PART MARKING Sum m it Part N u m b er SU M M IT SM T4004F Annn Status Tracking Code (Blank, MS, ES, 01, 02,...) (Sum m it Use) xx AYYW W Pin 1 Date Code (YYW W ) Lot tracking code (Sum m it use) Drawing not to scale Part N u m ber su ffix Product Tracking Code (Sum m it use) ORDERING INFORMATION SMT4004 F nnn Part Number Suffix Package F = 48 Pin TQFP Summit Part Number NOTICE SUMMIT Microelectronics, Inc. reserves the right to make changes to the products contained in this publication in order to improve design, performance or reliability. SUMMIT Microelectronics, Inc. assumes no responsibility for the use of any circuits described herein, conveys no license under any patent or other right, and makes no representation that the circuits are free of patent infringement. Charts and schedules contained herein reflect representative operating parameters, and may vary depending upon a user's specific application. While the information in this publication has been carefully checked, SUMMIT Microelectronics, Inc. shall not be liable for any damages arising as a result of any error or omission. SUMMIT Microelectronics, Inc. does not recommend the use of any of its products in life support or aviation applications where the failure or malfunction of the product can reasonably be expected to cause any failure of either system or to significantly affect their safety or effectiveness. Products are not authorized for use in such applications unless SUMMIT Microelectronics, Inc. receives written assurances, to its satisfaction, that: (a) the risk of injury or damage has been minimized; (b) the user assumes all such risks; and (c) potential liability of SUMMIT Microelectronics, Inc. is adequately protected under the circumstances. Revision 4.0 - This document supersedes all previous versions and covers Status Tracking Codes up to 10 and Windows GUI revision 2.39.3 and later. Please check the Summit Microelectronics, Inc. web site at www.summitmicro.com for data sheet updates. (c) Copyright 2002 SUMMIT MICROELECTRONICS, Inc. Power Management for CommunicationsTM I2C is a trademark of Philips Corporation. IBM, the IBM logo, PowerPC, and PowerPC 750 are trademarks of International Business Machines in the United States and/or other countries. Summit Microelectronics, Inc 2049 4.0 3/04/02 35