SMT4004Fnnn - Summit Microelectronics, Inc.

SMT4004

2049 4.0 3/04/02 1

FEATURES & APPLICATIONS

• Programmable Softstart, Tracking and Voltage

Monitoring Functions

• Controls 4 Independent Supplies Down to 0.9V

• Programmable Bus-Side and Card-Side UV and

OV Thresholds

• Guarantees Differential Supply Tracking

• Operates From Any One of Four Supply

Voltages down to 2.7V

• Four independent RST#s, two IRQ#s,

CROWBAR and Circuit breaker functions

• I2C 2-Wire Serial Bus Interface for

Programming, Power On/Off and Operational

Status

• 256X8 Nonvolatile EEPROM Memory Array

Applications

• Power Supply Management

• Telecom/Datacom Motherboards/Servers

• Mezzanine Line Cards

• Compact PCITM Hot Swap Control

• Network Processors, DSPs, ASICs

INTRODUCTION

The SMT4004 is a fully integrated programmable

voltage manager IC, providing supervisory functions

and tracking control for up to four independent power

supplies. The four internal managers perform the

following functions: monitor source (bus-side) voltages

for under-voltage and over-voltage conditions, monitor

back end (card-side) voltages for under-voltage

conditions, ensure voltages to the card-side track

within specified parametric limits, and provide status

information to a host processor.

The SMT4004 incorporates nonvolatile

programmable circuits for setting all monitored

thresholds for each manager. Individual functions are

also programmable allowing Interrupts or Reset

conditions to be generated by many combinations of

events. Also included are nonvolatile fault status

registers and a 2K-bit (256 byte) nonvolatile memory.

User programming of configuration and control

values is simplified with the interface adapter

(SMX3200) and Windows GUI software obtainable

from Summit Microelectronics.

SIMPLIFIED APPLICATIONS DRAWING

Bus-Side Connector

Card-Side Application Circuits

2.5V

10Ω

1.5V

10Ω

SMT4004

10Ω

SCL

SDA

SEATED1#

SEATED2#

ENABLE

PWR_ON

HEALTHY#

IRQ_CLR#

GND

VI2

CB2

VGATE2

VO2

VGG_CAP

VDD_CAP

VI1

CB1

VGATE1

VO1

VI3

CB3

VGATE3

VO3

VI4

CB4

VGATE4

VO4

1uF 10µF

RST1#

RST2#

RST3#

RST4#

IRQ#

TRKR_IRQ#

MR#

WDO#

LDO#

RS1

RS2

RS4

RS3

41 37 32 20 39 35 30 22 34 29 2338

5

1

2

7

9

13

14

15

16

28 421836 31 2140

26

6

33

10

11

47

46

24

Note: This is an applications example only. Some pins, components and values are not shown.

QUAD TRACKING POWER SUPPLY MANAGER

SMT4004

Summit Microelectronics, Inc 2049 4.0 3/04/02 2

SUPPLY MANAGERS

The SMT4004 has four distinct programmable

power supply managers and associated circuitry. The

managers are individually programmable and can

operate independently or together with the other

managers. Each manager monitors the bus and card-

side voltages and current for that supply (Figure 1).

The VI pin is the bus-side input that connects to two

comparators to monitor under-voltage (UV) and over-

voltage conditions (OV). The threshold for the UV

detector is programmable in 20mV increments, from

0.9V to 6.0V. The OV detector is programmable in 4%

increments of the UV settings, from 120% to 244% of

the UV settings. The OV threshold is an offset from the

UV sensor and the offset varies as the UV threshold; if

UV is set to 0.9V then OV can be set from 1.08 to

2.2V.

The OV setting is related to the UV setting according

to:

OV = UV X [(0.04 X DecVal) + 1.2]

Where:

OV = Bus-side Over-voltage setting.

UV = Bus-side Under-voltage setting.

DecVal = Decimal value of OV Register contents.

If the VI input is below the UV threshold the

manager generates a UV fault status on the internal

bus. If the VI input is above the OV threshold the

manager generates an OV fault status on the internal

bus. The UV and OV status information can be

selected to generate an IRQ# output. Refer to Figure

3 for an illustration of the IRQ# function and the

relation of the UV and OV status of the four managers.

The VO pin is the card-side input that connects to

two comparators to monitor two under-voltage

threshold conditions. The threshold for the first under-

voltage monitor (UV1) is programmable in 20mV

increments, from 0.9V to 6.0V. If the VO input is below

the UV1 threshold the manager generates an UV1

fault status on the internal bus.

The threshold for the second under-voltage monitor

can be set equal to the UV1 threshold or to one of 31

values less than UV1. The UV2 setting is related to the

UV1 setting according to:

UV2 = UV1 X [1-(0.01 X DecVal)]

Where:

UV1 = Card-side primary Under-voltage setting.

UV2 = Card-side secondary Under-voltage setting.

DecVal = Decimal value of UV2 Register contents.

If the VO input is below the UV2 threshold the

manager generates an UV2 fault status on the internal

bus. Generally the first threshold, UV1, is used to

provide a warning that the supply is deteriorating while

the second threshold, UV2, is set lower to indicate the

supply is out of the operating range. The UV1 and

UV2 status outputs from the manager can be

programmed to generate a Reset or an Interrupt.

DETAILED DEVICE DESCRIPTION

VI

CB

Programmable

Offset

-

+

VREF

-

+

-

+

VREF

-

+

-

+

25mV

50mV

Programmable

Delay

Programmable

QuickTrip

Threshold

QT-CB

VO

OV

UV

UV1

UV2

VO

Programmable

Threshold

Programmable

Offset

-

+

Internal Bus

UV_OVERRIDE

Programmable

Threshold

Figure 1. Supply Manager Schematic.

SMT4004

Summit Microelectronics, Inc 2049 4.0 3/04/02 3

The UV_OVERRIDE input is used to mask under-

voltage conditions. When asserted (high) all under-

voltage conditions are ignored. This function is used

either during system test or when performing voltage

margin tests. During normal operation this pin must be

connected to ground.

CB is the circuit breaker input. A series resistor

placed between VI and CB causes the circuit breaker

to trip when the voltage across the resistor exceeds

the programmed value of 25mV or 50mV (VCB). A

programmable filter is provided to allow voltage drops

greater than VCB for selected delays of 25µs, 50µs,

100µs or 200µs. If the filter time is exceeded; an over-

current condition (QT-CB) is generated from the

manager.

The CB pin is also connected to the QuickTrip

comparator. It is used in conjunction with the circuit

breaker function or may be disabled. When enabled, a

voltage across the series resistor exceeding the

QuickTrip threshold (VQT) instantly generates a QT-CB

signal from the manager. VQT can be set to different

levels depending on the CB selection; see VQT page

13.

The QT-OC output from the manager can generate

a RST# (Figure 2), an IRQ#, (Figure 3) or an internal

force shutdown (FSD) and crowbar output (Figure 5).

DEVICE POWER SUPPLY

The VI inputs also provide the operating supply

voltage for the SMT4004. Internally they are diode-

OR’ed, so the highest potential VI input becomes the

VDD supply. Refer to the functional Block Diagram on

page 8.

RESET CIRCUIT

The SMT4004 has four active-low, open-drain

Reset pins (RST1# - RST4#). All RST# outputs are

asserted once power is applied; remaining asserted

for tPRTO (programmable reset timeout period, Figure

10) after all Reset generating conditions are removed.

Individual RST# outputs can be programmed to

become active from three manager status conditions:

UV1, UV2 or QT-CB. The RST# output remains active

for tPRTO after the fault condition is removed (Figure 2).

Asserting the Manual Reset input (MR# low) forces all

RST# outputs low. The RST# outputs remain low while

MR# is low, returning high tPRTO seconds after MR# is

de-asserted.

INTERRUPT (IRQ#) CIRCUIT

The SMT4004 has an active-low open-drain IRQ#

output. The sources for triggering an interrupt are

selected from the UV, OV, UV1 and UV2 status

outputs of each manager. When asserted, IRQ# is

latched and can only be cleared by a high to low

transition on the IRQ_CLR# pin (Figure 3).

01234567

RESET & TRKR_IRQ SELECT REG

01234567

RESET & TRKR_IRQ SELECT REG

UV22

UV12

UV21

UV11

UV23

QT-CB3

UV13

UV24

UV14

RST2#

RST1#

RST3#

RST4#

reset circuit

PRT

MR#

PRT Programmable Reset Timer





QT-CB4

QT-CB1

QT-CB2

PRT

Figure 2. Programmable and hard-wired sources for

generating resets.

DETAILED DEVICE DESCRIPTION (CONTINUED)

SMT4004

Summit Microelectronics, Inc 2049 4.0 3/04/02 4

QT_CB1

IRQ#

01234567

IRQ# SELECT REGISTER

UV22

UV12

UV2

OV2

UV21

UV11

UV1

OV1

UV24

UV14

UV4

OV4

UV23

UV13

UV3

OV3



SET

RESET

Q

IRQ_CLR#

VDD_CAP



0123

IRQ# SELECT

REGISTER

01234567

IRQ# SELECT REGISTER

QT_CB2

QT_CB3

QT_CB4

Figure 3. Interrupt sources from the SMT4004 supply managers.

DETAILED DEVICE DESCRIPTION (CONTINUED)

SMT4004

Summit Microelectronics, Inc 2049 4.0 3/04/02 5

Active Low

Active High

Active Low

Active High

SEATED1#

PWR_ON

SEATED2#

FORCE_SD

VDD_CAP

100KΩ

4 plcs

VG

1

VG

2

VG

3

VG

4

Tracker Select

Regs

UV1

OV1

UV2

OV2

UV3

OV3

UV4

OV4

UV1

OV1

UV2

OV2

UV3

OV3

UV4

OV4

Active Low

Active High

ENABLE



SEQUENCE

ENABLE

LOGIC

VGATE

Circuit

VGATE

Circuit

VGATE

Circuit

VGATE

Circuit

Charge

Pump

VGATE

CONTROL

SOFTSTART

VGATE

CONTROL

TRACKING

DONE

VGATE1

VGATE2

VGATE3

VGATE4

VO1

VO2

VO3

VO4



TRKR_IRQ#

TRKR_IRQ

SELECT

TRKR3

TRKR1

TRKR4

TRKR2

FSD

Figure 4. Charge Pump and VGATE Control

CHARGE PUMP AND VGATE CONTROL

The VGATE outputs control the gate voltages of

external N-channel MOSFETs. Each MOSFET

separates the bus and card-side voltages. The VGATE

outputs control the card-side slew rates during the

power-on/off interval. The VGATEs are turned on

when their controlling inputs meet either softstart

conditions or when tracking conditions are met so the

MOSFET card-side voltages track. The manager

inputs (Figure 1) and the control inputs (Figure 4)

control the VGATE outputs.

Certain conditions must be met for the VGATE

outputs to become active. The conditions are defined

by the sequence enable logic, the manager inputs and

the user selected function (softstart or track) for each

VGATE output.

The VGATE control blocks (Figure 4) are the logic

functions controlling the VGATE outputs. All inputs to

these blocks are used to enable the VGATE outputs to

drive the external MOSFETs.

The ENABLE input only affects the charge pump

(VGG_CAP voltage). Its active state is programmable

and must be true to turn-on the charge pump. The

charge pump provides the high-side drive voltage to

the VGATE pins.

The PWR_ON and FORCE_SD inputs active

states are programmable. PWR_ON, SEATED1# and

SEATED2# must be true and FORCE_SD false to

enable a power-on sequence.

DETAILED DEVICE DESCRIPTION (CONTINUED)

SMT4004

Summit Microelectronics, Inc 2049 4.0 3/04/02 6

If both softstart and tracking are enabled, the

softstart VGATE outputs must be fully on (VGATE =

VGG_CAP) before the tracking VGATEs are enabled.

The VO inputs are monitored and compared by the

tracking logic to control the VGATEs of the tracked

voltages. They are also used by the VGATE tracking

control logic to generate a TRKR_IRQ# output if a

differential of >300mV between any tracked VO input

occurs during the tracking interval.

FORCE SHUTDOWN AND CROWBAR

The VGATE outputs can be rapidly shutdown by

asserting the FORCE_SD input or when an internally

generated force shutdown (FSD) occurs.

Internal sources that generate a force shutdown

are programmable and are: a TRKR_IRQ#, a general

IRQ# or an over-current condition (QT-CB) (Figure 5).

HEALTHY# AND CBFAULT

The SMT4004 has two status output pins,

HEALTHY# and CBFAULT (Figure 6). HEALTHY# is

an active-low open-drain output that is asserted when

all bus and card-side conditions are within the

programmed settings, i.e., there must be no bus or

card-side fault conditions (programmed RST#s,

IRQ#s, or TRKR_IRQ#s) from the bus-side UV, OV

and card-side UV1, UV2 and QT-CB outputs from the

managers. If no RST#s, IRQ#s, or TRKR_IRQ#s are

enabled, HEALTHY# will stay asserted even if fault

conditions exist. HEALTHY# is an instantaneous

indication of the status of the signals RST#s, IRQ#,

and TRKR_IRQ# and is derived from the unlatched

versions of these signals.

The CBFAULT is programmable as an active high

or active low output. It is asserted when an over-

current condition (QT-CB) occurs (Figure 6).

FAULT STATUS REGISTERS

The SMT4004 has three nonvolatile fault status

registers. When an IRQ# is generated the cause of the

interrupt is recorded in the fault register. The fault

source is indicated as a ‘1’ in the assigned bit location

(Figure 7). The fault status registers are overwritten

each time an IRQ# is generated. The fault status

registers are always available for reading except for

when a nonvolatile write is in progress. The conditions

for overwriting (clearing) the fault condition is

dependent upon the device configuration with regard

to the programmable ‘active writing state’ of the MR#

input. Clearing the fault status registers is not

necessary as the last fault condition overwrites any

information previously stored. If clearing the registers

is desired, it is accomplished by forcing a write to

those registers while no fault conditions exist.

FORCE_SD

REG



QT-CB1

FORCE_SD

IRQ

TRKR_IRQ

CROWBAR

VDD_CAP

SET

RESET

Q

CROWBAR

FUNCTION

SELECT

BEGIN_TRK

QT-CB2

QT-CB3

QT-CB4

FSD

Figure 5. Force Shutdown (FSD) and CROWBAR circuitry.

HEALT

H

CBFAUL

T

Card-Side UV1X

Card-Side UV2X

Bus-Side UVX

Bus-Side OVX

TRKR_IRQ

IRQ

X

Typical of All Channels

Card-Side UV1X

Card-Side UV2X

QT-CBX

RSTX

RST1

IRQ1

RST2

IRQ2

RST3

IRQ3

RST4

IRQ4

QT-CB1

QT-CB2

QT-CB3

QT-CB4

Figure 6. HEALTHY# and CBFAULT circuitry.

DETAILED DEVICE DESCRIPTION (CONTINUED)

SMT4004

Summit Microelectronics, Inc 2049 4.0 3/04/02 7

For prototyping purposes, the Windows GUI

(described in the Serial Interface section) has an

option to clear the fault status registers.

Fault recording is disabled when the PWR_ON

input is de-asserted.

WATCHDOG AND LONGDOG TIMERS

The SMT4004’s internal timer triggers the

activation of the LDO# and WDO# outputs. LDO# and

WDO# are active-low open-drain outputs that can be

wire-OR’ed with other open-drain signals.

During a power-on sequence the timers are

disabled until all four Resets are released. At this time

both timers, if enabled, begin clocking at t0. If either

times out, it asserts its respective output. The timers

work in tandem, so any high to low transition on the

WLDI input Resets both timers to t0.

The longdog timer must be programmed to timeout

sometime after the watchdog timer. The WDO# could

then be wire-OR’ed with the IRQ# output to provide an

alert that action needs to be taken. The LDO# output

could be wire-OR’ed with a system RST# signal to

indicate a shutdown condition exists.

Both timers can be programmed off, facilitating

system debug. This feature can also be used to allow

an operating system to boot-up and configure itself

without Interrupts or Resets.

SERIAL INTERFACE

The SMT4004 uses the industry standard I2C, 2-

wire serial data interface. This interface provides

access to the configuration registers, the nonvolatile

fault registers and a 2K-bit (256 byte) nonvolatile

memory. The interface has three address inputs (A0 -

A2) allowing up to eight devices on the same bus. This

allows multiple devices on the same board or multiple

boards in a system to be controlled with two signals;

SDA and SCL.

The configuration and nonvolatile fault registers

share the same device type identifier, 1001[bin], which

is distinct from the 2K memory device type identifier,

optionally 1010[bin] or 1011[bin]. The separation of

address space allows full utilization of the memory

array. The memory is functionally identical to the

industry standard 24C02.

The memory array can be read with MR# low. The

memory array cannot be written when the part is in

reset whether from MR# being low or from any other

reset source. The configuration and fault registers may

be read regardless of the state of MR#. A user option

selects the active state of the MR# input for writing to

the configuration and fault registers.

Device configuration utilizing the Windows based

SMT4004 graphical user interface (GUI) is highly

recommended. The software is available from the

Summit website (www.summitmicro.com). Using the

GUI in conjunction with this datasheet and Application

Note 22, simplifies the process of device prototyping

and the interaction of the various functional blocks. A

programming Dongle (SMX3200) is available from

Summit to communicate with the SMT4004. The

Dongle connects directly to the parallel port of a PC

and programs the device through a cable using the I2C

bus protocol.

DETAILED DEVICE DESCRIPTION (CONTINUED)

7 6 5 4 3 2 1 0

UV1

UV2

UV3

UV4

OV1

OV2

OV3

OV4

7 6 5 4 3 2 1 0

TRKR1

TRKR2

TRKR3

TRKR4

QT-CB1

QT-CB2

QT-CB3

QT-CB4

7 6 5 4 3 2 1 0

UV11

UV12

UV13

UV14

UV21

UV22

UV23

UV24

Fault Status Register Address 1D

Fault Status Register Address 1E

Fault Status Register Address 1F

Figure 7. Fault Status register bit allocation

SMT4004

Summit Microelectronics, Inc 2049 4.0 3/04/02 8

INTERNAL BLOCK DIAGRAM

SUPPLY

MANAGER

#1

SUPPLY

MANAGER

#2

SUPPLY

MANAGER

#3

SUPPLY

MANAGER

#4

RESET

INTERRUPT

CONTROL

&

FAULT STATUS

REGISTERS

RST1#

13

14

CHARGE

PUMP & VGATE

CONTROL

TIMER LOGIC

SERIAL

INTERFACE

&

MEMORY

ARRAY

5 624

VDD_CAP

SEQUENCE

ENABLE

LOGIC

POWER SUPPLY

ARBITRATION

WLDI

LDO#

WDO#

SCL

SDA

A0

A1

A2

VGATE1

VGATE2

VGATE3

VGATE4

VGG_CAP

RST2#

RST3#

RST4#

IRQ#

TRKR_IRQ#

CBFAULT

CROWBAR

HEALTHY#

IRQ_CLR#

MR#

ENABLE

27 33 10 11

SEATED2#

SEATED1#

PWR_ON

FORCE_SD

15

16

7

9

3

26

25

32

31

30

29

28

48

1

2

47

46

43

44

45

817 18 19 42

PGND

DGND

AGND

VDD_CAP

41

20

37

VI1

VO1

CB1

40

21

36

VI2

VO2

CB2

39

22

35

VI3

VO3

CB3

38

23

34

VI4

VO4

CB4

4

1.25VREF



All Resistors

are 100KΩ

12

UV_

OVERRIDE



Figure 7A. SMT4004 Internal Block Diagram.

SMT4004

Summit Microelectronics, Inc 2049 4.0 3/04/02 9

PIN D

PIN DESCRIPTIONS

Number

Type Pin Name Description

1 O LDO#

The longdog timer output is an active low open-drain output. It is driven low

when the longdog timer has timed out.

2 O WDO#

The watchdog timer output is an active low open-drain output. It is driven low

when the watchdog timer has timed out.

3 O P CROWBAR

CROWBAR is an active high totem pole output. It is a programmable output;

it can act as a CROWBAR output or as an Early-Voltage-Drive (EVD) output.

As a CROWBAR it generates a short duration (≈20µs) positive pulse

generally used to trigger an external SCR. The sources for initiating the pulse

are user selectable and are illustrated in Figure 5.

As an EVD output, the pin is held high until the SMT4004 begins tracking,

allowing an external MOSFET to discharge any residual voltages on the card-

side power rails.

4 PWR

(out) 1.25VREF The 1.25VREF pin provides a 1.25V reference output voltage. It requires a

0.1µF bypass capacitor to AGND (pin 19).

5 I MR#

The MR# (manual Reset) pin is an active low input. When MR# is driven low,

the RST1#-RST4# pins are driven low and stay low while MR# is asserted.

After MR# returns high, the Reset outputs remain low for tPRTO. Asserting

MR# also resets the watchdog and longdog timers to t0 after the expiration of

tPRTO. The MR# pin is internally pulled-up to VDD_CAP with a 100KΩ resistor.

6 I IRQ_CLR#

The IRQ_CLR# pin is an active low input. A low on IRQ_CLR# clears any

active IRQ#. As long as IRQ_CLR# is held low, IRQ#s are blocked. The

IRQ_CLR# pin is internally pulled-up to VDD_CAP with a 100KΩ resistor.

7 O IRQ#

The IRQ# is an active low open-drain output. It is driven low when one or

more of its programmable triggers are active. The programmable trigger

sources are illustrated in Figure 3.

8 PWR PGND

PGND is the ground for the power portion of the internal circuitry. It is

internally tied to pin 17. Both pins must be tied to system ground.

9 O TRKR_IRQ#

TRKR_IRQ# is an active low open-drain output. It is driven low when one or

more of its programmable triggers are active. The programmable trigger

sources are tracking errors detected by the managers and are illustrated in

Figure 4.

10 I SEATED1#

11 I SEATED2#

The SEATED# inputs are effectively enable inputs. Both must be low for the

power-on sequence to proceed. In applications utilizing staggered pin lengths

the SEATED# inputs should be tied to the short pins. Internally these pins

are pulled-up to VDD_CAP with 100KΩ resistors.

12 I UV_OVERRIDE

The UV_OVERRIDE pin is an active high input. When asserted, the UV

comparators are disabled (Figure 1). Internally this pin is pulled-up to

VDD_CAP with a 100KΩ resistor. This pin must be low for normal operation.

Note: P indicates the pin’s function or the active state of the pin is programmable.

SMT4004

Summit Microelectronics, Inc 2049 4.0 3/04/02 10

PIN DESCRIPTIONS (CONTINUED)

Number

Type Pin Name Description

13 O RST1#

14 O RST2#

15 O RST3#

16 O RST4#

The RST# outputs are active low open-drain outputs. The supply manager

trigger source for each Reset output is individually programmable and is

illustrated in Figure 2.

Each output remains low until the fault is removed and tPRTO has expired.

All Reset outputs are driven low when the MR# input is asserted; remaining

low while MR# is asserted and for tPRTO after MR# is released.

17 PWR PGND

PGND is the ground for the power portion of the internal circuitry. It is

internally tied to pin 8. Both pins must be tied to system ground.

18 PWR DGND

DGND is the ground for the digital portion of the internal circuitry. It must be

tied to system ground.

19 PWR AGND

AGND is the ground for the analog portion of the internal circuitry. It must be

tied to system ground.

20 I VO1

21 I VO2

22 I VO3

23 I VO4

The VO inputs are used to monitor the card-side voltages for the individual

managers.

24 I P ENABLE

ENABLE is an input with a programmable active true state. When the input is

true, the charge pump that supplies the high side drive voltage for the VGATE

outputs is turned on. The ENABLE input is internally tied to VDD_CAP with a

100KΩ resistor.

25 O P CBFAULT

CBFAULT is an output with a programmable true state. CBFAULT is asserted

when there is an over-current condition (QT-CB).

26 O HEALTHY#

HEALTHY# is an unlatched active-low open-drain output. It is asserted when

all four managers report no bus-side over-voltages (OV), under-voltages (UV)

or card-side under-voltages (UV1 or UV2) or over-current (QT-CB)

conditions. See Figure 6.

27 I P FORCE_SD

FORCE_SD is an input with a programmable active true state. When the

input is true, the VGATE outputs are immediately turned off and clamped to

ground. The FORCE_SD input is internally tied to VDD_CAP with a 100KΩ

resistor.

28 PWR VGG_CAP

VGG_CAP is a charge storage connection for the SMT4004 internal charge

pump. A 1µF capacitor rated above 16V is recommended for most

applications.

29 O VGATE4

30 O VGATE3

31 O VGATE2

32 O VGATE1

The VGATE outputs are used to control the turn-on of the card-side voltages

by providing a high side voltage to a power MOSFET. The fully on output

voltage is 14.5V.

Note: P indicates the pin’s function or the active state of the pin is programmable.

SMT4004

Summit Microelectronics, Inc 2049 4.0 3/04/02 11

PIN DESCRIPTIONS (CONTINUED)

Number

Type Pin Name Description

33 I PWR_ON

PWR_ON is an input with a programmable active true state. It must be true

for the SMT4004 to begin turning on the VGATE outputs. The PWR_ON input

is internally tied to VDD_CAP with a 100KΩ resistor.

Once the power-on operation is complete, de-asserting the PWR_ON input

forces the tracked channels to track down. The channels programmed for

softstart are unaffected and their respective VGATE outputs remain active.

34 I CB4

35 I CB3

36 I CB2

37 I CB1

CBX are inputs monitoring a voltage drop across an external sense resistor

placed between the respective VI and CB inputs.

38 I/PWR VI4

39 I/PWR VI3

40 I/PWR VI2

41 I/PWR VI1

The VI inputs provide two functions. They are primarily the bus-side

(unswitched) voltage monitoring inputs for the individual supply managers.

In addition, they are internally diode-OR’ed to provide the SMT4004’s

VDD_CAP supply.

42 PWR VDD_CAP

VDD_CAP is a charge storage connection to the SMT4004’s internal power

supply. For most applications this pin is tied to a 10µF capacitor.

43 I A0

44 I A1

45 I A2

The address pins are biased either to VDD_CAP or GND and provide a

mechanism for assigning a unique I2C serial bus address to the SMT4004.

These pins are internally pulled-up to VDD_CAP with 100KΩ resistors.

46 I/O SDA

SDA is the bidirectional serial data pin. This pin is internally pulled-up to

VDD_CAP with 100KΩ resistor. SDA is configured as an open-drain output

and requires a pull-up resistor to the highest VDD of the I2C system for proper

operation.

47 I SCL

SCL is the serial clock input, used for clocking data into or out of the

SMT4004. This pin is internally pulled-up to VDD_CAP with 100KΩ resistor.

SCL is configured as an open-drain output and requires a pull-up resistor to

the highest VDD of the I2C system for proper operation.

48 I WLDI

WLDI is an input. A low-to-high transition on this pin resets both the watchdog

and longdog timers to t0. If the WLDI input is held high, WDO# is disabled

while the LDO# output remains active. The WLDI input is internally tied to

VDD_CAP through a 100KΩ resistor.

SMT4004

Summit Microelectronics, Inc 2049 4.0 3/04/02 12

PACKAGE AND PIN CONFIGURATION

ABSOLUTE MAXIMUM RATINGS RECOMMENDED OPERATING CONDITIONS

Temperature Under Bias .................... -55°C to +125°C

Storage Temperature.......................... -65°C to +150°C

Terminal Voltage with Respect to GND:

VI & VO Inputs ……………….………..-0.3V to 7.0V

VGATE Outputs…………………………………...16V

All Others………………………………..-0.3V to 7.0V

Output Short Circuit Current……………………….100mA

Lead Solder Temperature (10 secs)……………….300°C

Junction Temperature............................….............150°C

ESD Rating per JEDEC……………………………..2000V

Latch-Up testing per JEDEC………………......+/- 100mA

Stresses listed under Absolute Maximum Ratings may cause

permanent damage to the device. These are stress ratings only and

functional operation of the device at these or any other conditions

outside those listed in the operational sections of the specification is

not implied. Exposure to any absolute maximum rating for extended

periods may affect device performance and reliability. Devices are

ESD sensitive. Handling precautions are recommended.

Temperature Range(Ambient)...………-40° C to +85°C

Supply Voltage………………….…………2.7V to 6.0V 1/

EEPROM Write Supply Voltage…………3.0V to 6.0V 2/

Package Thermal Resistance (θ JA)

48 Lead TQFP…………………………………80oC/W

Moisture Classification Level 1 (MSL 1) per J-STD- 020

Notes: 1/ For reliable operation the VDD_CAP node voltage must

be equal to or greater than 2.7V (voltage level measured

on pin 42).

2/ During an EEPROM memory array or Configuration

Register Write, the supply voltage minimum is 3.0V.

RELIABILITY CHARACTERISTICS

Data Retention……………………………..…..100 Years

Endurance……………………….……….100,000 Cycles

1

2

3

4

5

6

7

8

9

10

11

12

13

14

15

16

17

18

19

20

21

22

23

24

36

35

34

33

32

31

30

29

28

27

26

25

48

47

46

45

44

43

42

41

40

39

38

37

LDO#

WDO#

CROWBAR

1.25VREF

MR#

IRQ_CLR#

IRQ#

PGND

TRKR_IRQ#

SEATED1#

UV_OVERRIDE

SEATED2#

CB2

CB3

CB4

PWR_ON

VGATE1

VGATE2

VGATE3

VGATE4

VGG_CAP

FORCE_SD

CBFAULT

HEALTHY#

WLDI

SCL

SDA

A2

A1

A0

VDD_CAP

VI1

VI2

VI3

CB1

VI4

RST1#

RST2#

RST3#

RST4#

PGND

DGND

AGND

VO1

VO2

VO3

ENABLE

VO4

48 Lead TQFP

SMT4004

Summit Microelectronics, Inc 2049 4.0 3/04/02 13

DC OPERATING CHARACTERISTICS

(Over recommended operating conditions, unless otherwise noted. All voltages are relative to GND.)

Symbol Parameter Conditions Min. Typ. Max Unit

VSUPPLY Power Supply Voltage

Device supply voltage

provided by the

highest VIX input.

2.7 6.0 V

VX Monitoring Voltage

VI1-VI4, VO1-VO4 0 6.6 V

IDD Power Supply Current

VGATE Outputs

enabled, write to EE

memory array - Note 1/

5 mA

PVITUV Programmable VI

Threshold for UV condition

See explanation on

page 2 0.9 6.0 V

PVITOV Programmable VI

Threshold for OV condition

See explanation on

page 2 1.08 6.6 V

PVITHYS OV/UV trip hysteresis 10 mV

No Write in Progress 0.97xPVITUV PVITUV 1.03xPVITUV V

PVITUVACC Programmable UV

Threshold Accuracy

Write In Progress 0.97xPVITUV PVITUV 1.06xPVITUV V

No Write in Progress 0.95xPVITOV PVITOV 1.05xPVITOV V

PVITOVACC Programmable OV

Threshold Accuracy Write In Progress 0.92xPVITOV PVITOV 1.05xPVITOV V

PVOTUV1

Programmable VO

Threshold for UV1

condition

See explanation on

page 2 0.9 6.0 V

PVOTUV2

Programmable VO

Threshold for UV2

condition

See explanation on

page 2 0.69xPVOTUV1 PVOTUV1 V

No Write in Progress 0.97xPVOTUV1 PVOTUV1 1.03xPVOTUV1 V

PVOTUV1ACC Programmable UV1

Threshold Accuracy

Write In Progress 0.97xPVOTUV1 PVOTUV1 1.06xPVOTUV1 V

No Write in Progress 0.95xPVOTUV2 PVOTUV2 1.05xPVOTUV2 V

PVOTUV2ACC Programmable UV2

Threshold Accuracy

Write in Progress 0.95xPVOTUV2 PVOTUV2 1.08xPVOTUV2 V

CB Trip Point = 25mV 19 25 31 mV

VCB Programmable circuit

breaker trip voltage CB Trip Point = 50mV 37 50 62 mV

CB=25mV QT=55mV 40 55 70

mV

CB=50mV QT=80mV 60 80 100

mV

CB=25mV QT=85mV 65 85 105 mV

CB=50mV QT=110mV 80 110 140 mV

CB=25mV QT=135mV 100 135 170 mV

VQT Programmable Quick Trip

Threshold Voltage

CB=50mV QT=160mV 120 160 200 mV

SMT4004

Summit Microelectronics, Inc 2049 4.0 3/04/02 14

DC OPERATING CHARACTERISTICS (CONTINUED)

(Over recommended operating conditions, unless otherwise noted. All voltages are relative to GND.)

Symbol Parameter Conditions Min. Typ. Max Unit

ON ( IVGATE = 4µA)

- Note 2/ 12 16 V

VVGATE VGATE drive output OFF (IVGATE = -8mA)

- Note 2/ 0 0.4 V

All VGATEs forced to

10V - Note 2/ 10

µA

IVGATE Total VGATE output drive

current All VGATEs forced to 1V

- Note 2/ 30 µA

SRVOX = 100V/s 60 100 140 V/s

SRVOX = 250V/s 150 250 350 V/s

SRVOX = 500V/s 400 500 600 V/s

SRVOX Tracking VOX Slew Rate

SRVOX = 1000V/s 800 1000 1200 V/s

VTRKR Tracking Differential Voltage

Differential between

Tracking VOX pins

- Note 3/

100 250 mV

VTRKR_IRQ# Tracking Differential Voltage

Causes TRKR_IRQ#

Differential between

Tracking VOX pins 300 mV

VREF 1.25VREF Output Voltage RLOAD = 2KΩ to gnd 1.23 1.25 1.27 V

VDD_CAP = 2.7V to

4.5V 0.9xVDD_CAP 6.0 V

VIH Input High Voltage VDD_CAP = 4.5V to

6.0V 0.7xVDD_CAP 6.0 V

VDD_CAP = 2.7V to

4.5V -0.1 0.1xVDD_CAP V

VIL Input Low Voltage VDD_CAP = 4.5V to

6.0V -0.1 0.2xVDD_CAP V

VOL Output Low Voltage Open-drain Outputs, IOL

= -2mA 0 0.4 V

VCSWFZ Card-Side Wait-For-Zero

Threshold Note 4/ 0.5 1.2 V

RPull-Up Input Pull-Up Resistors See Pin Descriptions 50 100 165 kΩ

VCROW CROWBAR Output Voltage RLOAD=10kΩ to gnd VDD_CAP-0.5 VDD_CAP V

Notes: 1/ - Does not include external load on VDD_CAP. Any external pull-up resistors tied to VDD_CAP

will increase IDD. Maximum allowable external current sourced from VDD_CAP is 1mA with VDD_CAP=10µF.

2/ - IVGATE is the sum of all VGATE output currents.

3/ - The SMT4004 adjusts the VGATE outputs to control the differential of the VOX outputs to within 100mV

nominally. External influences may increase the differential until the VGATE outputs adjust to minimize

the differential.

4/ - Guaranteed by Design.

SMT4004

Summit Microelectronics, Inc 2049 4.0 3/04/02 15

AC OPERATING CHARACTERISTICS

(Over recommended operating conditions, unless otherwise noted. All voltages are relative to GND.)

Symbol Description Conditions Min. Typ. Max. Unit

CBDELAY = 25µs 20 25 40 µs

CBDELAY = 50µs 40 50 80 µs

CBDELAY = 100µs 80 100 140 µs

CBDELAY Programmable Circuit Breaker Filter

CBDELAY = 200µs 160 200 280 µs

tPWDTO = 400ms

tPWDTO = 800ms

tPWDTO = 1600ms

tPWDTO Programmable Watchdog Timer

Time-Out Period

tPWDTO = 3200ms

-25 tPWDTO +25 %

tPLDTO = 800ms

tPLDTO = 1600ms

tPLDTO = 3200ms

tPLDTO Programmable Longdog Timer Time-

Out Period

tPLDTO = 6400ms

-25 tPLDTO +25 %

tPRTO = 25ms

tPRTO = 50ms

tPRTO = 100ms

tPRTO Programmable Reset Time-Out

Period

tPRTO = 200ms

-25 tPRTO +25 %

tCROW CROWBAR output pulse width SCR Mode, RLOAD=10kΩ 16 28 µs

tDFIRQ Delay from fault detection to IRQ# 1 µs

tDFRST Delay from fault detection to RST# 1 µs

tDFHEALTHY# Delay from fault detection to

HEALTHY#

1 µs

tDTKRIRQ Delay from tracking fault detection to

TRKR_IRQ#

1 µs

tDFCR Delay from fault detection to

CROWBAR

1 µs

tDMRRST Delay from assertion of MR# to

RST# Active

100 ns

tDVIVG Delay from VIX valid to VGATEX

activated VGG_CAP=14V 0 µs

tDFSVG Delay from assertion of FORCE_SD

to VGATE clamped to ground.

10 µs

SMT4004

Summit Microelectronics, Inc 2049 4.0 3/04/02 16

I2C 2-WIRE SERIAL INTERFACE AC OPERATING CHARACTERISTICS - 100kHz

(Over recommended operating conditions, unless otherwise noted. All voltages are relative to GND.)

Symbol Description Conditions Min Typ Max Units

fSCL SCL Clock Frequency 0 100 KHz

tLOW Clock Low Period 4.7 µs

tHIGH Clock High Period 4.0 µs

tBUF Bus Free Time Before New Transmission

Note 1/ 4.7 µs

tSU:STA Start Condition Setup Time 4.7 µs

tHD:STA Start Condition Hold Time 4.0 µs

tSU:STO Stop Condition Setup Time 4.7 µs

tAA Clock Edge to Data Valid SCL low to valid SDA (cycle n) 0.2 3.5 µs

tDH Data Output Hold Time SCL low (cycle n+1) to SDA

change 0.2 µs

tR SCL and SDA Rise Time Note 1/ 1000 ns

tF SCL and SDA Fall Time Note 1/ 300 ns

tSU:DAT Data In Setup Time 250 ns

tHD:DAT Data In Hold Time 0 ns

TI Noise Filter SCL and SDA Noise suppression 100 ns

tWR Write Cycle Time 5 ms

Note: 1/ - Guaranteed by Design.

TIMING DIAGRAMS

tRtF

tHIGH tLOW

tSU:SDA tHD:SDA tSU:DAT

tHD:DAT tSU:STO tBUF

tDH

tAA

SCL

SDA (IN)

SDA (OUT)

Figure 8 . Basic I2C Serial Interface Timing

SMT4004

Summit Microelectronics, Inc 2049 4.0 3/04/02 17

Soft Start

VGATEs

ENABLE

PWR_ON

SEATED1&2#

Tracking

VGATEs

FORCE_SD

Figure 9. Relationship of de-asserting the enabling inputs on the VGATE outputs.

Composite

RST#

MR#

WDO#

LDO#

WLDI

t0t0

tPWDTO tPWDTO

tPLDTO

t0

<tPWDTO

tPLDTO

tPRTO

tPLDTO

t0

tPWDTO

tPRTO

t0

<tPLDTO

tPRTO

Figure 10. Relation of LDO# and WDO# with WLDI, RST# and MR#

TIMING DIAGRAMS (CONTINUED)

SMT4004

Summit Microelectronics, Inc 2049 4.0 3/04/02 18

APPLICATIONS INFORMATION

APPLICATIONS EXAMPLE

The timing diagram in Figure 11 illustrates a full power-on and power-off sequence and the relationship between

many of the signals. This is based on the simplified applications diagram on Page 1. Manager 1 is programmed to

softstart. Its’ supply feeds two power supplies that are monitored by managers 3 and 4 that, along with manager 2,

are programmed for tracking. The flow chart in Figure 12A and B are a further illustration for the same application.

VI1

VGATE1

VO1

VI2

VI3

VI4

PVIT1

PVIT2

PVIT3

PVIT4

PVOT1

PVOT2

PVOT3

PVOT4

VO2

VO3

VO4

Composite

VO2,3 & 4

VGATE2

VGATE3

VGATE4

VO2

VO3

VO4

=

+

RST#s

tPRTO

HEALTHY#

PWR_ON

ENABLE

Figure 11 – Timing relationship of events during a Power-On and Power- Off sequence.

SMT4004

Summit Microelectronics, Inc 2049 4.0 3/04/02 19

APPLICATIONS INFORMATION (CONTINUED)

YES

COMPARE VO INPUTS

YES

NO

YES

TRACKING ROUTINE

VI4>PVITOV4?

NO

YES

ADJUST VGATE OUTPUTS

REMOVE VO4 FROM TRACKING

∆ > 100mV?

∆ > 300mV?

ADJUST VGATE OUTPUTS

COMPARE VO INPUTS

∆ > 100mV?

COMPARE VO INPUTS

YES

NO

YES

VI3>PVITOV3?

NO

∆ > 100mV?

∆ > 300mV?

ADJUST VGATE OUTPUTS

COMPARE VO INPUTS

∆ > 100mV?

REMOVE VO3 FROM TRACKING

VI2 > PVITOV2? NO

YES

START RESET TIMER

ASSERT HEALTHY# OUTPUT

RESET TIMED OUT?

START LONGDOG

START WATCHDOG

GO TO GENERAL

MONITOR ROUTINE

NO

YES

GO TO SHUTDOWN

ROUTINE

YES

NO

GO TO SHUTDOWN

ROUTINE

NO

YES

VI2,VI3,VI4 ≥ PVITUV1 &

VI2,VI3,VI4 < PVITOV1?

TURN ON VGATE OUTPUTS

YES

Turn ON VGATE1

PWR_ON TRUE?

ENABLE ASSERTED?

FORCE_SD

FALSE ?

VI1 ≥ PVITUV1

&

VI1 < PVITOV1?

CB1 OK?

VI1 ≥ PVITOV1?

NO

YES

NO

YES

NO

YES

NO

YES

NO

YES

NO

SEATED1#

and

SEATED2# TRUE?

NO

YES

GO TO TRACKING

ROUTINE

GO TO

SHUTDOWN

ROUTINE

Manager 1 = Softstart

Managers 2, 3 and 4 =

Tracking

VI2 > VI3 > VI4

IS VGG Voltage Fully ON ?

NO

YES

Figure 12A – Power-On Sequence of Events

SMT4004

Summit Microelectronics, Inc 2049 4.0 3/04/02 20

YES

ALL VOLTAGES WITHIN LIMITS?

VO4 <PVOT4?

ADJUST VGATE4

GENERAL MONITORING

OPERATION

NO

GO TO SHUTDOWN

ROUTINE

ALL CONTROL INPUTS VALID?

YES

NO

DID SEATED# GO HIGH?

YES

WAS ENABLE DEASSERTED?

YES

NO

WAS PWR_ON DEASSERTED?

YES

NO

ENABLE REMOVED ROUTINEPWR_ON REMOVED ROUTINE

SEATED# REMOVED ROUTINE

GO TO PWR_ON

REMOVED ROUTINE

NO

GO TO ENABLE

REMOVED ROUTINE

GO TO SEATED#

REMOVED ROUTINE

DE-ASSERT HEALTHY#

ASSERT ENABLED RST#S

VO4 = VO3?

ADJUST VGATE4

NO

VO4&VO3 = VO2?

ADJUST VGATE4 & VGATE3

NO

YES

VO4&VO3&VO2 = 0V?

ADJUST VGATE4, VGATE3 &

VGATE2

NO

YES

IS ENABLE DEASSERTED?

YES

GO TO ENABLE

REMOVED ROUTINE

NO

SHUTDOWN ALL ACTIVE VGATE

OUTPUTS

IF ON DE-ASSERT HEALTHY# &

IF OFF ASSERT ALL RST#

OUTPUTS

SHUTDOWN ALL ACTIVE VGATE

OUTPUTS

IF ON DE-ASSERT HEALTHY# &

IF OFF ASSERT ALL RST#

OUTPUTS

SHUTDOWN ROUTINE

SHUTDOWN ALL ACTIVE VGATE

OUTPUTS

IF ON DE-ASSERT HEALTHY# &

IF OFF ASSERT ALL RST#

OUTPUTS

IS VOX HIGH?

YES

NO

Figure 12B – Power-Off Sequence of Events

APPLICATIONS INFORMATION (CONTINUED)

SMT4004

Summit Microelectronics, Inc 2049 4.0 3/04/02 21

SOFTSTART VS TRACKING

As a power supply manager the SMT4004

separates two power domains; the bus-side, or source

power supplies, and the card-side that contain the

application circuitry. Its primary tasks are to monitor

the voltages and control the switching of the bus-side

voltages to the card-side circuits. The switching is

accomplished by providing a high-side drive output on

the VGATE pins. The VGATE output is applied to the

gates of the power MOSFET.

Softstart

The supply managers can act as either tracking

managers or as softstart managers. Individual

managers turn on their VGATE outputs once all

enabling conditions for that class of manager (softstart

or tracking) are met. If a manager is set to soft start, its

VGATE output ramps at a programmable constant

slew rate until it reaches its maximum value. This

operation is commonly used when a voltage (e.g., 5V)

is first switched into a DC-to-DC converter or group of

LDOs. These outputs may then be tracked to the card-

side logic.

Tracking

When a manager is programmed for tracking all

enabling conditions for that class of manager

(tracking) must be met before the VGATE outputs are

turned on. The enabling conditions also include all

softstart managers having their VGATE outputs fully

on with no existing fault conditions for the softstart

managers.

During tracking, the card-side voltages are

monitored to minimize the differential voltage between

each tracked voltage until they reach their respective

undervoltage thresholds (UV1). In tracking mode, the

ramp rates are constant but can stop and wait. That is,

if during the tracking interval there is any difference

between the VO inputs, the VGATE outputs will stop

and wait for the slow channel to catch up.

POWER-ON

Initial Conditions

At least one of the VI pins must be equal to or

greater than 2.85V before the power-on operation can

proceed. For reliable operation the VDD_CAP node

voltage must be equal to or greater than 2.7V (voltage

level measured on pin 42). This requires that at least

one of the VI inputs needs to be at or above 2.85V for

proper device operation. There is internal arbitration

circuitry which chooses the highest VIX to power the

SMT4004 and causes an internal voltage drop from

VIX to VDD_CAP.

Both SEATED# inputs must be low. The SEATED#

inputs are generally used with staggered-pin

applications where the connector for the application

card has two or three levels of pin lengths. This allows

‘early-power’ to be applied to the SMT4004 so it can

begin to monitor bus side supplies as they come up,

and also a method to indicate the application board is

fully seated and ready for operation. Removal of a

powered board is first recognized by the SEATED#

pins going high, causing power-off of the board by

shutting down the charge-pump, not ensuring a track

Scope Shot 1. Typical softstart Power-On by two

managers and tracking by two managers.

Scope Shot 2. Power-On with all four managers

set to track.

APPLICATIONS INFORMATION

(

CONTINUED

)

SMT4004

Summit Microelectronics, Inc 2049 4.0 3/04/02 22

down. In this application the SEATED# pins are

routed to the board’s short pins and grounded when

the board is fully inserted. The SEATED# pins can be

tied to card insertion switches or they actively driven

and used as device enable inputs.

FORCE_SD can be programmed as a true high or

true low input. When asserted, the VGATE outputs are

turned off and clamped to ground. Therefore, this input

must be false for power-on to proceed. This pin is

internally pulled up to the VDD_CAP node with a

100KΩ resistor.

The PWR_ON input can be programmed as a true

high or true low input. It must be true for both soft start

and tracking managers to turn on their VGATE

outputs. If the SMT4004 has already activated the

VGATE outputs and PWR_ON is turned off, only the

VGATE outputs for the tracking managers are turned

off. VGATE outputs programmed for soft start remain

active.

An I2C power-on function is available. This allows

the tracking power-on/off operations to be initiated by

the 2-wire serial interface.

If the SMT4004 is configured for I2C power-on, the

PWR_ON pin must be in its true state.

The ENABLE input can be programmed to a true

high or true low input. The ENABLE input activates the

high-side driver charge pump and must be true for the

VGATE outputs to be able to drive the gates of the

external MOSFETs.

Managers programmed for soft start enable their

VGATE outputs once all softstarted VI inputs are

within their programmed threshold limits (UV and OV)

(Figure 13). Managers programmed for tracking

enable their VGATE output once softstarting is

successful conditions and all tracking manager’s VI

inputs are within their programmed threshold limits

(Figure 14).

POWER-ON OPTIONS

Bus-side Over-voltage

If OV detection is selected and is programmed to

be a trigger source for IRQ# and if IRQ# is a trigger

source for force shutdown (FSD), the user has several

options as to how the part reacts to an OV. Different

options can be chosen for how the SMT4004 will

respond during the time periods during power-on, after

power-on has completed, or when normal monitoring

is underway. OV detection must not be enabled on

disabled manager channels.

If an OV occurs after softstart has completed and

before tracking has begun, the SMT4004 can be

programmed to ignore the OV. A case where this

would be selected might be as illustrated in the

Simplified Applications drawing on Page 1. Assume

the +5V softstarts as planned and the LDO’s are

energized. The LDO’s might cause a temporary OV

condition before full regulation on the 1.5V or 2.5V

supplies occurs.

If the ignore option is selected the following are true:

1. Only managers with OV detection are

affected.

2. If OV occurs during softstart, the VGATE

outputs are turned off and remain off until the

OV condition is cleared.

3. If tracking has started and OV is detected, a

FORCE_SD is initiated.

APPLICATIONS INFORMATION

(

CONTINUED

)

Assumptions: managers 1 & 2 are softstart, managers 3 & 4

are tracking and are not shown; Staggered pin application;

ENABLE true low and FORCE_SD true high, both tied to

ground; PW R_ON active high, tied to +5V thru pull up; only

RST1# and RST2# enabled.

FORCE_SD

VI1

PWR_ON

SEATED1&2#

VGATE1

VO1

VI2

VGATE2

VO2

VI1UV

RST1# & RST2#

tPRTO

VI1OV

VO1UV2

VO1UV1

VI2UV

VI2OV

VO2UV2

VO2UV1

GND

ENABLE

Figure 13. Typical Soft Start Sequence

SMT4004

Summit Microelectronics, Inc 2049 4.0 3/04/02 23

Card-side Voltage

When tracking is selected the SMT4004 monitors

the VO inputs prior to initiating the tracking function.

The SMT4004 will not start tracking until the VO inputs

are below 0.5V (VCSWFZ). However, some systems may

partially charge one or more of the power busses if a

softstart voltage has energized some of the application

circuitry. If the charge is excessive (>VCSWFZ), tracking

will not start. The SMT4004 has two options that can

be selected to accommodate this situation.

1. The “Don’t-Wait-For-Zero” (DWFZ) option can be

enabled. As the name implies the SMT4004 will

not monitor the VO inputs and tracking starts once

all UV, OV and enabling inputs are valid.

NOTE: If the starting VO potentials are too high,

tracking of low voltage supplies may not meet

some system specifications.

2. The CROWBAR pin is normally configured to

output a short positive pulse to trigger an SCR.

Optionally it can be configured as a normally active

high output during the power-on phase prior to

tracking. Configured as such, it can be used to

drive the gate of an N-channel MOSFET to actively

discharge any ‘early voltages.’ Once tracking is

initiated, the CROWBAR output goes low allowing

the card-side voltages to turn-on. Refer to Figure

15 for a schematic illustration.

NOTE: This feature can be used independently or

in conjunction with the DWFZ option.

Tracking Failure Options

During tracking, differentials greater than 300mV

between VO inputs can be reported through the

assertion of the TRKR_IRQ# output. Any tracking

manager detecting a failure can generate an interrupt;

and any tracking manager can be assigned to track

but not generate an interrupt.

If a manager is assigned to track and a tracking

error is detected the SMT4004 can be programmed to

take one of the following actions.

• Ignore the condition and proceed with the

power-on operation.

• Shutdown all supplies and generate a

TRKR_IRQ#.

• Generate a TRKR_IRQ# and proceed with the

power-on operation.

RG1

10Ω

VI1

CB1

VGATE1

VO1

Q1

VOUT

to Application

Circuit

RS

PGND

CROWBAR

VIN

Common

GND

SMT4004

Figure 15 - Example implementation of the ‘Early

Drive Function.’

APPLICATIONS INFORMATION

(

CONTINUED

)

Assumptions: managers 1 and 2 are tracking managers;

Managers 3 & 4 are turned off; FORCE_SD is active high

and ENABLE is active low, both tied to ground; PW R_ON is

active high tied to VDD thru a pull-up resistor; the SEATED#

inputs are tied to ground.

VI1

PWR_ON

SEATED1&2#

VGATE1

VO1

VI2

VGATE2

VO2

VI1UV

RST1# & RST2# tPRTO

VI1OV

VO1UV2

VO1UV1

VI2UV

VI2OV

VO2UV2

VO2UV1

gnd

VO1UV1

Composite VO1

and VO2

VO1

VO2

FORCE_SD

GND

ENABLE

Figure 14 - Typical tracking sequence of operation.

SMT4004

Summit Microelectronics, Inc 2049 4.0 3/04/02 24

POWER-OFF

Power-off of the application circuit is affected by

turning off the VGATE outputs. This can be done by

de-asserting one of the enabling signals or the

detection of a fault condition. When the SMT4004

receives a power-off command whether it be from the

PWR_ON pin, an I2C command or from the latching of

a fault, there will be a delay of approximately

VIMAX/Tracking Slew Rate (where VIMAX is the VI with

the highest voltage level) before the first tracked

VGATE begins to discharge.

Enabling Inputs

If the PWR_ON input is de-asserted tracking

managers will ‘track down’ their voltages. The softstart

managers are unaffected and their VGATE outputs

remain active. If either or both SEATED# inputs are

de-asserted the SMT4004 immediately powers-off the

VGATE outputs.

If the FORCE_SD input is asserted, the managers

immediately shut off the VGATE drivers by clamping

these outputs to ground (Scope Shot 4).

If the ENABLE input is de-asserted, the VGATE

outputs are shutoff. Refer to Figure 9 for an illustration

of de-asserting the various enabling inputs.

SOFTWARE POWER-ON/POWER-OFF

The SMT4004 has an option allowing a

commanded power-on and power-off via the I2C serial

interface of tracked channels. If the device is

configured for this option, the PWR_ON pin must be in

the true state. Once all enabling conditions are met

and all voltages are within their thresholds the

SMT4004 can be tracked-up by writing to register 16.

Once the application circuit is tracked-up, a

subsequent write to register 17 initiates a track down.

Refer to the applications circuits and descriptions for a

system level description.

RESET OPERATION

Once power is applied to the SMT4004 the four

RST# outputs are driven low. Because they are meant

to be used by the application circuitry, the RST#

outputs remain low until all Reset trigger sources (for

any manager’s UV1, UV2 or QT-CB output) are

removed. The RST# outputs remain low for the

duration of the programmable reset time-out period

(tPRTO) after the triggers are cleared.

After the circuitry is ‘powered-on’ and the SMT4004

is in the steady-state monitoring mode, the RST#

outputs remain high unless one of the enabled fault

conditions is detected by a manager. When this occurs

only the RST# output affected by that manager is

asserted. All RST# outputs that have gone low to

indicate a problem on their corresponding channel will

remain low until all reset conditions have been

removed and tPRTO has expired.

Scope Shot 3. Power-Off caused by de-assertion of

PWR_ON( all managers selected for tracking).

Scope Shot 4. Power-Off of all managers using

the FORCE_SD pin.

APPLICATIONS INFORMATION

(

CONTINUED

)

SMT4004

Summit Microelectronics, Inc 2049 4.0 3/04/02 25

All four RST# outputs are driven low when the MR#

input is taken low. They continue to assert their

outputs after MR# returns high for tPRTO seconds.

INTERRUPTS, FORCE SHUTDOWN AND

CROWBAR

The SMT4004 has two interrupt outputs: IRQ# and

TRKR_IRQ#. The CROWBAR output is configurable

to operate in conjunction with the IRQ# outputs.

The IRQ# output has a large number of

programmable sources for latching its output. Any

combination of supply manager fault condition outputs

(UV, OV, UV1, UV2 and QT-CB) can be enabled as a

trigger for the IRQ# latched output. Once triggered the

IRQ# output is latched and remains asserted even if

the fault condition is removed. IRQ# can only be

cleared by asserting the IRQ_CLR# input.

IRQ# can also trigger a force shutdown (FSD)

and/or a CROWBAR pulse. Refer to Figure 3 and the

graphical user interface (GUI) for the SMT4004.

During initial power-on of the SMT4004 the IRQ#

output is disabled until the SMT4004 comes out of

Reset. The hold off can be extended from the end of

the Reset timeout period for 0ms, 200ms, 400ms,

800ms or 1600ms. This allows the application circuit

and all of the supplies time to stabilize after the initial

power-on.

The VGATE control circuitry monitors VO inputs for

those managers selected for tracking. If a VO input is

found to not be tracking or deviates from the other

voltages by more than 300mV, the control circuitry

generates a tracker error. If that output is AND’ed with

an enable bit it forces the TRKR_IRQ# output low. No

other fault conditions can generate a TRKR_IRQ#:

Like the IRQ# output TRKR_IRQ# can trigger an

internal force shutdown and/or a CROWBAR pulse.

If the fault latch feature is enabled the fault

condition is captured. The fault sources are a force

shutdown, CROWBAR, or IRQ#. When a fault is

detected a volatile latch is set to keep the SMT4004

from being powered-up again until IRQ_CLR# is

toggled.

The CROWBAR pin is designed to deliver an active

high pulse to an external SCR to shutdown the card-

side voltages as quickly as possible. A CROWBAR

pulse can be triggered by one of seven inputs: a QT-

CB fault, an IRQ#, a TRKR_IRQ# and/or assertion of

the FORCE_SD input. These trigger sources are

optional and any combination can be selected. Note:

Because an over-current condition is potentially

catastrophic, each manager has a unique source input

to the CROWBAR logic even though they are included

in the trigger sources for an IRQ#. This allows less

harmful fault triggers to be used as inputs for the

IRQ#, without generating a CROWBAR. There is also

an option to change the CROWBAR pin output from

an SCR pulse to a voltage level to discharge Card-

side early voltages prior to tracking (see Figure 15).

WATCHDOG AND LONGDOG TIMERS

The SMT4004 has two timers that generate

independent outputs: the WDO#, output, or watchdog

timer output and the LDO# or longdog timer output.

Both timers use the same clock circuitry; however, the

time out period for both timers is independently

programmable. When the timer has timed out for

either the watchdog or the longdog, their respective

outputs are driven low. The timers are Reset to t0 by a

low-to-high transition on the WLDI input.

Note: If WLDI is held high the WDO# output is

disabled and the LDO# transitions low after its

programmed time out period tPLDTO. It remains low for

tPLDTO returning high for tPLDTO seconds, repeating the

pulse output until the next low-to-high transition on the

WLDI input.

Both timers are disabled during the initial power-on

operation and will not start until all RST# outputs have

been released. The end of the initial programmable

reset time-out period, tPRTO, is effectively t0 for both

timers. Asserting MR# or the occurrence of a fault

condition causing any Reset disables the timers until

the RST# outputs are released. Refer to Figure 10 for

an illustration of the relation between the timer

outputs, WLDI and the Reset functions.

SERIAL INTERFACE

Access to the configuration registers and

memory array is carried out over an industry standard

2-wire serial interface (I2C). SDA is a bi-directional

data line and SCL is the clock input. Data is clocked in

on the rising edge of SCL and clocked out by the

falling edge of SCL. All data transfers begin with the

MSB. During data transfers SDA must remain stable

while SCL is high. Data are transferred in 8-bit packets

with an intervening clock period in which an

acknowledge is provided by the device receiving data.

The SCL high period (tHIGH) is used for

generating start and stop conditions that precede and

APPLICATIONS INFORMATION

(

CONTINUED

)

SMT4004

Summit Microelectronics, Inc 2049 4.0 3/04/02 26

end most transactions on the serial bus. A high-to-low

transition of SDA during tHIGH is a start condition and a

low-to-high transition of SDA during tHIGH is a stop

condition.

The interface protocol allows operation of

multiple devices and types of devices on a single bus

through the use of unique device addressing. The

address byte is comprised of a 4-bit device type

identifier, a 3-bit bus address and a single bit

indicating that the operation is a read or a write. Refer

to Table 1 for an illustration of the configuration of the

address as defined for the SMT4004.

The device type identifier for the memory array is

generally set to 1010[bin] following the industry

standard for a typical nonvolatile memory. There is an

option to change the identifier to 1011[bin] allowing it to

be used on a bus that may be occupied by other

memory devices. The configuration and fault status

registers are accessible with a separate device type

identifier of 1001[bin].

The bus address is defined by the state (‘0’ or ‘1’)

of the A0, A1 and A2 pins. The serial data stream

must match the state of these pins.

WRITE

Writing to the memory or a configuration register is

illustrated in Figures 16 and 18. A start condition

followed by the address byte is provided by the host;

the SMT4004 responds with an acknowledge; the host

then responds by sending the memory address pointer

or configuration register address pointer; the SMT4004

responds with an acknowledge; the host then clocks in

the data. For memory writes an additional 15 bytes of

data can be written. Only one configuration register

can be written per data transfer. After the last byte is

clocked in, a stop condition must be issued for the

nonvolatile write operation to proceed.

READ

The address pointer for the registers and the

memory can only be changed by a write command. If

a read command is issued without address

conditioning, the data that is clocked out will be from a

location pointed to by the last written (or read) address

incremented by 1.

In order to read data from a specific location a false

write command is issued. The sequence is: issue a

start and a device address with a write command; wait

for an acknowledge; send the array or register

address; wait for an acknowledge; issue a new start

and device address with a read command; wait for an

acknowledge then proceed to clock out data. For

memory reads, the host can acknowledge receipt of

data and then continue clocking out data and

acknowledging without restriction. For register reads,

only a single location can be read with each command

sequence. All read operations are concluded by

issuing a stop condition. Refer to Figures 17 and 19

for an illustration of the read sequence.

MR# AND THE SERIAL INTERFACE

When writing the memory array the MR# input

must be high. When writing the memory array the

SMT4004 cannot be in reset.

When reading the status registers or memory

array, the state of the MR# input is ignored.

When writing the configuration registers the default

requirement for MR# is for it to be asserted or low.

There is an option that allows this to be a ‘don’t care’

input; that is, the pin can be high or low and the

configuration registers can be written. [This option is

chosen on the Miscellaneous Settings tab of the

Windows GUI]

Device Identifier Bus Address R/W

D7 D6 D5 D4 D3 D2 D1 D0

Action

1 0 1 0 A2 A1 A0 1 Read Memory

1 0 1 0 A2 A1 A0 0 Write Memory

1 0 1 1 A2 A1 A0 1 Read Memory (alternate address)

1 0 1 1 A2 A1 A0 0 Write Memory (alternate address)

1 0 0 1 A2 A1 A0 1 Read Registers

1 0 0 1 A2 A1 A0 0 Write Registers

Table 1. Illustration of serial address bytes.

APPLICATIONS INFORMATION

(

CONTINUED

)

SMT4004

Summit Microelectronics, Inc 2049 4.0 3/04/02 27

10 0

1A

2

A

1

A

0W

A

C

K

A

2

A

1

A

0

D

2

D

1

D

0

D

5

D

4

D

3

D

7

D

6

A

7

A

6

A

5

A

4

A

3

SDA

A

C

K

A

C

K

S

T

O

P

S

T

A

R

T

Master

SMT4004

10 1

1

Optional Device

Type Identifier

Bus Address =

Address Pins Memory Address Location

Figure 16. Memory write sequence.

A

C

K

A

2

A

1

A

0

D

2

D

1

D

0

D

5

D

4

D

3

D

7

D

6

A

7

A

6

A

5

A

4

A

3

SDA

A

C

K

A

C

K

S

T

O

P

S

T

A

R

T

Master

SMT4004

10 01 A

2

A

1

A

0W10 0

1A

2

A

1

A

0R

S

T

A

R

T

A

C

K

N

A

C

K

10 1

1

Optional Device

Type Identifier

10 1

1

Optional Device

Type Identifier

Bus Address =

Address Pins Memory Address Location

Figure 17. Memory read sequence.

10

01

A

2

A

1

A

0W

A

C

K

C

2

C

1

C

0

D

2

D

1

D

0

D

5

D

4

D

3

D

7

D

6

11111

SDA

A

C

K

A

C

K

S

T

O

P

S

T

A

R

T

Master

SMT4004

Bus Address =

Address Pins

Configuration

Register

Address

Figure 18. Write configuration register sequence.

A

C

K

C

2

C

1

C

0

D

2

D

1

D

0

D

5

D

4

D

3

D

7

D

6

11111

SDA

A

C

K

N

A

C

K

S

T

O

P

S

T

A

R

T

Master

SMT4004

10

01

A

2

A

1

A

0W10

01

A

2

A

1

A

0R

S

T

A

R

T

A

C

K

Bus Address =

Address Pins

Configuration

Register

Address

Bus Address =

Address Pins

Figure 19. Read Configuration register or status register sequence.

APPLICATIONS INFORMATION

(

CONTINUED

)

SMT4004

Summit Microelectronics, Inc 2049 4.0 3/04/02 28

PROTOTYPING WITH THE SMT4004 WINDOWS

GUI SOFTWARE

For prototyping and device evaluation, use the

Windows Graphical User Interface (GUI) and

SMX3200 device programmer with the SMT4004. The

programming system is available from the Summit

website (www.summitmicro.com). Further explanation

of the 32 individual configuration registers and

associated GUI settings are included in Application

Note 22.

After installing and starting the interface, the screen

will display six different tabs. (Before proceeding, click

on the Read Config button or Load Defaults). Each tab

represents a group of functions and features that need

to be selected for the end application.

Power Managers, Resets and IRQ#s TAB

This screen allows the user to select any one of the

four managers and then configure its operation. The

required information for each manager is:

 Enable or disable the manager. If a manager is

disabled, OV must be disabled on that manager.

 Tracking Mode or Soft Start.

 Bus-Side Operation: adjust the UV and OV

thresholds enable their use individually.

 Card-Side Operation: adjust the UV1 and UV2

thresholds and enable the use of UV2.

 Turn off or select a QT threshold.

 Select the sources that can trigger an interrupt.

 Select the sources that can trigger a Reset.

Slew Rate, Timer and Circuit Breaker

 Select the VGATE slew rate for both power-on and

power-off.

 The Circuit breaker delay is the programmable

filter.

 The 300mV Trakker Action refers to the optional

actions that can be taken if a differential of more

than 300mV is detected by tracking managers.

 Select which manager can generate a

TRKR_IRQ#.

 Select the reset timeout period.

 Select both the LDO# and WDO# timer values.

Crowbar and Pin Polarity

 Select one or more Crowbar Source Enables.

 Select Crowbar pin function.

 Select “Active” pin polarity.

IRQ#, Circuit Breaker, OV Settings

These are important house keeping chores that

need to be selected.

Starting at the bottom:

 Configure the IRQ# options.

across the sense resistor that will be used to

determine an over-current condition.

 The last two boxes determine the action that is

taken if an over-current condition exists.

Miscellaneous Settings

 MRB (MR#), I2C power-On/Off Memory Address

Select and Bus Address Response all configure

the operation of the serial interface.

 Select Fault Latching Capability.

 Select whether the VO inputs need to be near 0V

before tracking commences. (Disable option)

Memory Array and Status Regs

The memory array function allows reading and

writing the array. The GUI screen displays an

‘address-relative’ bit map of the contents of the array.

This TAB provides access to the fault status

registers and the ability to clear them during debug.

APPLICATIONS INFORMATION

(

CONTINUED

)

SMT4004

Summit Microelectronics, Inc 2049 4.0 3/04/02 29

APPLICATIONS INFORMATION (CONTINUED)

USE A KELVIN CONNECTION FOR ACCURATE

CURRENT MEASUREMENT

High current measurements using a series resistor

can be very accurate when a Kelvin connection is

used between the resistor and the VI and CB inputs. A

Kelvin connection is a 4-terminal connection, usually

made to a 2-terminal device, separating the current

path through the resistor from the voltage drop across

the resistor. The sense points are located as

physically close to the resistor terminals as possible.

This eliminates inaccuracies that may be caused by

randomly placing the sense connection along the

power trace on the printed circuit board. Figure 20

illustrates the 4-wire Kelvin principle applied to a 2-

terminal surface mount sense resistor.

Current sense resistors are available from a

number of manufacturers in two basic styles: open air

and resistor chips. Open air resistors are metal strips

and are available in both leaded and surface mount

packages. Resistor chips are surface mount packages

and offer excellent thermal characteristics. Both styles

are available in resistance ranges from <1mΩ to 1Ω.

True 4-terminal sense resistors are available, but are

generally more expensive. Unless extreme precision is

required, the 2-terminal resistor is the economical

choice with PCB traces tapping off the trace at the

resistor ends to provide the 4-terminal Kelvin

connection.

The VI input with highest potential is effectively the

power supply pin for the SMT4004. This means there

will be additional current (max. 3mA) on this PCB

trace. Therefore, this sense resistor (RS) to VI trace

should be of sufficient size to eliminate any unwanted

voltage drop. For optimal performance the other three

RS/VI & RS/CB traces should be near equal length

and the sense resistor(s) should be as close to the

SMT4004 as possible.

POWER MOSFETS

Selection of MOSFET switches for the SMT4004

Tracker is a compromise between load regulation,

board area, and MOSFET cost. To obtain good load

regulation with low supply voltages, the MOSFET must

have a very low ON resistance (RDS(ON)).

SELECTING A MOSFET AND THE SENSE

RESISTOR VALUES FOR THE SMT4004.

The following is an example of how to determine

the MOSFET and Sense resistor values for a given

power supply.

For a 1.8V supply with a 10A maximum load

current, the load resistance is equivalent to 180mΩ. If

the total resistance of the sense resistor plus trace

resistance plus MOSFET ON (RDS(ON)) resistance is

9mΩ, the load regulation is approximately 5% for a

load change from 0A to 10A.

Assume the selected circuit breaker trip voltage is

25mV. If the voltage drop across the MOSFET is kept

below 25mV at maximum current, then a total drop of

50mV yields a load regulation of less than 3% with a

1.8V supply, and 1% with a 5V supply. Choosing a

suitable MOSFET is simply a matter of applying Ohm’s

law once the supply voltage, load current, and load

regulation requirements are known.

For the 1.8V & 10A example, first choose the

current sense resistor. A margin should be allowed;

therefore, set the trip current higher than the operating

current. For example, choosing 12.5A yields 25%

over-current and allows for the tolerances of the

resistor and trip voltage. With a nominal trip voltage of

25mV and a trip current of 12.5A, the current sense

resistor is 2mΩ. Therefore, the MOSFET RDS(ON) must

be below 7mΩ. Some low RDS(ON) MOSFETs are

shown in Table 2.

Supply

To MOSFET

Drain

High Current Path

Sense Resistor

Kelvin Connections

VI

CB

SMT4004

Copper

Trace

Copper

Trace

Figure 20. Typical Kelvin Connection

SMT4004

Summit Microelectronics, Inc 2049 4.0 3/04/02 30

PARALLELING MOSFETS REDUCES VOLTAGE

DROPS AND POWER DISSIPATION

When supply regulation is unacceptable due to high

RDS(ON), two or more MOSFETs may be wired in

parallel to lower the RDS(ON). For lower voltage

supplies with high current, such as a 1V supply

delivering 15A of load current, load regulation is

improved by using two or more MOSFETs in parallel.

The RDS(ON) is halved when two identical MOSFETs

are connected as in Figure 21. The MOSFET gates

must be connected with identical gate resistors (RGx)

as shown.

REMOTE SENSING

This technique can be used with power supplies

that have Sense inputs. Remote sensing eliminates

the effect of the current sense resistor voltage drop.

With this arrangement (Figure 22) only the MOSFET

RDS(ON) must be considered and a wider selection of

devices can be used.

SMT4004

RG1

10Ω

VI1

CB1

VGATE1

VO1

RG2

10Ω

Q1

Q2

VIN VOUT

to Application Circuit

RS

Figure 21. Parallel MOSFET connections

SMT4004

RG1

10Ω

VI1

CB1

VGATE1

VO1

Q1

DC-to-DC

Converter

VOUT

to Application Circuit

RS

+VSENSE

+VFORCE

-VSENSE

-VFORCE

5x

220µF

100µF

PGND

Figure 22. Remote sense connections

Table 2. Available low RDS(ON) power MOSFETs

Part Number Manufacturer V(BR)DSS R

DS(ON) @ VGS = 10V ID@100°C Package

IRF3703 International Rectifier 30V

2.8mΩ max. 180A Super D2

IRF1404S International Rectifier 40V 4mΩ max. 162A D2PAK

IRF6603 International Rectifier 30V

3.9mΩ max. 22A DirectFET™

IRL3803S International Rectifier 30V 6mΩ max. 140A D2PAK

HUF76145S3S Fairchild Semiconductor 30V 4.5mΩ max. 75A D2PAK

HUF76145S3S Fairchild Semiconductor 30V 5.5mΩ max. 75A D2PAK

STV160NF03L ST Microelectronics 30V 2.8mΩ max. 113A Power SO-10

STB80NF03L-04 ST Microelectronics 30V 4mΩ max. 56A D2PAK

SUB75N03-04 Vishay Siliconix 30V 4mΩ max. 75A TO-263

SUB75N04-05L Vishay Siliconix 40V 5.5mΩ max. 55A TO-263

APPLICATIONS INFORMATION

(

CONTINUED

)

SMT4004

2049 4.0 3/04/02 31

DDD

S

D

SS

G

756 8

213

4IRF7805

SMT4004

A0

A1

A2

Memory Address = A2

Register Address = 92

SCL

SDA

DDD

S

D

SS

G

756 8

213

4IRF7805

bi

in

out

330Ω

Watch_Long_Dog_In

in

10Ω

adjust value for current trip

RS1 0.002Ω

adjust value for current trip

RS2 0.002Ω

10Ω

D

S

G

2

3

1

IRL3803S

D

S

G

2

3

1

IRL3803S

VGATE3

CB3

VI3

VO3

LT1431

3

4

1

2

7

8

56

V+

RTOP

COMP

COLLECTOR

RMID

REF

GND-S GND-F

6.81KΩ

2.21KΩ

10Ω

360Ω

10Ω

0.1µF

DDD

S

D

SS

G

756 8

213

4IRF7805

10Ω

RS4 0.002Ω

adjust value for current trip

RS3 0.002Ω

adjust value for current trip

VGATE4

CB4

VI4

VGATE1

CB1

VI1

VO1

VGATE2

CB2

VI2

VO2

in

3.7V

1.8V

WLDI

WDO#

LDO#

ENABLE

PWR_ON

DGND

FORCE_SD

PGND

AGND

PGND

UV_OVERRIDE

in

out

Force_Shutdown_ In in

in

Watch_Dog_Out

Long_Dog_Out

SEAT_1

SEAT_2 SEATED2#

SEATED1#

VREFH1

VREFL1

VOUT1

5.1V

2.5V

+5V (Vcc)

+2.5V

+1.8V

+3.3V

VDD

SCL

SDA

A0

A1

A2 GND

Vcc

14

11

1

2

3

12

13

7

10

9

10KΩ

2plcs

330Ω

Out

RST1#

RST2#

RST3#

RST4#

CROWBAR

Out

5V_RST

3.3V_RST

2.5V_RST

1.8V_RST

NC

SMP9210

2_W ire_Data

2_W ire_Clock

SCL

SDA

SCL

SDA

1

2

3

8

10

11

12

14

13

15

16

19

32 21

17

18

2922

43

44

45

46

47

48

27

33

24

3839 3035 34

40 36 31

37

41 20

VGG_CAP

1uF

28

10KΩ

+5.1V or

VDD_CAP

10KΩ

+5.1V or

VDD_CAP

IRQ_CLR#

MR# In Manual_Reset

In Interrupt_Clear

5

6

CBFAULT

HEALTHY#

TRKR_IRQ#

IRQ#

Out

Current_Trip

Pwr_Sys_OK

TRKR_IRQ

PWR_IRQ

7

9

26

25

10KΩ

+5.1V or

VDD_CAP

10uF

42

VO4

23

4

1.25VREF

0.1µF

Figure 23 – IBMTM PowerNP NP4GS3 network processor reference platform. (Not all connections are

shown. Please contact IBM

TM

for further information).

APPLICATIONS INFORMATION

(

CONTINUED

)

SMT4004

Summit Microelectronics, Inc 2049 4.0 3/04/02 32

DEVELOPMENT HARDWARE AND SOFTWARE

The end user can obtain the Summit SMX3200

programming system for device prototype

development. The SMX3200 system consists of a

programming Dongle, cable and Windows GUI

software. It can be ordered on the website or from a

local Summit representative. The latest revisions of all

software and an Application Brief describing the

SMX3200 is available from the website

(www.summitmicro.com).

The SMX3200 programming Dongle/cable

interfaces directly between a PC’s parallel port and the

target application. The SMT4004 is then configured

on-screen via an intuitive graphical user interface

employing drop-down menus.

The Windows GUI software will generate the data

and send it in I2C serial bus format so that it can be

directly downloaded to the SMT4004 via the

programming Dongle and cable. An example of the

connection interface is shown in Figure 24.

When design prototyping is complete, the software

can generate a HEX data file that should be

transmitted to Summit for design verification and

approval. Summit will then assign a unique customer

ID to the HEX code and program production devices.

The devices are marked with the customer ID as a

part number suffix per the marking specification shown

at the end of the data sheet.

Please be aware that the end user can always

reconfigure a product that has been programmed by

Summit, however, doing so does not allow the part to

be fully tested with the new configuration register

settings.

Pin 9, 5V

Pin 7, 10V

Pin 5, Reserved

Pin 3, GND

Pin 1, GND

Pin 6, MR#

Pin 4, SDA

Pin 2, SCL

Pin 8, Reserved

Pin 10, Reserved

Top view of straight 0.1" x 0.1 closed-side

connector. SMX3200 interface cable connector.

9

7

5

3

1

10

8

6

4

2

SMT4004

SDA

SCL

VDD_CAP

GND

0.1µF

Positive

Supply

Common

Ground

MR#

Figure 24 SMX3200 Programmer I2C serial bus connections to program the SMT4004.

SMT4004

Summit Microelectronics, Inc 2049 4.0 3/04/02 33

DEFAULT CONFIGURATION REGISTER SETTINGS – SMT4004F-017

retsigeRstnetnoCxeH:saderugifnoC

00R4BediS-suBTIVP-V5.4ottesdlohserhTVU1IV

VU

10R96ediS-suB2IVottesdlohserhTVUV0.3TIVP-

VU

20R14ediS-suB3IVottesdlohserhTVUV2.2TIVP-

VU

30R82ediS-suB4IVottesdlohserhTVUV7.1TIVP-

VU

40R06VO,delbaneVOdnaVU1IVediS-suBdlohserhTV5.5ottesTIVP-

VO

50R06ediS-suBVO,delbaneVOdnaVU2IVdlohserhTV6.3tatesTIVP-

VO

60R26ediS-suBVO,delbaneVOdnaVU3IVdlohserhTV8.2tatesTIVP-

VO

70R76ediS-suBVO,delbaneVOdnaVU4IVdlohserhTV5.2tatesTIVP-

VO

80R9BdlohserhT1OVediS-draC4ottesV6.TOVP-

1VU

90RE6dlohserhT2OVediS-draCottesV1.3TOVP-

1VU

A0R64dlohserhT3OVediS-draCottesV3.2TOVP-

1VU

B0RD2dlohserhT4OVediS-draCottesV8.1TOVP-

1VU

C0R2AediS-draC1OV2dlohserhTottesV5.4TOVP-

2VU

D0R3A2dlohserhT2OVediS-draCottesV0.3TOVP-

2VU

E0R4A2dlohserhT3OVediS-draCottesV2.2TOVP-

2VU

F0R6A2dlohserhT4OVediS-draCottesV7.1TOVP-

2VU

01R500101,sesserddadesaibnipotsdnopseR

NIB

ffodnanoetarwelss/V052,

11RDDBCroftpecxEsecruos#TSRllaelbanE

21RDDBCroftpecxEsecruos#TSRllaelbanE

31RFFsecruos#QRIllaelbanE

41RFFsecruos#QRIllaelbanE

51RF6 Vm52ottestnioppirTBC,secruosllaelbane,yaled#QRIotROPsm008

81R00etoN-1/I,delbasidgnihctaLtluaF,margorPotderiuqeR#RM

2

ffO/nOrewoPC

nwoDtuhSdecroFasesuaCVO,delbasiD

91R18ylnopirtkciuQdnatupnilaunamnorabworCelbanE

A1RAAstiucricreganamllapirtkciuQVm001elbanE

B1R20sµ001yaledtnerrucrevo,wolevitcastuptuollA

C1R6Fsm0061godhctaW,sm0023godgnoL,sm002teseR

Note 1/ - Bits D5, D6 and D7 are reserved bits; therefore the contents of R18 may not be 00h.

Application Note 22 contains a complete description of the default settings and each of the

32 individual Configuration Registers. The default configuration does not include

Registers R16 and R17 (virtual addresses) or R1D, R1E and R1F (Fault Status Registers).

SMT4004

Summit Microelectronics, Inc 2049 4.0 3/04/02 34

PACKAGE

AB

Pin 1

Indicator

Inches

(Millimeters)

0.002 - 0.006

(0.05-0.15)

MAX.

0.047

(1.2)

0.037 - 0.041

0.95 - 1.05

0.018 - 0.030

(0.45 - 0.75)

0.039

(1.00)

0.02

(0.5) BSC

0.007 - 0.011

(0.17 - 0.27)

D E T A IL " A "

DETAIL "B"

(B)

(A)

0.354

(9.00) BSC

0.276

(7.00) BSC (B)

48 PIN TQFP PACKAGE

0o Min to

7o Max

Ref Jedec MS-026

Ref

SMT4004

Summit Microelectronics, Inc 2049 4.0 3/04/02 35

PART MARKING

SUMMIT

SMT4004F

AYYWW

Pin 1

Annn

Summit Part Number

Date Code (YYW W )

Part Number suffix

Product Tracking Code

(Summit use)

Lot tracking code (Summit use)

Drawing not to scale

xx Status Tracking Code

(Blank, MS, ES, 01, 02,...)

(Summit Use)

ORDERING INFORMATION

SMT4004 F

Summit Part Number Package

F = 48 Pin TQFP

nnn Part Number Suffix

NOTICE

SUMMIT Microelectronics, Inc. reserves the right to make changes to the products contained in this publication in order to improve design,

performance or reliability. SUMMIT Microelectronics, Inc. assumes no responsibility for the use of any circuits described herein, conveys no license

under any patent or other right, and makes no representation that the circuits are free of patent infringement. Charts and schedules contained

herein reflect representative operating parameters, and may vary depending upon a user’s specific application. While the information in this

publication has been carefully checked, SUMMIT Microelectronics, Inc. shall not be liable for any damages arising as a result of any error or

omission.

SUMMIT Microelectronics, Inc. does not recommend the use of any of its products in life support or aviation applications where the failure or

malfunction of the product can reasonably be expected to cause any failure of either system or to significantly affect their sa fety or effectiveness.

Products are not authorized for u se in such applications unless SUMMIT Micro electronics, Inc. receives written assurance s, to its satisfaction, that:

(a) the risk of injury or damage has been minimized; (b) the user assumes all such risks; and (c) potential liability of SUMMIT Mi croelectronic s, Inc.

is adequately protected under the circumstances.

Revision 4.0 - This document supersedes all previous versions and covers Status Tracking Codes up to 10 and Windows GUI re vision 2.39.3 and

later. Please check the Summit Microelectronics, Inc. web site at www.summitmicro.com for data sheet updates.

I2C is a trademark of Philips Corporation.

IBM, the IBM logo, PowerPC, and PowerPC 750 are trademarks of International Business Machines in the United States and/or other countries.