IRF240 - Intersil Corporation

File Number

1584.3

CAUTION: These devices are sensitive to electrostatic discharge; follow proper ESD Handling Procedures.

IRF240

18A, 200V, 0.180 Ohm, N-Channel

Power MOSFET

This N-Channel enhancement mode silicon gate power ﬁeld

effect transistor is an advanced power MOSFETs designed,

tested, and guaranteed to withstand a speciﬁed level of

energy in the breakdown avalanche mode of operation. All of

these power MOSFETs are designed for applications such

as switching regulators, switching converters, motor drivers,

relay drivers, and drivers for high power bipolar switching

transistors requiring high speed and low gate drive power.

These types can be operated directly from integrated

circuits.

Formerly developmental type TA17422.

Features

• 18A, 200V

•r

DS(ON) = 0.180Ω

• Single Pulse Avalanche Energy Rated

• SOA is Power Dissipation Limited

• Nanosecond Switching Speeds

• Linear Transfer Characteristics

• High Input Impedance

• Related Literature

- TB334, “Guidelines for Soldering Surface Mount

Components to PC Boards”

Symbol

Packaging

JEDEC TO-204AE

TOP VIEW

Ordering Information

PART NUMBER PACKAGE BRAND

IRF240 TO-204AE IRF240

NOTE: When ordering, include the entire part number. G

DRAIN

(FLANGE)

SOURCE (PIN 2)

GATE (PIN 1)

Data Sheet March 1999

Absolute Maximum Ratings TC = 25oC, Unless Otherwise Speciﬁed

IRF240 UNITS

Drain to Source Voltage (Note 1). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . VDS 200 V

Drain to Gate Voltage (RGS = 20kΩ) (Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . VDGR 200 V

Continuous Drain Current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ID18 A

TC = 100oC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ID11 A

Pulsed Drain Current (Note 3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .IDM 72 A

Gate to Source Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . VGS ±20 V

Maximum Power Dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . PD125 W

Linear Derating Factor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.0 W/oC

Single Pulse Avalanche Energy Rating (Note 4) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . EAS 580 mJ

Operating and Storage Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . TJ, TSTG -55 to 150 oC

Maximum Temperature for Soldering

Leads at 0.063in (1.6mm) from Case for 10s. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .TL

Package Body for 10s, See Techbrief 334 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Tpkg 300

260

CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operationofthe

device at these or any other conditions above those indicated in the operational sections of this speciﬁcation is not implied.

NOTE:

1. TJ = 25oC to 125oC.

Electrical Speciﬁcations TC = 25oC, Unless Otherwise Speciﬁed

PARAMETER SYMBOL TEST CONDITIONS MIN TYP MAX UNITS

Drain to Source Breakdown Voltage BVDSS VGS = 0V, ID = 250µA (Figure 10) 200 - - V

Gate to Threshold Voltage VGS(TH) VGS = VDS, ID = 250µA 2.0 - 4.0 V

Zero Gate Voltage Drain Current IDSS VDS = Rated BVDSS, VGS = 0V - - 25 µA

VDS = 0.8 x Rated BVDSS, VGS = 0V, TJ = 125oC - - 250 µA

On-State Drain Current (Note 2) ID(ON) VDS > ID(ON) x rDS(ON)MAX, VGS = 10V 18 - - A

Gate to Source Leakage IGSS VGS = ±20V - - ±100 nA

Drain to Source On Resistance rDS(ON) VGS = 10V, ID = 10A (Figures 8, 9) - 0.14 0.180 Ω

Forward Transconductance (Note 2) gfs VDS = 10V, ID = 11V (Figure 12) 6.7 9.0 - S

Turn-On Delay Time tD(ON) VDD = 100V, ID≈ 18A, RG = 9.1Ω, RL = 5.3Ω

(Figures 17, 18) MOSFET Switching Times are

Essentially Independent of Operating Temperature

-1630ns

Rise Time tr-2760ns

Turn-Off Delay Time tD(OFF) -4080ns

Fall Time tf-3160ns

Total Gate Charge

(Gate to Source + Gate to Drain) QgVGS = 10V, ID = 18A, VDS = 0.8 x Rated BVDSS,

Ig(REF) = 1.5mA (Figures 14, 19, 20) Gate Charge is

Essentially Independent of Operating Temperature

-4360nC

Gate to Source Charge Qgs -8-nC

Gate to Drain “Miller” Charge Qgd -27- nC

Input Capacitance CISS VGS = 0V, VDS = 25V, f = 1.0MHz (Figure 11) - 1275 - pF

Output Capacitance COSS - 500 - pF

Reverse-Transfer Capacitance CRSS - 160 - pF

Internal Drain Inductance LDMeasured between the

Contact Screw on Header

that is Closer to Source

and Gate Pins and Center

of Die

Modified MOSFET

Symbol Showing the

Internal Devices

Inductances

- 5.0 - nH

Internal Source Inductance LSMeasured from the

Source Lead, 6mm

(0.25in) from Header to

Source Bonding Pad

- 12.5 - nH

Thermal Resistance Junction to Case RθJC - - 1.0 oC/W

Thermal Resistance Junction to Ambient RθJA Free Air Operation - - 30 oC/W

IRF240

Source to Drain Diode Speciﬁcations

PARAMETER SYMBOL TEST CONDITIONS MIN TYP MAX UNITS

Continuous Source to Drain Current ISD Modified MOSFET

Symbol Showing the

Integral Reverse P-N

Junction Diode

- - 18 A

Pulse Source to Drain Current

(Note 3) ISM - - 72 A

Source to Drain Diode Voltage (Note 2) VSD TJ = 25oC, ISD = 18A, VGS = 0V (Figure 13) - - 2.0 V

Reverse Recovery Time trr TJ = 150oC, ISD = 18A, dISD/dt = 100A/µs - 650 - ns

Reverse Recovered Charge QRR TJ = 150oC, ISD = 18A, dISD/dt = 100A/µs - 4.1 - µC

NOTES:

2. Pulse Test: Pulse width ≤ 300µs, duty cycle ≤ 2%.

3. Repetitive Rating: Pulse width limited by Max junction temperature. See Transient Thermal Impedance curve (Figure 3).

4. VDD = 50V, starting TJ = 25oC, L = 2.7mH, RG = 25Ω, peak IAS = 9A. See Figures 15 and 16.

Typical Performance Curves

Unless Otherwise Speciﬁed

FIGURE 1. NORMALIZED POWER DISSIPATION vs CASE

TEMPERATURE FIGURE 2. MAXIMUM CONTINUOUS DRAIN CURRENT vs

CASE TEMPERATURE

FIGURE 3. NORMALIZED MAXIMUM TRANSIENT THERMAL IMPEDANCE

0 50 100 150

TC, CASE TEMPERATURE (oC)

POWER DISSIPATION MULTIPLIER

0.2

0.4

0.6

0.8

1.0

1.2

TC, CASE TEMPERATURE (oC)

50 75 10025 150

ID, DRAIN CURRENT (A)

125

ZθJC, THERMAL IMPEDANCE

1.0

0.1

10-2

10-5 10-4 10-3 0.1 1 10

t1, RECTANGULAR PULSE DURATION (s)

0.01

0.02

0.01

0.05

0.1

0.2

0.5

DUTY FACTOR: D = t1/t2

NOTES:

PER UNIT BASE =

TJM - TC= PDM x ZθJC (t)

PDM

t1t2

RθJC = 1.0oCW

SINGLE PULSE

IRF240

FIGURE 4. FORWARD BIAS SAFE OPERATING AREA FIGURE 5. OUTPUT CHARACTERISTICS

FIGURE 6. SATURATION CHARACTERISTICS FIGURE 7. TRANSFER CHARACTERISTICS

NOTE: Heating effect of 2µs pulse is minimal.

FIGURE 8. DRAIN TO SOURCE ON RESISTANCE vs GATE

VOLTAGE AND DRAIN CURRENT FIGURE 9. NORMALIZED DRAIN TO SOURCE ON

RESISTANCE vs JUNCTION TEMPERATURE

Typical Performance Curves

Unless Otherwise Speciﬁed (Continued)

1.0 10 102

0.1

ID, DRAIN CURRENT (A)

VDS, DRAIN TO SOURCE VOLTAGE (V)

100

TJ = MAX RATED

SINGLE PULSE

TC = 25oC

1ms

10ms

100ms

100µs

10µs

OPERATION IN THIS

REGION IS LIMITED

BY rDS(ON)

103

VDS, DRAIN TO SOURCE VOLTAGE (V)

10 20 30 400

ID, DRAIN CURRENT (A)

10V

VGS = 6V

80µs PULSE TEST

VDS, DRAIN TO SOURCE VOLTAGE (V)

123405

ID, DRAIN CURRENT (A)

80µs PULSE TEST

VGS = 4V

VGS = 7V

VGS = 6V

VGS = 10V

VGS = 5V

VGS = 9V

VGS = 8V

ID, DRAIN CURRENT (A)

VSD, GATE TO SOURCE VOLTAGE (V)

002 10

80µs PULSE TEST

VDS > ID(ON) x RDS(ON)MAX

TJ = 125oC

TJ = 25oC

TJ = -55oC

ID, DRAIN CURRENT (A)

200

0.5

0.4

rDS(ON), DRAIN TO SOURCE

0.3

ON RESISTANCE (Ω)

0.2

0.1

60 80

VGS = 20V

VGS = 10V

80µs PULSE TEST

100 0 80 120-40 40 160

2.5

1.5

0.5

NORMALIZED DRAIN TO SOURCE

2.0

1.0

ON RESISTANCE

TJ, JUNCTION TEMPERATURE (oC)

ID = 18A

VGS = 10V

IRF240

FIGURE 10. NORMALIZED DRAIN TO SOURCE BREAKDOWN

VOLTAGE vs JUNCTION TEMPERATURE FIGURE 11. CAPACITANCE vs DRAIN TO SOURCE VOLTAGE

FIGURE 12. TRANSCONDUCTANCE vs DRAIN CURRENT FIGURE 13. SOURCE TO DRAIN DIODE VOLTAGE

FIGURE 14. GATE TO SOURCE VOLTAGE vs GATE CHARGE

Typical Performance Curves

Unless Otherwise Speciﬁed (Continued)

1.25

1.05

0.85

TJ, JUNCTION TEMPERATURE (oC)

NORMALIZED DRAIN TO SOURCE

1.15

0.95

0.75

BREAKDOWN VOLTAGE

0 80 120-40 40 160

ID = 250µA

010

C, CAPACITANCE (pF)

VDS, DRAIN TO SOURCE VOLTAGE (V)

2000

1800

1200

800

400

020 30

VGS = 0V, f = 1MHz

CISS = CGS + CGD

CRSS = CGD

COSS ≈ CDS + CGS

CISS

COSS

CRSS

40 50

ID, DRAIN CURRENT (A)

8162432040

19.0

15.2

11.4

7.6

gfs, TRANSCONDUCTANCE (S)

3.8

80µs PULSE TEST

TJ = 25oC

TJ = -55oC

TJ = 125oC

ISD, SOURCE TO DRAIN CURRENT (A)

VSD, SOURCE TO DRAIN VOLTAGE (V)

10 0.4 0.8 1.2 2.0

TJ = 25oC

TJ = 150oC

1.6

Qg, TOTAL GATE CHARGE (nC)

12 24 36 48060

VGS, GATE TO SOURCE VOLTAGE (V)

ID = 18A

VDS = 160V

VDS = 100V

VDS = 40V

IRF240

Test Circuits and Waveforms

FIGURE 15. UNCLAMPED ENERGY TEST CIRCUIT FIGURE 16. UNCLAMPED ENERGY WAVEFORMS

FIGURE 17. SWITCHING TIME TEST CIRCUIT FIGURE 18. RESISTIVE SWITCHING WAVEFORMS

FIGURE 19. GATE CHARGE TEST CIRCUIT FIGURE 20. GATE CHARGE WAVEFORMS

VGS

0.01Ω

IAS

VDS

VDD

DUT

VARY tP TO OBTAIN

REQUIRED PEAK IAS

VDD

VDS

BVDSS

IAS

tAV

VGS

DUT

-VDD

tON

td(ON)

90%

10%

VDS 90%

10%

td(OFF)

tOFF

90%

50%

10% PULSE WIDTH

VGS

0.3µF

12V

BATTERY 50kΩ

VDS

DUT

Ig(REF)

(ISOLATED

VDS

0.2µF

CURRENT

REGULATOR

ID CURRENT

SAMPLING

IG CURRENT

SAMPLING

SUPPLY)

RESISTOR RESISTOR

SAME TYPE

AS DUT Qg(TOT)

Qgd

Qgs

VDS

VGS

VDD

Ig(REF)

IRF240

All Intersil semiconductor products are manufactured, assembled and tested under ISO9000 quality systems certiﬁcation.

Intersil semiconductor products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design and/or specifications at any time with-

out notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and

reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result

from its use. No license is gr anted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.

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IRF240