ESMT
M13S5121632A
Elite Semiconductor Memory Technology Inc. Publication Date : Oct. 2008
Revision : 1.0 1/47
DDR SDRAM 8M x 16 Bit x 4 Banks
Double Data Rate SDRAM
Features
z JEDEC Standard
z Internal pipelined double-data-rate architecture, two data access per clock cycle
z Bi-directional data strobe (DQS)
z On-chip DLL
z Differential clock inputs (CLK and CLK )
z DLL aligns DQ and DQS transition with CLK transition
z Quad bank operation
z CAS Latency : 2; 2.5; 3
z Burst Type : Sequential and Interleave
z Burst Length : 2, 4, 8
z All inputs except data & DM are sampled at the rising edge of the system clock(CLK)
z Data I/O transitions on both edges of data strobe (DQS)
z DQS is edge-aligned with data for reads; center-aligned with data for WRITE
z Data mask (DM) for write masking only
z VDD, VDDQ = 2.5V ~ 2.7V
z Auto & Self refresh
z 7.8us refresh interval (64ms refresh period, 8K cycle)
z SSTL-2 I/O interface
z 66pin TSOPII package
Ordering information:
PRODUCT ID MAX FREQ VDD PACKAGE COMMENTS
M13S5121632A -5TG 200MHz 2.5V TSOPII Pb-free
ESMT
M13S5121632A
Elite Semiconductor Memory Technology Inc. Publication Date : Oct. 2008
Revision : 1.0 2/47
Functional Block Diagram
DLL
CS
Memory
Array
Bank#0
I/O Buffer DQS Buffer
Memory
Array
Bank#1
Memory
Array
Bank#2
Memory
Array
Bank#3
Mode Register
Control Circuitry
Address Buffer
Clock Buffer
Control Signal Butter
RAS CAS WE DM
CLK CKE
CLK
BA0,1A0-12
DQ0 - 15 UDQS, LDQS
ESMT
M13S5121632A
Elite Semiconductor Memory Technology Inc. Publication Date : Oct. 2008
Revision : 1.0 3/47
Pin Arrangement
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
66 PIN TSOP(II)
(400mil x 875mil)
(0.65 mm PIN PITCH)
VDD
DQ 0
VDD Q
DQ 1
DQ 2
VSS Q
DQ 3
DQ 4
VDD Q
DQ 5
DQ 6
VSS Q
DQ 7
NC
VDD Q
LD QS
NC
VDD
NC
LD M
WE
CAS
RAS
CS
NC
BA0
BA1
A10/AP
A0
A1
A2
A3
VDD
VSS
DQ15
VSS Q
DQ14
DQ13
VDD Q
DQ12
DQ11
VSS Q
DQ10
DQ9
VDD Q
DQ8
NC
VSS Q
UDQS
NC
VRE F
VSS
UDM
CLK
CLK
CKE
NC
A12
A11
A9
A8
A7
A6
A5
A4
VSS
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
x16 x16
Pin Description
Pin Name Function Pin Name Function
A0~A12,
BA0,BA1
Address inputs
- Row address A0~A12
- Column address A0~ A9
A10/AP : AUTO Precharge
BA0, BA1 : Bank selects (4 Banks)
LDM, UDM
DM is an input mask signal for write
data. LDM corresponds to the data
on DQ0~DQ7; UDM correspond to
the data on DQ8~DQ15.
DQ0~DQ15 Data-in/Data-out CLK, CLK Clock input
RAS Row address strobe CKE Clock enable
CAS Column address strobe CS Chip select
WE Write enable VDDQ Supply Voltage for GDQ
VSS Ground VSSQ Ground for DQ
VDD Power VREF Reference Voltage for SSTL-2
LDQS, UDQS
Bi-directional Data Strobe. LDQS
corresponds to the data on DQ0~DQ7;
UDQS correspond to the data on
DQ8~DQ15.
NC No connection
ESMT
M13S5121632A
Elite Semiconductor Memory Technology Inc. Publication Date : Oct. 2008
Revision : 1.0 4/47
Absolute Maximum Rating
Parameter Symbol Value Unit
Voltage on any pin relative to VSS V
IN, VOUT -0.5 ~ VDDQ + 0.5 V
Voltage on VDD supply relative to VSS V
DD -0.5 ~ 3.7 V
Voltage on VDDQ supply relative to VSSQ V
DDQ -0.5 ~ 3.7 V
Storage temperature TSTG -55 ~ +150 C°
Power dissipation PD 1500 mW
Short circuit current IOS 50 mA
Note : Permanent device damage may occur if ABSOLUTE MAXIMUM RATINGS are exceeded.
Functional operation should be restricted to recommend operation condition.
Exposure to higher than recommended voltage for extended periods of time could affect device reliability.
DC Operation Condition & Specifications
DC Operation Condition
Recommended operating conditions (Voltage reference to VSS = 0V, TA = 0 to 70 C°)
Parameter Symbol Min Max Unit Note
Supply voltage VDD 2.5 2.7 V
I/O Supply voltage VDDQ 2.5 2.7 V
I/O Reference voltage VREF 0.49*VDDQ 0.51*VDDQ V 1
I/O Termination voltage (system) VTT V
REF - 0.04 VREF + 0.04 V 2
Input logic high voltage VIH (DC) VREF + 0.15 VDDQ + 0.3 V
Input logic low voltage VIL (DC) -0.3 VREF - 0.15 V
Input Voltage Level, CLK and CLK inputs VIN (DC) -0.3 VDDQ + 0.3 V
Input Differential Voltage, CLK and CLK inputs VID (DC) 0.36 VDDQ + 0.6 V 3
Input leakage current II -2 2
μA
Output leakage current IOZ -5 5
μA
Output High Current (Normal strength driver)
(VOUT =VDDQ-0.373V, min VREF, min VTT) IOH -16.2 mA
Output Low Current (Normal strength driver)
(VOUT = 0.373V) IOL +16.2 mA
Notes 1. VREF is expected to be equal to 0.5* VDDQ of the transmitting device, and to track variations in the DC level of the same.
Peak-to-peak noise on VREF may not exceed 2% of the DC value.
2. VTT is not applied directly to the device. VTT is system supply for signal termination resistors, is expected to be set equal
to VREF, and must track variations in the DC level of VREF .
3. VID is the magnitude of the difference between the input level on CLK and the input level on CLK .
ESMT
M13S5121632A
Elite Semiconductor Memory Technology Inc. Publication Date : Oct. 2008
Revision : 1.0 5/47
DC Specifications
Version
Parameter Symbol Test Condition -5 Unit Note
Operation Current
(One Bank Active) IDD0 tRC = tRC (min), tCK = tCK (min), Active – Precharge 180 mA
Operation Current
(One Bank Active) IDD1 Burst Length = 2, tRC = tRC (min), CL= 2.5,
IOUT = 0mA, Active-Read- Precharge 210 mA
Precharge Power-down
Standby Current IDD2P CKE VIL(max), tCK = tCK (min), All banks idle 10 mA
Idle Standby Current IDD2N CKE VIH(min), CS V
IH(min), tCK = tCK (min) 55 mA
Active Power-down
Standby Current IDD3P All banks ACT, CKE
VIL(max), tCK = tCK (min) 45 mA
Active Standby Current IDD3N One bank; Active-Precharge, tRC = tRAS(max),
tCK = tCK (min) 60 mA
Operation Current (Read) IDD4R Burst Length = 2, CL= 2.5, tCK = tCK (min), IOUT = 0 mA 460 mA
Operation Current (Write) IDD4W Burst Length = 2, CL= 2.5, tCK = tCK (min) 360 mA
Auto Refresh Current IDD5 tRC t
RFC(min) 290 mA
Self Refresh Current IDD6 CKE 0.2V 6 mA 1
Operation Current
(Four Bank Operation) IDD7
Four bank interleaving with BL=4, tRC = tRC (min),
burst mode; Read with auto precharge;
Address and control inputs on NOP edge are not
changing. IOUT = 0 mA
630 mA
Note 1. Enable on-chip refresh and address counters.
AC Operation Conditions & Timing Specification
AC Operation Conditions
Parameter Symbol Min Max Unit Note
Input High (Logic 1) Voltage, DQ, DQS and DM signals VIH(AC) VREF + 0.31 V
Input Low (Logic 0) Voltage, DQ, DQS and DM signals VIL(AC) VREF - 0.31 V
Input Different Voltage, CLK and CLK inputs VID(AC) 0.7 VDDQ+0.6 V 1
Input Crossing Point Voltage, CLK and CLK inputs VIX(AC) 0.5*VDDQ-0.2 0.5*VDDQ+0.2 V 2
Note 1. VID is the magnitude of the difference between the input level on CLK and the input on CLK .
2. The value of VIX is expected to equal 0.5*VDDQ of the transmitting device and must track variations in the DC level of the
same.
Input / Output Capacitance
(VDD = 2.5V~2.7V, VDDQ = 2.5V~2.7V, TA = 25 C° , f = 1MHz)
Parameter Symbol Min Max Unit
Input capacitance
(A0~A11, BA0~BA1, CKE, CS , RAS , CAS , WE ) CIN1 2.0 3.5 pF
Input capacitance (CLK, CLK ) CIN2 2.0 3.5 pF
Data & DQS input/output capacitance COUT 4.0 5.0 pF
Input capacitance (DM) CIN3 4.0 5.0 pF
ESMT
M13S5121632A
Elite Semiconductor Memory Technology Inc. Publication Date : Oct. 2008
Revision : 1.0 6/47
AC Operating Test Conditions
Parameter Value Unit
Input reference voltage for clock (VREF) 0.5*VDDQ V
Input signal maximum peak swing 1.5 V
Input signal minimum slew rate 1.0 V/ns
Input levels (VIH/VIL) VREF+0.31/VREF-0.31 V
Input timing measurement reference level VREF V
Output timing reference level VTT V
AC Timing Parameter & Specifications
(VDD = 2.5V~2.7V, VDDQ= 2.5V~2.7V, TA =0 C°~ 70C°)
-5
Parameter Symbol
min max
Unit Note
CL2 7.5 13
CL2.5 6.0 13
Clock Period
CL3
tCK
5.0 10
ns
Access time from CLK/ CLK tAC -0.7 +0.7
ns
CLK high-level width tCH 0.45 0.55
tCK
CLK low-level width tCL 0.45 0.55
tCK
Data strobe edge to clock edge tDQSCK -0.6 +0.6
ns
Clock to first rising edge of DQS delay tDQSS 0.75 1.25
tCK
Data-in and DM setup time (to DQS) tDS 0.5 -
ns
Data-in and DM hold time (to DQS) tDH 0.5 -
ns
DQ and DM input pulse width (for each
input) tDIPW 1.75 -
ns
Input setup time tIS 0.9 -
ns 5
Input hold time tIH 0.9 -
ns 5
DQS input high pulse width tDQSH 0.35 -
tCK
DQS input low pulse width tDQSL 0.35 -
tCK
DQS falling edge to CLK rising-setup time tDSS 0.2 -
tCK
DQS falling edge from CLK rising-hold time tDSH 0.2 -
tCK
Data strobe edge to output data edge tDQSQ - 0.40 ns
Data-out high-impedance window from
CLK/ CLK tHZ -0.7 +0.7 ns 1
Data-out low-impedance window from
CLK/ CLK tLZ -0.7 +0.7 ns 1
ESMT
M13S5121632A
Elite Semiconductor Memory Technology Inc. Publication Date : Oct. 2008
Revision : 1.0 7/47
AC Timing Parameter & Specifications-continued
-5
Parameter Symbol
min max Unit Note
Half Clock Period tHP tCLmin or tCHmin - ns
DQ-DQS output hold time tQH tHP-tQHS - ns
Data hold skew factor tQHS - 0.5 ns
ACTIVE to PRECHARGE command tRAS 40 70K ns
Row Cycle Time tRC 55 - ns
AUTO REFRESH Row Cycle Time tRFC 70 - ns
ACTIVE to READ,WRITE delay tRCD 15 - ns
PRECHARGE command period tRP 15 - ns
ACTIVE bank A to ACTIVE bank B
command tRRD 10 - ns
Write recovery time tWR 15 - ns
Write data in to READ command delay tWTR 2 - tCK
Average periodic refresh interval tREFI - 7.8 us 4
Write preamble tWPRE 0.25 - tCK 3
Write postamble tWPST 0.4 0.6 tCK 2
DQS read preamble tRPRE 0.9 1.1 tCK
DQS read postamble tRPST 0.4 0.6 tCK
Clock to DQS write preamble setup
time tWPRES 0 - ns
Load Mode Register / Extended Mode
register cycle time tMRD 10 - ns
Exit self refresh to READ command tXSRD 200 - tCK
Exit self refresh to non-READ
command tXSNR 75 - ns
Autoprecharge write
recovery+Precharge time tDAL 30 - ns
Note :
1. tHZ and tLZ transitions occur in the same access time windows as valid data transitions. These parameters are not referenced
to a specific voltage level, but specify when the device output is no longer driving (HZ), or begins driving (LZ).
2. The maximum limit for this parameter is not a device limit. The device will operate with a greater value for this parameter, but
system performance (bus turnaround) will degrade accordingly.
3. The specific requirement is that DQS be valid (HIGH, LOW, or at some point on a valid transition) on or before this CLK edge.
A valid transition is defined as monotonic, and meeting the input slew rate specifications of the device. When no writes were
previously in progress on the bus, DQS will be transitioning from High-Z to logic LOW. If a previous write was in progress,
DQS could be HIGH, LOW, or transitioning from HIGH to LOW at this time, depending on tDQSS.
4. A maximum of eight AUTO REFRESH commands can be posted to any given DDR SDRAM device.
5. For command/address and CLK & CLK slew rate > 1.0V/ns.
ESMT
M13S5121632A
Elite Semiconductor Memory Technology Inc. Publication Date : Oct. 2008
Revision : 1.0 8/47
Command Truth Table
COMMAND CKEn-1 CKEn CS RAS CAS WE DM BA0,1 A10/AP
A11,A12,
A9~A0 Note
Register Extended MRS H X L L L L X OP CODE 1,2
Register Mode Register Set H X L L L L X OP CODE 1,2
Auto Refresh H 3
Entry
H
L
L L L H X X 3
L H H H 3
Refresh Self
Refresh Exit L H
H X X X
XX 3
Bank Active & Row Addr. H X L L H H X V Row Address
Auto Precharge Disable L 4
Read &
Column
Address Auto Precharge Enable
H X L H L H X V
H
Column
Address 4
Auto Precharge Disable L 4
Write &
Column
Address Auto Precharge Enable
H X L H L L X V
H
Column
Address 4,6
Burst Stop H X L H H L X X 7
Bank Selection V L
Precharge All Banks H X L L H L X X H
X
5
H X X X
Entry H L
L V V V
X
Active Power Down
Exit L H X X X X X
X
H X X X
Entry H L
L H H H
X
H X X X
Precharge Power Down
Mode
Exit L H
L V V V
X
X
DM H X V X 8
H X X X
No Operation Command H X L H H H
XX
(V = Valid, X = Don’t Care, H = Logic High, L = Logic Low)
1. OP Code: Operand Code. A0~A12 & BA0~BA1: Program keys. (@EMRS/MRS)
2. EMRS/MRS can be issued only at all banks precharge state.
A new command can be issued 1 clock cycles after EMRS or MRS.
3. Auto refresh functions are same as the CBR refresh of DRAM.
The automatic precharge without row precharge command is meant by “Auto”..
Auto/self refresh can be issued only at all banks precharge state.
4. BA0~BA1: Bank select addresses.
If both BA0 and BA1 are “Low” at read, write, row active and precharge, bank A is selected.
If BA0 is “High” and BA1 is “Low” at read, write, row active and precharge, bank B is selected.
If BA0 is “Low” and BA1 is “High” at read, write, row active and precharge, bank C is selected.
If both BA0 and BA1 are “High” at read, write, row active and precharge, bank D is selected.
5. If A10/AP is “High” at row precharge, BA0 and BA1 are ignored and all banks are selected.
6. During burst write with auto precharge, new read/write command can not be issued.
Another bank read/write command can be issued after the end of burst.
New row active of the associated bank can be issued at tRP after end of burst.
7. Burst stop command is valid at every burst length.
8. DM sampling at the rising and falling edges of the DQS and Data-in are masked at the both edges (Write DM latency is 0).
ESMT
M13S5121632A
Elite Semiconductor Memory Technology Inc. Publication Date : Oct. 2008
Revision : 1.0 9/47
Basic Functionality
Power-Up and Initialization Sequence
The following sequence is required for POWER UP and Initialization.
1. Apply power and attempt to maintain CKE at a low state (all other inputs may be undefined.)
- Apply VDD before or at the same time as VDDQ.
- Apply VDDQ before or at the same time as VTT & VREF).
2. Start clock and maintain stable condition for a minimun of 200us.
3. The minimun of 200us after stable power and clock (CLK, CLK ), apply NOP & take CKE high.
4. Issue precharge commands for all banks of the device.
*1 5. Issue EMRS to enable DLL. (To issue “DLL Enable” command, provide “Low” to A0, “High” to BA0 and “Low” to all of the
rest address pins, A1~A12 and BA1)
*1 6. Issue a mode register set command for “DLL reset”. The additional 200 cycles of clock input is required to lock the DLL.
(To issue DLL reset command, provide “High” to A8 and “Low” to BA0)
*2 7. Issue precharge commands for all banks of the device.
8. Issue 2 or more auto-refresh commands.
9. Issue a mode register set command with low to A8 to initialize device operation.
*1 Every “DLL enable” command resets DLL. Therefore sequence 6 can be skipped during power up. Instead of it, the additional
200 cycles of clock input is required to lock the DLL after enabling DLL.
*2 Sequence of 6 & 7 is regardless of the order.
CLK
CLK
Command
0 1 2345678910111213141516171819
tRP
precharge
All Banks EMRS MRS
Dll Reset
tRP
precharge
All Banks
1st Auto
Refres h
tRFC
2nd A uto
Refresh
tRFC
Mode
Regi s te r S e t
Any
Command
min . 200 Cycl e
Power up & Initialization Sequence
ESMT
M13S5121632A
Elite Semiconductor Memory Technology Inc. Publication Date : Oct. 2008
Revision : 1.0 10/47
Mode Register Definition
Mode Register Set (MRS)
The mode register stores the data for controlling the various operating modes of DDR SDRAM. It programs CAS latency,
addressing mode, burst length, test mode, DLL reset and various vendor specific options to make DDR SDRAM useful for variety
of different applications. The default value of the register is not defined, therefore the mode register must be written after EMRS
setting for proper DDR SDRAM operation. The mode register is written by asserting low on CS , RAS , CAS , WE and BA0
(The DDR SDRAM should be in all bank precharge with CKE already high prior to writing into the mode register). The state of
address pins A0~A12 in the same cycle as CS , RAS , CAS , WE and BA0 going low is written in the mode register. Two clock
cycles are requested to complete the write operation in the mode register. The mode register contents can be changed using the
same command and clock cycle requirements during operation as long as all banks are in the idle state. The mode register is
divided into various fields depending on functionality. The burst length uses A0~A2, addressing mode uses A3, CAS latency (read
latency from column address) uses A4~A6. A7 is used for test mode. A8 is used for DLL reset. A7 must be set to low for normal
MRS operation. Refer to the table for specific codes for various burst length, addressing modes and CAS latencies.
BA1 BA0 A12 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0 Address Bus
0 0 0 0 0 0 DLL TM CAS Latency BT Burst Length Mode Register
A8 DLL Reset A7 Mode A3 Burst Type
0 No 0 Normal 0 Sequential
1 Yes 1 Test 1 Interleave
Burst Length
CAS Latency Latency
A6 A5 A4 Latency A2 A1 A0
Sequential Interleave
BA1 BA0 Operating Mode 0 0 0 Reserve 0 0 0 Reserve Reserve
0 0 MRS Cycle 0 0 1 Reserve 0 0 1 2 2
0 1 EMRS Cycle 0 1 0 2 0 1 0 4 4
0 1 1 3 0 1 1 8 8
1 0 0 Reserve 1 0 0 Reserve Reserve
1 0 1 Reserve 1 0 1 Reserve Reserve
1 1 0 2.5 1 1 0 Reserve Reserve
1 1 1 Reserve 1 1 1 Reserve Reserve
ESMT
M13S5121632A
Elite Semiconductor Memory Technology Inc. Publication Date : Oct. 2008
Revision : 1.0 11/47
Burst Address Ordering for Burst Length
Burst
Length Starting
Address (A2, A1,A0) Sequential Mode Interleave Mode
xx0 0, 1 0, 1
2 xx1 1, 0 1, 0
x00 0, 1, 2, 3 0, 1, 2, 3
x01 1, 2, 3, 0 1, 0, 3, 2
x10 2, 3, 0, 1 2, 3, 0, 1
4
x11 3, 0, 1, 2 3, 2, 1, 0
000 0, 1, 2, 3, 4, 5, 6, 7 0, 1, 2, 3, 4, 5, 6, 7
001 1, 2, 3, 4, 5, 6, 7, 0 1, 0, 3, 2, 5, 4, 7, 6
010 2, 3, 4, 5, 6, 7, 0, 1 2, 3, 0, 1, 6, 7, 4, 5
011 3, 4, 5, 6, 7, 0, 1, 2 3, 2, 1, 0, 7, 6, 5, 4
100 4, 5, 6, 7, 0, 1, 2, 3 4, 5, 6, 7, 0, 1, 2, 3
101 5, 6, 7, 0, 1, 2, 3, 4 5, 4, 7, 6, 1, 0, 3, 2
110 6, 7, 0, 1, 2, 3, 4, 5 6, 7, 4, 5, 2, 3, 0, 1
8
111 7, 0, 1, 2, 3, 4, 5, 6 7, 6, 5, 4, 3, 2, 1, 0
DLL Enable / Disable
The DLL must be enabled for normal operation. DLL enable is required during power-up initialization, and upon returning to
normal operation after having disabled the DLL for the purpose of debug or evaluation (upon exiting Self Refresh Mode, the DLL is
enable automatically). Any time the DLL is enabled, 200 clock cycles must occur before a READ command can be issued.
Output Drive Strength
The normal drive strength for all outputs is specified to be SSTL_2, Class II. The device also support a weak drive strength
option, intended for lighter load and/or point-to-point environments.
Mode Register Set
*1 : MRS can be issued only at all banks precharge state.
*2 : Minimum tRP is required to issue MRS command.
01 234 5678
COMMAND
tCK
Precharge
All Banks
Mode
Register Set
Any
Command
tRP
*2
*1
CLK
CLK
ESMT
M13S5121632A
Elite Semiconductor Memory Technology Inc. Publication Date : Oct. 2008
Revision : 1.0 12/47
Extended Mode Register Set (EMRS)
The extended mode register stores the data enabling or disabling DLL. The default value of the extended mode register is not
defined, therefore the extended mode register must be written after power up for enabling or disabling DLL. The extended mode
register is written by asserting low on CS , RAS , CAS , WE and high on BA0 (The DDR SDRAM should be in all bank
precharge with CKE already high prior to writing into the extended mode register). The state of address pins A0~A12 and BA1 in
the same cycle as CS , RAS , CAS and WE going low is written in the extended mode register. The mode register contents
can be changed using the same command and clock cycle requirements during operation as long as all banks are in the idle state.
A0 is used for DLL enable or disable. “High” on BA0 is used for EMRS. All the other address pins except A0 and BA0 must be set
to low for proper EMRS operation. Refer to the table for specific codes.
BA1 BA0 A12 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0
0 1 RFU : Must be set “0” D.I.C DLL
Output Driver Strength Control A0 DLL Enable
0 Normal 0 Enable
1 Weak 1 Disable
BA1 BA0 Operaing Mode
0 0 MRS Cycle
0 1 EMRS Cycle
ESMT
M13S5121632A
Elite Semiconductor Memory Technology Inc. Publication Date : Oct. 2008
Revision : 1.0 13/47
Precharge
The precharge command is used to precharge or close a bank that has activated. The precharge command is issued when CS ,
RAS and WE are low and CAS is high at the rising edge of the clock. The precharge command can be used to precharge
each bank respectively or all banks simultaneously. The bank select addresses (BA0, BA1) are used to define which bank is
precharged when the command is initiated. For write cycle, tWR(min.) must be satisfied until the precharge command can be issued.
After tRP from the precharge, an active command to the same bank can be initiated.
Burst Selection for Precharge by Bank address bits
A10/AP BA1 BA0 Precharge
0 0 0 Bank A Only
0 0 1 Bank B Only
0 1 0 Bank C Only
0 1 1 Bank D Only
1 X X All Banks
NOP & Device Deselect
The device should be deselected by deactivating the CS signal. In this mode DDR SDRAM should ignore all the control inputs.
The DDR SDRAMs are put in NOP mode when CS is active and by deactivating RAS , CAS and WE . For both Deselect and
NOP the device should finish the current operation when this command is issued.
ESMT
M13S5121632A
Elite Semiconductor Memory Technology Inc. Publication Date : Oct. 2008
Revision : 1.0 14/47
Row Active
The Bank Activation command is issued by holding CAS and WE high with CS and RAS low at the rising edge of the
clock (CLK). The DDR SDRAM has four independent banks, so two Bank Select addresses (BA0, BA1) are required. The Bank
Activation command to the first read or write command must meet or exceed the minimum of RAS to CAS delay time (tRCD min).
Once a bank has been activated, it must be precharged before another Bank Activation command can be applied to the same bank.
The minimum time interval between interleaved Bank Activation command (Bank A to Bank B and vice versa) is the Bank to Bank
delay time (tRRD min).
Bank Activation Command Cycle (CAS Latency = 3)
Read Bank
This command is used after the row activate command to initiate the burst read of data. The read command is initiated by
activating CS , CAS , and deasserting WE at the same clock sampling (rising) edge as described in the command truth table.
The length of the burst and the CAS latency time will be determined by the values programmed during the MRS command.
Write Bank
This command is used after the row activate command to initiate the burst write of data. The write command is initiated by
activating CS , CAS , and WE at the same clock sampling (rising) edge as describe in the command truth table. The length of
the burst will be determined by the values programmed during the MRS command.
Address
01 2
Command
Bank A
Row Addr.
Bank A
Col. Addr.
Bank A
Row. Addr.
Bank B
Row Addr.
Bank A
Activate NOP Write A
with Auto
Precharge
Bank B
Activate NOP Bank A
Activate
RAS-CAS delay (tRCD) RAS-RAS delay (tRRD)
ROW Cycle Time (tRC)
: Don't Care
CLK
CLK
ESMT
M13S5121632A
Elite Semiconductor Memory Technology Inc. Publication Date : Oct. 2008
Revision : 1.0 15/47
Essential Functionality for DDR SDRAM
Burst Read Operation
Burst Read operation in DDR SDRAM is in the same manner as the current SDRAM such that the Burst read command is
issued by asserting CS and CAS low while holding RAS and WE high at the rising edge of the clock (CLK) after tRCD from
the bank activation. The address inputs determine the starting address for the Burst, The Mode Register sets type of burst
(Sequential or interleave) and burst length (2, 4, 8). The first output data is available after the CAS Latency from the READ
command, and the consecutive data are presented on the falling and rising edge of Data Strobe (DQS) adopted by DDR SDRAM
until the burst length is completed.
<Burst Length = 4, CAS Latency = 3>
01 234 5 678
CO MM AND READ A NOP NO P NOP NO P NOP NOP NOP NO P
CLK
CLK
CAS Latency=3
DQS
DQ' s Dout0 Dout1 Do ut2 Dout3
ESMT
M13S5121632A
Elite Semiconductor Memory Technology Inc. Publication Date : Oct. 2008
Revision : 1.0 16/47
Burst Write Operation
The Burst Write command is issued by having CS , CAS and WE low while holding RAS high at the rising edge of the
clock (CLK). The address inputs determine the starting column address. There is no write latency relative to DQS required for burst
write cycle. The first data of a burst write cycle must be applied on the DQ pins tDS (Data-in setup time) prior to data strobe edge
enabled after tDQSS from the rising edge of the clock (CLK) that the write command is issued. The remaining data inputs must be
supplied on each subsequent falling and rising edge of Data Strobe until the burst length is completed. When the burst has been
finished, any additional data supplied to the DQ pins will be ignored.
<Burst Length = 4>
01 234 5678
COMMAND
DQS
DQ's
NOP WRITE NOP NOP NOP NOP NOP NOP
tDQSS tWPST
Din0 Din1 Din2 Din3
tWPRES
CLK
CLK
tDSH
tDSS
NOP
ESMT
M13S5121632A
Elite Semiconductor Memory Technology Inc. Publication Date : Oct. 2008
Revision : 1.0 17/47
Read Interrupted by a Read
A Burst Read can be interrupted before completion of the burst by new Read command of any bank. When the previous burst is
interrupted, the remaining addresses are overridden by the new address with the full burst length. The data from the first Read
command continues to appear on the outputs until the CAS latency from the interrupting Read command is satisfied. At this point
the data from the interrupting Read command appears. Read to Read interval is minimum 1 Clock.
<Burst Length = 4, CAS Latency = 3>
CAS Latency=3
01 234 5678
COMMAND
DQS
DQ's
READ A NOP NOP NOP NOP NOP NOP NOP
Dout A
0
READ B
Dout A
1
Dout B
2
Dout B
3
Dout B
0
Dout B
1
CLK
CLK
Read Interrupted by a Write & Burst Stop
To interrupt a burst read with a write command, Burst Stop command must be asserted to avoid data contention on the I/O bus
by placing the DQ’s(Output drivers) in a high impedance state. To insure the DQ’s are tri-stated one cycle before the beginning the
write operation, Burt stop command must be applied at least RU(CL) clocks RU means round up to the nearest integer before
the Write command.
<Burst Length = 4, CAS Latency = 3>
CAS Latency=3
01 234 5678
COMMAND
DQS
DQ's
READ NOP WRITENOP NOP NOP NOP NOP
Dout 0
Burst Stop
Din 0
Dout 1 Din 1 Din 2 Din 3
CLK
CLK
ESMT
M13S5121632A
Elite Semiconductor Memory Technology Inc. Publication Date : Oct. 2008
Revision : 1.0 18/47
Read Interrupted by a Precharge
A Burst Read operation can be interrupted by precharge of the same bank. The minimum 1 clock is required for the read to
precharge intervals. A precharge command to output disable latency is equivalent to the CAS latency.
<Burst Length = 8, CAS Latency = 3>
When a burst Read command is issued to a DDR SDRAM, a Precharge command may be issued to the same bank before the
Read burst is complete. The following functionality determines when a Precharge command may be given during a Read burst and
when a new Bank Activate command may be issued to the same bank.
1. For the earliest possible Precharge command without interrupting a Read burst, the Precharge command may be given on the
rising clock edge which is CL clock cycles before the end of the Read burst where CL is the CAS Latency. A new Bank
Activate command may be issued to the same bank after tRP (RAS precharge time).
2. When a Precharge command interrupts a Read burst operation, the Precharge command may be given on the rising clock edge
which is CL clock cycles before the last data from the interrupted Read burst where CL is the CAS Latency. Once the last
data word has been output, the output buffers are tristated. A new Bank Activate command may be issued to the same bank
after tRP.
3. For a Read with autoprecharge command, a new Bank Activate command may be issued to the same bank after tRP where tRP
begins on the rising clock edge which is CL clock cycles before the end of the Read burst where CL is the CAS Latency.
During Read with autoprecharge, the initiation of the internal precharge occurs at the same time as the earliest possible
external Precharge command would initiate a precharge operation without interrupting the Read burst as described in 1 above.
4. For all cases above, tRP is an analog delay that needs to be converted into clock cycles. The number of clock cycles between a
Precharge command and a new Bank Activate command to the same bank equals tRP / tCK (where tCK is the clock cycle time)
with the result rounded up to the nearest integer number of clock cycles.
In all cases, a Precharge operation cannot be initiated unless tRAS(min) [minimum Bank Activate to Precharge time] has been
satisfied. This includes Read with autoprecharge commands where tRAS(min) must still be satisfied such that a Read with
autoprecharge command has the same timing as a Read command followed by the earliest possible Precharge command which
does not interrupt the burst.
CAS Latency=3
01 234 5678
COMMAND
DQS
DQ's
READ NOP NOP NOP NOP NOP NOP
Dout 0
Precharge
Dout 1
1tCK
NOP
Dout 2 Dout 3 Dout 4 Dout 5
Interrupted by precharge
Dout 6 Dout 7
CLK
CLK
ESMT
M13S5121632A
Elite Semiconductor Memory Technology Inc. Publication Date : Oct. 2008
Revision : 1.0 19/47
Write Interrupted by a Write
A Burst Write can be interrupted before completion of the burst by a new Write command, with the only restriction that the
interval that separates the commands must be at least one clock cycle. When the previous burst is interrupted, the remaining
addresses are overridden by the new address and data will be written into the device until the programmed burst length is satisfied.
<Burst Length = 4>
The following functionality establishes how a Write command may interrupt a Read burst.
1. For Write commands interrupting a Read burst, a Read burst, a Burst Terminate command is required to stop the read burst
and tristate the DQ bus prior to valid input write data. Once the Burst Terminate command has been issued, the minimum
delay to a Write command = RU(CL) [CL is the CAS Latency and RU means round up to the nearest integer].
2. It is illegal for a Write command to interrupt a Read with autoprecharge command.
01 234 5678
COMMAND
DQS
DQ's
NOP NOP NOP NOP NOP NOP
Din A0
WRITE A
Din A1Din B0Din B1Din B2Din B3
1tCK
NOP WRITE B
CLK
CLK
ESMT
M13S5121632A
Elite Semiconductor Memory Technology Inc. Publication Date : Oct. 2008
Revision : 1.0 20/47
Write Interrupted by a Read & DM
A burst write can be interrupted by a read command of any bank. The DQ’s must be in the high impedance state at least one
clock cycle before the interrupting read data appear on the outputs to avoid data contention. When the read command is registered,
any residual data from the burst write cycle must be masked by DM. The delay from the last data to read command (tWTR) is
required to avoid the data contention DRAM inside. Data that are presented on the DQ pins before the read command is initiated
will actually be written to the memory. Read command interrupting write can not be issued at the next clock edge of that of write
command.
<Burst Length = 8, CAS Latency = 3>
The following functionality established how a Read command may interrupt a Write burst and which input data is not written into
the memory.
1. For Read commands interrupting a Write burst, the minimum Write to Read command delay is 2 clock cycles. The case where
the Write to Read delay is 1 clock cycle is disallowed.
2. For read commands interrupting a Write burst, the DM pin must be used to mask the input data words which immediately
precede the interrupting Read operation and the input data word which immediately follows the interrupting Read operation.
3. For all cases of a Read interrupting a Write, the DQ and DQS buses must be released by the driving chip (i.e., the memory
controller) in time to allow the buses to turn around before the SDRAM drives them during a read operation.
4. If input Write data is masked by the Read command, the DQS inputs is ignored by the SDRAM.
5. It is illegal for a Read command interrupt a Write with autoprecharge command.
CAS Latency=3
01 234 5678
COMMAND
DQS
DQ's
CAS Latency=3
DQS
DQ's
NOP NOP NOP NOP Read NOP NOP NOP
tDQSSmax
Din 0 Din 1
WRITE
tWPRES
tWTR
Din 2 Din 3 Din 4 Din 5 Din 6 Din 7 Dout 0 Dout 1
tDQSSmin
Din 0 Din 1
tWPRES
tWTR
Din 2 Din 3 Din 4 Din 5 Din 6 Din 7 Dout 0 Dout 1
DM
CLK
CLK
ESMT
M13S5121632A
Elite Semiconductor Memory Technology Inc. Publication Date : Oct. 2008
Revision : 1.0 21/47
Write Interrupted by a Precharge & DM
A burst write operation can be interrupted before completion of the burst by a precharge of the same bank. Random column
access is allowed. A write recovery time (tWR) is required from the last data to precharge command. When precharge command is
asserted, any residual data from the burst write cycle must be masked by DM.
<Burst Length = 8>
Precharge timing for Write operations in DRAMs requires enough time to allow “Write recovery” which is the time required by a
DRAM core to properly store a full “0” or “1” level before a Precharge operation. For DDR SDRAM, a timing parameter, tWR, is used
to indicate the required of time between the last valid write operation and a Precharge command to the same bank.
The precharge timing for writes is a complex definition since the write data is sampled by the data strobe and the address is
sampled by the input clock. Inside the SDRAM, the data path is eventually synchronizes with the address path by switching clock
domains from the data strobe clock domain to the input clock domain.
This makes the definition of when a precharge operation can be initiated after a write very complex since the write recovery
parameter must reference only the clock domain that is used to time the internal write operation i.e., the input clock domain.
tWR starts on the rising clock edge after the last possible DQS edge that strobed in the last valid and ends on the rising clock
edge that strobes in the precharge command.
1. For the earliest possible Precharge command following a Write burst without interrupting the burst, the minimum time for write
recovery is defined by tWR.
2. When a precharge command interrupts a Write burst operation, the data mask pin, DQ, is used to mask input data during the
time between the last valid write data and the rising clock edge in which the Precharge command is given. During this time, the
DQS input is still required to strobe in the state of DM.
The minimum time for write recovery is defined by tWR.
3. For a Write with autoprecharge command, a new Bank Activate command may be issued to the same bank after tWR + tRP where
tWR + tRP starts on the falling DQS edge that strobed in the last valid data and ends on the rising clock edge that strobes in the
Bank Activate commands. During write with autoprecharge, the initiation of the internal precharge occurs at the same time as
the earliest possible external Precharge command without interrupting the Write burst as described in 1 above.
4. In all cases, a Precharge operation cannot be initiated unless tRAS(min) [minimum Bank Activate to Precharge time] has been
satisfied. This includes Write with autoprecharge commands where tRAS(min) must still be satisfied such that a Write with
autoprecharge command has the same timing as a Write command followed by the earliest possible Precharge command
which does not interrupt the burst.
01 234 5678
COMMAND
DQS
DQ's
DQS
DQ's
NOP NOP NOP NOP N O P Precharge NOP
tDQSSmax
Dina0 Dina1
WRITE A
Dina2 Dina3 Dina4 Dina5 Dina6 Dina7
tDQSSmin
DM
WRITE B
Dinb0
tWR
Dina0 Dina1 Dina2 Dina3 Dina4 Dina5 Dina6 Dina7 Dinb0 Dinb1
CLK
CLK
tWR
ESMT
M13S5121632A
Elite Semiconductor Memory Technology Inc. Publication Date : Oct. 2008
Revision : 1.0 22/47
Burst Stop
The burst stop command is initiated by having RAS and CAS high with CS and WE low at the rising edge of the clock
(CLK). The burst stop command has the fewest restriction making it the easiest method to use when terminating a burst read
operation before it has been completed. When the burst stop command is issued during a burst read cycle, the pair of data and
DQS (Data Strobe) go to a high impedance state after a delay which is equal to the CAS latency set in the mode register. The
burst stop command, however, is not supported during a write burst operation.
<Burst Length = 4, CAS Latency = 3 >
01 234 5678
COMMAND READ A NOP NOP NOP NOP NOP NOP NOP
Burst Stop
CLK
CLK
CAS Lat en cy=3
DQS
DQ's Dout 0 Dout 1
The Burst Stop command is a mandatory feature for DDR SDRAMs. The following functionality is required.
1. The BST command may only be issued on the rising edge of the input clock, CLK.
2. BST is only a valid command during Read burst.
3. BST during a Write burst is undefined and shall not be used.
4. BST applies to all burst lengths.
5. BST is an undefined command during Read with autoprecharge and shall not be used.
6. When terminating a burst Read command, the BST command must be issued LBST ( “BST Latency”) clock cycles before the
clock edge at which the output buffers are tristated, where LBST equals the CAS latency for read operations.
7. When the burst terminates, the DQ and DQS pins are tristated.
The BST command is not byte controllable and applies to all bits in the DQ data word and the (all) DQS pin(s).
ESMT
M13S5121632A
Elite Semiconductor Memory Technology Inc. Publication Date : Oct. 2008
Revision : 1.0 23/47
DM masking
The DDR SDRAM has a data mask function that can be used in conjunction with data write cycle. Not read cycle. When the
data mask is activated (DM high) during write operation, DDR SDRAM does not accept the corresponding data. (DM to data-mask
latency is zero) DM must be issued at the rising or falling edge of data strobe.
<Burst Length = 8>
Read With Auto Precharge
If a read with auto-precharge command is initiated, the DDR SDRAM automatically enters the precharge operation BL/2 clock
later from a read with auto-precharge command when tRAS(min) is satisfied. If not, the start point of precharge operation will be
delayed until tRAS(min) is satisfied. Once the precharge operation has started the bank cannot be reactivated and the new
command can not be asserted until the precharge time (tRP) has been satisfied
<Burst Length = 4, CAS Latency = 3>
01 234
5
67
8
COMMAND Bank A
AC T I VE NOP NOP NOP NOP NOP NOP NOP
Re a d A
Au to Pr e charg e
CLK
CLK
C AS L aten cy =3
DQS
DQ's Dout 0 D out 1 Dout 2 Dout 3
At burst read / write with auto precharge, CAS interrupt of the same bank is illegal.
01 234 5678
COMMAND
tDQSS
DQS
DQ's
DM
WRITE NOP NOP NOP NOP NOP NOP NOP
Din 0
NOP
Din 1 Din 2 Din 3 Din 4 Din 6 Din 7
Din 5
masked by DM = H
CLK
CLK
ESMT
M13S5121632A
Elite Semiconductor Memory Technology Inc. Publication Date : Oct. 2008
Revision : 1.0 24/47
Write with Auto Precharge
If A10 is high when write command is issued, the write with auto-precharge function is performed. Any new command to the
same bank should not be issued until the internal precharge is completed. The internal precharge begins after keeping tWR(min).
<Burst Length = 4>
Auto Refresh & Self Refresh
Auto Refresh
An auto refresh command is issued by having CS , RAS and CAS held low with CKE and WE high at the rising edge of
the clock(CLK). All banks must be precharged and idle for tRP(min) before the auto refresh command is applied. No control of the
external address pins is requires once this cycle has started because of the internal address counter. When the refresh cycle has
completed, all banks will be in the idle state. A delay between the auto refresh command and the next activate command or
subsequent auto refresh command must be greater than or equal to the tRFC(min).
01 234 5678
COMMAND
DQS
DQ's
Bank A
ACTIVE NOP NOP NOP NOP NOP NOP NOP
Dout 0 Dout 1
Write A
Auto Precharge
Dout 2 Dout 3
*Bank can be reactivated at
completion of tRP
tWR tRP
Inte
r
nal
p
r
echa
r
g
e sta
r
t
CLK
CLK
COMMAND
CKE = High
tRP
PRE Au to
Refresh CMD
tRFC
CLK
CLK
ESMT
M13S5121632A
Elite Semiconductor Memory Technology Inc. Publication Date : Oct. 2008
Revision : 1.0 25/47
Self Refresh
A self refresh command is defines by having CS , RAS , CAS and CKE held low with WE high at the rising edge of the
clock (CLK). Once the self refresh command is initiated, CKE must be held low to keep the device in self refresh mode. During the
self refresh operation, all inputs except CKE are ignored. The clock is internally disabled during self refresh operation to reduce
power consumption. The self refresh is exited by supplying stable clock input before returning CKE high, asserting deselect or NOP
command and then asserting CKE high for longer than tXSRD for locking of DLL.
Note: 8K cycles of burst auto refresh is required immediately before self refresh entry and immediately after self refresh exit.
Power Down
Power down is entered when CKE is registered low (no accesses can be in progress). If power-down occurs when all banks are
idle, this mode is referred to as precharge power-down; if power-down occurs when there is a row active in any bank, this mode is
referred to as active power-down. Entering power-down deactivates the input and output buffers, excluding CLK, CLK and CKE.
For maximum power savings, the user has the option of disabling the DLL prior to entering power-down. In that case, the DLL must
be enabled after exiting power-down, and 200 clock cycles must occur before a READ command can be issued. However,
power-down duration is limited by the refresh requirements of the device, so in most applications, the self-refresh mode is preferred
over the DLL disable power-down mode. In the power-down, CKE LOW and a stable clock signal must be maintained at the inputs
of the DDR SDRAM, and all other input signals are “Don’t Care”. The power-down state is synchronously exited when CKE is
registered HIGH (along with a NOP or DESELECT command). A valid executable command may be applied one clock cycle later.
COMMAND
CKE
tXSNR
Self
Refresh
Aut o
Refresh Read
tXSRD
CLK
CLK
COMMAND
CKE
CLK
CLK
VALID NOP NOP VALID
Enter power-down
mode
No column
acess
in program
tIS tIS
Exit power-down
mode
ESMT
M13S5121632A
Elite Semiconductor Memory Technology Inc. Publication Date : Oct. 2008
Revision : 1.0 26/47
Functional Truth Table
Current CS RAS CAS WE Address Command Action
H X X X X DESEL NOP
L H H H X NOP NOP
L H H L BA Burst Stop ILLEGAL*2
L H L X BA, CA, A10 READ / WRITE ILLEGAL*2
L L H H BA, RA Active Bank Active, Latch RA
L L H L BA, A10 PRE / PREA NOP*4
L L L H X Refresh AUTO-Refresh*5
IDLE
L L L L Op-Code Mode-Add MRS Mode Register Set*5
H X X X X DESEL NOP
L H H H X NOP NOP
L H H L BA Burst Stop NOP
L H L H BA, CA, A10 READ / READA Begin Read, Latch CA,
Determine Auto -precharge
L H L L BA, CA, A10 WRITE / WRITEA Begin Write, Latch CA,
Determine Auto -precharge
L L H H BA, RA Active Bank Active/ILLEGAL*2
L L H L BA, A10 PRE / PREA Precharge/Precharge All
L L L H X Refresh ILLEGAL
ROW ACTIVE
L L L L Op-Code Mode-Add MRS ILLEGAL
H X X X X DESEL NOP (Continue Burst to END)
L H H H X NOP NOP (Continue Burst to END)
L H H L BA Burst Stop Terminate Burst
L H L H BA, CA, A10 READ / READA
Terminate Burst, Latch CA,
Begin New Read, Determine
Auto-Precharge*3
L H L L BA, CA, A10 WRITE / WRITEA ILLEGAL
L L H H BA, RA Active Bank Active/ILLEGAL*2
L L H L BA, A10 PRE / PREA Terminate Burst, Precharge
L L L H X Refresh ILLEGAL
READ
L L L L Op-Code Mode-Add MRS ILLEGAL
ESMT
M13S5121632A
Elite Semiconductor Memory Technology Inc. Publication Date : Oct. 2008
Revision : 1.0 27/47
Current State CS RAS CAS WE Address Command Action
H X X X X DESEL NOP (Continue Burst to end)
L H H H X NOP NOP (Continue Burst to end)
L H H L BA Burst Stop ILLEGAL
L H L H BA, CA, A10 READ/READA
Terminate Burst With DM=High,
Latch CA, Begin Read, Determine
Auto-Precharge*3
L H L L BA, CA, A10 WRITE/WRITEA
Terminate Burst, Latch CA,
Begin new Write, Determine
Auto-Precharge*3
L L H H BA, RA Active Bank Active/ILLEGAL*2
L L H L BA, A10 PRE / PREA Terminal Burst With DM=High,
Precharge
L L L H X Refresh ILLEGAL
WRITE
L L L L Op-Code Mode-Add MRS ILLEGAL
H X X X X DESEL NOP (Continue Burst to end)
L H H H X NOP NOP (Continue Burst to end)
L H H L BA Burst Stop ILLEGAL
L H L H BA, CA, A10 READ READ*7
L H L L BA, CA, A10 WRITE ILLEGAL
L L H H BA, RA Active Bank Active/ILLEGAL*2
L L H L BA, A10 PRE / PREA ILLEGAL*2
L L L H X Refresh ILLEGAL
READ with
AUTO
PRECHARGE
L L L L Op-Code Mode-Add MRS ILLEGAL
H X X X X DESEL NOP (Continue Burst to END)
L H H H X NOP NOP (Continue Burst to END)
L H H L BA Burst Stop ILLEGAL
L H L H BA, CA, A10 READ ILLEGAL
L H L L BA, CA, A10 WRITE Write
L L H H BA, RA Active Bank Active/ILLEGAL*2
L L H L BA, A10 PRE / PREA ILLEGAL*2
L L L H X Refresh ILLEGAL
WRITE with
AUTO
PRECHARGE
L L L L Op-Code Mode-Add MRS ILLEGAL
ESMT
M13S5121632A
Elite Semiconductor Memory Technology Inc. Publication Date : Oct. 2008
Revision : 1.0 28/47
Current State CS RAS CAS WE Address Command Action
H X X X X DESEL NOP (Idle after tRP)
L H H H X NOP NOP (Idle after tRP)
L H H L BA Burst Stop ILLEGAL*2
L H L X BA, CA, A10 READ/WRITE ILLEGAL*2
L L H H BA, RA Active ILLEGAL*2
L L H L BA, A10 PRE / PREA NOP*4 (Idle after tRP)
L L L H X Refresh ILLEGAL
PRE-CHARGIN
G
L L L L Op-Code Mode-Add MRS ILLEGAL
H X X X X DESEL NOP (ROW Active after tRCD)
L H H H X NOP NOP (ROW Active after tRCD)
L H H L BA Burst Stop ILLEGAL*2
L H L X BA, CA, A10 READ / WRITE ILLEGAL*2
L L H H BA, RA Active ILLEGAL*2
L L H L BA, A10 PRE / PREA ILLEGAL*2
L L L H X Refresh ILLEGAL
ROW
ACTIVATING
L L L L Op-Code Mode-Add MRS ILLEGAL
H X X X X DESEL NOP
L H H H X NOP NOP
L H H L BA Burst Stop ILLEGAL*2
L H L H BA, CA, A10 READ ILLEGAL*2
L H L L BA, CA, A10 WRITE WRITE
L L H H BA, RA Active ILLEGAL*2
L L H L BA, A10 PRE / PREA ILLEGAL*2
L L L H X Refresh ILLEGAL
WRITE
RECOVERING
L L L L Op-Code Mode-Add MRS ILLEGAL
ESMT
M13S5121632A
Elite Semiconductor Memory Technology Inc. Publication Date : Oct. 2008
Revision : 1.0 29/47
Current State CS RAS CAS WE Address Command Action
H X X X X DESEL NOP (Idle after tRP)
L H H H X NOP NOP (Idle after tRP)
L H H L BA Burst Stop ILLEGAL
L H L X BA, CA, A10 READ/WRITE ILLEGAL
L L H H BA, RA Active ILLEGAL
L L H L BA, A10 PRE / PREA ILLEGAL
L L L H X Refresh ILLEGAL
RE-FRESHING
L L L L Op-Code Mode-Add MRS ILLEGAL
H X X X X DESEL NOP (Idle after tRP)
L H H H X NOP NOP (Idle after tRP)
L H H L BA Burst Stop ILLEGAL
L H L X BA, CA, A10 READ / WRITE ILLEGAL
L L H H BA, RA Active ILLEGAL
L L H L BA, A10 PRE / PREA ILLEGAL
L L L H X Refresh ILLEGAL
MODE
REGISTER
SETTING
L L L L Op-Code Mode-Add MRS ILLEGAL
ABBREVIATIONS :
H = High Level, L = Low level, V = Valid, X = Don’t Care
BA = Bank Address, RA =Row Address, CA = Column Address, NOP = No Operation
Note :
1. All entries assume that CKE was High during the preceding clock cycle and the current clock cycle.
2. ILLEGAL to bank in specified state; function may be legal in the bank indicated by BA, depending on the state of the
bank.
3. Must satisfy bus contention, bus turn around and write recovery requirements.
4. NOP to bank precharging or in idle state. May precharge bank indicated by BA.
5. ILLEGAL of any bank is not idle.
6. Same bank’s previous auto precharg will not be performed. But if the bank is different, previous auto precharge will be
performed.
7. Refer to “Read with Auto Precharge: for more detailed information.
ILLEGAL = Device operation and / or data integrity are not guaranteed.
ESMT
M13S5121632A
Elite Semiconductor Memory Technology Inc. Publication Date : Oct. 2008
Revision : 1.0 30/47
Current State CKE
n-1 CKE
n CS RAS CAS WE Add Action
H X X X X X X INVALID
L H H X X X X Exit Self-Refresh
L H L H H H X Exit Self-Refresh
L H L H H L X ILLEGAL
L H L H L X X ILLEGAL
L H L L X X X ILLEGAL
SELF-REFRESHING*
1
L L X X X X X NOP (Maintain Self-Refresh)
H X X X X X X INVALID
L H X X X X X Exit Power Down (Idle after tPDEX)
POWER DOWN
L L X X X X X NOP (Maintain Power Down)
H H X X X X X Refer to Function True Table
H L L L L H X Enter Self-Refresh
H L H X X X X Exit Power Down
H L L H H H X Exit Power Down
H L L H H L X ILLEGAL
H L L H L X X ILLEGAL
H L L L X X X ILLEGAL
ALL BANKS IDLE*2
L L L X X X X Refer to Current State = Power Down
H H X X X X X Refer to Function True Table
ANY STATE other
than listed above
ABBREVIATIONS :
H = High Level, L = Low level, V = Valid, X = Don’t Care
Note :
1. CKE Low to High transition will re-enable CLK, CLK and other inputs asynchronously. A minimum setup time must be
satisfied before issuing any command other than EXIT.
2. Power-Down and Self-Refresh can be entered only from All Bank Idle state.
ESMT
M13S5121632A
Elite Semiconductor Memory Technology Inc. Publication Date : Oct. 2008
Revision : 1.0 31/47
Basic Timing (Setup, Hold and Access Time @ BL=4, CL=3)
Note 1. tHP is lesser of tCL or tCH clock transition collectively when a bank is active.
CKE
CS
RAS
CAS
BA0,BA1
ADDR
(A0~An)
WE
DQS
DQ
01 234 5678910
HIGH
DM
COMMAND
A10/AP
BAa BAb
Cb
Db0 Db1 Db3
Db2
tCK
tIS
tIH
tDQSCK
tRPRE
tLZ
tDQSQ
tDQSCK
Da0 Da1 Da2 Da3
tRPST
Hi-Z
Hi-Z
tDQSS
tWPRES
tDQSH
tDQSL
tDS tDH tDS tDH
tWPST Hi-Z
Hi-Z
READ WRITE
CLK
CLK
tCL
tWPRE
BAa
tHP
Note1
tHZ
tAC
tQH
ESMT
M13S5121632A
Elite Semiconductor Memory Technology Inc. Publication Date : Oct. 2008
Revision : 1.0 32/47
Multi Bank Interleaving READ (@BL=4, CL=3)
CKE
CS
RAS
CAS
BA0,BA1
WE
DQS
DQ
01 234 5678910
HIGH
DM
COMMAND
A10/AP
ADDR
(A0~An)
BAa
Qb0 Qb1 Qb3
Qb2
ACTIVE
BAb BAa BAb
Ra Rb
Ra Ca Cb
Qa0 Qa1 Qa3
Qa2
ACTIVE READ
tRCD
READ
tRRD tRCD
Rb
CLK
CLK
ESMT
M13S5121632A
Elite Semiconductor Memory Technology Inc. Publication Date : Oct. 2008
Revision : 1.0 33/47
Multi Bank Interleaving WRITE (@BL=4)
CKE
CS
RAS
CAS
BA0,BA1
WE
DQS
DQ
01 234 5678910
HIGH
DM
COMMAND
A
10
/AP
ADDR
(A0~An)
BAa
Qb0 Qb1 Qb3
Qb2
ACTIVE
BAb BAa BAb
Ra Rb
Ra Ca Cb
Qa0 Qa1 Qa3
Qa2
ACTIVE WRITE
t
RCD
WRITE
t
RRD
t
RCD
Rb
CLK
CLK
ESMT
M13S5121632A
Elite Semiconductor Memory Technology Inc. Publication Date : Oct. 2008
Revision : 1.0 34/47
Read with Auto Precharge (@BL=8)
Note 1. The row active command of the precharge bank can be issued after tRP from this point.
The new read/write command of another activated bank can be issued from this point.
At burst read/write with auto precharge, CAS interrupt of the same bank is illegal.
CKE
CS
RAS
CAS
BA0,BA1
WE
DQS(CL=3)
DQ(CL=3)
01 234 5678910
HIGH
DM
COMMAND
A10/AP
ADDR
(A0~An)
BAa
Qa4 Qa5 Qa7
Qa6
BAa
tRP
Qa0 Qa1 Qa3
Qa2
ACTI VE
READ
Ca
Auto precharge start
Note1
CLK
CLK
Ra
Ra
ESMT
M13S5121632A
Elite Semiconductor Memory Technology Inc. Publication Date : Oct. 2008
Revision : 1.0 35/47
Write with Auto Precharge (@BL=8)
Note 1. The row active command of the precharge bank can be issued after tRP from this point.
The new read/write command of another activated bank can be issued from this point.
At burst read/write with auto precharge, CAS interrupt of the same/another bank is illegal.
ESMT
M13S5121632A
Elite Semiconductor Memory Technology Inc. Publication Date : Oct. 2008
Revision : 1.0 36/47
Read Interrupted by Precharge (@BL=8)
CKE
CS
RAS
CAS
BA0,BA1
WE
DQS(CL=3)
DQ(CL=3)
01 234 5678910
HIGH
COMMAND
A
10
/AP
ADDR
(A0~An)
BAa
Qa0 Qa1
READ
BAb
Ca
PRE
CHARGE
CLK
CLK
Qa2 Qa3 Qa4 Qa5
DM
ESMT
M13S5121632A
Elite Semiconductor Memory Technology Inc. Publication Date : Oct. 2008
Revision : 1.0 37/47
Read Interrupted by a Read (@BL=8, CL=3)
CKE
CS
RAS
CAS
BA0,BA1
WE
DQS
DQ
01 234 5678910
HIGH
DM
COMMAND
A10/AP
ADDR
(A0~An)
BAa
Qa0 Qa1 Qb1Qb0
READ
Ca
BAb
Cb
Qb2 Qb3 Qb5
Qb4 Qb7
Qb6
READ
CLK
CLK
ESMT
M13S5121632A
Elite Semiconductor Memory Technology Inc. Publication Date : Oct. 2008
Revision : 1.0 38/47
Read Interrupted by a Write & Burst stop (@BL=8, CL=3)
CKE
CS
RAS
CAS
BA0,BA1
WE
DQS
DQ
01 234 5678910
HIGH
DM
COMMAND
BAa
Qa0 Qa1
READ
Qb0 Qb5
Qb1 Qb4
Qb3Qb2 Qb6
BAb
Cb
Burst
Stop WRITE
Qb7
CLK
CLK
A10/AP
ADDR
(A0~An) Ca
ESMT
M13S5121632A
Elite Semiconductor Memory Technology Inc. Publication Date : Oct. 2008
Revision : 1.0 39/47
Write followed by Precharge (@BL=4)
CKE
CS
RAS
CAS
BA0,BA1
WE
DQS
DQ
01 234 5678910
HIGH
DM
COMMAND
A10/AP
ADDR
(A0~An)
BAa BAa
tWR
Da0 Da1 Da3
Da2
PRE
CHARGE
WRITE
Ca
CLK
CLK
ESMT
M13S5121632A
Elite Semiconductor Memory Technology Inc. Publication Date : Oct. 2008
Revision : 1.0 40/47
Write Interrupted by Precharge & DM (@BL=8)
CKE
CS
RAS
CAS
BA0,BA1
WE
DQS
DQ
01 234 012345
HIGH
DM
COMMAND
A10/AP
ADDR
(A0~An)
BAa BAa
Da0 Da1 Da3
Da2
PRE
CHAR GE
WRITE WRITE WRITE
Ca
CLK
CLK
BAb BAc
Cb Cc
Da4 Da5 Da6 Da7 Db0 Db1 Dc1Dc0 Dc3
Dc2
tWR
ESMT
M13S5121632A
Elite Semiconductor Memory Technology Inc. Publication Date : Oct. 2008
Revision : 1.0 41/47
Write Interrupted by a Read (@BL=8, CL=3)
CKE
CS
RAS
CAS
BA0,BA1
WE
DQS
DQ
01 234 5678910
HIGH
DM
COMMAND
BAa
tWTR
Da0 Da1 Da3
Da2
WRITE READ
Ca
CLK
CLK
BAb
Cb
Da5
Da4 Qb0 Qb1 Qb3
Qb2 Qb4 Qb5
Maskecd by DM
A10/AP
ADDR
(A0~An)
ESMT
M13S5121632A
Elite Semiconductor Memory Technology Inc. Publication Date : Oct. 2008
Revision : 1.0 42/47
DM Function (@BL=8) only for write
CKE
CS
RAS
CAS
BA0,BA1
WE
DQS(CL=3)
DQ(CL=3)
01 234 5678910
HIGH
DM
COMMAND
A10/AP
ADDR
(A0~An)
BAa
Qa4 Qa5 Qa7
Qa6
Qa0 Qa1 Qa3
Qa2
WRITE
Ca
CLK
CLK
ESMT
M13S5121632A
Elite Semiconductor Memory Technology Inc. Publication Date : Oct. 2008
Revision : 1.0 43/47
Power up & Initialization Sequence
CKE
CS
RAS
CAS
A10/AP
Precharge
All Bank
A7
213
45 678910 11 12 13 14 15 16 17 18 19
0
DQ
Precharge
All Bank
BA0
WE
DQS
High-Z
High-Z
t
RP
High level is required
BA1,A9,
A11~A12
A1~A6
A0
ADDRESS KEY
Minimum 200 Cycle
t
RP
t
RC
t
RC
Minimum of 2 Refresh Cycles are required
EMRS
DLL Enable
MRS
DLL Reset
1st Auto Refresh 2ndAutoRefresh Mode Resister Set
Any
Command
:Don'tCare
CLK
CLK
A8
t
MRD
(Power & Clock must be
stable for200us
before precharge
All Bank)
ESMT
M13S5121632A
Elite Semiconductor Memory Technology Inc. Publication Date : Oct. 2008
Revision : 1.0 44/47
Mode Register Set
CKE
CS
RAS
CAS
ADDR
(A0~An)
Precharge
Command
All Bank
DM
DQ
Mode Register Set
Command
Any
Command
BA0,BA1
A10/AP
tCK
WE
DQS
ADDRESS KEY
High-Z
High-Z
tRP
CLK
CLK
tMRD
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19
ESMT
M13S5121632A
Elite Semiconductor Memory Technology Inc. Publication Date : Oct. 2008
Revision : 1.0 45/47
PACKING DIMENSIONS
66-LEAD TSOP(II) DRAM(400mil)
Symbol Dimension in inch Dimension in mm
Min Norm Max Min Norm Max
A
0.047
1.2
A1 0.002 0.004 0.006 0.05 0.1 0.15
A2 0.037 0.039 0.041 0.95 1 1.05
b 0.009
0.015 0.22
0.38
b1 0.009 0.012 0.013 0.22 0.3 0.33
c 0.005
0.008 0.12
0.21
c1 0.0047 0.005 0.006 0.12 0.127 0.16
D 0.875 BSC 22.22 BSC
ZD 0.028 REF 0.71 REF
E 0.455 0.463 0.471 11.56 11.76 11.96
E1 0.400 BSC 10.16 BSC
e 0.026 BSC 0.65 BSC
L 0.016 0.02 0.024 0.4 0.5 0.6
L1 0.031 REF 0.80 REF
°θ °0 °8 °0 °8
°1θ °10 °15 °20 °10 °15 °20
ESMT
M13S5121632A
Elite Semiconductor Memory Technology Inc. Publication Date : Oct. 2008
Revision : 1.0 46/47
Revision History
Revision Date Description
1.0 2008.10.06 Original
ESMT
M13S5121632A
Elite Semiconductor Memory Technology Inc. Publication Date : Oct. 2008
Revision : 1.0 47/47
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rights of ESMT or others.
A
ny semiconductor devices may have inherently a certain rate of failure. To
minimize risks associated with customer's application, adequate design and
operating safeguards against injury, damage, or loss from such failure, should be
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ESMT's products are not authorized for use in critical applications such as, but
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