LM5175PWPT - NATIONAL SEMICONDUCTOR

VIN

ISNS(-)

RT/SYNC

VIN

BOOT1

EN/UVLO

VOUT

AGND

CSG

PGND

VOSNS

HDRV1

SW1

COMP

LM5175

LDRV1

LDRV2

HDRV2

BOOT2

SW2

MODE

DITH

Enable

VCC

ISNS(+)

VCC

SLOPE

VISNS

BIAS

PGOOD

Power Good

Product

Folder

Sample &

Buy

Technical

Documents

Tools &

Software

Support &

Community

An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,

intellectual property matters and other important disclaimers. PRODUCTION DATA.

LM5175

SNVSA37A –OCTOBER 2015–REVISED MAY 2016

LM5175 42-V Wide V

Synchronous 4-Switch Buck-Boost Controller

1 Features

1• Single Inductor Buck-Boost Controller for Step-

Up/Step-Down DC/DC Conversion

• Wide VIN Range: 3.5 V to 42 V, 60 V Maximum

• Flexible VOUT Range: 0.8 V to 55 V

• VOUT Short Protection

• High Efficiency Buck-Boost Transition

• Adjustable Switching Frequency

• Optional Frequency Sync and Dithering

• Integrated 2-A MOSFET Gate Drivers

• Cycle-by-Cycle Current Limit and Optional Hiccup

• Optional Input or Output Average Current Limiting

• Programmable Input UVLO and Soft-Start

• Power Good and Output Overvoltage Protection

• Selectable CCM or DCM with Pulse Skipping

• Available in HTSSOP-28 and QFN-28 Packages

• Create a Custom Design Using the LM5175 with

the WEBENCH Power Designer

2 Applications

• Automotive Start-Stop Systems

• Backup Battery and Supercapacitor Charging

• Industrial PC Power Supplies

• USB Power Delivery

• LED Lighting

3 Description

The LM5175 is a synchronous four-switch buck-boost

DC/DC controller capable of regulating the output

voltage at, above, or below the input voltage. The

LM5175 operates over a wide input voltage range of

3.5 V to 42 V (60 V maximum) to support a variety of

applications.

The LM5175 employs current-mode control both in

buck and boost modes of operation for superior load

and line regulation. The switching frequency is

programmed by an external resistor and can be

synchronized to an external clock signal.

The device also features a programmable soft-start

function and offers protection features including

cycle-by-cycle current limiting, input undervoltage

lockout (UVLO), output overvoltage protection (OVP),

and thermal shutdown. In addition, the LM5175

features selectable Continuous Conduction Mode

(CCM) or Discontinuous Conduction Mode (DCM)

operation, optional average input or output current

limiting, optional spread spectrum to reduce peak

EMI, and optional hiccup mode protection in

sustained overload conditions.

Device Information

ORDER NUMBER PACKAGE BODY SIZE

LM5175PWP HTSSOP-28 9.7 mm x 4.4 mm

LM5175RHF QFN-28 4.0 mm x 5.0 mm

4 Simplified Schematic

LM5175

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Table of Contents

1 Features.................................................................. 1

2 Applications ........................................................... 1

3 Description............................................................. 1

4 Simplified Schematic............................................. 1

5 Revision History..................................................... 2

6 Pin Configuration and Functions......................... 3

7 Specifications......................................................... 5

7.1 Absolute Maximum Ratings ...................................... 5

7.2 ESD Ratings.............................................................. 5

7.3 Recommended Operating Conditions....................... 5

7.4 Thermal Information.................................................. 6

7.5 Electrical Characteristics........................................... 6

7.6 Typical Characteristics.............................................. 9

8 Detailed Description............................................ 12

8.1 Overview................................................................. 12

8.2 Functional Block Diagram....................................... 13

8.3 Feature Description................................................. 13

8.4 Device Functional Modes........................................ 19

9 Application and Implementation ........................ 20

9.1 Application Information............................................ 20

9.2 Typical Application.................................................. 20

10 Power Supply Recommendations ..................... 28

11 Layout................................................................... 28

11.1 Layout Guidelines ................................................. 28

11.2 Layout Example .................................................... 29

12 Device and Documentation Support................. 30

12.1 Custom Design with WEBENCH Tools................. 30

12.2 Receiving Notification of Documentation Updates 30

12.3 Documentation Support ........................................ 30

12.4 Community Resources.......................................... 30

12.5 Trademarks........................................................... 30

12.6 Electrostatic Discharge Caution............................ 30

12.7 Glossary................................................................ 30

13 Mechanical, Packaging, and Orderable

Information........................................................... 31

5 Revision History

Changes from Original (October 2015) to Revision A Page

• Added QFN-28 Packages....................................................................................................................................................... 1

• Added LM5175RHF information ............................................................................................................................................ 1

• Added RHF package.............................................................................................................................................................. 3

• Added QFN pins .................................................................................................................................................................... 4

• Changed first plus to minus ................................................................................................................................................. 18

• Changed all 1.22 V to 1.23 V .............................................................................................................................................. 19

• Changed equation ............................................................................................................................................................... 24

• Changed equation ............................................................................................................................................................... 26

SLOPE

COMP

AGND

DITH

MODE

CSG

PGOOD

ISNS(+)

ISNS(±)

VOSNS

LDRV1

BIAS

VCC

PGND

LDRV2

BOOT2

HDRV2

SW2

HDRV1

SW1

BOOT1

EN/UVLO

VIN

VISNS

LM5175

QFN-28

VIN

EN/UVLO

SLOPE

COMP

AGND

ISNS(+)

ISNS(±)

VOSNS

DITH

MODE

VISNS

SW1

HDRV1

BOOT1

LDRV1

BIAS

VCC

PGND

LDRV2

BOOT2

HDRV2

SW2

CSG

PGOOD

LM5175

HTSSOP-28

LM5175

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6 Pin Configuration and Functions

HTSSOP-28

PWP Package

Top View

QFN-28

RHF Package

Top View

LM5175

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Pin Functions

PIN DESCRIPTION

NAME HTSSOP QFN

EN/UVLO 1 26 Enable pin. For EN/UVLO < 0.4 V, the LM5175 is in a low current shutdown mode. For 0.7 V <

EN/UVLO < 1.23 V, the controller operates in standby mode in which the VCC regulator is enabled but

the PWM controller is not switching. For EN/UVLO > 1.23 V, the PWM function is enabled, provided

VCC exceeds the VCC UV threshold.

VIN 2 27 The input supply pin to the IC. Connect VIN to a supply voltage between 3.5 V and 42 V.

VISNS 3 28 VIN sense input. Connect to the input capacitor.

MODE 4 1

Mode = GND, DCM, Hiccup Disabled (Set RMODE resistor to GND = 0 Ω)

Mode = 1.00 V, DCM, Hiccup Enabled (Set RMODE resistor to GND = 49.9 kΩ)

Mode = 1.85 V, CCM, Hiccup Enabled (Set RMODE resistor to GND = 93.1 kΩ)

Mode = VCC, CCM, Hiccup Disabled (Set RMODE resistor to VCC = 0 Ω)

DITH 5 2 A capacitor connected between the DITH pin and AGND is charged and discharged with a 10 uA

current source. As the voltage on the DITH pin ramps up and down the oscillator frequency is

modulated between –5% and +5% of the nominal frequency set by the RT resistor. Grounding the

DITH pin will disable the dithering feature. In the external Sync mode, the DITH pin voltage is ignored.

RT/SYNC 6 3 Switching frequency programming pin. An external resistor is connected to the RT/SYNC pin and

AGND to set the switching frequency. This pin can also be used to synchronize the PWM controller to

an external clock.

SLOPE 7 4 A capacitor connected between the SLOPE pin and AGND provides the slope compensation ramp for

stable current mode operation in both buck and boost mode.

SS 8 5 Soft-start programming pin. A capacitor between the SS pin and AGND pin programs soft-start time.

COMP 9 6 Output of the error amplifier. An external RC network connected between COMP and AGND

compensates the regulator feedback loop.

AGND 10 7 Analog ground of the IC.

FB 11 8 Feedback pin for output voltage regulation. Connect a resistor divider network from the output of the

converter to the FB pin.

VOSNS 12 9 VOUT sense input. Connect to the output capacitor.

ISNS(–)

ISNS(+) 13

14 10

Input or Output Current Sense Amplifier inputs. An optional current sense resistor connected between

ISNS(+) and ISNS(–) can be located either on the input side or on the output side of the converter. If

the sensed voltage across the ISNS(+) and ISNS(-) pins reaches 50 mV, a slow Constant Current (CC)

control loop becomes active and starts discharging the soft-start capacitor to regulated the drop across

ISNS(+) and ISNS(-) to 50 mV. Short ISNS(+) and ISNS(-) together to disable this feature.

CSG 15 12 The negative or ground input to the PWM current sense amplifier. Connect directly to the low-side

(ground) of the current sense resistor.

CS 16 13 The positive input to the PWM current sense amplifier.

PGOOD 17 14 Power Good open drain output. PGOOD is pulled low when FB is outside a 0.8 V ±10% regulation

window.

SW2

SW1 18

28 15

25 The boost and the buck side switching nodes respectively.

HDRV2

HDRV1 19

27 16

24 Output of the high-side gate drivers. Connect directly to the gates of the high-side MOSFETs.

BOOT2

BOOT1 20

26 17

23 An external capacitor is required between the BOOT1, BOOT2 pins and the SW1, SW2 pins

respectively to provide bias to the high-side MOSFET gate drivers.

LDRV2

LDRV1 21

25 18

22 Output of the low-side gate drivers. Connect directly to the gates of the low-side MOSFETs.

PGND 22 19 Power ground of the IC. The high current ground connection to the low-side gate drivers.

VCC 23 20 Output of the VCC bias regulator. Connect capacitor to ground.

BIAS 24 21 Optional input to the VCC bias regulator. Powering VCC from an external supply instead of VIN can

reduce power loss at high VIN. For VBIAS > 8 V, the VCC regulator draws power from the BIAS pin. The

BIAS pin voltage must not exceed 40 V.

PowerPAD

™- - The PowerPAD should be soldered to the analog ground. If possible, use thermal vias to connect to a

PCB ground plane for improved power dissipation.

LM5175

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(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings

only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended

Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

7 Specifications

7.1 Absolute Maximum Ratings(1)

MIN MAX UNIT

VIN, EN/UVLO, VISNS, VOSNS, ISNS(+), ISNS(–) –0.3 60

BIAS –0.3 40

FB, SS, DITH, RT/SYNC, SLOPE, COMP –0.3 3.6

SW1, SW2 –1 60

SW1, SW2 (20 ns transient) –3.0 65

VCC, MODE, PGOOD –0.3 8.5

LDRV1, LDRV2 –0.3 8.5

BOOT1, HDRV1 with respect to SW1 –0.3 8.5

BOOT2, HDRV2 with respect to SW2 –0.3 8.5

BOOT1, BOOT2 –0.3 68

CS, CSG –0.3 0.3

Operating junction temperature –40 150 °C

Storage temperature, Tstg -65 150

(1) Electrostatic discharge (ESD) to measure device sensitivity and immunity to damage caused by assembly line electrostatic discharges

into the device.

(2) Level listed above is the passing level per ANSI/ESDA/JEDEC JS-001. JEDEC document JEP155 states that 500 V HBM allows safe

manufacturing with a standard ESD control process.

(3) Level listed above is the passing level per EIA-JEDEC JESD22-C101. JEDEC document JEP157 states that 250 V CDM allows safe

manufacturing with a standard ESD control process.

7.2 ESD Ratings VALUE UNIT

VESD(1) Human body model (HBM) ESD stress voltage(2) ±2000 V

Charged device model (CDM) ESD stress voltage(3) ±750

(1) Recommended Operating Conditions are conditions under the device is intended to be functional. For specifications and test conditions,

see Electrical Characteristics .

(2) High junction temperatures degrade operating lifetimes. Operating lifetime is de-rated for junction temperatures greater than 125°C.

7.3 Recommended Operating Conditions

over operating free-air temperature range (unless otherwise noted)(1)

MIN NOM MAX UNIT

VIN Input voltage range 3.5 42

BIAS Bias supply voltage range 8 36

VOUT Output voltage range 0.8 55

EN/UVLO Enable voltage range 0 42

ISNS(+), ISNS(-) Average current sense common mode range 0 55

TJOperating temperature range(2) –40 125 °C

Fsw Operating frequency range 100 600 kHz

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(1) For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report, SPRA953.

7.4 Thermal Information

THERMAL METRIC(1) LM5175

UNITHTSSOP QFN

28 PINS 28 PINS

RθJA Junction-to-ambient thermal resistance 33.1 34.7

°C/W

RθJC(top) Junction-to-case (top) thermal resistance 17.7 26.6

RθJB Junction-to-board thermal resistance 14.9 6.3

ψJT Junction-to-top characterization parameter 0.4 0.3

ψJB Junction-to-board characterization parameter 14.7 6.2

RθJC(bot) Junction-to-case (bottom) thermal resistance 1.1 2.0

(1) All minimum and maximum limits are specified by correlating the electrical characteristics to process and temperature variations and

applying statistical process control.

7.5 Electrical Characteristics

Typical values correspond to TJ= 25°C. Minimum and maximum limits apply over the –40°C to 125°C junction temperature

range unless otherwise stated. VIN = 24 V unless otherwise stated.(1)

PARAMETER TEST CONDITION MIN TYP MAX UNIT

SUPPLY VOLTAGE (VIN)

VIN Operating input voltage 3.5 42 V

IQVIN shutdown current VEN/UVLO = 0 V 1.4 10 µA

VIN standby current VEN/UVLO = 1.1 V, non-switching 0.7 2

VIN operating current VEN/UVLO = 2 V, VFB = 0.9 V 1.65 4 mA

VCC

VVCC(VIN) Regulation voltage VBIAS = 0 V, VCC open 6.95 7.35 7.88 V

VUV(VCC) VCC Undervoltage lockout VCC increasing 3.11 3.27 3.43

Undervoltage hysteresis 160 mV

IVCC VCC current limit VVCC = 0 V 65 mA

ROUT(VCC) VCC regulator output impedance IVCC = 30 mA, VIN = 3.5 V 9.3 16 Ω

BIAS

VBIAS(SW) BIAS switchover voltage VIN = 24 V 7.25 8 8.75 V

EN/UVLO

VEN(STBY) Standby threshold EN/UVLO rising 0.55 0.79 0.97 V

IEN(STBY) Standby source current VEN/UVLO = 1.1 V 1 2 3 µA

VEN(OP) Operating threshold EN/UVLO rising 1.17 1.23 1.29 V

ΔIHYS(OP) Operating hysteresis current VEN/UVLO = 2.4 V 1.5 3.5 5.5 µA

ISS Soft-start pull up current VSS = 0 V 4.30 5.65 7.25 µA

VSS(CL) SS clamp voltage SS open 1.27 V

VFB - VSS FB to SS offset VSS = 0 V -15 mV

EA (ERROR AMPLIFIER)

VREF Feedback reference voltage FB = COMP 0.788 0.800 0.812 V

gmEA Error amplifier gm 1.27 mS

ISINK/ISOURCE COMP sink/source current VFB=VREF ± 300 mV 280 µA

ROUT Amplifier output resistance 20 MΩ

BW Unity gain bandwidth 2 MHz

IBIAS(FB) Feedback pin input bias current FB in regulation 100 nA

FREQUENCY

fSW(1) Switching Frequency 1 RT = 133 kΩ180 200 220 kHz

fSW(2) Switching Frequency 2 RT = 47 kΩ430 500 565

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Electrical Characteristics (continued)

Typical values correspond to TJ= 25°C. Minimum and maximum limits apply over the –40°C to 125°C junction temperature

range unless otherwise stated. VIN = 24 V unless otherwise stated.(1)

PARAMETER TEST CONDITION MIN TYP MAX UNIT

DITHER

IDITHER Dither source/sink current 10.5 µA

VDITHER Dither high threshold 1.27 V

Dither low threshold 1.16

SYNC

VSYNC Sync input high threshold 2.1 V

Sync input low threshold 1.2

PWSYNC Sync input pulse width 75 500 ns

CURRENT LIMIT

VCS(BUCK) Buck current limit threshold (Valley) VIN = VVISNS = 24 V, VVOSNS = 12 V,

VSLOPE = 0 V, TJ= 25°C 53.2 76 98 mV

VCS(BOOST) Boost current limit threshold (Peak) VIN = VVISNS = 12 V, VVOSNS = 18 V,

VSLOPE = 0 V, TJ= 25°C 119 170 221

IBIAS(CS/CSG) CS/CSG pin bias current VCS = VCSG = 0 V -75 µA

IOFFSET(CS/CS

G) CSG pin bias current VCS = VCSG = 0 V 14

CONSTANT CURRENT LOOP

VSNS Average current loop regulation target VISNS(-) = 24 V, sweep ISNS(+), VSS =

0.8 V 43 50 57 mV

ISNS ISNS(+)/ISNS(–) pin bias currents VISNS(+) = VISNS(–) = VIN = 24 V 7 µA

Gm gm of soft-start pull down amplifier VISNS(+)–VISNS(–) = 55 mV, VSS = 0.5

V1 mS

SLOPE

ISLOPE Buck adaptive slope current VIN = VVINSNS = 24 V, VVOSNS = 12 V,

VSLOPE = 0 V 24 30 35 µA

Boost adaptive slope current VIN = VVINSNS = 12 V, VVOSNS = 18 V,

VSLOPE = 0 V 13 17 21

gmSLOPE Slope compensation amplifier gm 2 µS

MODE

IMODE Source current out of MODE pin 17 20 23 µA

VDCM_HIC DCM with hiccup threshold 0.60 0.7 0.76 VVCCM_HIC CCM with hiccup threshold 1.18 1.28 1.38

VCCM CCM no hiccup threshold 2.22 2.4 2.6

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Electrical Characteristics (continued)

Typical values correspond to TJ= 25°C. Minimum and maximum limits apply over the –40°C to 125°C junction temperature

range unless otherwise stated. VIN = 24 V unless otherwise stated.(1)

PARAMETER TEST CONDITION MIN TYP MAX UNIT

PGOOD

VPGD PGOOD trip threshold for falling FB Measured with respect to VREF –9 %

PGOOD trip threshold for rising FB Measured with respect to VREF 10 %

Hysteresis 1.6 %

ILEAK(PGD) PGOOD leakage current 100 nA

ISINK(PGD) PGOOD sink current VPGOOD = 0.4 V 2 4.2 6.5 mA

OUTPUT OVP

VOVP Output overvoltage threshold At the FB pin 0.86 V

Hysteresis 21 mV

NMOS DRIVERS

IHDRV1,2 Driver peak source current VBOOT - VSW = 7 V 1.8

Driver peak sink current VBOOT - VSW = 7 V 2.2

ILDRV1,2 Driver peak source current 1.8

Driver peak sink current 2.2

RHDRV1,2 Driver pull up resistance VBOOT - VSW = 7 V 1.9 Ω

Driver pull down resistance VBOOT - VSW = 7 V 1.3

VUV(BOOT1,2) BOOT1,2 to SW1,2 UVLO threshold HDRV1,2 shut off 2.73 V

BOOT1,2 to SW1,2 UVLO hysteresis HDRV1,2 start switching 280 mV

BOOT1,2 to SW1,2 threshold for refresh

pulse 4.45 V

RLDRV1,2 Driver pull up resistance IDRV1,2 = 0.1 A 2 Ω

Driver pull down resistance IDRV1,2 = 0.1 A 1.5

tDT1 Dead time HDRV1,2 off to LDRV1,2 on 55 ns

tDT2 Dead time LDRV1,2 off to HDRV1,2 on 55

THERMAL SHUTDOWN

TSD Thermal shutdown temperature 165 °C

TSD(HYS) Thermal shutdown hysteresis 15

VIN (V)

IIN (mA)

0 5 10 15 20 25 30 35 40 45

0.2

0.4

0.6

0.8

D006

BIAS = 12V

BIAS = 0V

VIN (V)

IIN (mA)

0 5 10 15 20 25 30 35 40 45

1.4

1.6

1.8

2.2

2.4

D007

BIAS = 12V

BIAS = 0V

RT (k:)

FREQUENCY (kHz)

0 50 100 150 200 250 300

100

200

300

400

500

600

D004

VIN (V)

VCC (V)

0 2 4 6 8 10 12 14 16 18

D002

VIN (V)

EFFICIENCY (%)

5 10 15 20 25 30 35 40 45

D009

LOAD CURRENT (A)

EFFICIENCY (%)

0 1 2 3 4 5 6

100

D008

VIN=6V

VIN=12V

VIN=24V

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7.6 Typical Characteristics

At TA= 25°C, unless otherwise stated.

VOUT=12 V Fsw=300 kHz L1=4.7 μH

IOUT=3 A

Figure 1. Efficiency vs VIN

VOUT =12 V Fsw=300 kHz L1=4.7 μH

Figure 2. Efficiency vs Load

Figure 3. Oscillator Frequency Figure 4. VCC vs VIN

Figure 5. IIN Standby Figure 6. IIN Operating vs VIN

TEMPERATURE (°C)

VREF (V)

-40 -20 0 20 40 60 80 100 120 140

0.795

0.797

0.799

0.801

0.803

0.805

D014

SW1 (20V/div)

IL (5A/div)

5 µs/div

SW2 (10V/div)

VOUT (200mV/div ac)

TEMPERATURE (qC)

BUCK CURRENT LIMIT (mV)

-40 -20 0 20 40 60 80 100 120 140

100

110

D012

TEMPERATURE (°C)

BOOST CURRENT LIMIT (mV)

-40 -20 0 20 40 60 80 100 120 140

140

150

160

170

180

190

200

D011

VIN (V)

IIN (PA)

0 5 10 15 20 25 30 35 40 45

0.8

1.6

2.4

3.2

D010

-40 °C

25 °C

125 °C

TEMPERATURE (°C)

VEN/UVLO (V)

-40 -20 0 20 40 60 80 100 120 140

1.10

1.14

1.18

1.22

1.26

1.30

D013

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Typical Characteristics (continued)

At TA= 25°C, unless otherwise stated.

Figure 7. IIN Shutdown vs VIN Figure 8. ENABLE/UVLO Rising Threshold vs Temperature

Figure 9. Buck Current Limit vs Temperature Figure 10. Boost Current Limit vs Temperature

Figure 11. VREF vs Temperature

VOUT=12 V VIN=24 V

Figure 12. Forced CCM Operation (Buck)

VOUT (1V/div)

COMP (1V/div)

VIN (10V/div)

IL (5A/div)

5ms/div

VOUT (500mV/div)

IL (5A/div)

500 µs/div

VOUT (500 mV/div ac)

IL (5A/div)

500 µs/div

VOUT (500mV/div)

IL (5A/div)

500 µs/div

SW1 (20V/div)

IL (5A/div)

5 µs/div

SW2 (10V/div)

VOUT (200mV/div ac)

SW1 (20V/div)

IL (5A/div)

5 µs/div

SW2 (10V/div)

VOUT (200mV/div ac)

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Typical Characteristics (continued)

At TA= 25°C, unless otherwise stated.

VOUT=12 V VIN=6 V

Figure 13. Forced CCM Operation (Boost)

VOUT=12 V VIN=12 V

Figure 14. Forced CCM Operation (Buck-Boost)

VIN=24 V VOUT=12 V Load 2A to 4A

Figure 15. Load Step (Buck)

VIN=6 V VOUT=12 V Load 2A to 4A

Figure 16. Load Step (Boost)

VIN=12 V VOUT=12 V Load 2A to 4A

Figure 17. Load Step (Buck-Boost)

VIN=8 V to 24 V VOUT=12 V IOUT=1A

Figure 18. Line Transient

VOUT (5V/div)

IL (5A/div)

Overload Release

Hiccup

20ms/div

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Typical Characteristics (continued)

At TA= 25°C, unless otherwise stated.

VIN=24 V VOUT=12 V Hiccup Enabled

Figure 19. Hiccup Mode Current Limit

8 Detailed Description

8.1 Overview

The LM5175 is a wide input voltage four-switch buck-boost controller IC with integrated drivers for N-channel

MOSFETs. It operates in the buck mode when VIN is greater than VOUT and in the boost mode when VIN is less

than VOUT. When VIN is close to VOUT, the device operates in a proprietary transition buck or boost mode. The

control scheme provides smooth operation for any input/output combination within the specified operating range.

The buck or boost transition control scheme provides a low ripple output voltage when VIN equals VOUT without

compromising the efficiency.

The LM5175 integrates four N-Channel MOSFET drivers including two low-side drivers and two high-side drivers,

eliminating the need for external drivers or floating bias supplies. The internal VCC regulator supplies internal

bias rails as well as the MOSFET gate drivers. The VCC regulator is powered either from the input voltage

through the VIN pin or from the output or an external supply through the BIAS pin for improved efficiency.

The PWM control scheme is based on valley current mode control for buck operation and peak current mode

control for boost operation. The inductor current is sensed through a single sense resistor in series with the low-

side MOSFETs. The sensed current is also monitored for cycle-by-cycle current limit. The behavior of the

LM5175 during an overload condition is dependent on the MODE pin programming (see MODE Pin

Configuration). If hiccup mode fault protection is selected, the controller turns off after a fixed number of

switching cycles in cycle-by-cycle current limit and restarts after another fixed number of clock cycles. The hiccup

mode reduces the heating in the power components in a sustained overload condition. If hiccup mode is disabled

through the MODE pin, the controller remains in a cycle-by-cycle current limit condition until the overload is

removed. The MODE pin also selects continuous conduction mode (CCM) for noise sensitive applications or

discontinuous conduction mode (DCM) for higher light load efficiency.

In addition to the cycle-by-cycle current limiting, the LM5175 also provides an optional average current regulation

loop that can be configured for either input or output current limiting. This is useful for battery charging or other

applications where a constant current behavior may be required.

The soft-start time of LM5175 is programmed by a capacitor connected to the SS pin to minimize the inrush

current and overshoot during startup.

The precision EN/UVLO pin supports programmable input undervoltage lockout (UVLO) with hysteresis. The

output overvoltage protection (OVP) feature turns off the high-side drivers when the voltage at the FB pin is 7.5%

above the nominal 0.8-V VREF. The PGOOD output indicates when the FB voltage is inside a ±10% regulation

window centered at VREF.



CS +

CSG

AMPLIFIER

COMP

SS 0.8 V GM ERROR

AMPLIFIER

VISNS

VOSNS

SLOPE

COMP

BUCK-BOOST CONTROLLER

LOGIC

VILIM

RT/SYNC

DITH OSC/SYNC CLK

ILIMIT

COMPARATOR

PWM

COMPARATOR

VCC

BOOT1

HDRV1

SW1

LDRV1

BOOT2

HDRV2

SW2

LDRV2

CCM/DCM

HICCUP CURRENT

LIMIT

MODE

A=5

AGND PGND

EN/UVLO 1.23 V

ISNS(+)

ISNS(-)

45 mV

CONSTANT

CURRENT LOOP

VIN

VCC

EN & BIAS

LOGIC THERMAL

SHUTDOWN

CLK

BIAS

0.88 V

0.72 V

0.86 V

PGOOD OV

1.2 V

1 mA/V

5 µA

0.7 V +

OPERATING

STANDBY

3.5 µA

1.5 µA

1.6 V

3.3 V

LM5175

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8.2 Functional Block Diagram

8.3 Feature Description

8.3.1 Fixed Frequency Valley/Peak Current Mode Control with Slope Compensation

The LM5175 implements a fixed frequency current mode control of both the buck and boost switches. The output

voltage, scaled down by the feedback resistor divider, appears at the FB pin and is compared to the internal

reference (VREF) by an internal error amplifier. The error amplifier produces an error voltage by driving the COMP

pin. An adaptive slope compensation signal based on VIN, VOUT, and the capacitor at the SLOPE pin is added to

the current sense signal measured across the CS and CSG pins. The result is compared to the COMP error

voltage by the PWM comparator.

Optional

Bias Supply/

VOUT

VIN

CVCC

CBIAS

VIN

BIAS

CVIN

VCC

LM5175

Series Blocking

Diode

LM5175

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Feature Description (continued)

The LM5175 regulates the output using valley current mode control in buck mode and peak current mode control

in boost mode. For valley current mode control, the high-side buck MOSFET controlled by HDRV1 is turned on

by the PWM comparator at the valley of the inductor ripple current and turned off by the oscillator clock signal.

Valley current mode control is advantageous for buck converters where the PWM controller must resolve very

short on-times. For peak current mode control in the boost mode, the low-side boost MOSFET controlled by

LDRV2 is turned on by the clock signal in each switching cycle and turned off by the PWM comparator at the

peak of the inductor ripple current.

The low-side gate drive LDRV1, complementary to the HDRV1 drive signal, controls the synchronous rectification

MOSFET of the buck stage. The high-side gate drive HDRV2, complementary to the low-side gate drive LDRV2,

controls the high-side synchronous rectifier of the boost stage. For operation with VIN close to VOUT, the LM5175

uses a proprietary buck or boost transition scheme to achieve smooth, low ripple transition zone behavior.

Peak and valley current mode controllers require slope compensation for stable current loop operation at duty

cycle greater than 50% in peak current mode control and less than 50% in valley current mode control. The

LM5175 provides a SLOPE pin to program optimum slope for any VIN and VOUT combination using an external

capacitor.

8.3.2 VCC Regulator and Optional BIAS Input

The VCC regulator provides a regulated 7.5-V bias supply to the gate drivers. When EN/UVLO is above the 0.7-

V (typical) standby threshold, the VCC regulator is turned on. For VIN less than 7.5 V, the VCC voltage tracks VIN

with a small voltage drop as shown in Figure 4. If the EN/UVLO input is above the 1.23 V operating threshold

and VCC exceeds the 3.3 V (typical) VCC UV threshold, the controller is enabled and switching begins.

The VCC regulator draws power from VIN when there is no supply voltage connected to the BIAS pin. If the BIAS

pin is connected to an external voltage source that exceeds VCC by one diode drop, the VCC regulator draws

power from the BIAS input instead of VIN. Connecting the BIAS pin to VOUT in applications with VOUT greater than

8.5 V improves the efficiency of the regulator in the buck mode. The BIAS pin voltage should not exceed 36 V.

For low VIN operation, ensure that the VCC voltage is sufficient to fully enhance the MOSFETs. Use an external

bias supply if VIN dips below the voltage required to sustain the VCC voltage. For these conditions, use a series

blocking diode between the input supply and the VIN pin (Figure 20). This prevents VCC from back-feeding into

VIN through the body diode of the VCC regulator.

A 1-µF capacitor to PGND is required to supply the VCC regulator load transients.

Figure 20. VCC Regulator

ss C 0.8 V

t5 A

RUV2

RUV1

VIN

EN/UVLO

LM5175

HYS(UV) UV2

V 3.5 A R' P u

UV2

IN(UV) UV2

UV1

V 1.23 V 1 R 1.5 A

§ ·

u   u P

¨ ¸

LM5175

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Feature Description (continued)

8.3.3 Enable/UVLO

The LM5175 has a dual function enable and undervoltage lockout (UVLO) circuit. The EN/UVLO pin has three

distinct voltage ranges: shutdown, standby, and operating (see Shutdown, Standby, and Operating Modes).

When the EN/UVLO pin is below the standby threshold (0.7 V typical), the converter is held in a low power

shutdown mode. When EN/UVLO voltage is greater than the standby threshold but less than the 1.23 V

operating threshold, the internal bias rails and the VCC regulator are enabled but the soft-start (SS) pin is held

low and the PWM controller is disabled. A 1.5 µA pull-up current is sourced out of the EN/UVLO pin in standby

mode to provide hysteresis between the shutdown mode and the standby mode. When EN/UVLO is greater than

the 1.23 V operating threshold, the controller commences operation if VCC is above VCC UV threshold (3.3 V). A

hysteresis current of 3.5 µA is sourced into the EN/UVLO pin when the EN/UVLO input exceeds the 1.23 V

operation threshold to provide hysteresis that prevents on/off chattering in the presence of noise with a slowly

changing input voltage.

The VIN undervoltage lockout turn-on threshold is typically set by a resistor divider from the VIN pin to AGND with

the mid-point of the divider connected to EN/UVLO. The turn-on threshold VINUV is calculated using Equation 1

where RUV2 is the upper resistor and RUV1 is the lower resistor in the EN/UVLO resistor divider:

(1)

The hysteresis between the UVLO turn-on threshold and turn-off threshold is set by the upper resistor in the

EN/UVLO resistor divider and is given by:

(2)

Figure 21. UVLO Threshold Programming

8.3.4 Soft-Start

The LM5175 soft-start time is programmed using a soft-start capacitor from the SS pin to AGND. When the

converter is enabled, an internal 5-µA current source charges the soft-start capacitor. When the SS pin voltage is

below the 0.8-V feedback reference voltage VREF, the soft-start pin controls the regulated FB voltage. Once SS

exceeds VREF, the soft-start interval is complete and the error amplifier is referenced to VREF. The soft-start time

is given by Equation 3:

(3)

The soft-start capacitor is internally discharged when the converter is disabled because of EN/UVLO falling

below the operation threshold or VCC falling below the VCC UV threshold. The soft-start pin is also discharged

when the converter is in hiccup mode current limiting or in thermal shutdown. When average input or output

current limiting is active, the soft-start capacitor is discharged by the constant current loop transconductance

(gm) amplifier to limit either input or output current.

1200 ns

R37 pF

§ · 

¨ ¸

CL(AVG) SNS

50 mV

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Feature Description (continued)

8.3.5 Overcurrent Protection

The LM5175 provides cycle-by-cycle current limit to protect against overcurrent and short circuit conditions. In

buck operation, the sensed valley voltage across the CSG and CS pins is limited to 76 mV. The high-side buck

switch skips a cycle if the sensed voltage does not fall below this threshold during the buck switch off time. In

boost operation, the maximum peak voltage across CS and CSG is limited to 170mV. If the peak current in the

low-side boost switch causes the CS pin to exceed this threshold voltage, the boost switch is turned off for the

remainder of the clock cycle.

Applying the appropriate voltage to the MODE pin of the LM5175 enables hiccup mode fault protection (see

MODE Pin Configuration). In the hiccup mode, the controller shuts down after detecting cycle-by-cycle current

limiting for 128 consecutive cycles and the soft-start capacitor is discharged. The soft-start capacitor is

automatically released after 4000 oscillator clock cycles and the controller restarts. If hiccup mode protection is

not enabled through the MODE pin, the LM5175 will operate in cycle-by-cycle current limiting as long as the

overload condition persists.

8.3.6 Average Input/Output Current Limiting

The LM5175 provides optional average current limiting capability to limit either the input or the output current of

the DC/DC converter. The average current limiting circuit uses an additional current sense resistor connected in

series with the input supply or output voltage of the converter. A current sense gm amplifier with inputs at the

ISNS(+) and ISNS(-) pins monitors the voltage across the sense resistor and compares it with an internal 50 mV

reference. If the drop across the sense resistor is greater than 50 mV, the gm amplifier gradually discharges the

soft-start capacitor. When the soft-start capacitor discharges below the 0.8-V feedback reference voltage VREF,

the output voltage of the converter decreases to limit the input or output current. The average current limiting

feature can be used in applications requiring a regulated current from the input supply or into the load. The target

constant current is given by Equation 4:

(4)

The average current loop can be disabled by shorting the ISNS(+) and ISNS(-) pins together.

8.3.7 CCM/DCM Operation

The LM5175 allows selection of continuous conduction mode (CCM) or discontinuous conduction mode (DCM)

operation using the MODE pin (see MODE Pin Configuration). In CCM operation the inductor current can flow in

either direction and the controller switches at a fixed frequency regardless of the load current. This mode is

useful for noise-sensitive applications where a fixed switching eases filter design. In DCM operation the

synchronous rectifier MOSFETs emulate diodes as LDRV1 or HDRV2 turn-off for the remainder of the PWM

cycle when the inductor current reaches zero. The DCM mode results in reduced frequency operation at light

loads, which lowers switching losses and increases light load efficiency of the converter.

8.3.8 Frequency and Synchronization (RT/SYNC)

The LM5175 switching frequency can be programmed between 100 kHz and 600 kHz using a resistor from the

RT/SYNC pin to AGND. The RTresistor is related to the nominal switching frequency (Fsw) by the following

equation:

(5)

Figure 3 in the Typical Characteristics shows the relationship between the programmed switching frequency (Fsw)

and the RTresistor.

The RT/SYNC pin can also be used for synchronizing the internal oscillator to an external clock signal. The

external synchronization pulse is ac coupled using a capacitor to the RT/SYNC pin. The voltage at the RT/SYNC

pin must not exceed 3.3 V peak. The external synchronization pulse frequency should be higher than the

internally set oscillator frequency and the pulse width should be between 75 ns and 500 ns.

DITH

LM5175

CDITH

1.22 V

1.22 V - 5 %

1.22 V + 5%

DITH MOD

10 A

CF 0.24 V

external SYNC RT/SYNC

LM5175

CSYNC

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Feature Description (continued)

Figure 22. Using External SYNC

8.3.9 Frequency Dithering

The LM5175 provides an optional frequency dithering function that is enabled by connecting a capacitor from

DITH to AGND. Figure 23 illustrates the dithering circuit. A triangular waveform centered at 1.22 V is generated

across the CDITH capacitor. This triangular waveform modulates the oscillator frequency by ±5% of the nominal

frequency set by the RTresistor. The CDITH capacitance value sets the rate of the low frequency modulation. A

lower CDITH capacitance will modulate the oscillator frequency at a faster rate than a higher capacitance. For the

dithering circuit to effectively reduce peak EMI, the modulation rate must be much less than the oscillator

frequency (Fsw). Equation 6 calculates the DITH pin capacitance required to set the modulation frequency, FMOD.

Connecting the DITH pin directly to AGND disables frequency dithering, and the internal oscillator operates at a

fixed frequency set by the RT resistor. Dither is disabled when external SYNC is used.

(6)

Figure 23. Dither Operation

8.3.10 Output Overvoltage Protection (OVP)

The LM5175 provides an output overvoltage protection (OVP) circuit that turns off the gate drives when the

feedback voltage is 7.5% above the 0.8 V feedback reference voltage VREF. Switching resumes once the output

falls within 5% of VREF.

8.3.11 Power Good (PGOOD)

PGOOD is an open drain output that is pulled low when the voltage at the FB pin is outside -9% / +10% of the

nominal 0.8-V reference voltage. The PGOOD internal N-Channel MOSFET pull-down strength is typically 4.2

mA. This pin can be connected to a voltage supply of up to 8 V through a pull-up resistor.

BOOST OUT

D 1 V



 

OUT IN

COMP(BOOST) CS SENSE OUT BOOST BOOST

IN sw SLOPE sw

2 S V V 5 A

V 1.6V A R I D D

V 2 L1 F C F

P ˜   P

§ ·

 ˜ ˜ ˜  ˜  ˜

¨ ¸

˜ ˜ ˜

OUT

BUCK IN

     

IN OUT

OUT

COMP(BUCK) CS SENSE BUCK BUCK

sw SLOPE sw

2 S V V 6 A

V 1.6 V A R 1 D 1 D

2 L1 F C F

P ˜   P

 ˜ ˜ ˜   ˜ 

˜ ˜ ˜

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Feature Description (continued)

8.3.12 Gm Error Amplifier

The LM5175 has a gm error amplifier for loop compensation. The gm amplifier output (COMP) range is 0.3 V to

3 V. Connect an Rc1-Cc1 compensation network between COMP and ground for type II (PI) compensation (see

Figure 24). Another pole is usually added using Cc2 to suppress higher frequency noise.

The COMP output voltage (VCOMP) range limits the possible VIN and IOUT range for a given design. In buck mode,

the maximum VIN for which the converter can regulate the output at no load is when VCOMP reaches 0.3 V.

Equation 7 gives VCOMP as a function of VIN at no load in CCM buck mode:

(7)

Where DBUCK in the equation Equation 7 is the buck duty cycle given by:

(8)

A larger L1, lower slope ripple (higher CSLOPE), smaller sense resistor (RSENSE), and higher frequency can

increase the maximum VIN range for buck operation.

For boost mode, the minimum VIN for which the converter can regulate the output at full load is when VCOMP

reaches 3 V. Equation 9 gives VCOMP as a function of VIN in boost mode:

(9)

Where DBOOST in the Equation 9 is the boost duty cycle given by:

(10)

A larger L1, lower slope ripple (higher CSLOPE), smaller sense resistor (RSENSE), and higher frequency can extend

the minimum VIN range for boost operation.

8.3.13 Integrated Gate Drivers

The LM5175 provides four N-channel MOSFET gate drivers: two floating high-side gate drivers at the HDRV1

and HDRV2 pins, and two ground referenced low-side drivers at the LDRV1 and LDRV2 pins. Each driver is

capable of sourcing 1.5 A and sinking 2 A peak current. In buck operation, LDRV1 and HDRV1 are switched by

the PWM controller while HDRV2 remains continuously on. In boost operation, LDRV2 and HDRV2 are switched

while HDRV1 remains continuously on.

In DCM buck operation, LDRV1 and HDRV2 turn off when the inductor current drops to zero (diode emulation).

In a DCM boost operation, HDRV2 turns off when inductor current drops to zero.

The gate drive output HDRV2 remains off during soft-start to prevent reverse current flow from a pre-biased

output.

The low-side gate drivers are powered from VCC and the high-side gate drivers HDRV1 and HDRV2 are

powered from bootstrap capacitors CBOOT1 (between BOOT1 and SW1) and CBOOT2 (between BOOT2 and SW2)

respectively. The CBOOT1 and CBOOT2 capacitors are charged through external Schottky diodes connected to the

VCC pin as shown in Figure 24.

8.3.14 Thermal Shutdown

The LM5175 is protected by a thermal shutdown circuit that shuts down the device when the internal junction

temperature exceeds 165°C (typical). The soft-start capacitor is discharged when thermal shutdown is triggered

and the gate drivers are disabled. The converter automatically restarts when the junction temperature drops by

the thermal shutdown hysteresis of 15°C below the thermal shutdown threshold.

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8.4 Device Functional Modes

Please refer to Enable/UVLO section for the description of EN/UVLO pin function. Shutdown, Standby, and

Operating Modes section lists the shutdown, standby, and operating modes for LM5175 as a function of

EN/UVLO and VCC voltages.

8.4.1 Shutdown, Standby, and Operating Modes

EN/UVLO VCC DEVICE MODE

EN/UVLO < 0.7 V — Shutdown: VCC off, No switching

0.7 V < EN/UVLO < 1.23 V — Standby: VCC on, No switching

EN/UVLO > 1.23 V VCC < 3.3 V Standby: VCC on, No switching

EN/UVLO > 1.23 V VCC > 3.3 V Operating: VCC on, Switching enabled

8.4.2 MODE Pin Configuration

The MODE pin is used to select CCM/DCM operation and hiccup mode current limit. Mode is latched at startup.

MODE PIN CONNECTION LIGHT LOAD MODE HICCUP FAULT PROTECTION

Connect to VCC CCM No Hiccup

RMODE to AGND = 93.1 kΩCCM Hiccup Enabled

RMODE to AGND = 49.9 kΩDCM Hiccup Enabled

Connect to AGND DCM No Hiccup

LM5175

RUV2

MODE

DITH

RT/SYNC

SLOPE

CSLOPE

CSS

Cc2

Cc1

Rc1

RRB2

RRB1

COMP

AGND

VOSNS

ISNS(+)ISNS(-)

CSG

PGOOD

SW2

HDRV2

BOOT2

LDRV2

PGND

VCC

BIAS

LDRV1

CBIAS

CVCC

CBOOT2

EN/UVLO VINSNS VIN

SW1

HDRV1

BOOT1

CSYNC

VOUT

CBOOT1

RUV1

VCC

RMODE

VCC

RSNS VOUT

VIN

CIN CIN

QH1 QH2

QL1 QL2

RSENSE

COUT COUT

CVIN

93.1 NŸ

84.5 NŸ

0.1 µF

1 µF

100 pF

22 nF

10 NŸ

100 pF

20 NŸ

280 NŸ

0.1 µF

8 PŸ

0 Ÿ

10 µF

x5 180 µF

4.7 µF

10 Ÿ

0.1 µF

1 µF 100 Ÿ100 Ÿ

249 NŸ

59.0 NŸ

68 µF

10 NŸ

1 nF

100 Ÿ

47 pF

4.7 µH

LM5175

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9 Application and Implementation

NOTE

Information in the following applications sections is not part of the TI component

specification, and TI does not warrant its accuracy or completeness. TI’s customers are

responsible for determining suitability of components for their purposes. Customers should

validate and test their design implementation to confirm system functionality.

9.1 Application Information

The LM5175 is a four-switch buck-boost controller. A quick-start tool on the LM5175 product webpage can be

used to design a buck-boost converter using the LM5175. Alternatively, Webench®software can create a

complete buck-boost design using the LM5175 and generate bill of materials, estimate efficiency, solution size,

and cost of the complete solution. The following sections describe a detailed step-by-step design procedure for a

typical application circuit.

9.2 Typical Application

A typical application example is a buck-boost converter operating from a wide input voltage range of 6 V to 36 V

and providing a stable 12 V output voltage with current capability of 6 A.

Figure 24. LM5175 Four-Switch Buck Boost Application Schematic

IN(MAX) OUT OUT

BUCK OUT(MAX) sw IN(MAX)

(V V ) V

L 11.1 H

0.4 I F V

 u

u u u

OUT

FB2 FB1

V 0.8 V

R R 280 k

0.8 V



u :

FB1

R 20 k :

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Typical Application (continued)

9.2.1 Design Requirements

For this design example, the following are used as the input parameters.

DESIGN PARAMETER EXAMPLE VALUE

Input Voltage Range 6 V to 36 V

Output 12 V

Load Current 6 A

Switching Frequency 300 kHz

Mode CCM, Hiccup

9.2.2 Detailed Design Procedure

9.2.2.1 Custom Design with WEBENCH Tools

Click here to create a custom design using the LM5175 device with the WEBENCH®Power Designer.

1. Start by entering your VIN, VOUT and IOUT requirements.

2. Optimize your design for key parameters like efficiency, footprint and cost using the optimizer dial and

compare this design with other possible solutions from Texas Instruments.

3. WEBENCH Power Designer provides you with a customized schematic along with a list of materials with real

time pricing and component availability.

4. In most cases, you will also be able to:

– Run electrical simulations to see important waveforms and circuit performance,

– Run thermal simulations to understand the thermal performance of your board,

– Export your customized schematic and layout into popular CAD formats,

– Print PDF reports for the design, and share your design with colleagues.

5. Get more information about WEBENCH tools at www.ti.com/webench.

9.2.2.2 Frequency

The switching frequency of LM5175 is set by an RTresistor connected from RT/SYNC pin to AGND. The RT

resistor required to set the desired frequency is calculated using Equation 5 or Figure 3 . A 1% standard resistor

of 84.5 kΩis selected for Fsw = 300 kHz.

9.2.2.3 VOUT

The output voltage is set using a resistor divider to the FB pin. The internal reference voltage is 0.8 V. Normally

the bottom resistor in the resistor divider is selected to be in the 1 kΩto 100 kΩrange. Select

(11)

The top resistor in the feedback resistor divider is selected using Equation 12:

(12)

9.2.2.4 Inductor Selection

The inductor selection is based on consideration of both buck and boost modes of operation. For the buck mode,

inductor selection is based on limiting the peak to peak current ripple ΔILto ~40% of the maximum inductor

current at the maximum input voltage. The target inductance for the buck mode is:

(13)

For the boost mode, the inductor selection is based on limiting the peak to peak current ripple ΔILto ~40% of the

maximum inductor current at the minimum input voltage. The target inductance for the boost mode is:

CIN(RMS) OUT

I I D (1 D) u 

IN(MIN)

OUT OUT

RIPPLE(COUT) OUT sw

I 1 V

VC F

§ ·

u 

¨ ¸

' u

OUT OUT

RIPPLE(ESR) IN(MIN)

I V

V ESR

' u

OUT

COUT(RMS) OUT IN

I I 1

u 

L(PEAK)

L(SAT) 1.2 I

I 21.6 A

0.8

IN(MIN) OUT IN(MIN)

L(PEAK) L(MAX) sw OUT

V (V V )

I I 14.4 A

2 L1 F V

u 



u u u

OUT OUT(MAX)

L(MAX) IN(MIN)

V I

I 13.3 A

0.9 V

IN(MIN) OUT IN(MIN)

BOOST 2

OUT(MAX) sw OUT

V (V V )

L 2.1 H

0.4 I F V

u 

u u u

LM5175

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(14)

In this particular application, the buck inductance is larger. Choosing a larger inductance reduces the ripple

current but also increases the size of the inductor. A larger inductor also reduces the achievable bandwidth of the

converter by moving the right half plane zero to lower frequencies. Therefore a judicious compromise should be

made based on the application requirements. For this design a 4.7-µH inductor is selected. With this inductor

selection, the inductor current ripple is 5.7 A, 4.3 A, and 2.1 A, at VIN of 36 V, 24 V, and 6 V respectively.

The maximum average inductor current occurs at the minimum input voltage and maximum load current:

(15)

where a 90% efficiency is assumed. The peak inductor current occurs at minimum input voltage and is given by:

(16)

To ensure sufficient output current, the current limit threshold must be set to allow the maximum load current in

boost operation. To ensure that the inductor does not saturate in current limit, the peak saturation current of the

inductor should be higher than the maximum current limit. Adjusting for a ±20% current limit threshold tolerance,

the peak inductor current limit is:

(17)

Therefore, the inductor saturation current should be greater than 21.6 A. If hiccup mode protection is not

enabled, the RMS current rating of the inductor should be sufficient to tolerate continuous operation in cycle-by-

cycle current limiting.

9.2.2.5 Output Capacitor

In the boost mode, the output capacitor conducts high ripple current. The output capacitor RMS ripple current is

given by Equation 18 where the minimum VIN corresponds to the maximum capacitor current.

(18)

In this example the maximum output ripple RMS current is ICOUT(RMS) = 6 A. A 5-mΩoutput capacitor ESR

causes an output ripple voltage of 60 mV as given by:

(19)

A 400 µF output capacitor causes a capacitive ripple voltage of 25 mV as given by:

(20)

Typically a combination of ceramic and bulk capacitors is needed to provide low ESR and high ripple current

capacity. The complete schematic in Figure 24 at the end of this section shows a good starting point for COUT for

typical applications.

9.2.2.6 Input Capacitor

In the buck mode, the input capacitor supplies high ripple current. The RMS current in the input capacitor is given

by:

(21)

SENSE(BOOST) L(PEAK)

170 mV 70%

R 8.2 m

SENSE(BUCK) OUT(MAX)

76 mV 70%

R 8.8 m

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The maximum RMS current occurs at D = 0.5, which gives ICIN(RMS) = IOUT/2 = 3 A. A combination of ceramic and

bulk capacitors should be used to provide short path for high di/dt current and to reduce the output voltage ripple.

The complete schematic in Figure 24 is a good starting point for CIN for typical applications.

9.2.2.7 Sense Resistor (RSENSE)

The current sense resistor between the CS and CSG pins should be selected to ensure that current limit is set

high enough for both buck and boost modes of operation. For the buck operation, the current limit resistor is

given by:

(22)

For the boost mode of operation, the current limit resistor is given by:

(23)

The closest standard value of RSENSE =8mΩis selected based on the boost mode operation.

DITH MOD

10 A

CF 0.24 V

ss 0.8 V C

t5 A

 

UV2

UV1 IN UV2

R 1.23 V

R 59.5 k

V 1.5 A R 1.23 V

 P u 

SLOPE SLOPE SENSE CS

L1 4.7 H

C gm 2 S 235pF

R A 8m 5

u P u

u : u

2IN(MIN)

RSENSE(MAX) SENSE

SENSE OUT

170mV

P R 1 1.8W

R V

§ ·

˜ ˜ 

¨ ¸

¨ ¸ ¨ ¸

LM5175

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The maximum power dissipation in RSENSE happens at VIN(MIN):

(24)

Based on this, select the current sense resistor with power rating of 2 W or higher.

For some application circuits, it may be required to add a filter network to attenuate noise in the CS and CSG

sense lines. Please see Figure 24 for typical values. The filter resistance should not exceed 100 Ω.

9.2.2.8 Slope Compensation

For stable current loop operation and to avoid sub-harmonic oscillations, the slope capacitor should be selected

based on Equation 25:

(25)

This slope compensation results in “dead-beat” operation, in which the current loop disturbances die out in one

switching cycle. Theoretically a current mode loop is stable with half the “dead-beat” slope (twice the calculated

slope capacitor value in Equation 25). A smaller slope capacitor results in larger slope signal which is better for

noise immunity in the transition region (VIN~VOUT). A larger slope signal, however, restricts the achievable input

voltage range for a given output voltage, switching frequency, and inductor. For this design CSLOPE = 100 pF is

selected for better transition region behavior while still providing the required VIN range. This selection of slope

capacitor, inductor, switching frequency, and inductor satisfies the COMP range limitation explained in Gm Error

Amplifier section.

9.2.2.9 UVLO

The UVLO resistor divider must be designed for turn-on below 6V. Selecting a RUV2 = 249 kΩgives a UVLO

hysteresis of 0.8 V. The lower UVLO resistor is the selected using Equation 26:

(26)

A standard value of 59.0 kΩis selected for RUV1.

When programming the UVLO threshold for lower input voltage operation, it is important to choose MOSFETs

with gate (Miller) plateau voltage lower than the minimum VIN.

9.2.2.10 Soft-Start Capacitor

The soft-start time is programmed using the soft-start capacitor. The relationship between CSS and the soft-start

time is given by:

(27)

CSS = 0.1 µF gives a soft-start time of 16 ms.

9.2.2.11 Dither Capacitor

The dither capacitor sets the modulation frequency of the frequency dithering around the nominal switching

frequency. A larger CDITH results in lower modulation frequency. For proper operation the modulation frequency

(FMOD) must be much lower than the switching frequency. Use Equation 28 to select CDITH for the target

modulation frequency.

(28)

For the current design dithering is not being implemented. Therefore a 0 Ωresistor from the DITH pin to AGND

disables this feature.

OUT

COND(QH2) OUT DSON(QH2)

OUT IN

P I R

V V

§ ·

˜ ˜ ˜

¨ ¸

 

OUT

SW(QL2) OUT OUT r f sw

P V I t t F

2 V

§ ·

˜ ˜ ˜ ˜  ˜

¨ ¸

OUT

COND(QL2) OUT DSON(QL2)

OUT IN

P 1 I R

V V

§ · § ·

 ˜ ˜ ˜

¨ ¸ ¨ ¸

COND(QH2) OUT DSON(QH2)

P I R ˜

OUT

COND(QL1) OUT DSON(QL1)

P 1 I R

§ ·

 ˜ ˜

¨ ¸

 

SW(QH1) IN OUT r f sw

P V I t t F

˜ ˜ ˜  ˜

OUT

COND(QH1) OUT DSON(QH1)

P I R

§ ·

˜ ˜

¨ ¸

OUT

COND(QH1) OUT DSON(QH1)

P I R

§ ·

˜ ˜

¨ ¸

LM5175

www.ti.com

SNVSA37A –OCTOBER 2015–REVISED MAY 2016

Product Folder Links: LM5175

9.2.2.12 MOSFETs QH1 and QL1

The input side MOSFETs QH1 and QL1 need to withstand the maximum input voltage of 36 V. In addition they

must withstand the transient spikes at SW1 during switching. Therefore QH1 and QL1 should be rated for 60 V.

The gate plateau voltages of the MOSFETs should be smaller than the minimum input voltage of the converter,

otherwise the MOSFETs may not fully enhance during startup or overload conditions.

The power loss in QH1 in the boost mode of operation is approximated by:

(29)

The power loss in QH1 in the buck mode of operation consists of both conduction and switching loss

components given by Equation 30 and Equation 31 respectively:

(30)

(31)

The rise (tr) and the fall (tf) times are based on the MOSFET datasheet information or measured in the lab.

Typically a MOSFET with smaller RDSON (smaller conduction loss) will have longer rise and fall times (larger

switching loss).

The power loss in QL1 in the buck mode of operation is given by the following equation:

(32)

9.2.2.13 MOSFETs QH2 and QL2

The output side MOSFETs QH2 and QL2 see the output voltage of 12 V and additional transient spikes at SW2

during switching. Therefore QH2 and QL2 should be rated for 20 V or more. The gate plateau voltages of the

MOSFETs should be smaller than the minimum input voltage of the converter, otherwise the MOSFETs may not

fully enhance during startup or overload conditions.

The power loss in QH2 in the buck mode of operation is approximated by:

(33)

The power loss in QL2 in the boost mode of operation consists of both conduction and switching loss

components given by Equation 34 and Equation 35 respectively:

(34)

(35)

The rise (tr) and the fall (tf) times can be based on the MOSFET datasheet information or measured in the lab.

Typically a MOSFET with smaller RDSON (lower conduction loss) has longer rise and fall times (larger switching

loss).

The power loss in QH2 in the boost mode of operation is given by the following equation:

(36)

c1 zc c1

C 27.9 nF

 ¦ 5

u S u u

bw CS SENSE OUT

FB1 FB2

c1 EA FB1 MAX

 ¦ $ 5 &

R R

R 9.49 k

gm R 1 D

S u u u



u u :



¦  +]

¦  N+]

p1(buck) OUT OUT

1 1

¦  +]

2 R C

§ ·

¨ ¸

S u

OUT MAX

RHP R (1 D )

¦  N+]

2 L1

§ ·

u 

¨ ¸

S© ¹

z1 ESR OUT

1 1

¦  N+]

2 R C

§ ·

¨ ¸

S u

p1(boost) OUT OUT

1 2

¦  +]

2 R C

§ ·

¨ ¸

S u

LM5175

SNVSA37A –OCTOBER 2015–REVISED MAY 2016

www.ti.com

Product Folder Links: LM5175

9.2.2.14 Frequency Compensation

This section presents the control loop compensation design procedure for the LM5175 buck-boost controller. The

LM5175 operates mainly in buck or boost modes, separated by a transition region, and therefore the control loop

design is done for both buck and boost operating modes. Then a final selection of compensation is made based

on the mode that is more restrictive from a loop stability point of view. Typically for a converter designed to go

deep into both buck and boost operating regions, the boost compensation design is more restrictive due to the

presence of a right half plane zero (RHPZ) in the boost mode.

The boost power stage output pole location is given by:

(37)

where ROUT = 2 Ωcorresponds to the maximum load of 6 A.

The boost power stage ESR zero location is given by:

(38)

The boost power stage RHP zero location is given by:

(39)

where DMAX is the maximum duty cycle at the minimum VIN.

The buck power stage output pole location is given by:

(40)

The buck power stage ESR zero location is the same as the boost power stage ESR zero.

It is clear from Equation 39 that RHP zero is the main factor limiting the achievable bandwidth. For a robust

design the crossover frequency should be less than 1/3 of the RHP zero frequency. Given the position of the

RHP zero, a reasonable target bandwidth in boost operation is around 4 kHz:

(41)

For some power stages, the boost RHP zero might not be as restrictive. This happens when the boost maximum

duty cycle (DMAX) is small, or when a really small inductor is used. In those cases, compare the limits posed by

the RHP zero (fRHP/3) with 1/20 of the switching frequency and use the smaller of the two values as the

achievable bandwidth.

The compensation zero can be placed at 1.5 times the boost output pole frequency. Keep in mind that this

locates the zero at 3 times the buck output pole frequency which results in approximately 30 degrees of phase

loss before crossover of the buck loop and 15 degrees of phase loss at intermediate frequencies for the boost

loop:

(42)

If the crossover frequency is well below the RHP zero and the compensation zero is placed well below the

crossover, the compensation gain resistor Rc1 is calculated using the approximation:

(43)

where DMAX is the maximum duty cycle at the minimum VIN in boost mode and ACS is the current sense amplifier

gain. The compensation capacitor Cc1 is then calculated from:

(44)

The standard values of compensation components are selected to be Rc1 = 10 kΩand Cc1 = 22 nF.

LOAD CURRENT (A)

EFFICIENCY (%)

0 1 2 3 4 5 6

100

D008

VIN=6V

VIN=12V

VIN=24V

LM5175

www.ti.com

SNVSA37A –OCTOBER 2015–REVISED MAY 2016

Product Folder Links: LM5175

A high frequency pole is added to suppress switching noise using a 100 pF capacitor (Cc2) in parallel with Rc1

and Cc1. These values provide a good starting point for the compensation design. Each design should be tuned

in the lab to achieve the desired balance between stability margin across the operating range and transient

response time.

9.2.3 Application Curves

Figure 25. Efficiency vs Load Figure 26. Output Voltage Ripple

Figure 27. Load Transient Response Figure 28. Line Transient Response (8 V - 24 V, IOUT = 2 A)

LM5175

SNVSA37A –OCTOBER 2015–REVISED MAY 2016

www.ti.com

Product Folder Links: LM5175

10 Power Supply Recommendations

The LM5175 is a power management device. The power supply for the device is any dc voltage source within the

specified input range. The supply should also be capable of supplying sufficient current based on the maximum

inductor current in boost mode operation. The input supply should be bypassed with additional electrolytic

capacitor at the input of the application board to avoid ringing due to parasitic impedance of the connecting

cables.

11 Layout

11.1 Layout Guidelines

The basic PCB board layout requires separation of sensitive signal and power paths. The following checklist

should be followed to get good performance for a well designed board.

• Place the power components including the input filter capacitor CIN, the power MOSFETs QL1 and QH1, and

the sense resistor RSENSE close together to minimize the loop area for input switching current in buck

operation.

• Place the power components including the output filter capacitor COUT, the power MOSFETs QL2 and QH2,

and the sense resistor RSENSE close together to minimize the loop area for output switching current in boost

operation.

• Use a combination of bulk capacitors and smaller ceramic capacitors with low series impedance for the input

and output capacitors. Place the smaller capacitors closer to the IC to provide a low impedance path for high

di/dt switching currents.

• Minimize the SW1 and SW2 loop areas as these are high dv/dt nodes.

• Layout the gate drive traces and return paths as directly as possible. Layout the forward and return traces

close together, either running side by side or on top of each other on adjacent layers to minimize the

inductance of the gate drive path.

• Use Kelvin connections to RSENSE for the current sense signals CS and CSG and run lines in parallel from the

RSENSE terminals to the IC pins. Avoid crossing noisy areas such as SW1 and SW2 nodes or high-side gate

drive traces. Place the filter capacitor for the current sense signal as close to the IC pins as possible.

• Place the CIN, COUT, and RSENSE ground pins as close as possible with thick ground trace and/or planes on

multiple layers.

• Place the VCC bypass capacitor close to the controller IC, between the VCC and PGND pins. A 1-µF ceramic

capacitor is typically used.

• Place the BIAS bypass capacitor close to the controller IC, between the BIAS and PGND pins. A 0.1-µF

ceramic capacitor is typically used.

• Place the BOOT1 bootstrap capacitor close to the IC and connect directly to the BOOT1 to SW1 pins.

• Place the BOOT2 bootstrap capacitor close to the IC and connect directly to the BOOT2 to SW2 pins.

• Bypass the VIN pin to AGND with a low ESR ceramic capacitor located close to the controller IC. A 0.1 µF

ceramic capacitor is typically used. When using external BIAS, use a diode between input rails and VIN pins to

prevent reverse conduction when VIN < VCC.

• Connect the feedback resistor divider between the COUT positive terminal and AGND pin of the IC. Place the

components close to the FB pin.

• Use care to separate the power and signal paths so that no power or switching current flows through the

AGND connections which can either corrupt the COMP, SLOPE, or SYNC signals, or cause dc offset in the

FB sense signal. The PGND and AGND traces can be connected near the PGND pin, near the VCC

capacitor PGND connection, or near the PGND connection of the CS, CSG pin current sense resistor.

• When using the average current loop, divide the overall capacitor (CIN or COUT) between the two sides of the

sense resistor to ensure small cycle-by-cycle ripple. Place the average current loop filter capacitor close to

the IC between the ISNS(+) and ISNS(-) pins.

LM5175

VIN

GND

VOUT

GND

SW1 SW2

RSENSE

QL1 QL2

QH1 QH2 RISNS

COUTCIN CIN COUT

LM5175

www.ti.com

SNVSA37A –OCTOBER 2015–REVISED MAY 2016

Product Folder Links: LM5175

11.2 Layout Example

Figure 29. LM5175 Power Stage Layout

LM5175

SNVSA37A –OCTOBER 2015–REVISED MAY 2016

www.ti.com

Product Folder Links: LM5175

12 Device and Documentation Support

12.1 Custom Design with WEBENCH Tools

Click here to create a custom design using the LM5175 device with the WEBENCH®Power Designer.

1. Start by entering your VIN, VOUT and IOUT requirements.

2. Optimize your design for key parameters like efficiency, footprint and cost using the optimizer dial and

compare this design with other possible solutions from Texas Instruments.

3. WEBENCH Power Designer provides you with a customized schematic along with a list of materials with real

time pricing and component availability.

4. In most cases, you will also be able to:

– Run electrical simulations to see important waveforms and circuit performance,

– Run thermal simulations to understand the thermal performance of your board,

– Export your customized schematic and layout into popular CAD formats,

– Print PDF reports for the design, and share your design with colleagues.

5. Get more information about WEBENCH tools at www.ti.com/webench.

12.2 Receiving Notification of Documentation Updates

To receive notification of documentation updates, navigate to the device product folder on ti.com. In the upper

right corner, click on Alert me to register and receive a weekly digest of any product information that has

changed. For change details, review the revision history included in any revised document.

12.3 Documentation Support

12.3.1 Related Documentation

Please visit TI homepage for latest technical document including application notes, user guides, and reference

designs.

IC Package Thermal Metrics application report, SPRA953.

12.4 Community Resources

The following links connect to TI community resources. Linked contents are provided "AS IS" by the respective

contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of

Use.

TI E2E™ Online Community TI's Engineer-to-Engineer (E2E) Community. Created to foster collaboration

among engineers. At e2e.ti.com, you can ask questions, share knowledge, explore ideas and help

solve problems with fellow engineers.

Design Support TI's Design Support Quickly find helpful E2E forums along with design support tools and

contact information for technical support.

12.5 Trademarks

PowerPAD, E2E are trademarks of Texas Instruments.

Webench, WEBENCH are registered trademarks of Texas Instruments.

All other trademarks are the property of their respective owners.

12.6 Electrostatic Discharge Caution

These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam

during storage or handling to prevent electrostatic damage to the MOS gates.

12.7 Glossary

SLYZ022 —TI Glossary.

This glossary lists and explains terms, acronyms, and definitions.

LM5175

www.ti.com

SNVSA37A –OCTOBER 2015–REVISED MAY 2016

Product Folder Links: LM5175

13 Mechanical, Packaging, and Orderable Information

The following pages include mechanical, packaging, and orderable information. This information is the most

current data available for the designated devices. This data is subject to change without notice and revision of

this document. For browser-based versions of this data sheet, refer to the left-hand navigation.

PACKAGE OPTION ADDENDUM

www.ti.com 10-Dec-2020

Addendum-Page 1

PACKAGING INFORMATION

Orderable Device Status

(1)

Package Type Package

Drawing Pins Package

Qty Eco Plan

(2)

Lead finish/

Ball material

(6)

MSL Peak Temp

(3)

Op Temp (°C) Device Marking

(4/5)

Samples

LM5175PWPR ACTIVE HTSSOP PWP 28 2000 RoHS & Green NIPDAU Level-3-260C-168 HR -40 to 125 LM5175

LM5175PWPT ACTIVE HTSSOP PWP 28 250 RoHS & Green NIPDAU Level-3-260C-168 HR -40 to 125 LM5175

LM5175RHFR ACTIVE VQFN RHF 28 3000 RoHS & Green NIPDAU Level-2-260C-1 YEAR -40 to 125 LM5175

LM5175RHFT ACTIVE VQFN RHF 28 250 RoHS & Green NIPDAU Level-2-260C-1 YEAR -40 to 125 LM5175

(1) The marketing status values are defined as follows:

ACTIVE: Product device recommended for new designs.

LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.

NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.

PREVIEW: Device has been announced but is not in production. Samples may or may not be available.

OBSOLETE: TI has discontinued the production of the device.

(2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance

do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may

reference these types of products as "Pb-Free".

RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.

Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based

flame retardants must also meet the <=1000ppm threshold requirement.

(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.

(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.

(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation

of the previous line and the two combined represent the entire Device Marking for that device.

(6) Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two

lines if the finish value exceeds the maximum column width.

Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information

provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and

PACKAGE OPTION ADDENDUM

www.ti.com 10-Dec-2020

Addendum-Page 2

continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.

TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.

In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.

OTHER QUALIFIED VERSIONS OF LM5175 :

•Automotive: LM5175-Q1

NOTE: Qualified Version Definitions:

•Automotive - Q100 devices qualified for high-reliability automotive applications targeting zero defects

TAPE AND REEL INFORMATION

*All dimensions are nominal

Device Package

Type Package

Drawing Pins SPQ Reel

Diameter

(mm)

Reel

Width

W1 (mm)

(mm) B0

(mm) K0

(mm) P1

(mm) W

(mm) Pin1

Quadrant

LM5175PWPR HTSSOP PWP 28 2000 330.0 16.4 6.9 10.2 1.8 12.0 16.0 Q1

LM5175PWPT HTSSOP PWP 28 250 180.0 16.4 6.9 10.2 1.8 12.0 16.0 Q1

LM5175RHFR VQFN RHF 28 3000 330.0 12.4 4.3 5.3 1.3 8.0 12.0 Q1

LM5175RHFT VQFN RHF 28 250 180.0 12.4 4.3 5.3 1.3 8.0 12.0 Q1

PACKAGE MATERIALS INFORMATION

www.ti.com 16-Feb-2019

Pack Materials-Page 1

*All dimensions are nominal

Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm)

LM5175PWPR HTSSOP PWP 28 2000 350.0 350.0 43.0

LM5175PWPT HTSSOP PWP 28 250 213.0 191.0 55.0

LM5175RHFR VQFN RHF 28 3000 367.0 367.0 35.0

LM5175RHFT VQFN RHF 28 250 210.0 185.0 35.0

PACKAGE MATERIALS INFORMATION

www.ti.com 16-Feb-2019

Pack Materials-Page 2

www.ti.com

PACKAGE OUTLINE

SEE TERMINAL

DETAIL

28X 0.30

0.18

2.55 0.1

28X 0.5

0.3

1 MAX

(0.2) TYP

0.05

0.00

24X 0.5

3.5

2X 2.5

3.55 0.1

A4.1

3.9 B

5.1

4.9

0.30

0.18

0.5

0.3

VQFN - 1.0 mm max heightRHF0028A

PLASTIC QUAD FLATPACK - NO LEAD

4220383/A 11/2016

PIN 1 INDEX AREA

0.08 C

SEATING PLANE

815

914

28 23

(OPTIONAL)

PIN 1 ID 0.1 C A B

0.05

EXPOSED

THERMAL PAD

29 SYMM

SYMM

NOTES:

1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing

per ASME Y14.5M.

2. This drawing is subject to change without notice.

3. The package thermal pad must be soldered to the printed circuit board for thermal and mechanical performance.

SCALE 3.000

DETAIL

OPTIONAL TERMINAL

TYPICAL

www.ti.com

EXAMPLE BOARD LAYOUT

0.07 MIN

ALL AROUND

0.07 MAX

ALL AROUND

28X (0.24)

28X (0.6)

( 0.2) TYP

VIA

24X (0.5)

(4.8)

(3.8)

(1.525)

(2.55)

(R0.05)

TYP

(1.025)

(3.55)

VQFN - 1.0 mm max heightRHF0028A

PLASTIC QUAD FLATPACK - NO LEAD

4220383/A 11/2016

SYMM

914

SYMM

LAND PATTERN EXAMPLE

SCALE:18X

NOTES: (continued)

4. This package is designed to be soldered to a thermal pad on the board. For more information, see Texas Instruments literature

number SLUA271 (www.ti.com/lit/slua271).

5. Vias are optional depending on application, refer to device data sheet. If any vias are implemented, refer to their locations shown

on this view. It is recommended that vias under paste be filled, plugged or tented.

SOLDER MASK

OPENING

METAL UNDER

SOLDER MASK

DEFINED

METAL

SOLDER MASK

OPENING

SOLDER MASK DETAILS

NON SOLDER MASK

DEFINED

(PREFERRED)

www.ti.com

EXAMPLE STENCIL DESIGN

28X (0.6)

28X (0.24)

24X (0.5)

(3.8)

(4.8)

4X (1.13)

(0.865)

TYP

(0.665) TYP

(R0.05) TYP 4X (1.53)

VQFN - 1.0 mm max heightRHF0028A

PLASTIC QUAD FLATPACK - NO LEAD

4220383/A 11/2016

NOTES: (continued)

6. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate

design recommendations.

SYMM

METAL

TYP

SOLDER PASTE EXAMPLE

BASED ON 0.125 mm THICK STENCIL

EXPOSED PAD 29

76% PRINTED SOLDER COVERAGE BY AREA UNDER PACKAGE

SCALE:20X

SYMM

914

www.ti.com

PACKAGE OUTLINE

26X 0.65

8.45

28X 0.30

0.19

TYP

6.6

6.2

0.15

0.05

0.25

GAGE PLANE

-80

1.2 MAX

2X 0.95 MAX

NOTE 5

2X 0.2 MAX

NOTE 5

5.18

4.48

3.1

2.4

B4.5

4.3

NOTE 3

9.8

9.6

0.75

0.50

(0.15) TYP

PowerPAD TSSOP - 1.2 mm max heightPWP0028C

SMALL OUTLINE PACKAGE

4223582/A 03/2017

14 15

0.1 C A B

PIN 1 INDEX

AREA

SEE DETAIL A

0.1 C

NOTES:

1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing

per ASME Y14.5M.

2. This drawing is subject to change without notice.

3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not

exceed 0.15 mm per side.

4. Reference JEDEC registration MO-153.

5. Features may differ or may not be present.

SEATING

PLANE

PowerPAD is a trademark of Texas Instruments.

A 20

DETAIL A

TYPICAL

SCALE 2.000

THERMAL

PAD

14 15

www.ti.com

EXAMPLE BOARD LAYOUT

0.05 MAX

ALL AROUND 0.05 MIN

ALL AROUND

28X (1.5)

28X (0.45)

26X (0.65)

(5.8)

(R0.05) TYP

(3.4)

NOTE 9

(9.7)

NOTE 9

(1.2) TYP

(0.6)

(1.2) TYP

( 0.2) TYP

VIA

(3.1)

(5.18)

PowerPAD TSSOP - 1.2 mm max heightPWP0028C

SMALL OUTLINE PACKAGE

4223582/A 03/2017

NOTES: (continued)

6. Publication IPC-7351 may have alternate designs.

7. Solder mask tolerances between and around signal pads can vary based on board fabrication site.

8. This package is designed to be soldered to a thermal pad on the board. For more information, see Texas Instruments literature

numbers SLMA002 (www.ti.com/lit/slma002) and SLMA004 (www.ti.com/lit/slma004).

9. Size of metal pad may vary due to creepage requirement.

10. Vias are optional depending on application, refer to device data sheet. It is recommended that vias under paste be filled, plugged

or tented.

LAND PATTERN EXAMPLE

EXPOSED METAL SHOWN

SCALE: 8X

SYMM

14 15

METAL COVERED

BY SOLDER MASK

SOLDER MASK

DEFINED PAD

SEE DETAILS

15.000

METAL

SOLDER MASK

OPENING METAL UNDER

SOLDER MASK SOLDER MASK

OPENING

EXPOSED METAL

SOLDER MASK DETAILS

NON-SOLDER MASK

DEFINED

(PREFERRED)

SOLDER MASK

DEFINED

www.ti.com

EXAMPLE STENCIL DESIGN

28X (1.5)

28X (0.45)

26X (0.65)

(5.8)

(R0.05) TYP

(5.18)

BASED ON

0.125 THICK

STENCIL

(3.1)

BASED ON

0.125 THICK

STENCIL

PowerPAD TSSOP - 1.2 mm max heightPWP0028C

SMALL OUTLINE PACKAGE

4223582/A 03/2017

2.62 X 4.380.175 2.83 X 4.730.15 3.10 X 5.18 (SHOWN)0.125 3.47 X 5.790.1

SOLDER STENCIL

OPENING

STENCIL

THICKNESS

NOTES: (continued)

11. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate

design recommendations.

12. Board assembly site may have different recommendations for stencil design.

SOLDER PASTE EXAMPLE

BASED ON 0.125 mm THICK STENCIL

SCALE: 8X

SYMM

14 15

METAL COVERED

BY SOLDER MASK

SEE TABLE FOR

DIFFERENT OPENINGS

FOR OTHER STENCIL

THICKNESSES

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