Microcontrollers
C166 Family
16-Bit Single-Chip Microcontroller
C164
Data Sheet 1999-08 Preliminary
C164
www.infineon.com
Edition 1999-08
Published by Infineon Technologies AG,
St.-Martin-Strasse 53
D-81541 Mü nch en
© Infineon Technologies AG 1999.
All Rights Reserv ed .
Attentio n pl ease!
The informat ion herein is given to describe certain components an d sh all not be considered as warranted cha racteristics.
Terms of de livery and r ight s to tec hnical chang e res erved.
We hereby disclaim any and all warranties, including but not limited to warranties of non-infringement, regarding circuits, descriptions and
charts state d herein.
Infineon Technologies is an approved CECC manufacturer.
Information
For further information on technology, delivery te rms and con dit ions and prices pleas e c ontact your nearest I nf ineon Technologies Office
in Germ any or our Infineon Techn ologies Represe nt atives worldwide (see address list) .
Warnings
Due to technical requireme nt s components may contain dangerous subst ances. For information on the typ es in ques tion please contact
your nearest Infineon Technologies Of f ic e.
Infineon Technologies Components may only be used in life-support devices or systems with the express written approval of Infineon Tech-
nologie s, if a failure of s uc h co mpon ents can re a sona bly be expected to c ause the failure o f that li fe-support device or syst em, or to affect
the saf e ty or e ffectiveness o f that de vi ce or system . Life support de vice s or sys tems a re inte nded to be im plant ed in th e human body, or to
support and /o r ma int ain and sustain and/or protect hum an life. If they fail, it is reasonable to assume t hat th e health of the user or other
persons may be endangered.
Controller Area Network (CAN): License of Robert Bosch GmbH
C164
Revision History: 1999-08 Preliminary
Previous Versio ns: 1998-02 (C161CI / Preliminary)
04.97 (C161CI / Advance Information)
Page Subjects
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• High Performance 16-bit CPU with 4-Stage Pipeline
– 80 ns Instruction Cycle Time at 25 MHz CPU Clock
– 400 ns Multiplicatio n (1 6 × 16 bit), 800 ns Division (32 / 16 bit)
– Enhanced Boolean Bit Manipulation Facilities
– Additional Instructions to Su pport HLL and Operating Systems
– Register -Based Design with Multiple Variabl e Register Banks
– Single-Cycle Context Switching Support
– 16 MBytes Total Line ar Address Space for Code and Data
– 1024 Bytes On-Chip Special Functio n Register Area
• 16-Priority-Level In terrupt Syste m with 32/33 Sources, Sample-Rate down to 40 ns
• 8-Channel Interrupt-Driven Single -Cycle Data Transfer Facilities via
Peripheral Event Controller (PEC)
• Clk. Generation via on-chip PLL (1:1.5/2/2.5/3/4/5), via prescaler or via direct clk. inp.
• On-Chip Memory Module s
– 2 KBytes O n-Chip Internal RAM (IRAM)
– 2 KBytes On-Ch ip Extension RAM (XRAM)
– 64 KBytes On-Chip ROM or Progra m Flash1) (Endur: 100 Prog./Er. Cycle s min .)
– 4 KBytes On-Chip DataFlash/EEPROM1) (Endur.: 100,000 P rog./Er. Cycles min.)
• On-Chip Peripheral Modules
– 8-Channel 10-bit A/D Converter with Programm. Conversion Time down to 7.8 µs
– Two Multi-Functiona l Gen eral Purpose Timer Units with 5 Timers
– Two Serial Channels (Synchronous/Asynchronous and High-Speed-Synchronous)
– 8-Channel 16-bit General Purpose Capture/Compare Unit (CAPCOM2)
– Capture/Comp are Unit for flexible PWM Sig nal Generati on (CAPCOM6)
(3/6 Capture/Co mpare Ch annels and 1 Compare Channel)
– On-Chip CAN Interface (Rev. 2.0B active) with 15 Message Objects
(Full-CAN / Basic CAN)
• Up to 4 MBytes Exte rna l Address Space for Code and Data
– Programmable External Bus Characteristics for Different Address Ran ges
– Multiplexed or Demultiplexed External Address/Data Buses with 8-Bit or 16-Bit
Data Bus Width
– Four Option al Programmable Chip -Select Signals
• Idle and Power Down Modes with Flexible Power Management
• Programmable Watchdog Timer and Oscillator Watchdog
1) Available only on devices in Flash technology.
Data Sheet 1 1999-08
C166 Family of C164
High-Performance CMOS 16-Bit Microcontrollers
Preliminary
C164 16-Bit Microcontroller
&
Data Sheet 2 1999-08
• On-Chip Real Time Clock
• Up to 59 Ge neral Purpose I/O Lines,
partly with Selectable Input Thresholds and Hysteresis
• Supported by a Large Range of Development Tools like C-Compile rs,
Macro-Assembler Packages, Emulators, Evaluation Boards, HLL-Debuggers,
Simulators, Logic Analyzer Disassemblers, Programming Boards
• On-Chip Bootstr ap Loader
• 80-Pin MQFP Package, 0.65 mm pitch
This document describes several derivatives of the C164 group. The table below
enumerates these derivatives and summarizes the differences. As this document refers
to all of these derivatives, some descriptions may not apply to a specific product.
For simplicity all ve rsions are referred to by the term C164 thro ughout this do cument.
Table 1 C164 Derivative Synopsis
Derivative Program Memory EEPROM CAPCOM6 CAN Interf.
SAK-C164CI-8RM 64 KByte ROM --- Full function CAN1
SAK-C164S I-8 RM 64 KByte ROM --- Full function ---
SAK-C164CL-8RM 64 KByte ROM --- Reduced fct. CAN1
SAK-C164SL-8RM 64 KByte ROM --- Reduced fct. ---
SAK-C164CH-8 FM 64 KByte Flash 4 KByte Full function CAN1
SAK-C164S H -8FM 64 KByte Flash 4 KByte Full function ---
&
Data Sheet 3 1999-08
Ordering Information
The ordering code for Infineon microcontrollers provides an exact reference to the
required product. This orderi ng code identifies:
• the derivative itself, i.e. its function set
• the spec ified temperatu re range
• the package
• the type of delivery.
For the available ordering codes for the C164 please refer to the
„Product Catalog Microcontrollers“, which summarizes all available microcontroller
variants.
Note: The ordering codes for Mask-ROM versions are defined for each product after
verification of the respective ROM code.
Introduction
The C164 is a derivative of the Infineon C166 Family of 16-bit single-chip CMOS
microcontro llers. It combines high CP U performance (up to 12.5 million instructions pe r
second) with high peripheral functionality and enhanced IO-capabilities. It also provides
on-chip program/data memory. The C164 derivative is especially suited for cost sensitive
applications.
Figure 1 Logic Symbol
&
XTAL2
XTAL1
RSTIN
NMI
EA
RSTOUT
ALE
RD
WR
V
DD
V
SS
PORT0
16 bit
PORT1
16 bit
Port 3
9 bit
Port 4
6 bit
Port 8
4 bit
V
AREF
V
AGND
Port 5
8 bit
&
Data Sheet 4 1999-08
Pin Configuration MQFP Package
(top view)
Figure 2
*) The marked pins of Port 4 and Port 8 can have CAN interface lines assigned to them.
Table 2 on the pages below lists the possible assignments.
The
marked input signal s
are available only in devices with a full function CAPCOM6.
They are not available in devices with a reduced CAPCOM6.
60
59
58
57
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
&
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
VSS
P1H.0/A8/
&&326
/EX0IN
P1L.7/A7/
&75$3
P1L.6/A6/COUT63
VSS
XTAL1
XTAL2
VDD
P1L.5/A5/COUT62
P1L.4/A4/CC62
P1L.3/A3/COUT61
P1L.2/A2/CC61
P1L.1/A1/COUT60
P1L.0/A0/CC60
P0H.7/AD15
P0H.6/AD14
P0H.5/AD13
P0H.4/AD12
P0H.3/AD11
Vss
VAREF
P5.4/AN4/T2EUD
P5.5/AN5/T4EUD
P5.6/AN6/T2IN
P5.7/AN7/T4IN
VSS
VDD
P3.4/T3EUD
P3.6/T3IN
P3.8/MRST
P3.9/MTSR
P3.10/TxD0
P3.11/RxD0
P3.12/BHE/WRH
P3.13/SCLK
P3.15/CLKOUT/FOUT
P4.0/A16/CS3
P4.1/A17/CS2
P4.2/A18/CS1
VSS
VAGND
P5.3/AN3
P5.2/AN2
P5.1/AN1
P5.0/AN0
P8.3/CC19IO / *
P8.2/CC18IO / *
P8.1/CC17IO / *
P8.0/CC16IO / *
NMI
RSTOUT
RSTIN
P1H.7/A15/CC27IO
P1H.6/A14/CC26IO
P1H.5/A13/CC25IO
P1H.4/A12/CC24IO
P1H.3/A11/EX3IN/T7IN
P1H.2/A10/
&
&
3
2
6
/EX2IN
P1H.1/A9/
&
&
3
2
6
/EX1IN
VDD
VDD
P4.3/A19/CS0
* /P4.5/A20
* /P4.6/A21
RD
WR/WRL
ALE
VPP/EA
P0L.0/AD0
P0L.1/AD1
P0L.2/AD2
P0L.3/AD3
P0L.4/AD4
P0L.5/AD5
P0L.6/AD6
P0L.7/AD7
P0H.0/AD8
P0H.1/AD9
P0H.2/AD10
VDD
&
Data Sheet 5 1999-08
Table 2 Pin Definitions and Functions
Symbol Pin
Num. Input
Outp. Function
P5
P5.0
P5.1
P5.2
P5.3
P5.4
P5.5
P5.6
P5.7
76
77
78
79
2
3
4
5
I
I
I
I
I
I
I
I
I
Port 5 is an 8-bit input-only port with Schmitt-Trigger charact.
The pins of Port 5 also serve as analog input channels for the
A/D converter, or they serve as time r inputs:
AN0
AN1
AN2
AN3
AN4, T2EUD GPT1 Timer T5 Ext. Up/Down Ctrl. Inp.
AN5, T4EUD GPT1 Timer T4 Ext. Up/Down Ctrl. Inp.
AN6, T2IN GPT1 Timer T2 Input for
Count/Gate/Reload/Capture
AN7, T4IN GPT1 Timer T4 Input for
Count/Gate/Reload/Capture
P3
P3.4
P3.6
P3.8
P3.9
P3.10
P3.11
P3.12
P3.13
P3.15
8
9
10
11
12
13
14
15
16
IO
I
I
I/O
I/O
O
I/O
O
O
I/O
O
O
Port 3 is a 9-bit bidirectional I/O port. It is bit-wise
programmable for input or output via direction bits. For a pin
configured as inpu t, the output driver is put into high-
impedance state. Port 3 outputs can be configure d as push/
pull or open dr ain drivers. The input threshold of Po rt 3 is
selectable (TTL or special).
The following Port 3 pin s also se rve for alternate functio ns:
T3EUD GPT1 Timer T3 External Up/Down Control Input
T3IN GPT1 Timer T3 Count/Gate Input
MRST SSC Master-Receive/Slave-Transmit Inp./Outp.
MTSR SSC Master-Transmit/Slave-Receive Outp./Inp.
T×D0 ASC0 Clock/Data Output (Async./Sync.)
R×D0 ASC0 Data Input (Async.) or Inp./Outp. (Sync.)
BHE External Memory High Byte E nable Signal,
WRH External Memory High Byte Write Strobe
SCLK SSC Master Clock Output / Slave Clock Inp ut.
CLKOUT System Clock Output (=CPU Clock)
FOUT Programmab le Frequency Output
&
Data Sheet 6 1999-08
P4
P4.0
P4.1
P4.2
P4.3
P4.5
P4.6
17
18
19
22
23
24
IO
O
O
O
O
O
O
O
O
O
I
O
O
Port 4 is a 6-bit bidirectional I/O port. It is bit-wise
programmable for input or output via direction bits. For a pin
configured as input, the output driver is put into high-
impedance state. Port 4 outputs can be con fig ured as push/
pull or open drain drivers. The input th reshold of Port 4 is
selectable (TTL or special).
Port 4 can be used to output the segment address lines, the
optional chip sele ct lines, and for serial interface lines: 1)
A16 Least Significant Se gment Address Line,
CS3 Chip Select 3 Output
A17 Segment Add ress Lin e,
CS2 Chip Select 2 Output
A18 Segment Add ress Lin e,
CS1 Chip Select 1 Output
A19 Segment Add ress Lin e,
CS0 Chip Select 0 Output
A20 Segment Add ress Lin e,
CAN1_RxDCAN 1 Receive Data Input
A21 Most Significant Segment Add ress Line,
CAN1_TxD CAN 1 Transmit Data Output
RD 25 O External Memory Re ad Strobe. RD is activated for every
external instruction or data read access.
WR/
WRL 26 O External Memory Write Strob e. In WR-mode this pin is
activated for every external data write access. In WRL-mode
this pin is activated for low byte data write accesses on a 16-
bit bus, and for every data write access on an 8-bit bus. See
WRCFG in register SYSCON for mode selection.
ALE 27 O Address Latch Enable Output. Can be used for latching the
address into external memory or an address latch in the
multiplexed bus modes.
EA 28 I External Access Enable pin. A low level at this pin during and
after Reset forces the C164 to beg in instruction execution
out of external memory. A high level forces execution out of
the internal program me mory.
“ROMless” ve rsions must ha ve this pin tied to ‘0’.
Table 2 Pin Definitions and Functions (continued)
Symbol Pin
Num. Input
Outp. Function
&
Data Sheet 7 1999-08
PORT0
P0L.0-7
P0H.0-7
29 -
36
37-39,
42-46
IO PORT0 consists of the two 8-bit bidirectional I/O ports P0L
and P0H. It is bit-wise progra mmable for input or outp ut via
direction bits. For a pin configured as input, the output driver
is put into high-impedance state.
In case of an extern al bus configuration , PO RT0 serves as
the address (A) and add ress/d ata (AD) bus in multiplexed
bus modes and as the data (D) bus in demultiplexed bu s
modes.
Demultiplexed bus modes:
Data Path W idth: 8-bit 16-bit
P0L.0 – P0L.7: D0 – D7 D0 - D7
P0H.0 – P0H.7: I/O D8 - D15
Multiplexed bus modes:
Data Path W idth: 8-bit 16-bit
P0L.0 – P0L.7: AD0 – AD7 AD0 - AD 7
P0H.0 – P0H.7: A8 - A15 AD8 - AD15
Table 2 Pin Definitions and Functions (continued)
Symbol Pin
Num. Input
Outp. Function
&
Data Sheet 8 1999-08
PORT1
P1L.0-7
P1H.0-7
P1L.0
P1L.1
P1L.2
P1L.3
P1L.4
P1L.5
P1L.6
P1L.7
P1H.0
P1H.1
P1H.2
P1H.3
P1H.4
P1H.5
P1H.6
P1H.7
47-52,
57-59
59,
62-68
47
48
49
50
51
52
57
58
59
62
63
64
65
66
67
68
IO
I/O
O
I/O
O
I/O
O
O
I
I
I
I
I
I
I
I
I/O
I/O
I/O
I/O
PORT1 consists of the two 8-bit bidirectional I/O ports P1L
and P1H. It is bit-wise programmable for inp ut or output via
direction bits. For a pin configured as input, the output driver
is put into high-impedance state . PO RT1 is us ed as the 1 6-
bit address bus (A) in demultiplexed bus modes and also
after switching from a demultiplexed bu s mode to a
multiplexed bus mode.
The following PORT1 pins also serve for alt. functions:
CC60 CAPCOM6: Input / Output of Channel 0
COUT60 CAPCOM6: Output of Channel 0
CC61 CAPCOM6: Input / Output of Channel 1
COUT61 CAPCOM6: Output of Channel 1
CC62 CAPCOM6: Input / Output of Channel 2
COUT62 CAPCOM6: Output of Channel 2
COUT63 Output of 10-bit Compare Cha nne l
CTRAP CAPCOM6: Trap Input **)
CTRAP is an input pin with an internal pullup resistor. A low
level on this pin switches the compare outputs of the
CAPCOM6 unit to the logi c level defined by software.
CC6POS0 CAPCOM6: Position 0 Input, **)
EX0IN Fast External In terrupt 0 Input
CC6POS1 CAPCOM6: Position 1 Input, **)
EX1IN Fast External In terrupt 1 Input
CC6POS2 CAPCOM6: Position 2 Input, **)
EX2IN Fast External In terrupt 2 Input
EX3IN Fast External Interrupt 3 Input,
T7IN CAPCOM2: Timer T7 Count Input
CC24IO CAPCOM2: CC24 Capture Inp./Compare Ou tp .
CC25IO CAPCOM2: CC25 Capture Inp./Compare Ou tp .
CC26IO CAPCOM2: CC26 Capture Inp./Compare Ou tp .
CC27IO CAPCOM2: CC27 Capture Inp./Compare Ou tp .
Note: The marked (**) input signals are available only in
devices with a fu ll function CAPCOM6.
Table 2 Pin Definitions and Functions (continued)
Symbol Pin
Num. Input
Outp. Function
&
Data Sheet 9 1999-08
XTAL2
XTAL1 54
55 O
IXTAL2: Output of the oscillator amplifier circuit.
XTAL1: Input to the oscillator amplifier and input to
the internal clock generator
To clock the device from an exte rnal source, dr ive XTAL1,
while leaving XTAL2 unconnected. Minimum and maximum
high/low and rise/fall times specified in the AC
Characteristics must be observed.
RSTIN 69 I/O Reset Input with Schmitt-Trigger characteristics. A low level
at this pin while the oscillator is running resets the C164. An
internal pullup resistor permits p ower-on reset usi ng only a
capacitor connected to 9SS.
A spike filter suppresses input pulses <10 ns. Input pulses
>100 ns safely pass the filter. The minimum duration for a
safe recognition should be 100 ns + 2 CPU clock cycles .
In bidirectional reset mode (enabled by setting bit BDRSTEN
in register SYSCON) the RSTIN line is internally pulled low
for the duration of the internal reset sequence upon any reset
(HW, SW, WDT). See note below this table .
RST
OUT 70 O Internal Reset Indication Output. This pin is set to a low level
when the part is executing either a hardware-, a software- or
a watchdog timer reset. RSTOUT remains low until the EINIT
(end of initialization) instruction is executed.
NMI 71 I Non-Maskable Interrupt Input. A high to low transition at this
pin causes the CPU to vector to the NMI trap routine. When
the PWRDN (power down) instruction is executed, the NMI
pin must be low in ord er to force the C164 to go into power
down mode. If NMI is high, when PWRDN is executed, the
part will continue to run in normal mode.
If not used, pin NMI should be pulled high externally.
Table 2 Pin Definitions and Functions (continued)
Symbol Pin
Num. Input
Outp. Function
&
Data Sheet 10 1999-08
Note: The following behaviour differences must be observed when the bidirectional reset
is active:
• Bit BDRSTEN in register SYSCON cannot be changed after EINIT and is cleared
automatica lly after a reset.
• Th e reset ind ication flags always indicate a long hardware reset.
• The PORT0 configuration is treated like on a hardware reset. Especially the bootstrap
loader may be activated when P0L .4 is low.
• Pin RSTIN may only be connected to external reset devices with an open drain output
driver.
• A short hardware reset is extended to the duration of the internal reset sequence.
P8
P8.0
P8.1
P8.2
P8.3
72
73
74
75
IO
I/O
I
I/O
O
I/O
I
I/O
O
Port 8 is a 4-bit bidirectional I/O port. It is bit-wise
programmable for input or output via direction bits. For a pin
configured as input, the output driver is put into high-
impedance state. Port 8 outputs can be con fig ured as push/
pull or open drain drivers. The input th reshold of Port 8 is
selectable (TTL or special). Port 8 pins provide inputs/
outputs for CAPCO M 2 and serial interface lin es. 1)
CC16IO CAPCOM2: CC16 Capture Inp./Compare Outp.,
CAN1_RxDCAN 1 Receive Data Input
CC17IO CAPCOM2: CC17 Capture Inp./Compare Outp.,
CAN1_TxD CAN 1 Transmit Data Output
CC18IO CAPCOM2: CC18 Capture Inp./Compare Outp.,
CAN1_RxDCAN 1 Receive Data Input
CC19IO CAPCOM2: CC19 Capture Inp./Compare Outp.,
CAN1_TxD CAN 1 Transmit Data Output
9AREF 1 - Reference voltage for the A/D converter.
9AGND 80 - Reference grou nd for the A/D converter.
9DD 7, 21,
40, 53 ,
61
- Digital Supply Voltage:
+ 5 V during normal opera tion and idle mode.
≥ 2.5 V during power down mode.
9SS 6, 20,
41, 56 ,
60
- Digital Ground.
1) The CAN interface lines are assigned to ports P4 and P8 under software control. Within the CAN module
several assignments can be selected.
Table 2 Pin Definitions and Functions (continued)
Symbol Pin
Num. Input
Outp. Function
&
Data Sheet 11 1999-08
Functional Description
The architecture of the C164 combines advantages of both RISC and CISC processors
and of advanced peripheral subsystems in a very well-balanced way. The following block
diagram gives an overview of the different on-chip components and of the advanced,
high bandwidth inte rnal bus structure of the C164.
Note: All time specifications refer to a CPU clock of 25 MHz
(see definition in the AC Cha racteristics section).
Figure 3 Block Diagram
64K
Internal ROM
(C164CI-8RM)
or OTP
(C164CI-8EM)
PLL-Oscillator
progr. Multiplier:
0.5; 1; 1.5; 2;
2.5; 3; 4; 5
Instr./Data
Full-CAN
Interface
V2.0B
active
3(&
&38&RUH
Interrupt Bus
Internal
RAM
.%\WH
Dual Port
Port 8Port 3
Port 0
Port 4 Po rt 1
16
16
4
16
16
Data
Data
WDT
Port 5
8 C164CI V1.2
&38
&&RUH
XBUS
(16-bit NON MUX Data / Addresses)
External
Bus
(8/16 bit;
MUX only)
&
XBUS
Control
16
Ext ernal Inst r./Data
16
8-
Channel
10-Bit
ADC
USART
ASC
Sync.
Channel
(SPI)
SSC
Tim e r 7
Timer 8
General Purpose
Capture/Compare
Unit
8-Channel 16-bit
Capture/Compare Unit
(CAPCOM2)
Capture/Compare Unit for
PWM Generation (CAPCOM6)
3/6 Capture/Compare
Channels
XTAL
P4.5/CAN_RxD
P4.6/CAN_TxD
9
BRG
BRG
5
16
Peripheral Data
1 Compare
Channel
Interrupt Controller up to 12
ext. IR
Timer 13
GPT 1
T 3
T 4
T 2
32
RTC
64 KB
ROM
or
Flash
&
Data Sheet 12 1999-08
Memory Organization
The memory space of the C164 is configured in a Von Neumann architecture which
means that code memory, data memory, registers and I/O ports are organized within the
same linear address space which includes 16 MBytes. The entire memory space can be
accessed bytewise or wordwise. Particular portions of the on-chip memory have
additi onally been made directly bitaddressa ble.
The C164 incorporates 64 KBytes of on-chip ROM or Flash memory for code or constant
data. The Flash memory is organized as one 16 KByte sector, two 8 KByte sectors, and
one 32 KByte sector. Each sector can be separately write protected, erased and
programmed (in blocks of 64 Byte).
The lower 32 KBytes of the on-chip ROM or Flash memory can be mapped either to
segment 0 or segment 1.
2 KBytes of on-chip Internal RAM (IRAM) are provided as a storage for user defined
variables, for the system stack, general purpose register banks and even for code. A
register bank can consist of up to 16 wordwide (R0 to R15) and/or bytewide (RL0, RH0,
…, RL 7, RH7 ) so-called General Purpose Registe rs (GPRs).
1024 bytes (2 * 512 bytes) of the a ddress space are reserved for the Special Fun ction
Register areas (SFR space and ESFR space). SFRs are wordwide registers which are
used for controlling and monitoring functions of the different on-chip units. Unused SFR
addresses are reserved for futu re members of the C166 Family.
2 KBytes of on-chip Extension RAM (XRAM) are provided to store user data, user
stacks, or code. The XRAM is accessed like exter nal memory and therefore cannot be
used for the system stack or for register banks and is not bitaddressable. The XRAM
permits 16-bit accesses with maximum spee d.
4 KBytes of on-chip Data Flash memory, organized as four 1 KByte sectors, provide
EEPROM functionality. Each byte/word can be erased or programmed separately. Each
sector ca n be erased as a unit. The low granularity (byte/word) and the high endu rance
of the DataFlash/EEP ROM su pp ort the non-volatile storage of changing system data.
Note: The DataFlash/EE PROM is only incorporated in the Flash versions.
In order to mee t the ne eds of design s where more memory is requir ed than is pr ovided
on chip, up to 4 MBytes of external RAM and/or ROM can be connected to the
microcontroller.
&
Data Sheet 13 1999-08
External Bus Controller
All of the external memory accesses are performed by a particular on-chip External Bus
Controller (EBC). It can be programmed either to Single Chip Mode when no external
memory is required, or to one of four different external memory access modes, which are
as follows:
– 16-/18 -/20-/22-bit Addresse s , 16-bit Data, Demultip lexed
– 16-/18 -/20-/22-bit Addresse s , 16-bit Data, Multiplexed
– 16-/18 -/20-/22-bit Addresse s , 8 -bit Data, Multiplexed
– 16-/18 -/20-/22-bit Addresse s , 8 -bit Data, Demultiplexed
In the demultiplexed bus modes, addresses are output on PORT1 and data is input/
output on PORT0 or P0L, respectively. In the multiplexed bus modes both addresses
and data use PO RT0 for input/output.
Important timing characteristics of the external bus interface (Memory Cycle Time,
Memory Tri-State Time, Length of ALE and Read Write Delay) have been made
programmable to allow the user the adaption of a wide range of different types of
memories and exter nal peripherals.
In addition, up to 4 independent address windows may be defined (via register pairs
ADDRSELx / BUSCONx) which allow to access different resources with different bus
characteristics. These address windows are arranged hierarchically where BUSCON4
overrides BUSCON3 and BUSCON2 overrides BUSCON1. All accesses to locations not
covered by thes e 4 address windows are controlled by BUSCON0.
Up to 4 external CS signals (3 windows plus default) can be generated in order to save
external glue logic. The C164 offers the possibility to switch the CS outputs to an
unlatche d mode. In this mod e the inte rnal filter logic is switched o ff and the CS signals
are directly gen erated from the addre ss. The unlatch ed CS mode is enabled b y setting
CSCFG (SYSCON.6).
For applications which require less than 4 MBytes of external memory space, this
address space can be restricted to 1 MByte, 256 KByte or to 64 KByte. In this case Port 4
outputs four, two, o r no address lin es at all. It outputs all 6 address lin es, if an add ress
space of 4 MBytes is used.
Note: When the on-chip CAN Module is activated on Port 4 the segment address output
is limited to 4 bits (i.e . A19...A16) due to the CAN interface pi ns.
&
Data Sheet 14 1999-08
Central Processing Unit (CPU)
The main core of the CPU consists of a 4-stage instructi on pipelin e, a 16-b it arithmetic
and logic unit (ALU) and dedicated SFRs. Additional hardware has been spent for a
separate multiply and di vide unit, a bit-mask generator and a barre l shifter.
Based on th ese hardware provisions, most of the C164’s in structions can be executed
in just on e machine cycle which require s 2 CPU clo cks (4 TCL) . For example, shift an d
rotate instru ctions are always processed durin g one machine cycle independent of the
number o f bits to be shifted. A ll multiple-cycle instru ctions have be en optimized so that
they can be executed very fast as well: branches in 2 cycles, a 16 × 16 bit multiplication
in 5 cycles and a 32-/16 bit division in 10 cycles. Another pipeline optimization, the so -
called ‘Jump Cache’, reduces the execution time of repeatedly performed jumps in a loop
from 2 cycles to 1 cycle.
Figure 4 CPU Block Diagram
&
Data Sheet 15 1999-08
The CPU has a register context consisting of up to 16 wordwide GPRs at its disposal.
These 16 GPRs are physically allocated within the on-chip RAM area. A Context Pointer
(CP) register determines the base address of the active register bank to be accessed by
the CPU at any time. The number of register banks is only restricted by the available
internal RAM space. For easy parame t er passing, a register bank may overlap others.
A system stack of up to 2048 bytes is provided as a storage for temporary data. The
system stack is allocated in the on-chip RAM area, and it is accessed by the CPU via the
stack pointer (SP) register. Two separate SFRs, STKOV and STKUN, are implicitly
compared against the stack pointer value upon each stack access for the detection of a
stack overflow or underflow.
The high performance offered by the hardware implementation of the CPU can efficiently
be utilized by a prog rammer via the highly efficient C16 4 instruction set wh ich includes
the following instruction classes:
– Arithmetic Instructions
– Logical Instructions
– Boolean Bit Manipulation Instructions
– Compare and Loop Control Instru ctions
– Shift and Rotate Instructions
– Prioritize Instruction
– Data Movement Instructions
– System Stack Instructions
– Jump and Call Instructions
– Return Instr uctions
– System Control Instructions
– Miscellaneous Instructions
The basic instruction length is either 2 or 4 bytes. Possible operand types are bits, bytes
and words. A variety of direct, indir ect or immediate addressing mo des are provided to
specify the re qu ired operands.
&
Data Sheet 16 1999-08
Interrupt System
With an i nterrupt re sponse time within a range fro m just 5 to 12 CPU clocks (in case of
internal program execution), the C164 is capable of reacting very fast to the occurrence
of non-deterministic events.
The architecture of the C164 supports several mechanisms for fast and flexible response
to service requests that can be generated from various sources internal or external to the
microcontroller. Any of these interrupt requests can be programmed to being serviced by
the Interrupt Controller or b y the Perip heral Event Controller (PEC).
In contrast to a standard interrupt service where the current program execution is
suspended and a branch to the interrupt vector table is performed, just one cycle is
‘stolen’ from the current CPU activity to perform a PEC service. A PEC service implies a
single byte or word data transfer be tween any two memo ry locations with an addition al
increment of either the PEC source or the destination pointer. An individual PEC transfer
counter is implicity decremented for each PEC service except when performing in the
continuous transfer mode. When this counter reaches zero, a standard interrupt is
performed to the corresponding source related vector location. PEC services are very
well suited, for example, for supporting the transmission or reception of blocks of data.
The C164 has 8 PEC channels each of which offers such fast interrupt-driven data
transfer capabil ities.
A separa te con trol re gister which contain s an interr upt requ est flag, an in terru pt enab le
flag and an interrupt priority bitfield exists for each of the possible interrupt sources. Via
its related re gister, each source can be progra mmed to one o f sixteen i nterrupt priority
levels. Once having been accepted by the CPU, an interrupt service can only be
interrupted by a higher prioritized service request. For the standard interrupt processing,
each of the possible interrupt sources ha s a dedicated vector location.
Fast external interrupt inputs are provided to service external interrupts with high
precision requirements. These fast interrupt inputs feature programmable edge
detection (rising edge, falling edge or both edges).
Software interrupts are supported by means of the ‘TRAP’ instruction in combination with
an individu al trap (interrupt) number.
The following table shows all of the possible C164 interrupt sources and the
corresponding hardware-related interrupt flags, vectors, vector locations and trap
(interrupt) numbers.
Note: Interrupt nodes which are not used by associated peripherals, may be used to
generate software controlled interrupt requests by setting the respective interrupt
request bit (xIR).
&
Data Sheet 17 1999-08
Table 3 C164 Interrupt Nodes
Source of Interrupt or
PEC Service Request Request
Flag Enable
Flag Interrupt
Vector Vector
Location Trap
Number
External Interrupt 0 CC8IR CC8IE CC8INT 00’0060H18H
External Interrupt 1 CC9IR CC9IE CC9INT 00’0064H19H
External Interrupt 2 CC10IR CC10IE CC10INT 00’0068H1AH
External Interrupt 3 CC11IR CC11IE CC11INT 00’006CH1BH
GPT1 Timer 2 T2IR T2IE T 2INT 00’0088H22H
GPT1 Timer 3 T3IR T3IE T 3INT 00’008CH23H
GPT1 Timer 4 T4IR T4IE T 4INT 00’0090H24H
A/D Conversion
Complete ADCIR ADCIE ADCINT 00’00A0H28H
A/D Overrun Error ADE IR ADEIE ADEINT 00’00A4H29H
ASC0 Transmit S0TIR S0TIE S0TINT 00’00A8H2AH
ASC0 Transmit Buffer S0TBIR S0TBIE S0TBINT 00’011CH47H
ASC0 Receive S0RIR S0RIE S0RINT 00’00ACH2BH
ASC0 Error S0EIR S0EIE S0EINT 00’00B 0H2CH
SSC Transmit SCTIR SCTIE SCTINT 00’00B4H2DH
SSC Receive SCRIR SCRIE SCRINT 00’00B8H2EH
SSC Error SCEIR SCEIE SCEINT 00’00B CH2FH
CAPCOM Register 16 CC16IR CC16IE CC16INT 00’00C0H30H
CAPCOM Register 17 CC17IR CC17IE CC17INT 00’00C4H31H
CAPCOM Register 18 CC18IR CC18IE CC18INT 00’00C8H32H
CAPCOM Register 19 CC19IR CC19IE CC19INT 00’00CCH33H
CAPCOM Register 20 CC20IR CC20IE CC20INT 00’00D0H34H
CAPCOM Register 21 CC21IR CC21IE CC21INT 00’00D4H35H
CAPCOM Register 22 CC22IR CC22IE CC22INT 00’00D8H36H
CAPCOM Register 23 CC23IR CC23IE CC23INT 00’00DCH37H
CAPCOM Register 24 CC24IR CC24IE CC24INT 00’00E0H38H
CAPCOM Register 25 CC25IR CC25IE CC25INT 00’00E4H39H
CAPCOM Register 26 CC26IR CC26IE CC426NT 00’0 0E8H3AH
CAPCOM Register 27 CC27IR CC27IE CC27INT 00’00ECH3BH
CAPCOM Register 28 CC28IR CC28IE CC28INT 00’00E0H3CH
&
Data Sheet 18 1999-08
CAPCOM Register 29 CC29IR CC29IE CC29INT 00’0110H44H
CAPCOM Register 30 CC30IR CC30IE CC30INT 00’0114H45H
CAPCOM Register 31 CC31IR CC31IE CC31INT 00’0118H46H
CAPCOM Timer 7 T7IR T7IE T 7 INT 00’00F4H3DH
CAPCOM Timer 8 T8IR T8IE T 8 INT 00’00F8H3EH
CAPCOM 6 Interrupt CC6IR CC6IE CC6INT 00’00FCH3FH
CAPCOM 6 Ti mer 12 T12IR T12IE T12INT 00’0134H4DH
CAPCOM 6 Ti mer 13 T13IR T13IE T13INT 00’0138H4EH
CAPCOM 6
Emergency CC6EIR CC6EIE CC6EINT 00’013CH4FH
CAN Interface 1 XP0IR XP0IE XP0INT 00’0100H40H
DataFlash Term ina tion XP1IR X P1IE XP1INT 00’010 4H41H 1)
PLL Unlock / RTC XP3IR XP3IE XP3INT 00’010CH43H
1) This interrupt node is only available in the Flash devices.
Table 3 C164 Interrupt Nodes (continued)
Source of Interrupt or
PEC Service Request Request
Flag Enable
Flag Interrupt
Vector Vector
Location Trap
Number
&
Data Sheet 19 1999-08
The C164 also provid es an excellent me chanism to ide ntify and to process exceptions
or error conditions that arise during run-time, so-called ‘Hardware Traps’. Hardware
traps cause immediate non-maskable system reaction which is similar to a standard
interrupt service (branching to a dedicated vector table location). The occurence of a
hardware trap is a dditional ly signifie d by an in dividual b it in the tra p flag reg ister (TFR).
Exce pt when anoth er highe r prioritize d trap servi ce is in p rogress, a hardware trap will
interrupt any actual program execution. In turn, hardware trap services can normally not
be interrupte d by stan da rd or PEC interrupts.
The following table shows all of the possible exceptions or error conditions that can arise
during run-time:
Table 4 Hardware Trap Summary
Exception Condition Trap
Flag Trap
Vector Vector
Location Trap
Number Trap
Prio
Reset Functions:
Hardware Reset
Software Reset
Watchdog Timer Overflow
RESET
RESET
RESET
00’0000H
00’0000H
00’0000H
00H
00H
00H
III
III
III
Class A Hardware Traps:
Non-Maskable Interrupt
Stack Overflow
Stack Underflow
NMI
STKOF
STKUF
NMITRAP
STOTRAP
STUTRAP
00’0008H
00’0010H
00’0018H
02H
04H
06H
II
II
II
Class B Hardware Traps:
Undefined O pcod e
Protected Instruction Fault
Illegal Wo rd Operand Access
Illegal Instructio n Access
Illegal External Bus Access
UNDOPC
PRTFLT
ILLOPA
ILLINA
ILLBUS
BTRAP
BTRAP
BTRAP
BTRAP
BTRAP
00’0028H
00’0028H
00’0028H
00’0028H
00’0028H
0AH
0AH
0AH
0AH
0AH
I
I
I
I
I
Reserved [2CH – 3CH][0B
H –
0FH]
Softwa re Tra p s:
TRAP Instruction Any
[00’0000H –
00’01FCH]
in steps
of 4H
Any
[00H –
7FH]
Current
CPU
Priority
&
Data Sheet 20 1999-08
The Capture/Compare Unit CAPCOM2
The general purpose CAPCOM2 unit supports generation and control of timing
sequences on up to 8 channels with a maximum resolution of 16 TCL. The CAPCOM
units are typically used to handle high speed I/O tasks such as pulse and waveform
generation, pulse width modulation (PMW), Digital to Analog (D/A) conversion, software
timing, or time recordin g relative to external events.
Two 16-bit timer s (T7/T8) with relo ad registe rs provide two indep endent time bases fo r
the capture/compa re register array.
Each dual purpose capture/compare register, which may be individually allocated to
either CAPCOM timer and programmed for capture or compare function, has one port
pin associated with it which serves as an input pin for triggering th e capture function, or
as an output pin to indicate the occu rren ce of a compare event.
When a capture/compare register has been selected for capture mode, the current
contents of the allocated timer will be latched (‘capture’d) into the capture/compare
register in response to an external event at the port pin which is associated with this
register. In addition, a specific interrupt request for this capture/compare register is
generated. Either a positive, a negative, or both a positive and a negative external signal
transition at the pin can be selected as the triggering event. The contents of all registers
which have been selected for one of the five compare modes are continuously compared
with the contents of the allocated timers. When a match occurs between the timer value
and the value in a capture/compare register, specific actions will be taken ba sed on the
selected compare mode.
Table 5 Compare Modes (CAPCOM)
Compare Modes Function
Mode 0 Interrupt-only compare mode;
several compare interrupts per timer period are possible
Mode 1 Pin toggles on each compare match;
several compare events per timer period are possible
Mode 2 Interrupt-only compare mode;
only one compare interrup t per timer period is generated
Mode 3 Pin set ‘1’ on match; pin rese t ‘0’ on compa re time overflow;
only one compare event per timer perio d is generated
Double
Register Mode Two registers operate on one pin; pin toggles on each compare
match;
several compare events per timer period are possible.
Registers CC16 & CC24 ➞ pin CC16IO
Registers CC17 & CC25 ➞ pin CC17IO
Registers CC18 & CC26 ➞ pin CC18IO
Registers CC19 & CC27 ➞ pin CC19IO
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Data Sheet 21 1999-08
The Capture/Compare Unit CAPCOM6
The CAPCOM6 unit supports generation and control of timing sequences on up to three
16-bit capture/compare channels plus one 10-bit compare chann el.
In compare mode the CAPCOM6 unit provides two output signals per channel which
have inverted polarity and non-overlapping pulse transitions. The compare channel can
generate a single PWM output signal and is further used to modulate the capture/
compare output signals.
In capture mode the contents of compare timer 12 is stored in the capture registers upon
a signal transition at pins CCx.
Compare timers T12 (16-bit) and T13 (10-bit) are free running timers which are clocked
by the prescaled CPU clock.
Figure 5 CAPCOM6 Block Diagram
For motor control app lications both subunits may generate versatile multicha nne l PWM
signals which are basically either controlled by compare timer 12 or by a typical hall
sensor pa tter n at the interrupt inputs (block commutation).
Note: Multichannel signal generation is provid ed only in devices with a full CAPCOM6.
1) These registers are not directly accessible. The period and offset registers are loading a value into the
timer registers.
The shaded blocks are available in the full function module only.
Control
CC Channel 0
CC60
CC Channel 1
CC61
CC Channel 2
CC62
MCB04109.VSD
Prescaler
Offset Register
T12OF
Compare
Timer T12
16-bit
1)
Period Register
T12P Mode Select Reg.
CC6MSEL Trap Register
Port
Control
Logic
Control Register
CTCON
Compare Register
CMP13
Prescaler
Compare
Timer T13
10-bit
1)
Period Register
T13P
Block
Commutation
Control
CC6MCON.H
CC60
COUT60
CC61
COUT61
CC62
COUT62
COUT63
CTRAP
CC6POS0
CC6POS1
CC6POS2
f
CPU
f
CPU
&
Data Sheet 22 1999-08
General Purpose Timer (GPT) Unit
The GPT unit represents a very flexible multifunctional timer/counter structure which
may be used for many different time related tasks such as event timing and counting,
pulse width and duty cycle measurements, pulse generation, or pulse multiplication.
The GPT un it incorporate s three 16 -bit timers (GPT1) . Each timer in e ach module may
operate independently in a number of different modes, or may be concatenated with
another timer of the same modu le.
Each of the three timers T2, T3, T4 of module GPT1 can be configured individually for
one of four basic modes of operation, which are Timer, Gated Timer, Counter, and
Incremental Interface Mode. In Timer Mode, the input clock for a timer is derived from
the CPU clock, divided by a programmable prescaler, while Counter Mode allows a timer
to be clocked in refere nce to external events.
Pulse width or duty cycle measurement is supported in Gated Timer Mode, where the
operation of a timer is controlled by the ‘gate’ leve l on an ex ternal input pin. For these
purposes, each timer has one associated port pin (TxIN) which serves as gate or clock
input. The maximum resolution o f the timer s in module GPT1 is 16 TCL .
The count direction (up/down) for each timer is programmable by software or may
additionally be altered dynamically by an external signal on a port pin (TxEUD) to
facilitate e.g. position tracking.
In Incremental Interface Mode the GPT1 timers ( T2, T3, T4) can be directly connecte d
to the incremental positio n sensor signals A and B via th eir respective inputs TxIN an d
TxEUD. Direction and cou nt sign als are internally d eri ved fro m these two in put sig nals,
so the contents of the respective timer Tx corresponds to the sensor position. The third
position sensor signal TOP0 can be connected to an interru pt inpu t.
Timer T3 has an output toggle latch (T3OTL) which changes its state on each timer over-
flow/underflow. The state of this latch may be output on a port pin (T3OUT) e.g. for time
out monitoring of external hardware components, or may be used internally to clock
timers T2 and T4 for measurin g long time periods with hig h resolution.
In addition to their basic operating modes, timers T2 and T4 may be configured as reload
or capture registers for timer T3. When used as capture or reload registers, timers T2
and T4 are stop ped. The contents of timer T3 are captured in to T2 or T4 in response to
a signal at their associated inpu t pins (TxIN). Time r T3 is r eloaded with the contents of
T2 or T4 triggered either by an external signal or by a selectable state transition of its
toggle latch T3OTL. When both T2 and T4 are configured to alternately reload T3 on
opposite state transitions of T3OTL with the low and high times of a PWM signal, this
signal can be constantly generated without software intervention.
&
Data Sheet 23 1999-08
Figure 6 Block Diagram of GPT1
T3
Mode
Control
2
n
: 1
f
CPU
2
n
: 1
f
CPU
T2
Mode
Control
GPT1 Timer T2
Reload
Capture
2
n
: 1
f
CPU
T4
Mode
Control GP T1 Timer T4
Reload
Capture
GPT1 Timer T3 T3OTL
U/D
T2EUD
T2IN
T3IN
T3EUD
T4IN
T4EUD
T3OUT
Toggle FF
U/D
U/D
Interrupt
Request
Interrupt
Request
Interrupt
Request
Other
Timers
MCT02141
&
Data Sheet 24 1999-08
Real Time Clock
The Real Time Clock (RTC) module of the C164 consists of a chain of 3 divider bl ocks,
a fixed 8:1 divider, the reloadable 16-bit timer T14, and the 32-bit RTC timer (accessible
via registers RTCH and RTCL). The RTC module is directly clocked with the on-chip
oscillator frequency divided by 32 via a separate clock driver (IRTC = IOSC / 32) and is
therefo re indepen dent from the selected clock ge neration mod e of the C164. Al l timers
count up.
The RTC module can be used for different purposes :
• System clock to determine the current time and date
• Cyclic time base d interr upt
• 48-bit timer for long term measuremen ts
Figure 7 RTC Block Diagram
Note: The registers associated with the RTC are not effected by a reset in order to
maintain the correct system time even when intermediate resets are executed.
RTCLRTCL
T14
T14REL
8:1 fRTC
Reload
Interrupt
Request
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Data Sheet 25 1999-08
A/D Converter
For analog signal measurement, a 10-bit A/D converter with 8 multiplexed input channels
and a sample and hold circuit has been integrated on-chip. It uses the method of
successive approximation. The sample time (for loading the capacitors) and the
conversio n time is programmable and can so be adjuste d to the external circuitry.
Overrun error detection/protection is provided for the conversion result register
(ADDAT): either an interrupt request will be generated when the result of a previous
conversio n has not been rea d fr om the result registe r at the time the ne xt co nversi on is
complete, or the next conversion is suspended in such a case until the previous result
has been rea d.
For applications which require less than 8 analog input channels, the remaining channel
inputs can be used as digital input port pins.
The A/D converter of the C164 supports four different conversion modes. In the standard
Single Channel conversion mode, the analog level on a specified channel is sampled
once and converted to a digital result. In the Single Channel Continuous mode, the
analog level on a specified channel is repeatedly sampled and converted without
software intervention. In the Auto Scan mode, the analog levels on a prespecified
number of channels are sequentially sampled and converted. In the Auto Scan
Continuous mode, the number of prespecified channels is repeatedly sampled and
converted. In addition, the conversion of a specific channel can be inserted (injected) into
a running sequence without disturbing this sequence. This is called Channel Injection
Mode.
The Peripheral Event Controller (PEC) may be used to automatically store the
conversion results into a table in memory for later evaluation, without requiring the
overhead of entering and exiting interrupt routines for each data transfer.
After each reset and also during normal operation the ADC automatically performs
calibration cycles. This automatic self-calibration constantly adjusts the converter to
changing operating conditions (e.g. te mperature) and compensates process vari ations.
These calibration cycles are part of the conversion cycle, so they do not affect the normal
operation of the A/D converter.
In order to decouple analog inputs from digital noise and to avoid input trigger noise
those pins used for analog input can be disconnected from the digital IO or input stages
under software control. This can be selected for each pin separately via registers
P5DIDIS (Port 5 Digital Input Disable).
&
Data Sheet 26 1999-08
Serial Channels
Serial communication with other microcontrollers, processors, terminals or external
peripheral components is provided by two serial interfaces with different functionality, an
Asynchronous/Synchronous Serial Channel (ASC0) and a High-Speed Synchronous
Serial Channel (SSC).
The ASC0 is upward compatible with the serial ports of the Infineon 8-bit microcontroller
families and supports full-duplex asynchronous communication at up to 780 KBaud and
half-duplex synchronous communication at up to 3.1 MBaud @ 25 MHz CPU clock.
A dedicated baud rate generator allows to set up all standard baud rates without
oscillator tuning. For transmission, reception and error handling 4 separate interrupt
vectors are pro vided. In asynchro nous mode, 8- or 9-bit data fr ames are transmitted or
received, preceded by a start bit and terminated by one or two stop bits. For
multiprocessor communication, a mechanism to distinguish address from data bytes has
been inclu ded (8-bit data plu s wake up bit mode).
In synchronous mode, the ASC0 transmits or receives bytes (8 bits) synchronously to a
shift clock which is generated by the ASC0. The ASC0 always shifts the LSB first. A loop
back option is available for testing purposes.
A number of optional hardware error detection capabilities has been included to increase
the reliability of data transfers. A parity bit can automatically be generated on
transmission or be checked on reception. Framing error detection allows to recognize
data frames with missing stop bits. An overrun error will be generated, if the last
character received has not been read out of the receive buffer register at the time the
reception of a ne w character is compl ete.
The SSC supports full-duplex synchronous communication at up to 6.25 Mbaud @
25 MHz CPU clock. It may be configured so it interfaces with serially linked peripheral
componen ts. A dedicated baud rate generator allows to set up all standard bau d rates
without oscillator tuning. For transmission, reception and error handling 3 separate
interrupt ve ctors are provided.
The SSC transmits or receives cha racters of 2...16 bits length synchr onously to a shift
clock which can be generated by the SSC (master mode) or by an external master (slave
mode). The SSC can start shifting with the LSB or with the MSB and allows the selection
of shifting and latching clock edges as well as the clock polarity.
A number of optional hardware error detection capabilities has been included to increase
the reliability of data transfers. Transmit and receive error supervise the correct handling
of the data buffer. Phase and b audrate error detect incorre ct serial data.
&
Data Sheet 27 1999-08
CAN-Module
The integrated CAN-Module handles the completely autonomous transmission and
reception of CAN frame s in accordance with the CAN specification V2.0 part B (active),
i.e. the on-chip CAN-Module can receive and transmit standard frames with 11-bit
identifiers as well as extende d frames with 29-bit identifiers.
The module provides Full CAN functionality on up to 15 message objects. Message
object 15 ma y be configured for Basic CA N functionality. Bo th mod es provid e separa te
masks for acceptance filtering which allows to accept a number of identifiers in Full CAN
mode and also allows to disregard a number of identifiers in Basic CAN mode. All
message objects ca n be updated independent from the other objects and are equip ped
for the maximum message length of 8 bytes.
The bit timing is derived from the CPU clock signal and is programmable up to a data
rate of 1 MBaud. The CAN-Module uses two pins of Port 4 or Port 8 to interface to an
external bus transceiver. The interface pins are assigned via software.
Note: When the CAN interface is assigned to Port 4, the respective segment address
lines on Port 4 can not be used. This will limit the externa l add ress space.
Watchdog Timer
The Watchdog Timer represents one of the fail-safe mechanisms which have been
implemented to prevent the controller from malfunctioning for longer periods of time.
The Watchdog Timer is always enabled after a reset of the chip, and can only be
disabled in the time interval until the EINIT (end of initialization) instruction has been
executed . Thus, the chip’s sta rt-up procedure is always monitore d. The software has to
be designed to service the Watchdog Timer before it overflows. If, due to hardware or
software related failures, the software fails to do so, the Watchdog Timer overflows and
generates an internal hardware reset and pulls the RSTOUT pin low in order to allow
external hardware components to be reset.
The Watchdog Timer is a 16-bit timer, clocked with the system clock divided eit her by 2/
4/128/256. The high byte of the Watchdog Timer register can be set to a prespecified
reload value (stored in WDTREL) in order to allow further variation of the monitored time
interval. Each time it is serviced by the application software, the high byte of the
Watchdog Timer is reloaded. Thus, time intervals between 20 µs and 336 ms can be
monitored (@ 25 MHz).
The default Watchdog Timer interval after reset is 5.24 ms (@ 25 MHz).
&
Data Sheet 28 1999-08
Parallel Ports
The C164 provides up to 59 IO lines which are organized into five input/output ports and
one input port. All port lines are bit-addressable, and all input/output lines are individually
(bit-wise) programmable as inputs or outputs via direction registers. The I/O ports are
true bidir ectiona l ports which are switched to high impeda nce state when co nfigu red as
inputs. The output drive rs of three IO ports ca n be configure d (pin by pin) for p ush/pull
operation or open-drain operation via control registers. The other IO ports operate in
push/pull mod e. During the internal reset, all port pin s are configured as inputs.
All port lines have programmable alternate input or output functions associated with
them. All port lines that are not used for these alternate functions may be used as general
purpose IO lines.
PORT0 and PORT1 may be used as address and data lines when accessing external
memory, while Port 4 outputs the additional segment address bits A21/19/17...A16 in
systems where segmentation is enabled to access more than 64 KBytes of memory.
Ports P1L, P1H, and P8 are associated with the capture inputs or compare outputs of
the CAPCOM uni t, and/or serve as external interrupt inputs.
Port 3 includes alternate functions of timers, serial interfaces, the optional bus control
signal BHE and the system clock output CLKOUT (or the programmable frequency
output FOUT).
Port 5 is used for the analog input channels to the A/D converter or timer control signals.
Port 4 or port 8 may be used for the CAN interfa ce lines.
The edge characteristics (transition time) and driver characteristics (output current) of
the C164’s port drivers can be selected via the Port Output Control registers (POCONx).
&
Data Sheet 29 1999-08
Instruction Set Summary
The table below lists the instructions of the C164 in a condensed way.
The various addressing modes that can be used with a specific instruction, the operation
of the instructions, parameters for conditional execution of instructions, and the opcodes
for each instruction can be found in the “C166 Family Instruction Set Manual”.
This docume nt also provides a detailled description of ea ch instruction.
Table 6 Instruction Set Summary
Mnemonic Description Bytes
ADD(B) Add word (byte) op erands 2 / 4
ADDC(B) Add word (byte) opera nds with Carry 2 / 4
SUB(B ) Subtract word (byte ) operands 2 / 4
SUBC(B ) Subtract word (byte) operands with Carry 2 / 4
MUL(U) (Un)Signed multiply dire ct G PR by direct GPR (16-16-bit) 2
DIV(U) (Un)Signed divide register MDL by direct GPR (16-/16-bit) 2
DIVL(U) (Un)Signed long divide reg. MD by direct GPR (32-/16-bit) 2
CPL(B) Complement direct word (b yte ) GPR 2
NEG(B) Neg ate direct word (byte) GPR 2
AND(B) Bitwise AND, (word/byte ope rands) 2 / 4
OR(B) Bitwise OR, (wor d/byte op erands) 2 / 4
XOR(B) Bitwise XOR, (word/byte operand s) 2 / 4
BCLR Clear direct bit 2
BSET Set direct bit 2
BMOV (N) Move (negated) direct bit to direct bit 4
BAND, BOR,
BXOR AND/OR/XOR direct bit with direct bit 4
BCMP Compare direct bit to direct bit 4
BFLDH/L Bitwise modify masked high/low byte of bit-addressable
direct word memory with immediate data 4
CMP(B) Compare word (byte) oper and s 2 / 4
CMPD1/2 Compare word data to GPR and decrement GPR by 1/2 2 / 4
CMPI1/2 Compare word da ta to GPR and increment GP R by 1/2 2 / 4
PRIO R Determi ne number of shift cycle s to no rmalize direct
word GPR and store result in direct word GPR 2
SHL / S HR Shift left/right di rect word GPR 2
ROL / ROR Rotate left/righ t d irect word GPR 2
ASHR Arithm etic (sign bit) shift right direct word GP R 2
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Data Sheet 30 1999-08
MOV(B) Move word (byte) data 2 / 4
MOVBS Move by te operan d to word operand with sign extension 2 / 4
MOVBZ M ove byte operand to word operand. with zero extension 2 / 4
JMPA, JMPI,
JMPR Jump absolute/indirect/relative if condition is met 4
JMPS Jump absolute to a code segment 4
J(N)B Jump relative if direct bit is (not) set 4
JBC Jump relative and clea r bit if direct bit is set 4
JNBS Jump relative and set bit if d irect bit is not set 4
CALLA, CALLI,
CALLR Call absolute/indirect/relative subroutine if condition is met 4
CALLS Call absolute subroutine in any code segment 4
PCALL Push direct word register onto system stack and call
absolute subroutine 4
TRAP Call interrupt service routine via immediate trap number 2
PUSH, POP Push/pop direct wor d reg ister onto/from system stack 2
SCXT Push direct word register onto system stack und update
register with word ope rand 4
RET Return from intra -segme nt subroutine 2
RETS Return from inter-segme nt su bro utine 2
RETP Return from intra-segme nt su bro utine and pop direct
word register from system stack 2
RETI Return from interrupt service subrouti ne 2
SRST Software Reset 4
IDLE Enter Idle Mode 4
PWRDN Enter Power Down Mode (supposes NMI-pin be ing low) 4
SRVWDT Service Watchd og Timer 4
DISWDT Disable Watchdog Timer 4
EINIT Signify End-of-Initi alization on RSTOUT-pin 4
ATOMIC Begin ATOMIC sequence 2
EXTR Begin EXTended Registe r sequence 2
EXTP(R) Begin EXTend ed Page (and Register) sequence 2 / 4
EXTS(R) Begin EX Tended Segme nt (and Register) sequence 2 / 4
NOP Null operation 2
Table 6 Instruction Set Summary (continued)
Mnemonic Description Bytes
&
Data Sheet 31 1999-08
Special Function Registers Overview
The following table lists all SFRs which are implemented in the C164 in alphabetical
order.
Bit-addressable SFRs are marked with the letter “b” in column “Name”. SFRs within the
Extended SFR-Space (ESFRs) are marked with the letter “E” in column “Physical
Address”. Registers within on-chip X-Peripherals are marked with the letter “X” in column
“Physical Address”.
An SFR can be specified via its individual mnem on ic name. Depending on the selected
addressing mode, an SFR can be accessed via its physical address (using the Data
Page Pointers), or via its short 8-bit addre ss (without using the Data Pag e Pointers).
Table 7 C164 Registers, Ordered by Name
Name Physical
Address 8-Bit
Addr. Description Reset
Value
ADCIC b FF98HCCHA/D Converter End of Conversi on
Interrupt Control Register 0000H
ADCON b FFA0HD0HA/D Converter Control Register 0000H
ADDAT FEA0H50HA/D Converter Result Registe r 0000H
ADDAT2 F0A0HE50HA/D Converter 2 Result Register 0000H
ADDRSEL1 FE18H0CHAddress Select Register 1 0000H
ADDRSEL2 FE1AH0DHAddress Select Register 2 0000H
ADDRSEL3 FE1CH0EHAddress Select Register 3 0000H
ADDRSEL4 FE1EH0FHAddress Select Register 4 0000H
ADEIC b FF9AHCDHA/D Converter Overrun Erro r Interrupt
Control Register 0000H
BUSCON0 b FF0CH86HBus Configuration Register 0 0000H
BUSCON1 b FF14H8AHBus Configuration Register 1 0000H
BUSCON2 b FF16H8BHBus Configuration Register 2 0000H
BUSCON3 b FF18H8CHBus Configuration Register 3 0000H
BUSCON4 b FF1AH8DHBus Configuration Register 4 0000H
C1BTR EF04HX--- CAN1 Bit Timing Register UUUUH
C1CSR EF00HX--- CAN1 Control / Status Register XX 01 H
C1GMS EF06HX--- CAN1 Global Mask Short UFUUH
C1LARn EFn4HX--- CAN Lower Arbitration Register (msg. n) UUUUH
C1LGML EF0AHX--- CAN Lower Global Mask Long UUUUH
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Data Sheet 32 1999-08
C1LMLM EF0EHX--- CAN Lower Mask of Last Message UUUUH
C1MCFGn EFn6HX--- CAN Message Configuration Register
(msg. n)UUH
C1MCRn EFn0HX--- CAN Message Control Register (msg. n) UUUUH
C1PCIR EF02HX--- CAN1 Por t Control / Interrupt Register XXXXH
C1UARn EFn2HX--- CAN Upper Arbitration Register (msg. n) UUUUH
C1UGML EF08HX--- CAN Upper Global Mask Lon g UUUUH
C1UMLM EF0CHX--- CAN Upper Mask of Last Message UUUUH
CC10IC b FF8CHC6HExternal Interrupt 2 Control Reg ister 0000 H
CC11IC b FF8EHC7HExternal Interrupt 3 Control Reg ister 0000 H
CC16 FE60H30HCAPCOM Reg iste r 16 0000H
CC16IC b F160HEB0HCAPCOM Reg . 16 In terrupt Ctrl. Reg. 0000 H
CC17 FE62H31HCAPCOM Reg iste r 17 0000H
CC17IC b F162HEB1HCAPCOM Reg . 17 In terrupt Ctrl. Reg. 0000 H
CC18 FE64H32HCAPCOM Reg iste r 18 0000H
CC18IC b F164HEB2HCAPCOM Reg . 18 In terrupt Ctrl. Reg. 0000 H
CC19 FE66H33HCAPCOM Reg iste r 19 0000H
CC19IC b F166HEB3HCAPCOM Reg . 19 In terrupt Ctrl. Reg. 0000 H
CC20 FE68H34HCAPCOM Reg iste r 20 0000H
CC20IC b F168HEB4HCA PCOM Reg. 20 Interrupt Ctrl. Reg. 0000H
CC21 FE6AH35HCAPCOM Reg iste r 21 0000H
CC21IC b F16AHEB5HCA PCOM Reg. 21 Interrupt Ctrl. Reg. 0000H
CC22 FE6CH36HCAPCOM Register 22 0000H
CC22IC b F16CHEB6HCAPCOM Reg. 22 Interrupt Ctrl. Reg. 0000 H
CC23 FE6EH37HCAPCOM Reg iste r 23 0000H
CC23IC b F16EHEB7HCA PCOM Reg. 23 Interrupt Ctrl. Reg. 0000H
CC24 FE70H38HCAPCOM Reg iste r 24 0000H
CC24IC b F170HEB8HCAPCOM Reg . 24 In terrupt Ctrl. Reg. 0000 H
CC25 FE72H39HCAPCOM Reg iste r 25 0000H
CC25IC b F172HEB9HCAPCOM Reg . 25 In terrupt Ctrl. Reg. 0000 H
Table 7 C164 Registers, Ordered by Name (continued)
Name Physical
Address 8-Bit
Addr. Description Reset
Value
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Data Sheet 33 1999-08
CC26 FE74H3AHCAPCOM Register 26 0000H
CC26IC b F174HEBAHCAPCOM Reg . 26 Interrupt Ctrl. Reg. 0000H
CC27 FE76H3BHCAPCOM Register 27 0000H
CC27IC b F176HEBBHCAPCOM Reg . 27 Interrupt Ctrl. Reg. 0000H
CC28 FE78H3CHCAPCOM Register 28 0000H
CC28IC b F178HEBCHCAPCOM Reg. 28 Inte rrupt Ctrl. Reg. 00 00H
CC29 FE7AH3DHCAPCOM Register 29 0000H
CC29IC b F184HEC2HCAPCOM Reg . 29 Interrupt Ctrl. Reg. 0000H
CC30 FE7CH3EHCAPCOM Register 30 0000H
CC30IC b F18CHEC6HCAPCOM Reg. 30 Interrupt Ctrl. Reg. 0000H
CC31 FE7EH3FHCAPCOM Register 31 0000H
CC31IC b F194HECAHCAPCOM Reg . 31 Interrupt Ctrl. Reg. 0000H
CC60 FE30H18HCAPCOM 6 Register 0 0000H
CC61 FE32H19HCAPCOM 6 Register 1 0000H
CC62 FE34H1AHCAPCOM 6 Register 2 0000H
CC6EIC b F188HEC4HCAPCOM 6 Emergency Interrrupt
Control Register 0000H
CC6IC b F17EHEBFHCAPCOM 6 Interrupt Contro l Register 00 00H
CC6MCON b FF32H99HCAPCOM 6 Mode Control Register 00FFH
CC6MIC b FF36H9BHCAPCOM 6 Mode Interrupt Ctrl. Reg . 0000H
CC6MSEL F036HE1BHCAPCOM 6 Mode Select Register 0000H
CC8IC b FF88HC4HExternal Interrupt 0 Control Register 0000H
CC9IC b FF8AHC5HExternal Interrupt 1 Control Register 0000H
CCM4 b FF22H91HCAPCOM Mode Control Register 4 00 00H
CCM5 b FF24H92HCAPCOM Mod e Control Register 5 0000 H
CCM6 b FF26H93HCAPCOM Mode Control Register 6 00 00H
CCM7 b FF28H94HCAPCOM Mod e Control Register 7 0000 H
CMP13 FE36H1BHCAPCOM 6 Timer 13 Compare Reg. 0000H
CP FE10H08HCPU Context Pointer Register FC00H
Table 7 C164 Registers, Ordered by Name (continued)
Name Physical
Address 8-Bit
Addr. Description Reset
Value
&
Data Sheet 34 1999-08
CSP FE08H04HCPU Co de Segment Pointe r Register
(8 bits, not di rectly writeable) 0000H
CTCON b FF30H98HCAPCOM 6 Compare Ti mer Ctrl. Reg. 1010H
DP0H b F102HE81HP0H Direction Control Reg ister 00H
DP0L b F100HE80HP0L Directio n Con tro l Register 00H
DP1H b F106HE83HP1H Direction Control Reg ister 00H
DP1L b F104HE82HP1L Directio n Con tro l Register 00H
DP3 b FFC6HE3HPort 3 Direction Control Register 0000H
DP4 b FFCAHE5HPort 4 Direction Control Register 00H
DP8 b FFD6HEBHPort 8 Direction Control Register 00H
DPP0 FE00H00HCPU Da ta Page Pointer 0 Reg . (1 0 bits) 0000H
DPP1 FE02H01HCPU Da ta Page Pointer 1 Reg . (1 0 bits) 0001H
DPP2 FE04H02HCPU Da ta Page Pointer 2 Reg . (1 0 bits) 0002H
DPP3 FE06H03HCPU Da ta Page Pointer 3 Reg . (1 0 bits) 0003H
EXICON b F1C0HEE0HExternal Interrup t Control Register 0000H
EXISEL b F1DAHEEDHExternal Interrupt Source Select Reg. 0000H
IDCHIP F07CHE3EHIdentifier XXXXH
IDMANUF F07EHE3FHIdentifier 1820H
IDMEM F07AHE3DHIdentifier XXXXH
IDPROG F078HE3CHIdentifier XXXXH
ISNC b F1DEHEEFHInter rupt Subnode Control Register 0000H
MDC b FF0EH87HCPU Multiply Divide Control Registe r 0000H
MDH FE0CH06HCP U Mu ltiply Divide Reg. – High Word 0000H
MDL FE0EH07HCPU Mu ltiply Divide Reg. – Low Word 0000H
ODP3 b F1C6HEE3HPort 3 Open Drain Control Register 0000H
ODP4 b F1CAHEE5HPort 4 Open Drain Control Register 00H
ODP8 b F1D6HEEBHPort 8 Open Drain Control Register 00H
ONES b FF1EH8FHConstant Value 1’ s Register (rea d only) FFFFH
P0H b FF02H81HPort 0 High Reg. (Upper half of PO RT0) 00H
P0L b FF00H80HP ort 0 Low Reg . (L ower half of PORT0 ) 00H
Table 7 C164 Registers, Ordered by Name (continued)
Name Physical
Address 8-Bit
Addr. Description Reset
Value
&
Data Sheet 35 1999-08
P1H b FF06H83HPort 1 High Reg. (Up per half of PORT1) 00H
P1L b FF04H82HPort 1 Low Reg. (Lower h alf of PORT1) 00H
P3 b FFC4HE2HPort 3 Register 0000H
P4 b FFC8HE4HPort 4 Register (7 bits) 00H
P5 b FFA2HD1HPort 5 Register (read only) XXXXH
P5DIDIS b FFA4HD2HPort 5 Digital Input Disable Register 0000H
P8 b FFD4HEAHPort 8 Register (8 bits) 00H
PECC0 FEC0H60HPEC Channel 0 Control Register 0000H
PECC1 FEC2H61HPEC Channel 1 Control Register 0000H
PECC2 FEC4H62HPEC Channel 2 Control Register 0000H
PECC3 FEC6H63HPEC Channel 3 Control Register 0000H
PECC4 FEC8H64HPEC Channel 4 Control Register 0000H
PECC5 FECAH65HPEC Channel 5 Control Register 0000H
PECC6 FECCH66HPEC Channel 6 Control Register 0000H
PECC7 FECEH67HPEC Channel 7 Control Register 0000H
PICON b F1C4HEE2HPort Input Threshold Control Register 0000H
POCON0H F082HE41HPort P0H Output Control Register 0000 H
POCON0L F080HE40HPort P0L Output Control Register 0000H
POCON1H F086HE43HPort P1H Output Control Register 0000 H
POCON1L F084HE42HPort P1L Output Control Register 0000H
POCON20 F0AAHE55HDedicated Pin Output Control Register 0000 H
POCON3 F08AHE45HPort P3 Output Control Register 0000H
POCON4 F08CHE46HPort P4 Outp ut Control Register 0000H
POCON8 F092HE49HPort P8 Output Control Register 0000H
PSW b FF10H88HCPU Program Status Word 0000H
PTCR F0AEHE57HPort Temperature Compensation Reg. 0000H
RP0H b F108HE84HSystem Startup Config. Reg. (Rd. only) XXH
RSTCON b F1E0HE--- Reset Con tro l Register 00XXH
RTCH F0D6HE6BHRTC High Register no
RTCL F0D4HE6AHRTC Low Register no
Table 7 C164 Registers, Ordered by Name (continued)
Name Physical
Address 8-Bit
Addr. Description Reset
Value
&
Data Sheet 36 1999-08
S0BG FEB4H5AHSerial Channel 0 Baud Rate Generator
Reload Register 0000H
S0CON b FFB0HD8HSerial Channel 0 Control Register 0000H
S0EIC b FF70HB8HSerial Channel 0 Error Interrupt Ctrl.
Reg. 0000H
S0RBUF FEB2H59HSerial Channel 0 Receive Buffer Reg.
(read only) XXXXH
S0RIC b FF6EHB7HSerial Channel 0 Receive Interrupt
Control Reg iste r 0000H
S0TBIC b F19CHECEHSerial Channel 0 Transmit Buffer
Interrupt Control Register 0000H
S0TBUF FEB0H58HSerial Channel 0 Transmit Buffer Reg.
(write only) 0000H
S0TIC b FF6CHB6HSerial Channel 0 Transmit Interrupt
Control Reg iste r 0000H
SP FE12H09HCPU System Stack Pointer Register FC00H
SSCBR F0B4HE5AHSSC Ba udrate Register 0000H
SSCCON b FFB2HD9HSSC Control Register 0000H
SSCEIC b FF76HBBHSSC Error Interrupt Control Register 0000H
SSCRB F0B2HE59HSSC Receive Buffer XXXXH
SSCRIC b FF74HBAHS SC Receive Interrupt Control Register 0000H
SSCTB F0B0HE58HSSC Tran smit Buffer 0000H
SSCTIC b FF72HB9HSSC Transmit Interrupt Control Register 0000H
STKOV FE14H0AHCPU S ta c k Overflow Pointer Register FA00H
STKUN FE16H0BHCPU Stack Underflow Poin ter Register FC00H
SYSCON b FF12H89HCPU System Configuration Register 1) 0xx0H
SYSCON1 b F1DCHEEEHCPU S ystem Confi guration Register 1 0000H
SYSCON2 b F1D0HEE8HCPU System Configuration Register 2 0 000H
SYSCON3 b F1D4HEEAHCPU System Configuration Register 3 0 000H
T12IC b F190HEC8HCAPCOM 6 Timer 12 Interrupt Ctrl. Reg. 0000H
T12OF F034HE1AHCAPCOM 6 Timer 12 Offset Register 0000H
Table 7 C164 Registers, Ordered by Name (continued)
Name Physical
Address 8-Bit
Addr. Description Reset
Value
&
Data Sheet 37 1999-08
T12P F030HE18HCAPCOM 6 Timer 12 Pe riod Register 0000H
T13IC b F198HECCHCAPCOM 6 Timer 13 Interrupt Ctrl. Reg. 0000H
T13P F032HE19HCAPCOM 6 Timer 13 Period Register 0000H
T14 F0D2HE69HRTC Timer 14 Register no
T14REL F0D0HE68HRTC Timer 14 Reload Register no
T2 FE40H20HGPT1 Timer 2 Register 0000H
T2CON b FF40HA0HGPT1 Timer 2 Control Reg ister 0000 H
T2IC b FF60HB0HGPT1 Timer 2 Interrupt Control Register 0000H
T3 FE42H21HGPT1 Timer 3 Register 0000H
T3CON b FF42HA1HGPT1 Timer 3 Control Reg ister 0000 H
T3IC b FF62HB1HGPT1 Timer 3 Interrupt Con tro l Register 0000H
T4 FE44H22HGPT1 Timer 4 Register 0000H
T4CON b FF44HA2HGPT1 Timer 4 Control Reg ister 0000 H
T4IC b FF64HB2HGPT1 Timer 4 Interrupt Con tro l Register 0000H
T7 F050HE28HCAPCOM Timer 7 Register 0000H
T78CON b FF20H90HCAPCOM Timer 7 and 8 Ctrl. Re g. 0000 H
T7IC b F17AHEBDHCAPCOM Timer 7 Interrupt Ctrl. Reg. 0000H
T7REL F054HE2AHCAPCOM Timer 7 Reload Re gister 0000H
T8 F052HE29HCAPCOM Timer 8 Register 0000H
T8IC b F17CHEBEHCAPCOM Timer 8 Interrupt Ctrl. Reg. 0000H
T8REL F056HE2BHCAPCOM Timer 8 Reload Re gister 0000H
TFR b FFACHD6HTrap Flag Register 0000H
TRCON b FF34H9AHCAPCOM 6 Trap Ena ble Ctrl. Reg. 00XXH
WDT FEAEH57HWatchdog Time r Register (re ad only) 0000H
WDTCON FFAEHD7HWatchdog Timer Control Register 2) 00xxH
XP0IC b F186HEC3HCAN1 Module Interrupt Control Register 0000H
XP1IC b F18EHEC7HFlash Termination Interrupt Control Reg. 0000H
XP3IC b F19EHECFHPLL/RTC Interrupt Control Register 0000H
ZEROS b FF1CH8EHConstant Value 0’s Reg ister (read only) 0000 H
1) The system configuration is selected during reset.
Table 7 C164 Registers, Ordered by Name (continued)
Name Physical
Address 8-Bit
Addr. Description Reset
Value
&
Data Sheet 38 1999-08
2) The reset value depends on the indicated reset source.
&
Data Sheet 39 1999-08
Absolute Maximum Ratings
Note: Stresses above those listed under “Absolute Maximum Ratings” may cause
permanent damage to the device. This is a stress rating only and functional
operation of the device at th ese or any othe r condition s above those indica ted in
the opera tional sections of th is specification is not implied . Exposure to absolu te
maximum rating cond itions for extended periods may affect d evice reli ability.
During absolute maximum rating overload conditions (
9
IN
>
9
DD
or
9
IN
<
9
SS
) the
voltage on
9
DD
pins with respect to ground (
9
SS
) must not exceed the values
defined by the absolute maximum ratings.
Table 8 Absolute Maximum Rating Parameters
Parameter Symbol Limit Values Unit Notes
min. max.
Storage temperature 7ST -65 150 °C
Voltage on 9DD pins with
respect to ground (9SS)9DD -0.5 6.5 V
Voltage on any pin with
respect to ground (9SS)9IN -0.5 9DD+0.5 V
Input current on any pi n
during overload co ndition -10 10 mA
Absolute su m of all input
currents during overload
condition
- |100| mA
Power di ssipa tion 3DISS 1.5 W
&
Data Sheet 40 1999-08
Operating Conditions
The following operating conditions must not be exceeded in order to ensure correct
operation of the C164. All p arameters specified in the following se ctions refer to the se
operating conditions, unless otherwise noticed.
Table 9 Operating Condition Parameters
Parameter Symbol Limit Values Unit Notes
min. max.
Standard
digital supply voltage 9DD 4.5 5.5 V Active mode,
ICPUmax = 25 MHz
2.5 1)
1) Output voltages and output currents will be reduced when 9DD leaves the range defined for active mode.
5.5 V PowerDown mode
Digital ground voltage 9SS 0 V Reference voltage
Overload current ,OV -±5 mA Per pin 2) 3)
2) Overload conditions occur if the standard operatings conditions are exceeded, i.e. the voltage on any pin
exceeds the specified range (i.e. 9OV !9DD+0.5V or 9OV 9SS-0.5V). The absolute sum of input overload
currents on all port pins may not exceed 50 mA. The supply voltage must remain within the specified limits.
3) Not 100% tested, guaranteed by design characterization.
Absolute sum of overlo ad
currents Σ|,OV|- 50 mA
3)
External Loa d
Capacitance &L- 1 00 pF Pin drivers in
fast edge mode 4)
4) The timing is valid for pin drivers in high current or dynamic current mode. The reduced static output current in
dynamic current mode must be respected when designing the system.
Ambie nt te mperature 7A070°C SAB-C164...
-40 85 °C SAF-C164...
-40 125 °C SAK-C164...
&
Data Sheet 41 1999-08
Parameter Interpretation
The parameters listed in the following partly represent the characteristics of the C164
and par tly its demands on the system. To aid in interpreting the pa rame te rs rig ht, when
evaluating them for a design, they are marked in colu mn “Symb ol”:
CC (Controller Characteristics):
The logic of the C164 will provide signals with the respective timing cha racteristics.
SR (System Requirement):
The external system must provide signals with the respective timing characteristics to
the C164.
DC Characteristics
(Operating Conditions apply)
Parameter Symbol Limit Values Unit Test Condition
min. max.
Input low voltage XTAL1,
P3.0, P3.1, P6.5, P6.6, P6.7 9IL1 SR – 0.5 0.3
V
DD V–
Input low voltage
(TTL) 9IL SR – 0.5 0 .2 9DD
– 0.1 V–
Input low voltage
(Spe cial Thresh old) 9ILS SR – 0.5 2.0 V –
Input high vo ltage RSTIN 9IH1 SR 0.6 9DD 9DD +
0.5 V–
Input high voltage XTAL1,
P3.0, P3.1, P6.5, P6.6, P6.7 9IH2 SR 0.7 9DD 9DD +
0.5 V–
Input high vo ltage
(TTL) 9IH SR 0.2 9DD
+ 0.9 9DD +
0.5 V–
Input high vo ltage
(Spe cial Thresh old) 9IHS SR 0.8 9DD
- 0.2 9DD +
0.5 V–
Input Hysteresis
(Spe cial Thresh old) HYS 400 – mV –
Output low voltage
(PORT0, PORT1, Port 4, ALE,
RD, WR, BHE, CLKOUT,
RSTOUT)
9OL CC – 0.45 V ,OL = 2.4 mA
Output low voltage
(P3.0, P3.1, P6.5, P6.6, P6.7 ) 9OL2 CC – 0.4 V ,OL2 = 3 mA
&
Data Sheet 42 1999-08
Output low voltage
(all other outputs) 9OL1 CC –0.45V,OL = 1.6 mA
Output hi gh voltage 1)
(PORT0, PORT1, Port 4, ALE,
RD, WR, BHE , CLKOUT,
RSTOUT)
9OH CC 2.4 – V ,OH = -2.4 mA
0.9 9DD –V,OH = -0.5 mA
Output hi gh voltage 1)
(all other outputs) 9OH1 CC 2.4 – V ,OH = -1.6 mA
0.9 9DD –V,OH = -0.5 mA
Input leakage current (P ort 5) ,OZ1 CC – ±200 nA 0.45V < 9IN < 9DD
Input leakage curren t (all other) ,OZ2 CC – ±500 nA 0.45V < 9IN < 9DD
RSTIN inactive current 2) ,RSTH 3) – -10 µA9IN = 9IH1
RSTIN active current 2) ,RSTL 4) -100 – µA9IN = 9IL
Read/Write inactive current 5) ,RWH 3) – -40 µA9OUT = 2.4 V
Read/Write active current 5) ,RWL 4) -500 – µA9OUT = 9OLmax
ALE inactive current 5) ,ALEL 3) –40µA9OUT = 9OLmax
ALE active current 5) ,ALEH 4) 500 – µA9OUT = 2.4 V
Port 4 ina ctive current 5) ,P4H 3) – -40 µA9OUT = 2.4 V
Port 4 active current 5) ,P4L 4) -500 – µA9OUT = 9OL1max
PORT0 configuration current 5) ,P0H 3) – -10 µA9IN = 9IHmin
,P0L 4) -100 – µA9IN = 9ILmax
XTAL 1 inp ut current ,IL CC – ±20 µA0 V < 9IN < 9DD
Pin capacitance 6)
(digital inputs/outputs) &IO CC – 10 pF I = 1 MHz
7A = 25 °C
1) This specification is not valid for outputs which are switched to open drain mode. In this case t he respective
output will float and the voltage results from the external circuitry.
2) These parameters describe the RSTIN pullup, which equals a resistance of ca. 50 to 250 KΩ.
3) The maximum current may be drawn while the respective signal line remains inactive.
4) The minimum current must be drawn in order to drive the respective signal line active.
5) This specification is only valid during Reset, or during Adapt-mode. The Port 4 current values are only v alid for
pins P4.3-0, which can act as chip select outputs.
6) Not 100% tested, guaranteed by design characterization.
DC Characteristics (continued)
(Operating Con ditions apply)
Parameter Symbol Limit Values Unit Test Condition
min. max.
&
Data Sheet 43 1999-08
Power Consumption C164-8R (ROM)
(Operating Conditions apply)
Parameter Symbol Limit Values Unit Test Condition
min. max.
Power supply curre nt (5V active)
with all periphe rals active ,DD5 –1 +
2.5*ICPU
mA RSTIN = 9IL2
ICPU in [MHz] 1)
1) The supply current is a function of the operating frequency. This dependency is illustrated in the figure below.
These parameters are tested at 9DDmax and maximum CPU clock with all outputs disconnected and all inputs
at 9IL or 9IH.
The oscillator also contributes to the total supply current . The given values refer to the worst case, i.e. I PDRmax.
For lower oscillator frequencies the respective supply current can be reduced accordingly.
Idle mode suppl y current (5V)
with all periphe rals active ,IDX5 –1 +
1.1*ICPU
mA RSTIN = 9IH1
ICPU in [MHz] 1)
Idle mode suppl y current (5V)
with all periphe rals deactivated,
PLL off, SDD factor = 32
,IDO5 2)
2) This parameter is determined mainly by the current consumed by the oscillator. This current, however, is
influenced by the external oscillator circuitry (crystal, capacitors). The values given refer to a typical circuitry
and may change in case of a not optimized external oscillator circuitry.
– 500 +
50*IOSC
µA RSTIN = 9IH1
IOSC in [MHz] 1)
Power-down mode supply
current (5V) with RTC running ,PDR5 2) – 200 +
25*IOSC
µA9DD = 9DDmax
IOSC in [MHz] 3)
3) This parameter is tested including lea kage currents. All inputs (including pins configured as inputs) at 0 V to
0.1 V or at 9DD – 0.1 V to 9DD, 9REF = 0 V, all outputs (including pins configured as outputs) disconnected.
Power-down mode suppl y
current (5V) with RTC disa ble d ,PDO5 –50µA9DD = 9DDmax 3)
&
Data Sheet 44 1999-08
Power Consumption C164-8F (Flash)
(Operating Con ditions apply)
Parameter Symbol Limit Values Unit Test Condition
min. max.
Power su pply current (5V active)
with all peripheral s active ,DD5 –40 +
3.5*ICPU
mA RSTIN = 9IL2
ICPU in [MHz] 1)
1) The supply current is a function of the operating frequency. This dependency is illustrated in the figure below.
These parameters are tested at 9DDmax and maxim um CP U clock with all outputs disconnected and all i nputs
at 9IL or 9IH.
The oscillator also contributes to the total supply current . The given values refer t o the worst case, i.e. I PDRmax.
For lower oscillator frequencies the respective supply current can be reduced accordingly.
Idle mode supply curren t (5V)
with all peripheral s active ,IDX5 –40 +
1.4*ICPU
mA RSTIN = 9IH1
ICPU in [MHz] 1)
Idle mode supply curren t (5V)
with all peripheral s deactivated,
PLL off, SDD factor = 32,
Flash modules off
,IDO5 2)
2) This parameter is determined mainly by the current consumed by the oscillator. This current, however, is
influenced by the external oscillator circuitry (crystal, capacitors). The values given refer to a typical circuitry
and may change in case of a not optimized external oscillator circuitry.
–500 +
50*IOSC
µARSTIN = 9IH1
IOSC in [MHz] 1)
Power-do wn mode supply
current (5V) with RTC running ,PDR5 2) –200 +
25*IOSC
µA9DD = 9DDmax
IOSC in [MHz] 3)
3) This parame ter is tested including leakage currents. All inputs (including pins configured as input s) at 0 V to
0.1 V or at 9DD – 0.1 V to 9DD, 9REF = 0 V, all outputs (including pins configured as outputs) disconnected.
Power-do wn mode supply
current (5V) with RTC disabled ,PDO5 –50µA9DD = 9DDmax 3)
&
Data Sheet 45 1999-08
Figure 8 Idle and Power Down Supply Current as a Function of Oscillator
Frequency
I [µA]
IOSC [MHz]
4
,
3'5PD[
812 16
,
3'2PD[
1500
1250
1000
750
500
250
,
,'2PD[
&
Data Sheet 46 1999-08
Figure 9 Supply/Idle Current as a Function of Operating Frequency
, [mA]
ICPU [MH z]
510 15 25
120
60
30
IDD5max
IIDX5max
IDD5typ
IIDX5typ
20
90
IDD5max
IIDX5max
IDD5typ
IIDX5typ
C164-8R (ROM) C164-8F (Flash)
&
Data Sheet 47 1999-08
AC Characteristics
Definition of Internal Timing
The internal operation of the C164 is controlled by the internal CPU clock ICPU. Both
edges of the CP U clock can trigger internal (e.g. pipeline ) or external (e.g. bus cycles)
operations.
The specification of the external timing (AC Characteristics) therefore depends on the
time between two consecutive edges of the CPU clock, called “TCL” (see figure below).
Figure 10 Generation Mechanisms for the CPU Clock
The CPU clock signal ICPU can be generated from the oscillator clock signal IOSC via
different mechanisms. The duration of TCLs and their variation (and also the derived
external timin g) depends o n the used me chanism to gene rate ICPU. This influence must
be regard ed when calculating the timings fo r the C164.
Note: The example for PLL operation shown in the fig. above refers to a PLL factor of 4.
The used mechanism to generate the CPU clock is selected during reset via the logic
levels on pins P0.15 -13 (P0H.7-5).
The table below associates the combinations of these three bits with the respective clock
generation mode.
TCLTCL
TCLTCL
I
&38
I
26&
I
&38
I
26&
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'LUHFW&ORFN'ULYH
TCL TCL
I
&38
I
26&
3UHVFDOHU2SHUDWLRQ
&
Data Sheet 48 1999-08
Prescaler Operation
When pins P0.15-13 (P0H.7-5) equal 001B during reset the CPU clock is derived from
the internal oscillator (input clock signal ) by a 2:1 prescaler.
The frequency of ICPU is half the frequency of IOSC and the high and low time of ICPU (i.e.
the duration of an individual TCL) is defined by th e period of the input clock IOSC.
The timings listed in the AC Characteristics that refer to TCLs therefore can be
calculated using th e period of IOSC for any TCL.
Phase Locked Loop
For all combinations of pins P0.15-13 (P0H.7-5) except for 001B and 011B the on-chip
phase lo cked loop is ena bled and provides the CPU cloc k (see table above). The PLL
multiplies the input frequency by the factor F which is selected via the combination of
pins P0.15-13 (i.e. ICPU = IOSC * F). With every F’th transition of IOSC the PLL circuit
synchron izes the CPU clock to the in put clock. This synchronization is d one smoothly,
i.e. the CPU clock frequency do es no t change abruptly.
Due to this adapta tion to the input clo ck the frequency of ICPU is constantly adjusted so
it is locked to IOSC. The slight variation causes a jitter of ICPU which also effects the
duration of individual TCLs.
Table 10 C164 Clock Generation Modes
P0.15-13
(P0H.7-5) CPU Frequency
ICPU = IOSC * F External Clock
Input Range 1) Notes
11 1 IOSC * 4 2.5 to 6.25 MHz Default configuration
110 IOSC * 3 3.33 to 8.33 MHz
101 IOSC * 2 5 to 12.5 MHz
100 IOSC * 5 2 to 5 MHz
011 IOSC * 1 1 to 25 MHz Direct drive 2)
010 IOSC * 1.5 6.66 to 16.6 MHz
001 IOSC / 2 2 to 50 MHz CPU clock via prescaler
000 IOSC * 2.5 4 to 10 MHz
1) The external clock input range refers to a CPU clock range of 10...25 MHz.
2) The maximum frequency depends on the duty cycle of the external clock signal.
&
Data Sheet 49 1999-08
The timings listed in the AC Characteristics that refer to TCLs therefore must be
calculated using the minimum TCL that is possible under the respective circumstances.
The actual minimum value for TCL depends on the jitter of the PLL. As the PLL is
constantly adjusting its output frequency so it corresponds to the applied input frequency
(crystal or oscillator) the relative deviation for periods of more than one TCL is lower than
for one single TCL (see form ula and figure below).
For a period of
N
* TCL the minimum value is computed using the corresponding
deviation D
N
:
(
N
* TCL)min =
N
* TCLNOM - D
N
D
N
[ns] = ±(13.3 +
N
*6.3) / ICPU [MHz],
where
N
= number of cons ecutive TCLs and 1 ≤
N
≤ 40.
So for a period of 3 TCLs @ 25 MHz (i.e.
N
= 3): D
3
= (13.3 +
3
* 6.3) / 25 = 1.288 ns,
and (3TCL)min = 3TCLNOM - 1.288 n s = 58.7 ns (@ ICPU = 25 MHz).
This is especi ally importa nt for bus cycles using waitsta tes and e.g. for th e opera tion of
timers, serial interfaces, etc. For all slower operations and longer periods (e.g. pulse train
generation or measurement, lower baudrates, etc.) the deviation caused by the PLL jitter
is neglectible.
Note: For all periods longer than 40 TCL the N=40 value can be used (see figure below).
Figure 11 Approximated Maximum Accumulated PLL Jitter
40201051
±1
±10
±20
N
This approximated fo rm ula is valid for
1 ≤ 1 ≤ 40 and 10MHz ≤ fCPU ≤ 25MHz.
±26.5
Max.jitter D
1
[ns]
20 MHz
25 MHz
16 MHz
10 MHz
&
Data Sheet 50 1999-08
Direct Drive
When pins P0.15-13 (P0H.7-5) equal 011B during reset the on-chip phase locked loop is
disabled and the CPU clock is directly driven from the internal oscillator with the input
clock sign al.
The frequen cy of ICPU directly follows the freque ncy of IOSC so the hig h and low time of
ICPU (i.e. the duration of an individual TCL) is defined by the duty cycle of the input clock
IOSC.
The timings listed below that refer to TCLs therefore must be calculated using the
minimum TCL that is possible under the respective circumstances. This minimum value
can be calcu lated via the fo llowing formula:
TCLmin = 1/IOSC * DCmin (DC = duty cycle)
For two consecutive TCLs the deviation caused by the duty cycle of IOSC is compensated
so the duration of 2TCL is always 1/IOSC. The minimum value TCLmin therefore has to be
used only once for timings that require an odd number of TCLs (1,3,...). Timings that
require an even number of TCL s (2,4,...) may use the formula 2TCL = 1/IOSC.
Note: The address flo at timi ngs in Multiplexed bus mode (
W
11
and
W
45
) use the maximum
duration of TCL (TCL
max
= 1/
IOSC
* DC
max
) instead of TCL
min
.
&
Data Sheet 51 1999-08
AC Characteristics
Figure 12 External Clock Drive XTAL1
Note: The main oscillator is optimized for oscillation with a crystal within a frequency
range of 4...16 MHz. When driven by an external clock signal it will accept the
specified frequency range. Operation at lower input frequencies is possible b ut is
guaranteed by design only (not 100% tested).
It is strongly recommended to measure the oscillation allowance (or margin) in the
final target system (layout) to determine the optimum parameters for the oscillator
operation.
External Clock Drive XTAL1
(Operating Conditions apply)
Parameter Symbol Direct Drive
1:1 Prescaler
2:1 PLL
1:N Unit
min. max. min. max. min. max.
Osci llator period WOSCSR 40 – 20 – 60 1)
1) The minimum and maximum oscillator periods for PLL operation depend on the selected CPU clock generation
mode. Please see respective table above.
500 1) ns
High time 2)
2) The clock input signal must reach the defined levels 9IL and 9IH2.
W1SR 20 3)
3) The minimum high and low time refers to a duty cycle of 50%. The maximum operating frequency (ICPU) in
direct drive mode depends on the duty cycle of the clock input signal.
–6–10–ns
Low time 2) W2SR 20 3) –6–10–ns
Rise time 2) W3SR–10–6–10ns
Fall time 2) W4SR–10–6–10ns
&
Data Sheet 52 1999-08
A/D Converter Characteristics
(Operating Con ditions apply)
4.0V (2.6V)≤9AREF ≤ 9DD + 0.1V (Note the influence on TUE.)
9SS - 0.1V ≤ 9AGND ≤ 9SS + 0.2V
Parameter Symbol Limit Values Unit Test Condition
min. max.
Analog input voltage range 9AIN SR 9AGND 9AREF V1)
1) 9AIN may exceed 9AGND or 9AREF up to the absolute maximum ratings. However, the conversion result in these
cases will be X000H or X3FFH, respectively.
Basic clock frequency IBC 0.5 6.25 MHz 2)
2) The limit values for IBC must not be exceeded when selecting the CPU frequency and the ADCTC setting.
Conversion time WCCC –40 WBC +
WS+2WCPU
3)
WCPU = 1 / ICPU
3) This paramet er includes the sample time WS, the time for determining the digital result and the time to load the
result register with the conversion result.
Values for the basic clock WBC depend on the conversion time programming.
This parameter depends on the ADC control logic. It is not a real maximum value, but rather a fixum.
Total unadjusted erro r TUE CC
4)
4) TUE is tested at 9AREF=5.0V (3.3V),9AGND=0V, 9DD=4.9V (3.2V). It is guaranteed by design for all other
voltages within the defined voltage range.
The specified TUE is guaranteed only if an overload condition (see ,OV specification) occurs on maximum 2 not
selected analog input pins and the ab solute sum of input overload currents on all analog input pins does not
exceed 10 mA.
During the reset calibration sequence the maximum TUE may be ±4 LSB (±8 LSB @ 3V).
–± 2LSB9AREF ≥ 4.0 V
–± 4LSB
9AREF ≥ 2.6 V
Internal resistance of
reference voltag e source 5AREF SR – WBC / 60
- 0.25 kΩWBC in [ns] 5) 6)
5) During the conversion the ADC’s capacitance must be repeatedly charged or discharged. The internal
resistance of the reference voltage source must allow the capacitance to reach its respective voltage level
within each conversion step. The maximum internal resistance results from the programmed conversion timing.
6) Not 100% tested, guaranteed by design.
Internal resistance of analo g
source 5ASRCSR –WS / 450
- 0.25 kΩWS in [ns] 6) 7)
7) During the sample time the input capacitance &I can be charged/discharged by the external source. The
internal resistance of the analog source must allow the capacitance to reach its final voltage level within WS.
After the end of the sample time WS, changes of the analog input voltage have no effect on the conversion result.
Values for the sample time WS depend on programming and can be taken from the table below.
ADC input capacitance &AIN CC – 33 pF 6)
&
Data Sheet 53 1999-08
Sample time and con version time o f the C164’s A/D Co nverter are progr ammable. The
table below should be used to calculate the ab ove timings.
The limit values for IBC must not be exceeded when selecting ADCTC.
Converter Timing Example:
Assumptions: ICPU = 25 MHz (i.e. WCPU = 40 ns), ADCTC = ’00’, ADSTC = ’00’.
Basic clock IBC = ICPU / 4 = 6.25 MHz, i.e. WBC = 160 ns.
Sample time WS= WBC * 8 = 1280 ns.
Conversion time WC= WS + 40 WBC + 2 WCPU = (12 80 + 6400 + 80) ns = 7.8 µs.
Memory Cycle Variables
The timing tables below use three variables which are derived from the BUSCONx
registers and represent the special characteristics of the programmed memory cycle.
The following table describes, how th ese variables are to be computed .
Table 11 A/D Converter Computation Table
ADCON.15|14
(ADCTC) A/D Converter
Basic clock IBC ADCON.13|12
(ADSTC) Sample time
WS
00 ICPU / 4 00 WBC * 8
01 ICPU / 2 01 WBC * 16
10 ICPU / 16 10 WBC * 32
11 ICPU / 8 11 WBC * 64
Table 12 Memory Cycle Variables
Description Symbol Values
ALE Ext en s ion WATCL * <ALECTL>
Memory Cycle Time Waitstates WC2TCL * (15 - <MCTC>)
Memory Tristate Time WF2TCL * (1 - <MTTC>)
&
Data Sheet 54 1999-08
Testing Waveforms
Figure 13 Input Output Waveforms
Figure 14 Float Waveforms
AC inputs during testing are driven at 2.4 V for a logic ‘1’ and 0.45 V for a logic ‘0’.
Timing measurements are made at 9IH min for a logic ’1’ and 9IL max for a logic ’0’.
2.4 V
0.45 V
Test Points
1.8 V 1.8 V
0.8 V 0.8 V
For timing purposes a port pin is no longer floating when a 100 mV change from load voltage occurs,
but begins to float when a 100 mV change from the loaded 9OH/9OL level occur s (,OH/,OL = 20 mA).
&
Data Sheet 55 1999-08
AC Characteristics
Multiplexed Bus
(Operating Conditions apply)
ALE cycle time = 6 TCL + 2 WA + WC + WF (120 ns at 25 MHz CPU clock wit hout waitstates)
Parameter Symbol Max. CPU Clock
= 25 MHz Variable CPU Clock
1 / 2TCL = 1 to 25 MHz Unit
min. max. min. max.
ALE hig h ti me W5CC 10 + WA– TCL - 10
+WA
–ns
Address setu p to ALE W6CC 4 +WA– TCL - 16
+WA
–ns
Address hold after ALE W7CC 10 +WA– TCL - 10
+WA
–ns
ALE falling edge to RD,
WR (with RW-delay) W8CC 10 +WA– TCL - 10
+WA
–ns
ALE falling edge to RD,
WR (no RW-de lay) W9CC -10 +WA– -10 +WA–ns
Address float after RD,
WR (with RW-delay) W10 CC–6–6ns
Address float after RD,
WR (no RW-de lay) W11 CC – 26 – TCL + 6 ns
RD, WR low time
(with RW-delay) W12 CC 30 +WC– 2TCL - 10
+WC
–ns
RD, WR low time
(no RW-delay) W13 CC 50 +WC– 3TCL-
10+WC
–ns
RD to valid data in
(with RW-delay) W14 SR – 20 +WC– 2TCL - 20
+WC
ns
RD to valid data in
(no RW-delay) W15 SR – 40 +WC– 3TCL - 20
+WC
ns
ALE low to valid data in W16 SR – 40 + WA
+ WC
– 3TCL - 20
+WA +WC
ns
Address to valid data in W17 SR – 50 + 2WA
+ WC
– 4TCL - 30
+2WA +WC
ns
Data hold after RD
rising edge W18 SR0–0–ns
Data float after RD W19 SR – 26 +WF– 2TCL - 14
+WF
ns
&
Data Sheet 56 1999-08
Data valid to WR W22 CC 20 +WC– 2TCL - 20
+WC
–ns
Data hold after WR W23 CC 26 +WF– 2TCL - 14
+WF
–ns
ALE rising edge after RD,
WR W25 CC 26 +WF– 2TCL - 14
+WF
–ns
Address hol d after RD,
WR W27 CC 26 +WF– 2TCL - 14
+WF
–ns
ALE falling edge to CS 1) W38 CC -4 -WA10 - WA-4 -WA10 -WAns
CS low to Valid Data In 1) W39 SR – 40
+WC
+2WA
– 3TCL - 20
+WC + 2WA
ns
CS hold after RD, WR 1) W40 CC 46 +WF– 3TCL - 14
+WF
–ns
ALE fall. edge to RdCS,
WrCS (with RW delay) W42 CC 16 +WA– TCL - 4
+WA
–ns
ALE fall. edge to RdCS,
WrCS (no RW delay) W43 CC -4 +WA–-4
+WA
–ns
Address float after RdCS,
WrCS (with RW delay) W44 CC–0–0ns
Address float after RdCS,
WrCS (no RW delay) W45 CC – 20 – TCL ns
RdCS to Valid Data In
(with RW delay) W46 SR – 16 +WC– 2TCL - 24
+WC
ns
RdCS to Valid Data In
(no RW delay) W47 SR – 36 +WC– 3TCL - 24
+WC
ns
RdCS, WrCS Low Time
(with RW delay) W48 CC 30 +WC– 2TCL - 10
+WC
–ns
RdCS, WrCS Low Time
(no RW delay) W49 CC 50 +WC– 3TCL - 10
+WC
–ns
Multiplexed Bus (continued)
(Operating Con ditions apply)
ALE cycle time = 6 TCL + 2 WA + WC + WF (120 ns at 25 MHz CPU cloc k without waitstates)
Parameter Symbol Max. CPU Clock
= 25 MHz Variable CPU Clock
1 / 2TCL = 1 to 25 MHz Unit
min. max. min. max.
&
Data Sheet 57 1999-08
Data valid to WrCS W50 CC 26 +WC– 2TCL - 14
+WC
–ns
Data hold after RdCS W51 SR0–0–ns
Data float after RdCS W52 SR – 20 +WF– 2TCL - 20
+WF
ns
Address hold after
RdCS, WrCS W54 CC 20 +WF– 2TCL - 20
+WF
–ns
Data hold after WrCS W56 CC 20 +WF– 2TCL - 20
+WF
–ns
1) These parameters refer to the latched chip select signals (CSxL). The early chip select signals (CSxE) are
specified together with the address and signal BHE (see figures below).
Multiplexed Bus (continued)
(Operating Conditions apply)
ALE cycle time = 6 TCL + 2 WA + WC + WF (120 ns at 25 MHz CPU clock wit hout waitstates)
Parameter Symbol Max. CPU Clock
= 25 MHz Variable CPU Clock
1 / 2TCL = 1 to 25 MHz Unit
min. max. min. max.
&
Data Sheet 58 1999-08
Figure 15 External Memory Cycle:
Multiplexed Bus, With Read/Write Delay, Normal ALE
A21-A16
(A15-A8)
BHE, CSxE
Data In
Data OutAddress
Address
W38
W44
W10
Address
ALE
CSxL
BUS
5HDG&\FOH
RD
RdCSx
BUS
:ULWH&\FOH
WR,
WRL,
WRH
WrCSx
W5W16
W17
W6W7
W39 W40
W25
W27
W18
W19
W14
W46
W12
W48
W10 W22
W23
W44 W12
W48
W8
W42
W42
W8
W50
W51
W54
W52
W56
&
Data Sheet 59 1999-08
Figure 16 External Memory Cycle:
Multiplexed Bus, With Read/Write Delay, Extended ALE
Data OutAddress
Dat a InAddress
W38
W44
W10
Address
ALE
CSxL
A21-A16
(A15-A8)
BHE, CSxE
BUS
5HDG&\FOH
RD
RdCSx
BUS
:ULWH&\FOH
WR,
WRL,
WRH
WrCSx
W5W16
W17
W6W7
W39 W40
W25
W27
W18
W19
W14
W46
W12
W48
W10 W22
W23
W44 W12
W48
W8
W42
W42
W8
W50
W51
W54
W52
W56
&
Data Sheet 60 1999-08
Figure 17 External Memory Cycle:
Multiplexed Bus, No Read/Write Delay, Normal ALE
Data OutAddress
Address Data In
W38
Address
ALE
CSxL
A21-A16
(A15-A8)
BHE, CSxE
BUS
5HDG&\FOH
RD
RdCSx
BUS
:ULWH&\FOH
WR,
WRL,
WRH
WrCSx
W5W16
W17
W6W7
W39 W40
W25
W27
W18
W19
W15
W47
W13
W49
W22
W23
W13
W49
W9
W43
W43
W9W11
W45
W11
W45 W50
W51
W54
W52
W56
&
Data Sheet 61 1999-08
Figure 18 External Memory Cycle:
Multiplexed Bus, No Read/Write Delay, Extended ALE
Data OutAddress
Data InAddress
W38
Address
ALE
CSxL
A21-A16
(A15-A8)
BHE, CSxE
BUS
5HDG&\FOH
RD
RdCSx
BUS
:ULWH&\FOH
WR,
WRL,
WRH
WrCSx
W5W16
W17
W6W7
W39 W40
W25
W27
W18
W19
W15
W47
W13
W49
W22
W23
W13
W49
W9
W43
W43
W9W11
W45
W11
W45 W50
W51
W54
W52
W56
&
Data Sheet 62 1999-08
AC Characteristics
Demultiplexed Bus
(Operating Con ditions apply)
ALE cycle time = 4 TCL + 2WA + WC + WF (80 ns at 25 MHz CPU clock without waitstates)
Parameter Symbol Max. CPU Clock
= 25 MHz Variable CPU Clock
1 / 2TCL = 1 to 25 MHz Unit
min. max. min. max.
ALE hig h ti me W5CC 10 +WA– TCL - 10
+WA
–ns
Address se tup to ALE W6CC 4 +WA– TCL - 16
+WA
–ns
ALE falling edge to RD,
WR (with RW-delay) W8CC 10 +WA– TCL - 10
+WA
–ns
ALE falling edge to RD,
WR (no RW-delay) W9CC -10 +WA–-10
+WA
–ns
RD, WR low time
(with RW-dela y) W12 CC 30 +WC– 2TCL - 10
+WC
–ns
RD, WR low time
(no RW-delay) W13 CC 50 +WC– 3TCL - 10
+WC
–ns
RD to valid data in
(with RW-dela y) W14 SR – 20 +WC– 2TCL - 20
+WC
ns
RD to valid data in
(no RW-delay) W15 SR – 4 0 +WC– 3TCL - 20
+WC
ns
ALE low to valid data in W16 SR – 40 +
WA +WC
– 3TCL - 20
+WA +WC
ns
Address to valid data in W17 SR – 50 +
2WA +WC
– 4TCL - 30
+2WA +WC
ns
Data hold afte r RD
rising edge W18 SR0–0–ns
Data float after RD rising
edge (with RW-de lay 1))W20 SR – 26 +
2WA +WF
1)
– 2TCL - 14
+22WA
+WF 1)
ns
Data float after RD rising
edge (no RW- dela y 1))W21 SR – 1 0 +
2WA +WF 1) – TCL - 10
+22WA
+WF 1)
ns
Data valid to WR W22 CC 20 +WC– 2TCL - 20
+WC
–ns
&
Data Sheet 63 1999-08
Data hold after WR W24 CC 10 +WF– TCL - 10
+WF
–ns
ALE rising edge after RD,
WR W26 CC -10 +WF– -10 +WF–ns
Address hold after WR 2) W28 CC 0 +WF–0 +
WF–ns
ALE falling edge to CS 3) W38 CC -4 -WA10 -WA-4 -WA10 -WAns
CS low to Valid Data In 3) W39 SR – 40 +
WC+2WA
– 3TCL - 20
+WC + 2WA
ns
CS hold after RD, WR 3) W41 CC 6 +WF– TCL - 14
+WF
–ns
ALE falling edge to
RdCS, WrCS (with RW-
delay)
W42 CC 16 +WA– TCL - 4
+WA
–ns
ALE falling edge to
RdCS, WrCS (no RW-
delay)
W43 CC -4 +WA–-4
+WA
–ns
RdCS to Valid Data In
(with RW-delay) W46 SR – 16 +WC– 2TCL - 24
+WC
ns
RdCS to Valid Data In
(no RW-de lay) W47 SR – 36 +WC– 3TCL - 24
+WC
ns
RdCS, WrCS Low Time
(with RW-delay) W48 CC 30 +WC– 2TCL - 10
+WC
–ns
RdCS, WrCS Low Time
(no RW-de lay) W49 CC 50 +WC– 3TCL - 10
+WC
–ns
Data valid to WrCS W50 CC 26 +WC– 2TCL - 14
+WC
–ns
Data hold after RdCS W51 SR0–0–ns
Data float after RdCS
(with RW-delay) 1) W53 SR – 20 +WF– 2TCL - 20
+2WA +WF 1) ns
Data float after RdCS
(no RW-delay) 1) W68 SR – 0 +WF– TCL - 20
+2WA +WF 1) ns
Demultiplexed Bus (continued)
(Operating Conditions apply)
ALE cycle time = 4 TCL + 2WA + WC + WF (80 ns at 25 MHz CPU clock without waitstates)
Parameter Symbol Max. CPU Clock
= 25 MHz Variable CPU Clock
1 / 2TCL = 1 to 25 MHz Unit
min. max. min. max.
&
Data Sheet 64 1999-08
Address hol d after
RdCS, WrCS W55 CC -6 +WF–-6 +
WF–ns
Data hold afte r WrCS W57 CC 6 +WF– TCL - 14 +
WF
–ns
1) RW-delay and WA refer to the next following bus cycle (including an access to an on-chip X-Peripheral).
2) Read data are latched with the same clock edge that triggers the address change and the rising RD edge.
Therefore address changes before the end of RD have no impact on read cycles.
3) These parameters refer to the latched chip select signals (CSxL). The early chip select signals (CSxE) are
specified together with the address and signal BHE (see figures below).
Demultiplexed Bus (continued)
(Operating Con ditions apply)
ALE cycle time = 4 TCL + 2WA + WC + WF (80 ns at 25 MHz CPU clock without waitstates)
Parameter Symbol Max. CPU Clock
= 25 MHz Variable CPU Clock
1 / 2TCL = 1 to 25 MHz Unit
min. max. min. max.
&
Data Sheet 65 1999-08
Figure 19 External Memory Cycle:
Demultiplexed Bus, With Read/Write Delay, Normal ALE
Data Out
Data In
W38
Address
ALE
CSxL
A21-A16
A15-A0
BHE, CSxE
BUS
(D15-D8)
D7-D0
5HDG&\FOH
RD
RdCSx
:ULWH&\FOH
WrCSx
W5W16
W17
W6
W39 W41
W26
W28
W18
W20
W14
W46
W12
W48
W22
W24
W12
W48
W8
W42
W42
W8
W50
W51
W55
W53
W57
BUS
(D15-D8)
D7-D0
WR,
WRL,
WRH
&
Data Sheet 66 1999-08
Figure 20 External Memory Cycle:
Demultiplexed Bus, With Read/Write Delay, Extended ALE
Data Out
Da ta In
W38
Address
ALE
CSxL
A21-A16
A15-A0
BHE,
CSxE
5HDG&\FOH
RD
RdCSx
:ULWH&\FOH
WrCSx
W5W16
W17
W6
W39 W41
W26
W28
W18
W20
W14
W46
W12
W48
W22
W24
W12
W48
W8
W42
W42
W8
W50
W51
W55
W53
W57
BUS
(D15-D8)
D7-D0
BUS
(D15-D8)
D7-D0
WR,
WRL,
WRH
&
Data Sheet 67 1999-08
Figure 21 External Memory Cycle:
Demultiplexed Bus, No Read/Write Delay, Normal ALE
Data Out
Data In
W38
Address
ALE
CSxL
A21-A16
A15-A0
BHE, CSxE
5HDG&\FOH
RD
RdCSx
:ULWH&\FOH
WrCSx
W5W16
W17
W6
W39 W41
W26
W28
W18
W21
W15
W47
W13
W49
W22
W24
W13
W49
W9
W43
W43
W9
W50
W51
W55
W68
W57
BUS
(D15-D8)
D7-D0
BUS
(D15-D8)
D7-D0
WR,
WRL,WRH
&
Data Sheet 68 1999-08
Figure 22 External Memory Cycle:
Demultiplexed Bus, No Read/Write Delay, Extended ALE
Data Out
Data In
W38
Address
ALE
CSxL
A21-A16
A15-A0
BHE,CSxE
5HDG&\FOH
RD
RdCSx
:ULWH&\FOH
WR,
WRL, WRH
WrCSx
W5W16
W17
W6
W39 W41
W26
W28
W18
W21
W15
W47
W13
W49
W22
W24
W13
W49
W9
W43
W43
W9
W50
W51
W55
W68
W57
BUS
(D15-D8)
D7-D0
BUS
(D15-D8)
D7-D0
&
Data Sheet 69 1999-08
AC Characteristics
Figure 23 CLKOUT Timi ng
Notes
1) Cycle as programmed, including MCTC waitstates (Example shows 0 MCTC WS).
2) The leading edge of the respective command depends on RW-delay.
3) Multiplexed bus modes have a MUX waitstate added after a bus cycle, and an additional MTTC waitstate may
be inserted here.
For a multiplexed bus with MTTC waitstate this delay is 2 CLKOUT cycles, for a demultiplexed bus without
MTTC waitstate this delay is zero.
4) The next external bus cycle may start here.
CLKOUT
(Operating Conditions apply)
Parameter Symbol Max. CPU Clock
= 25 MHz Variable CPU Clock
1 / 2TCL = 1 to 25 MHz Unit
min. max. min. max.
CLKOUT cycle time W29 CC 40 40 2TCL 2TCL ns
CLKOUT hi gh time W30 CC 14 – TCL – 6 – ns
CLKOUT low time W31 CC 10 – TCL – 10 – ns
CLKOUT rise time W32 CC–4–4ns
CLKOUT fall time W33 CC–4–4ns
CLKOUT rising edge to
ALE falling edge W34 CC 0 +WA10 +WA0 +WA10 +WAns
CLKOUT
ALE
t
30
t
34
MUX/Tristate 3)
t
32
t
33
t
29
Running cycle 1)
t
31
Command
RD, WR 2)
4)
&
Data Sheet 70 1999-08
Package Outl ines
Figure 24
Sorts of Packing
Package ou tlines for tubes, trays, etc. are conta ined in our
Data Book “Package Information”
SMD = Surface Mounted Device Dimensions in mm
Plastic Package, P-MQFP-80-1 (SMD)
(Plastic Metric Quad Flat Package)
&
Data Sheet 71 1999-08
&
Data Sheet 72 1999-08
Published by Infineon Technologies AG
