CH7317A Chrontel CH7317A SDVO / RGB DAC Features General Description * The CH7317A is a Display Controller device which accepts a digital graphics high speed AC coupled serial differential RGB input signal, and encodes and transmits data through analog RGB port. The device accepts one channel of RGB data over three pairs of serial data ports. * * * * * * * * * High-speed SDVO (1G~2Gbps) AC-coupled serial differential RGB inputs Support for VGA RGB bypass Output Analog RGB. Three 10-bit video DAC outputs DAC output CRT RGB connector Fully programmable through serial port Programmable power management Configuration through Intel(R) SDVO OpCode Complete Windows driver support Offered in 64-pin LQFP and 64-pin QFN package CH7317A output VGA style analog RGB for use as a CRT DAC. Supported analog video VGA connector. Intel(R) Proprietary. XI/FIN,XO PLL 2 AS SPC SPD Serial Port Control RESET* BCO/VSYNC C/HSYNC SDVO_Clk(+,-) SC_DDC SD_DDC SC_PROM SD_PROM Control 2 Clock Driver DAC 2 DAC 1 10bit-8bit decoder SDVO_R(+,-) SDVO_G(+,-) SDVO_B(+,-) DACA[2:0] DAC 0 Three 10-bit DAC's 6 3 ISET Data Latch, Serial to Parallel Figure 1: Functional Block Diagram 201-0000-087 Rev. 1.2, 12/2/2008 1 CHRONTEL CH7317A Table of Contents 1.0 1.1 1.2 2.0 2.1 2.2 2.3 2.4 Package Diagram ___________________________________________________________________4 Pin Description _____________________________________________________________________6 Functional Description________________________________________________________ 8 Input Interface______________________________________________________________________8 CRT Bypass Operation _______________________________________________________________8 Command Interface _________________________________________________________________9 Boundary scan Test__________________________________________________________________9 3.0 Register Control ____________________________________________________________ 12 4.0 Electrical Specifications ______________________________________________________ 13 4.1 4.2 4.3 4.4 4.5 2 Pin-Out ____________________________________________________________________ 4 Absolute Maximum Ratings __________________________________________________________13 Recommended Operating Conditions ___________________________________________________13 Electrical Characteristics ____________________________________________________________14 DC Specifications __________________________________________________________________14 AC Specifications __________________________________________________________________16 5.0 Package Dimensions _________________________________________________________ 18 6.0 Revision History ____________________________________________________________ 20 201-0000-087 Rev. 1.2, 12/2/2008 CHRONTEL CH7317A Figures and Tables List of Figures Figure 1: Functional Block Diagram .............................................................................................................................1 Figure 2: 64-Pin LQFP Package ....................................................................................................................................4 Figure 3: 64-Pin QFN Package......................................................................................................................................5 Figure 4: Control Bus Switch ........................................................................................................................................9 Figure 5: NAND Tree Connection...............................................................................................................................10 Figure 6: 64 Pin LQFP Package ..................................................................................................................................18 Figure 7: 64 Pin QFN Package (8 x 8 x 0.8mm) .........................................................................................................19 List of Tables Table 1: Pin Description ................................................................................................................................................6 Table 2: CH7317A supported Pixel Rates, Clock Rates, Data Transfer Rates and Fill Patterns...................................8 Table 3: Video DAC Configurations for CH7317A ......................................................................................................9 Table 4: Signal Order in the NAND Tree Testing .......................................................................................................10 Table 5: Signals not be tested in NAND Test besides power pins...............................................................................11 Table 6: Revisions .......................................................................................................................................................20 201-0000-087 Rev. 1.2, 12/2/2008 3 CHRONTEL CH7317A 1.0 Pin-Out AGND RPLL NC AVDD SDVO_R+ SDVO_R- AGND SDVO_G+ SDVO_G- AVDD SDVO_B+ SDVO_B- AGND 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 SDVO_CLK+ The 64-Pin LQFP Package Diagram AVDD 1.1.1 Package Diagram SDVO_CLK- 1.1 NC SD_DDC SC_DDC SD_PROM SC_PROM DVDD RESET* AS DGND DGND SPD SPC DVDD BSCAN NC 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 Chrontel CH7317 NC NC NC DGND NC NC DVDD DVDD XO XI/FIN DGND DGND BCO/VSYNC DVDD C/HSYNC V3V ISET GDAC0 NC NC DACA[0] VDAC0 NC NC GDAC1 DACA[1] NC NC DACA[2] VDAC1 NC GDAC2 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 VDAC2 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 Figure 2: 64-Pin LQFP Package 4 201-0000-087 Rev. 1.2, 12/2/2008 CHRONTEL AVDD SDVO_CLK- SDVO_CLK+ AGND SDVO_B- SDVO_B+ AVDD SDVO_G- SDVO_G+ AGND SDVO_R- SDVO_R+ AVDD NC RPLL AGND 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 The 64-Pin QFN Package Diagram 64 1.1.2 CH7317A 1 48 NC SD_DDC 2 47 NC SC_DDC 3 46 NC SD_PROM 4 45 DGND SC_PROM 5 44 NC DVDD 6 43 NC RESET* 7 42 DVDD AS 8 41 DVDD DGND 9 40 XO DGND 10 39 XI/FIN SPD 11 38 DGND SPC 12 37 DGND DVDD 13 36 BCO/VSYNC BSCAN 14 35 DVDD NC 15 34 C/HSYNC VDAC2 16 33 V3V 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 NC VDAC1 DACA[2] NC NC GDAC1 DACA[1] NC NC VDAC0 DACA[0] NC NC GDAC0 ISET Chrontel CH7317 GDAC2 NC Figure 3: 64-Pin QFN Package 201-0000-087 Rev. 1.2, 12/2/2008 5 CHRONTEL 1.2 CH7317A Pin Description Table 1: Pin Description Pin # 2 Type In/Out Symbol SD_DDC 3 In/Out SC_DDC 4 In/Out SD_PROM 5 Out SC_PROM 7 In RESET* Description Routed Serial Port Data Output to DDC This pin functions as the bi-directional data pin of the serial port to DDC receiver. This pin will require a 10k pull-up resistor to the desired high state voltage. Leave open if unused. Routed Serial Port Clock Output to DDC This pin functions as the clock bus of the serial port to DDC receiver. This pin will require a 10k pull-up resistor to the desired high state voltage. Leave open if unused. Routed Data Output to PROM This pin functions as the bi-directional data pin of the serial port for PROM on ADD2 card. This pin will require a 10k pull-up resistor to the desired high state voltage. Leave open if unused. Routed Clock Output to PROM This pin functions as the clock bus of the serial port to PROM on ADD2 card. This pin will require a 10k pull-up resistor to the desired high state voltage. Leave open if unused. Reset* Input (Internal pull-up) When this pin is low, the device is held in the power-on reset condition. When this pin is high, reset is controlled through the serial port register. This pin is 3.3V compliant. 8 In AS Address Select (Internal pull-up) This pin determines the serial port address of the device (0,1,1,1,0,0,AS*,0). When AS is low the address is 72h, when high the address is 70h. 11 In/Out SPD Serial Port Data Input / Output This pin functions as the bi-directional data pin of the serial port and operates with inputs from 0 to 2.5V. Outputs are driven from 0 to 2.5V. This pin requires an external 4k - 9 k pull up resistor to 2.5V. 12 In/Out SPC Serial Port Clock This pin functions as the clock of the serial port and operates from 0 to 2.5V. This pin requires an external 4k - 9k pull up resistor to 2.5V. 14 In BSCAN BSCAN (internal pull low) This pin should be left open or pulled low with a 10k resistor in the application. This pin enables the boundary scan for in-circuit testing. Voltage level is 0 to DVDD. This pin should be pulled low during normal operation. 20,24,28 Out DACA[2:0] DAC Output A Video Digital-to-Analog outputs. Refer to section 2.2.1 for information regarding support for RGB Bypass outputs. Each output is capable of driving a 75-ohm doubly terminated load. No Connect ( Reserved ) 3 1,15,18,21, 22,25,26, 29,30,43, 44,46,47, 48,51 6 NC Intel Proprietary. 201-0000-087 Rev. 1.2, 12/2/2008 CHRONTEL CH7317A Table 1: Pin Description (contd.) Pin # 32 Type Ref. Symbol ISET Description Current Set Resistor This pin sets the DAC current. A 1.2Kohm (+/- 1%) resistor should be connected between this pin and DAC ground (pin 31) using short and wide traces. 34 Out CHSYNC Composite / Horizontal Sync Output A buffered version of VGA composite sync as well as horizontal sync can be acquired from this pin. 36 Out VSYNC VSYNC A buffered version of VGA vertical sync can be acquired from this pin. 39 In XI/FIN 40 Out XO 50 In RPLL 53,54,56, 57,59,60 In 62,63 In SDVO_R+/-, These pins accept 3 AC-coupled differential pair of RGB inputs from a digital video SDVO_G+/-, port of a graphics controller. SDVO_B+/SDVO_CLK+/- Differential Clock Input associated with SDVO Data channel Crystal Input / External Reference Input A parallel resonant 27MHz crystal (100 ppm) should be attached between this pin and XO. However, an external CMOS clock can drive the XI/FIN input. Crystal Output A parallel resonant 27MHz crystal (100 ppm) should be attached between this pin and XI/FIN. However, if an external CMOS clock is attached to the XI/FIN input, XO should be left open. PLL Resistor Input External resistor 10Kohm should be connected between this pin and pin 49. SDVO Data Channel Inputs (SDVO_R+/-, SDVO_G+/-, SDVO_B+/-) The range of this clock pair is 100~200MHz. For specified pixel rates in specified modes this clock pair will run at an integer multiple of the pixel rate. Refer to section 2.1.3 for details. 3 6,13,35,41, 42 9,10,37,38, 45 16 17 19 23 27 31 52,58,64 49,55,61 33 Power DVDD Digital Supply Voltage (2.5V) Power DGND Digital Ground Power Power Power Power Power Power Power Power Power VDAC2 GDAC2 VDAC1 GDAC1 VDAC0 GDAC0 AVDD AGND V3V DAC Supply Voltage DAC Ground DAC Supply Voltage DAC Ground DAC Supply Voltage DAC Ground Analog Supply Voltage Analog Ground 3.3V Supply Voltage 201-0000-087 Rev. 1.2, 12/2/2008 (3.3V) (3.3V) (3.3V) (2.5V) (3.3V) 7 CHRONTEL CH7317A 2.0 Functional Description 2.1 Input Interface 2.1.1 Overview One pair of differential clock signal and three differential pairs of data signals (R/G/B) form one channel data. The input data are 10-bit serialized data. Input data run at 1Gbits/s~2Gbits/s, being a 10x multiple of the clock rate (SDVO_CLK+/-). The CH7317A de-serializes the input into 10-bit parallel data with synchronization and alignment. Then the 10-bit characters are mapped into 8-bit color data or control data (Hsync, Vsync, DE). 2.1.2 Interface Voltage Levels All differential SDVO pairs are AC coupled differential signals. Therefore, there is not a specified DC signal level for the signals to operate at. The differential p-p input voltage has a min of 175mV, and a max of 1.2V. The differential p-p output voltage has a min of 0.8V, with a max of 1.2V. 2.1.3 Input Clock and Data Timing A data character is transmitted least significant bit first. The beginning of a character is noted by the falling edge of the SDVO_CLK+ edge. The skew among input lanes is required to be no larger than 2ns. The clock rate runs at 100MHz~200MHz. The pixel rate can be 25MP/s~165MP/s. The pixel rate and the clock rate do not always equal. The clock rate can be a multiple of the pixel rate (1x, 2x or 4x depending on the pixel rate) so that the clock rate will be stay in the 100MHz~200MHz range. In the condition that the clock rate is running at a multiple of the pixel rate, there isn't enough pixel data to fill the data channels. Dummy fill characters (`0001111010') are used to stuff the data stream. The CH7317A supports the following clock rate multipliers and fill patterns shown in Table 2. 3 Table 2: CH7317A supported Pixel Rates, Clock Rates, Data Transfer Rates and Fill Patterns Pixel Rate 25~50 MP/s 50~100 MP/s 100~200 MP/s Clock Rate - Multiplier 100~200 MHz - 4xPixel Rate 100~200 MHz - 2xPixel Rate 100~200 MHz - 1xPixel Rate Stuffing Format Data, Fill, Fill, Fill Data, Fill Data Data Transfer Rate - Multiplier 1.00~2.00 Gbits/s - 10xClock Rate 1.00~2.00 Gbits/s - 10xClock Rate 1.00~2.00 Gbits/s - 10xClock Rate 2.1.4 Synchronization Synchronization and channel-to-channel de-skewing is facilitated by the transmission of special characters during the blank period. The CH7317A synchronizes during the initialization period and subsequently uses the blank periods to re-synch to the data stream. 2.2 CRT Bypass Operation The CH7317A operates in CRT RGB Bypass mode. In CRT Bypass mode, data from the graphics device, after proper decoding, are bypassed directly to the video DACs to implement a second CRT DAC function. Sync signals, after proper decoding, are buffered internally, and can be output to drive the CRT. The CH7317A can support a pixel rate of 200MHz. This operating mode uses 8-bits of the DAC's 10-bit range, and provides a nominal signal swing of 0.661V (or 0.7V depending on DAC Gain setting in control registers) when driving a 75 doubly terminated load. No scaling, scan conversion or flicker filtering is applied in CRT Bypass modes. 8 201-0000-087 Rev. 1.2, 12/2/2008 CHRONTEL CH7317A 2.2.1 Video DAC Outputs Table 3 below lists the DAC output configurations of the CH7317A. 3 Table 3: Video DAC Configurations for CH7317A Output Type CRT RGB 2.3 DACA[0] B DACA[1] G DACA[2] R Command Interface Communication is through two-wire path, control clock (SPC) and data (SPD). The CH7317A accepts incoming control clock and data from graphics controller, and is capable of redirecting that stream to an ADD2 card PROM, DDC, or CH7317A internal registers. The control bus is able to run up to 1MHz when communicating with internal registers, up to 400kHz for the PROM and up to 100kHz for the DDC. Internal Device Registers observer control the switch on/off SPC,SPD DDC default position PROM Figure 4: Control Bus Switch Upon reset, the default state of the directional switch is to redirect the control bus to the ADD2 PROM. At this stage, the CH7317A observes the control bus traffic. If the observing logic sees a control bus transaction destined for the internal registers (device address 70h or 72h), it disables the PROM output pairs, and switches to internal registers. In the condition that traffic is to the internal registers, an op-code command is used to set the redirection circuitry to the appropriate destination (ADD2 PROM or DDC). Redirecting the traffic to internal registers while at the stage of traffic to DDC occurs on observing a STOP after a START on the control bus. 2.4 Boundary scan Test CH7317A provides a called "NAND TREE Testing" to verify IO cell function at the PC board level. This test will check the interconnection between chip I/O and the printed circuit board for faults (soldering, bend leads, open printed circuit board traces, etc.). NAND tree test is a simple serial logic which turns all IO cell signals to input mode, connects all inputs with NAND gates as shown in the figure below and switches each signal to high or low according to the sequence in Table 4. The test results then pass out at pin 51 (NC). 4 201-0000-087 Rev. 1.2, 12/2/2008 9 CHRONTEL CH7317A Figure 5: NAND Tree Connection Testing Sequence Set BSCAN =1; (internal weak pull low) Set all signals listed in Table 4 to 1. Set all signals listed in Table 4 to 0, toggle one by one with certain time period suggested 100ns. Pin 51 (NC) will change its value each time an input value changed. 4 4 Table 4: Signal Order in the NAND Tree Testing Order 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 10 Pin Name SD_DDC SC_DDC SD_PROM SC_ PROM RESETB AS SPD SPC NC DACA[2] NC NC DACA[1] NC NC DACA[0] NC NC ISET CHSYNC VSYNC XI/FIN XO NC NC NC NC NC NC LQFP Pin 2 3 4 5 7 8 11 12 18 20 21 22 24 25 26 28 29 30 32 34 36 39 40 43 44 46 47 48 51 201-0000-087 Rev. 1.2, 12/2/2008 CHRONTEL CH7317A Table 5: Signals not be tested in NAND Test besides power pins Pin Name SDVO_R+ SDVO_RSDVO_G+ SDVO_GSDVO_B+ SDVO_BSDVO_CLK+ SDVO_CLKBSCAN NC NC 201-0000-087 Rev. 1.2, LQFP Pin 53 54 56 57 59 60 62 63 14 15 1 12/2/2008 11 CHRONTEL CH7317A 3.0 Register Control The CH7317A is controlled via a serial control port. The serial bus uses only the SC clock to latch data into registers, and does not use any internally generated clocks so that the device can be written to in all power down modes. The device will retain all register values during power down modes. Registers 00h to 11h are reserved for op-code use. All registers except bytes 00h to 11h are reserved for internal factory use. For details regarding Intel(R) SDVO op-codes, please contact Intel(R). 12 201-0000-087 Rev. 1.2, 12/2/2008 CHRONTEL CH7317A 4.0 Electrical Specifications 4.1 Absolute Maximum Ratings Symbol Description Min All 2.5V power supplies relative to GND All 3.3V power supplies relative to GND -0.5 -0.5 Typ Max Units 3.0 5.0 V TSC Analog output short circuit duration TAMB Ambient operating temperature -20 85 C TSTOR Storage temperature -65 150 C TJ Junction temperature 150 C TVPS Vapor phase soldering (5 second) Vapor phase soldering (11 second) Vapor phase soldering (1 minute) 260 245 225 C Indefinite Sec Note: 1) Stresses greater than those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings only. Functional operation of the device at these or any other conditions above those indicated under the normal operating condition of this specification is not recommended. Exposure to absolute maximum rating conditions for extended periods may affect reliability. The temperature requirements of vapor phase soldering apply to all standard and lead free parts. 2) The device is fabricated using high-performance CMOS technology. It should be handled as an ESD sensitive device. Voltage on any signal pin that exceeds the power supply voltages by more than 0.5V can induce destructive latch-up. 4.2 Recommended Operating Conditions Symbol Description Min Typ Max Units AVDD Analog Power Supply Voltage 2.375 2.5 2.625 V DVDD Digital Power Supply Voltage 2.375 2.5 2.625 V VDAC DAC Power Supply 3.100 3.3 3.500 V VDD33 Generic for all 3.3V supplies 3.100 3.3 3.500 V VDD25 Generic for all 2.5V supplies 2.375 2.5 2.625 V V3V 3.3V Power Supply 3.100 3.3 3.500 V RSET Resistor on ISET pin (32) 1188 1200 1212 70 C Ambient operating temperature 201-0000-087 Rev. 1.2, 12/2/2008 -20 13 CHRONTEL 4.3 CH7317A Electrical Characteristics (Operating Conditions: TA = -20C - 70C, VDD25 =2.5V 5%, VDD33 = 3. 3V 5%,) Symbol Description Min Video D/A Resolution 10 Full scale output current Typ Max Units 10 10 bits 35. 3 Video level error IVDD25 (162 MHz mA 10 % Total VDD25 supply current (2.5V supplies) with 1600x1200, 32bit, 60H 131 mA Total VDD33 supply current (3.3V supplies) with 1600x1200, 32bit, 60H 105 mA 0 mA 0.1 mA pixel clock) IVDD33 (162 MHz pixel clock) IVDDV Total V3V current (3.3V supply) IPD Total Power Down Current 4.4 DC Specifications Symbol Description Test Condition Min VRX-DIFFp-p = 2 * VRX-D+ - VRX-D- 0.175 Typ Max Unit 1.200 V VRX-DIFFp-p SDVO Receiver Differential Input Peak to Peak Voltage ZRX-DIFF-DC SDVO Receiver DC Differential Input Impedance 80 100 120 ZRX-COM-DC SDVO Receiver DC Common Mode Input Impedance 40 50 60 5 50 60 20k 200k 0.8 1.2 V 0.4 V ZRX-COM-INITIALDC ZRX-COM-HighIMP-DC VPP_POCLK Impedance allowed when receiver terminations are first turned on SDVO Receiver Powered Down DC Common Mode Input Impedance Impedance allowed when receiver terminations are not powered POCLK Differential Pk - Pk Output Voltage VSDOL 1 SPD (serial port data) Output Low Voltage VSPIH 2 Serial Port (SPC, SPD) Input High Voltage 2.0 +5V +0.5 V VSPIL 2 Serial Port (SPC, SPD) Input Low Voltage GND-0.5 0.4 V VHYS VDDCIH VDDCIL VPROMIH 14 SDVO Receiver Initial DC Common Mode Input Impedance Hysteresis of Serial Port Inputs IOL = 2.0 mA 0.25 DDC Serial Port V +5V Input High Voltage 4.0 +0.5 DDC Serial Port Input Low Voltage GND-0.5 0.4 PROM Serial Port Input High Voltage 4.0 +5V +0.5 V V 201-0000-087 Rev. 1.2, V 12/2/2008 CHRONTEL CH7317A Symbol Description VPROMIL PROM Serial Port Input Low Voltage VSD_DDCOL3 VDDCOL 4 Test Condition Min Typ Max Unit V GND-0.5 SPD (serial port data) Output Low Voltage from SD_DDC (or SD_EPROM) Input is VINL at SD_DDC or SD_EPROM. SC_DDC and SD_DDC Output Low Voltage Input is VINL at SPC and SPD. 0.4 0.9*VINL + 0.25 V 0.933*VINL + 0.35 V 0.933*VINL + 0.35 V 2.7 VDD33 + 0.5 V GND-0.5 0.5 V 2.0 VDD25 + 0.5 V GND-0.5 0.5 V 4.0k pullup to 2.5V. 5.6k pullup to 5.0V. VEPROMOL5 SC_EPROM and SD_EPROM Output Low Voltage Input is VINL at SPC and SPD. 5.6k pullup to 5.0V. VMISC1IH 6 RESET* Input High Voltage VMISC1IL 6 RESET* VMISC2IH7 AS, BSCAN Input High Voltage VMISC2IL7 AS, BSCAN Input Low Voltage DVDD=2.5V IPU AS, RESET* Pull Up Current VIN = 0V 10 30 A IPD BSCAN VIN = 2.5V 10 30 A IOH = -0.4mA 2.0 Input Low Voltage Pull Down Current VSYNCOH8 CHSYNC, VSYNC V Output High Voltage VSYNCOL8 ZDL CHSYNC, VSYNC Output Low Voltage IOL = 3.2mA DL[3:1] DC 7 10 0.4 V 13 k Output Impedance Notes: 1. VSDOL is the SPD output low voltage when transmitting from internal registers, not from DDC or EEPROM. 2. VSPIH and VSPIL are the serial port (SPC and SPD) input low voltage when transmitting to internal registers. Separate requirements may exist for transmission to the DDC and EEPROM. 3. VSD_DDCOL is the output low voltage at the SPD pin when the voltage at SD_DDC or SD_EPROM is VINL. Maximum output voltage has been calculated with a worst case pull-up of 4.0k to 2.5V on SPD. 4. VDDCOL is the output low voltage at the SC_DDC and SD_DDC pins when the voltage at SPC and SPD is VINL. Maximum output voltage has been calculated with 5.6k pull-up to 5V on SC_DDC and SD_DDC. 5. VEPROMOL is the output low voltage at the SC_EPROM and SD_EPROM pins when the voltage at SPC and SPD is VINL. Maximum output voltage has been calculated with 5.6k pull-up to 5V on SC_EPROM and SD_EPROM. 6. VMISC1 - refers to RESET* input which is 3.3V compliant. 7. VMISC2 - refers to AS, BSCAN which are 2.5V compliant 8. VSYNC - refers to CHSYNC and VSYNC outputs. 201-0000-087 Rev. 1.2, 12/2/2008 15 CHRONTEL 4.5 CH7317A AC Specifications Symbol Description UIDATA fSDVO_CLK Min Typ Max Unit SDVO Receiver Unit Interval for Data Channels Typ. - 300ppm 1/[Data Transfer Rate] Typ. + 300ppm ps SDVO CLK Input Frequency 100 200 MHz SDVO Receiver Pixel frequency 25 165 MHz fSYMBOL SDVO Receiver Symbol frequency 1 2 GHz tRX-EYE SDVO Receiver Minimum Eye Width fPIXEL tRX-EYE-JITTER Test Condition 0.4 UI SDVO Receiver Max. time between jitter median and 0.3 UI 150 mV max. deviation from median VRX-CM-ACp SDVO Receiver AC Peak Common Mode Input Voltage RLRX-DIFF Differential Return Loss 50MHz - 1.25GHz 15 dB RLRX-CM Common Mode Return Loss 50MHz - 1.25GHz 6 dB SPC, SPD Rise Time Standard mode 100k 1000 ns (20% - 80%) Fast mode 400k 300 ns 1M running speed 150 ns SPC, SPD Fall Time Standard mode 100k 300 ns (20% - 80%) Fast mode 400k 300 ns 1M running speed 150 ns TSPR TSPF TPROMR SC_PROM, SD_PROM Rise Time (20% - 80%) Fast mode 400K 300 ns TPROMF SC_PROM, SD_PROM Rise Time (20% - 80%) Fast mode 400K 300 ns TDDCR SC_DDC, SD_DDC Rise Time (20% - 80%) Standard mode 100k 1000 ns TDDCF SC_DDC, SD_DDC Fall Standard mode 100k 300 ns Time (20% - 80%) TDDCR-DELAY1 SC_DDC, SD_DDC Rise Time Delay (50%) Standard mode 100k 0 ns TDDCF-DELAY1 SC_DDC, SD_DDC Fall Standard mode 100k 3 ns Time Delay (50%) tSKEW SDVO Receiver Total Lane to Lane Skew of Inputs Across all lanes tR CHSYNC and VSYNC (when configured as outputs) 15pF load 2 ns 1.50 ns DVDD = 2.5V Output Rise Time (20% - 80%) 16 201-0000-087 Rev. 1.2, 12/2/2008 CHRONTEL tF CH7317A H and V (when configured as outputs) 15pF load 1.50 ns DVDD = 2.5V Output Fall Time (20% - 80%) Notes: 1. Refers to the figure below, the delay refers to the time pass through the internal switches. 3.3V typ. 2.5V typ. R=5K To SPC/SPD pin To DDC pin 201-0000-087 Rev. 1.2, 12/2/2008 17 CHRONTEL CH7317A 5.0 Package Dimensions A B I 1 A B H D C J LEAD CO-PLANARITY .004 " E F G Figure 6: 64 Pin LQFP Package Table of Dimensions No. of Leads 64 (10 X 10 mm) MilliMIN meters MAX A B C 12 10 0.50 D 0.17 0.27 SYMBOL E F 1.35 0.05 1.45 0.15 G 1.00 H 0.45 0.75 I 0.09 0.20 J 0 7 Notes: 1. Conforms to JEDEC standard JESD-30 MS-026D. 2. Dimension B: Top Package body size may be smaller than bottom package size by as much as 0.15 mm. 3. Dimension B does not include allowable mold protrusions up to 0.25 mm per side. 18 201-0000-087 Rev. 1.2, 12/2/2008 CHRONTEL CH7317A TOP VIEW BOTTOM VIEW B A 16 1 B/2 1 17 64 64 A 16 17 Pin 1 C C/2 32 49 49 33 32 48 48 D I G E F 33 H Figure 7: 64 Pin QFN Package (8 x 8 x 0.8mm) Table of Dimensions No. of Leads 64 (8 X 8 mm) MilliMIN meters MAX A 8 B 6.1 6.3 C 6.1 6.3 D 0.4 SYMBOL E 0.15 0.25 F 0.35 0.45 G 0.7 0.8 H 0 0.05 I 0.203 Notes: 1. Conforms to JEDEC standard JESD-30 MO-220. 201-0000-087 Rev. 1.2, 12/2/2008 19 CHRONTEL CH7317A 6.0 Revision History Table 6: Revisions Rev. # Date 1.0 12/19/06 1.1 9/13/07 1.11 10/26/07 1.2 12/2/08 20 Section All 1.1, 5.0 4.4 4.2, 4.3 Description Initial official release. Add 64-QFN package. Change VDD5+ to +5V Update operating temperature. 201-0000-087 Rev. 1.2, 12/2/2008 CHRONTEL CH7317A Disclaimer This document provides technical information for the user. Chrontel reserves the right to make changes at any time without notice to improve and supply the best possible product and is not responsible and does not assume any liability for misapplication or use outside the limits specified in this document. We provide no warranty for the use of our products and assume no liability for errors contained in this document. The customer should make sure that they have the most recent data sheet version. Customers should take appropriate action to ensure their use of the products does not infringe upon any patents. Chrontel, Inc. respects valid patent rights of third parties and does not infringe upon or assist others to infringe upon such rights. Chrontel PRODUCTS ARE NOT AUTHORIZED FOR AND SHOULD NOT BE USED WITHIN LIFE SUPPORT SYSTEMS OR NUCLEAR FACILITY APPLICATIONS WITHOUT THE SPECIFIC WRITTEN CONSENT OF Chrontel. Life support systems are those intended to support or sustain life and whose failure to perform when used as directed can reasonably expect to result in personal injury or death. ORDERING INFORMATION Part Number Package Type Number of Pins Voltage Supply CH7317A-TF Lead Free LQFP 64 2.5V & 3.3V CH7317A-TF-TR Lead Free LQFP in Tape & Reel 64 2.5V & 3.3V CH7317A-BF Lead Free QFN 64 2.5V & 3.3V CH7317A-BF-TR Lead Free QFN in Tape & Reel 64 2.5V & 3.3V Chrontel 2210 O'Toole Avenue, Suite 100, San Jose, CA 95131-1326 Tel: (408) 383-9328 Fax: (408) 383-9338 www.chrontel.com E-mail: sales@chrontel.com (c)2008 Chrontel, Inc. All Rights Reserved. Printed in the U.S.A. 201-0000-087 Rev. 1.2, 12/2/2008 21