This is information on a product in full production.
March 2012 Doc ID 022564 Rev 1 1/30
1
M24C16-125 M24C08-125
M24C04-125 M24C02-125
Automotive 16-Kbit, 8-Kbit, 4-Kbit and 2-Kbit
serial I²C bus EEPROM
Datasheet − production data
Features
■Compatible with I²C bus modes:
– 400 kHz Fast mode
– 100 kHz Standard mode
■Memory array:
– 2 Kb, 4 Kb, 8 Kb, 16 Kb of EEPROM
– Page size: 16 bytes
■Write
– Byte Write within 5 ms
– Page Write within 5 ms
■Single supply voltage:
– 2.5 V to 5.5 V
■Operating temperature range: -40°C up to
+125°C
■Random and sequential Read modes
■Automatic address incrementing
■Write protect of the whole memory array
■Enhanced ESD/Latch-Up protection
■More than 1 million Write cycles
■More than 40-year data retention
■Packages
– RoHS-compliant and halogen-free
(ECOPACK2®)
SO8 (MN)
150 mils width
TSSOP8 (DW)
169 mils width
www.st.com
Contents M24C16-125 M24C08-125 M24C04-125 M24C02-125
2/30 Doc ID 022564 Rev 1
Contents
1 Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
2 Signal description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
2.1 Serial Clock (SCL) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
2.2 Serial Data (SDA) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
2.3 Chip Enable (E0, E1, E2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
2.3.1 Write Control (WC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
2.4 Supply voltage (VCC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
2.4.1 Operating supply voltage VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
2.4.2 Power-up conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
2.4.3 Device reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
2.4.4 Power-down conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
3 Device operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
3.1 Start condition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
3.2 Stop condition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
3.3 Acknowledge bit (ACK) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
3.4 Data input . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
3.5 Memory addressing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
3.6 Write operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
3.6.1 Byte Write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
3.6.2 Page Write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
3.6.3 Minimizing system delays by polling on ACK . . . . . . . . . . . . . . . . . . . . . 16
3.7 Read operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
3.7.1 Random Address Read . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
3.7.2 Current Address Read . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
3.7.3 Sequential Read . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
3.7.4 Acknowledge in Read mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
4 Initial delivery state . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
5 Maximum rating . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
6 DC and AC parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
M24C16-125 M24C08-125 M24C04-125 M24C02-125 Contents
Doc ID 022564 Rev 1 3/30
7 Package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
8 Part numbering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
9 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
List of tables M24C16-125 M24C08-125 M24C04-125 M24C02-125
4/30 Doc ID 022564 Rev 1
List of tables
Table 1. Signal names . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Table 2. Device select code . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Table 3. Operating modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Table 4. Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Table 5. Operating conditions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Table 6. AC measurement conditions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Table 7. Input parameters. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Table 8. DC characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Table 9. AC characteristics at 400 kHz (I2C Fast mode) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
Table 10. AC characteristics at 100 kHz (I2C Standard mode) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
Table 11. SO8 narrow – 8 lead plastic small outline, 150 mils body width,
package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
Table 12. TSSOP8 – 8 lead thin shrink small outline, package mechanical data. . . . . . . . . . . . . . . . 27
Table 13. Ordering information scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
Table 14. Document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
M24C16-125 M24C08-125 M24C04-125 M24C02-125 List of figures
Doc ID 022564 Rev 1 5/30
List of figures
Figure 1. Logic diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Figure 2. 8-pin package connections (top view) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Figure 3. Device select code . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Figure 4. I2C Fast mode (fC = 400 kHz): maximum Rbus value versus bus parasitic
capacitance (Cbus) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Figure 5. I²C bus protocol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Figure 6. Write mode sequences with WC = 1 (data write inhibited) . . . . . . . . . . . . . . . . . . . . . . . . . 13
Figure 7. Write mode sequences with WC = 0 (data write enabled) . . . . . . . . . . . . . . . . . . . . . . . . . 15
Figure 8. Write cycle polling flowchart using ACK . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Figure 9. Read mode sequences . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Figure 10. AC measurement I/O waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Figure 11. AC waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
Figure 12. SO8 narrow – 8 lead plastic small outline, 150 mils body width, package outline . . . . . . . 26
Figure 13. TSSOP8 – 8 lead thin shrink small outline, package outline . . . . . . . . . . . . . . . . . . . . . . . 27
Description M24C16-125 M24C08-125 M24C04-125 M24C02-125
6/30 Doc ID 022564 Rev 1
1 Description
The devices are Electrically Erasable PROgrammable Memories (EEPROMs) organized as
as 2048x8 bits, 1024x8 bits, 512x8 bits, 256x8 bits (M24C16, M24C08, M24C04 and
M24C02).
The devices are compatible with all I²C modes up to 400 kHz and can operate with a supply
voltage range from 2.5 V up to 5.5 V. The devices are guaranteed over the -40°C/+125°C
temperature range and are compliant with the Automotive standard AEC-Q100 Grade 1.
Figure 1. Logic diagram
Figure 2. 8-pin package connections (top view)
1. NC = Not connected
2. See Section 7: Package mechanical data for package dimensions, and how to identify pin-1.
Table 1. Signal names
Signal name Function Direction
E0, E1, E2 Chip Enable Input
SDA Serial Data Input/output
SCL Serial Clock Input
WC Write Control Input
VCC Supply voltage
VSS Ground
AI02033
3
E0-E2 SDA
VCC
M24Cxx
WC
SCL
VSS
-36
3$!633
3#,
7#
6##
-#XX
+B +B +B +B
.# .# .# %
.# .# % %
.# % % %
M24C16-125 M24C08-125 M24C04-125 M24C02-125 Signal description
Doc ID 022564 Rev 1 7/30
2 Signal description
2.1 Serial Clock (SCL)
This input signal is used to strobe all data in and out of the device. In applications where this
signal is used by slave devices to synchronize the bus to a slower clock, the bus master
must have an open drain output, and a pull-up resistor can be connected from Serial Clock
(SCL) to VCC. (Figure 4 indicates how the value of the pull-up resistor can be calculated). In
most applications, though, this method of synchronization is not employed, and so the pull-
up resistor is not necessary, provided that the bus master has a push-pull (rather than open
drain) output.
2.2 Serial Data (SDA)
This bidirectional signal is used to transfer data in or out of the device. It is an open drain
output that may be wire-ORed with other open drain or open collector signals on the bus. A
pull up resistor must be connected from Serial Data (SDA) to VCC. (Figure 4 indicates how
the value of the pull-up resistor can be calculated).
2.3 Chip Enable (E0, E1, E2)
These input signals are used to set the value that is to be looked for on the least significant
bits of the 7-bit device select code. These inputs must be tied to VCC or VSS, to establish the
device select code as shown in Figure 3. When not connected (left floating), Ei inputs are
read as low (0).
Figure 3. Device select code
2.3.1 Write Control (WC)
This input signal is useful for protecting the entire contents of the memory from inadvertent
write operations. Write operations are disabled to the entire memory array when Write
Control (WC) is driven High. When unconnected, the signal is internally read as VIL, and
Write operations are allowed.
When Write Control (WC) is driven High, device select and address bytes are
acknowledged, data bytes are not acknowledged.
Ai11650
VCC
M24Cxx
VSS
Ei
VCC
M24Cxx
VSS
Ei
Signal description M24C16-125 M24C08-125 M24C04-125 M24C02-125
8/30 Doc ID 022564 Rev 1
2.4 Supply voltage (VCC)
2.4.1 Operating supply voltage VCC
Prior to selecting the memory and issuing instructions to it, a valid and stable VCC voltage
within the specified [VCC(min), VCC(max)] range must be applied (see Operating conditions
in Section 6: DC and AC parameters). In order to secure a stable DC supply voltage, it is
recommended to decouple the VCC line with a suitable capacitor (usually of the order of 10
nF to 100 nF) close to the VCC/VSS package pins.
This voltage must remain stable and valid until the end of the transmission of the instruction
and, for a Write instruction, until the completion of the internal write cycle (tW).
2.4.2 Power-up conditions
The VCC voltage has to rise continuously from 0 V up to the minimum VCC operating voltage
defined in Operating conditions in Section 6: DC and AC parameters and the rise time must
not vary faster than 1 V/µs.
2.4.3 Device reset
In order to prevent inadvertent write operations during power-up, a power-on-reset (POR)
circuit is included. At power-up (continuous rise of VCC), the device does not respond to any
instruction until VCC reaches the power-on-reset threshold voltage (this threshold is lower
than the minimum VCC operating voltage defined in Operating conditions in Section 6: DC
and AC parameters). When VCC passes over the POR threshold, the device is reset and
enters the Standby Power mode. The device, however, must not be accessed until VCC
reaches a valid and stable VCC voltage within the specified [VCC(min), VCC(max)] range.
In a similar way, during power-down (continuous decrease in VCC), as soon as VCC drops
below the power-on-reset threshold voltage, the device stops responding to any instruction
sent to it.
2.4.4 Power-down conditions
During power-down (continuous decrease in VCC), the device must be in the Standby Power
mode (mode reached after decoding a Stop condition, assuming that there is no internal
write cycle in progress).
M24C16-125 M24C08-125 M24C04-125 M24C02-125 Signal description
Doc ID 022564 Rev 1 9/30
Figure 4. I2C Fast mode (fC = 400 kHz): maximum Rbus value versus bus parasitic
capacitance (Cbus)
Figure 5. I²C bus protocol
AIB
"USLINECAPACITORP&
"USLINEPULLUPRESISTOR
K
)£#BUS
MASTER -XXX
2BUS
6##
#BUS
3#,
3$!
2BUS§#BUSNS
(ERE2BUS§#BUSNS
K½
P&
4HE2X#TIMECONSTANT
MUSTBEBELOWTHENS
TIMECONSTANTLINEREPRESENTED
ONTHELEFT
BUS BUS
SCL
SDA
SCL
SDA
SDA
Start
condition
SDA
Input
SDA
Change
AI00792c
Stop
condition
123 789
MSB ACK
Start
condition
SCL 123 789
MSB ACK
Stop
condition
Signal description M24C16-125 M24C08-125 M24C04-125 M24C02-125
10/30 Doc ID 022564 Rev 1
Table 2. Device select code
Device type identifier(1)
1. The most significant bit, b7, is sent first.
Chip Enable(2),(3)
2. E0, E1 and E2 are compared against the respective external pins on the memory device.
3. A10, A9 and A8 represent most significant bits of the address.
RW
b7 b6 b5 b4 b3 b2 b1 b0
M24C02 select code 1 0 1 0 E2 E1 E0 RW
M24C04 select code 1 0 1 0 E2 E1 A8 RW
M24C08 select code 1 0 1 0 E2 A9 A8 RW
M24C16 select code 1 0 1 0 A10 A9 A8 RW
M24C16-125 M24C08-125 M24C04-125 M24C02-125 Device operation
Doc ID 022564 Rev 1 11/30
3 Device operation
The device supports the I²C protocol. This is summarized in Figure 5. Any device that sends
data on to the bus is defined to be a transmitter, and any device that reads the data to be a
receiver. The device that controls the data transfer is known as the bus master, and the
other as the slave device. A data transfer can only be initiated by the bus master, which will
also provide the serial clock for synchronization. The device is always a slave in all
communication.
3.1 Start condition
Start is identified by a falling edge of Serial Data (SDA) while Serial Clock (SCL) is stable in
the High state. A Start condition must precede any data transfer command. The device
continuously monitors (except during a Write cycle) Serial Data (SDA) and Serial Clock
(SCL) for a Start condition.
3.2 Stop condition
Stop is identified by a rising edge of Serial Data (SDA) while Serial Clock (SCL) is stable
and driven High. A Stop condition terminates communication between the device and the
bus master. A Read command that is followed by NoAck can be followed by a Stop condition
to force the device into the Standby mode. A Stop condition at the end of a Write command
triggers the internal Write cycle.
3.3 Acknowledge bit (ACK)
The acknowledge bit is used to indicate a successful byte transfer. The bus transmitter,
whether it be bus master or slave device, releases Serial Data (SDA) after sending eight bits
of data. During the 9th clock pulse period, the receiver pulls Serial Data (SDA) Low to
acknowledge the receipt of the eight data bits.
3.4 Data input
During data input, the device samples Serial Data (SDA) on the rising edge of Serial Clock
(SCL). For correct device operation, Serial Data (SDA) must be stable during the rising edge
of Serial Clock (SCL), and the Serial Data (SDA) signal must change only when Serial Clock
(SCL) is driven Low.
Device operation M24C16-125 M24C08-125 M24C04-125 M24C02-125
12/30 Doc ID 022564 Rev 1
3.5 Memory addressing
To start communication between the bus master and the slave device, the bus master must
initiate a Start condition. Following this, the bus master sends the device select code, shown
in Ta b l e 2 (on Serial Data (SDA), most significant bit first).
The device select code consists of a 4-bit Device Type Identifier, and a 3-bit Chip Enable
“Address” (E2, E1, E0). To address the memory array, the 4-bit Device Type Identifier is
1010b.
Each device is given a unique 3-bit code on the Chip Enable (E0, E1, E2) inputs. When the
device select code is received, the device only responds if the Chip Enable Address is the
same as the value on the Chip Enable (E0, E1, E2) inputs. However, those devices with
larger memory capacities (the M24C16, M24C08 and M24C04) need more address bits. E0
is not available for use on devices that need to use address line A8; E1 is not available for
devices that need to use address line A9, and E2 is not available for devices that need to
use address line A10 (see Figure 2 and Ta b l e 2 for details). Using the E0, E1 and E2 inputs,
up to eight M24C02, four M24C04, two M24C08 or one M24C16 devices can be connected
to one I²C bus.
The 8th bit is the Read/Write bit (RW). This bit is set to 1 for Read and 0 for Write operations.
If a match occurs on the device select code, the corresponding device gives an
acknowledgment on Serial Data (SDA) during the 9th bit time. If the device does not match
the device select code, it deselects itself from the bus, and goes into Standby mode.
Table 3. Operating modes
Mode RW bit WC(1)
1. X = VIH or VIL.
Bytes Initial sequence
Current Address Read 1 X 1 Start, Device Select, RW = 1
Random Address Read 0X1Start, Device Select, RW = 0, Address
1 X reStart, Device Select, RW = 1
Sequential Read 1 X ≥ 1 Similar to Current or Random Address
Read
Byte Write 0 VIL 1 Start, Device Select, RW = 0
Page Write 0 VIL ≤ 16 Start, Device Select, RW = 0
M24C16-125 M24C08-125 M24C04-125 M24C02-125 Device operation
Doc ID 022564 Rev 1 13/30
Figure 6. Write mode sequences with WC = 1 (data write inhibited)
3.6 Write operations
Following a Start condition the bus master sends a device select code with the Read/Write
bit (RW) reset to 0. The device acknowledges this, as shown in Figure 7, and waits for an
address byte. The device responds to the address byte with an acknowledge bit, and then
waits for the data byte.
When the bus master generates a Stop condition immediately after a data byte Ack bit (in
the “10th bit” time slot), either at the end of a Byte Write or a Page Write, the internal write
cycle is triggered. A Stop condition at any other time slot does not trigger the internal write
cycle.
After the Stop condition, the tw delay, and the successful completion of a Write operation,
the device internal address counter is automatically incremented, to point to the next byte
address after the last one that was modified. During the internal Write cycle,
Serial Data (SDA) is disabled internally, and the device does not respond to any request.
If the Write Control (WC) input is driven High, the Write instruction is not executed and the
corresponding data bytes are not acknowledged as shown in Figure 6.
Stop
Start
Byte Write Dev select Byte address Data in
WC
Start
Page Write Dev select Byte address Data in 1 Data in 2
WC
Data in 3
AI02803d
Page Write
(cont'd)
WC (cont'd)
Stop
Data in N
ACK ACK NO ACK
R/W
ACK ACK NO ACK NO ACK
R/W
NO ACK NO ACK
Device operation M24C16-125 M24C08-125 M24C04-125 M24C02-125
14/30 Doc ID 022564 Rev 1
3.6.1 Byte Write
After the device select code and the address byte, the bus master sends one data byte. If
the addressed location is Write-protected, by Write Control (WC) being driven High, the
device replies to the data byte with NoAck, as shown in Figure 6, and the location is not
modified. If, instead, the addressed location is not Write-protected, the device replies with
Ack. The bus master terminates the transfer by generating a Stop condition, as shown in
Figure 7.
3.6.2 Page Write
The Page Write mode allows up to 16 bytes to be written in a single Write cycle, provided
that they are all located in the same page in the memory: that is, the most significant
memory address bits are the same. If more bytes are sent than will fit up to the end of the
page, a condition known as ‘roll-over’ occurs. This should be avoided, as data starts to
become overwritten in an implementation dependent way.
The bus master sends from 1 to 16 bytes of data, each of which is acknowledged by the
device if Write Control (WC) is Low. If the addressed location is Write-protected, by Write
Control (WC) being driven High, the device replies to the data bytes with NoAck, as shown
in Figure 6, and the locations are not modified. After each byte is transferred, the internal
byte address counter (the 4 least significant address bits only) is incremented. The transfer
is terminated by the bus master generating a Stop condition.
M24C16-125 M24C08-125 M24C04-125 M24C02-125 Device operation
Doc ID 022564 Rev 1 15/30
Figure 7. Write mode sequences with WC = 0 (data write enabled)
Stop
Start
Byte Write Dev Select Byte address Data in
WC
Start
Page Write Dev Select Byte address Data in 1 Data in 2
WC
Data in 3
AI02804c
Page Write
(cont'd)
WC (cont'd)
Stop
Data in N
ACK
R/W
ACK ACK
ACK ACK ACK ACK
R/W
ACKACK
Device operation M24C16-125 M24C08-125 M24C04-125 M24C02-125
16/30 Doc ID 022564 Rev 1
Figure 8. Write cycle polling flowchart using ACK
3.6.3 Minimizing system delays by polling on ACK
During the internal Write cycle, the device disconnects itself from the bus, and writes a copy
of the data from its internal latches to the memory cells. The maximum Write time (tw) is
shown in Tab l e 9 , but the typical time is shorter. To make use of this, a polling sequence can
be used by the bus master.
The sequence, as shown in Figure 8, is:
●Initial condition: a Write cycle is in progress.
●Step 1: the bus master issues a Start condition followed by a device select code (the
first byte of the new instruction).
●Step 2: if the device is busy with the internal Write cycle, no Ack will be returned and
the bus master goes back to Step 1. If the device has terminated the internal Write
cycle, it responds with an Ack, indicating that the device is ready to receive the second
part of the instruction (the first byte of this instruction having been sent during Step 1).
Write cycle
in progress
AI01847d
Next
operation is
addressing the
memory
Start condition
Device select
with RW = 0
ACK
Returned
YES
NO
YESNO
ReStart
Stop
Data for the
Write operation
Device select
with RW = 1
Send Address
and Receive ACK
First byte of instruction
with RW = 0 already
decoded by the device
YESNO Start
condition
Continue the
Write operation
Continue the
Random Read operation
M24C16-125 M24C08-125 M24C04-125 M24C02-125 Device operation
Doc ID 022564 Rev 1 17/30
Figure 9. Read mode sequences
1. The seven most significant bits of the device select code of a Random Read (in the 1st and 3rd bytes) must
be identical.
3.7 Read operations
Read operations are performed independently of the state of the Write Control (WC) signal.
The device has an internal address counter which is incremented each time a byte is read.
3.7.1 Random Address Read
A dummy Write is first performed to load the address into this address counter (as shown in
Figure 9) but without sending a Stop condition. Then, the bus master sends another Start
condition, and repeats the device select code, with the Read/Write bit (RW) set to 1. The
device acknowledges this, and outputs the contents of the addressed byte. The bus master
must not acknowledge the byte, and terminates the transfer with a Stop condition.
Start
Dev select * Byte address
Start
Dev select Data out 1
AI01942b
Data out N
Stop
Start
Current
Address
Read
Dev select Data out
Random
Address
Read
Stop
Start
Dev select * Data out
Sequentila
Current
Read
Stop
Data out N
Start
Dev select * Byte address
Sequential
Random
Read
Start
Dev select * Data out 1
Stop
ACK
R/W
NO ACK
ACK
R/W
ACK ACK
R/W
ACK ACK ACK NO ACK
R/W
NO ACK
ACK ACK
R/W
ACK ACK
R/W
ACK NO ACK
Device operation M24C16-125 M24C08-125 M24C04-125 M24C02-125
18/30 Doc ID 022564 Rev 1
3.7.2 Current Address Read
For the Current Address Read operation, following a Start condition, the bus master only
sends a device select code with the Read/Write bit (RW) set to 1. The device acknowledges
this, and outputs the byte addressed by the internal address counter. The counter is then
incremented. The bus master terminates the transfer with a Stop condition, as shown in
Figure 9, without acknowledging the byte.
3.7.3 Sequential Read
This operation can be used after a Current Address Read or a Random Address Read. The
bus master does acknowledge the data byte output, and sends additional clock pulses so
that the device continues to output the next byte in sequence. To terminate the stream of
bytes, the bus master must not acknowledge the last byte, and must generate a Stop
condition, as shown in Figure 9.
The output data comes from consecutive addresses, with the internal address counter
automatically incremented after each byte output. After the last memory address, the
address counter ‘rolls-over’, and the device continues to output data from memory address
00h.
3.7.4 Acknowledge in Read mode
For all Read commands, the device waits, after each byte read, for an acknowledgment
during the 9th bit time. If the bus master does not drive Serial Data (SDA) Low during this
time, the device terminates the data transfer and switches to its Standby mode.
M24C16-125 M24C08-125 M24C04-125 M24C02-125 Initial delivery state
Doc ID 022564 Rev 1 19/30
4 Initial delivery state
The device is delivered with all bits in the memory array set to 1 (each byte contains FFh).
5 Maximum rating
Stressing the device outside the ratings listed in Ta b l e 4 may cause permanent damage to
the device. These are stress ratings only, and operation of the device at these, or any other
conditions outside those indicated in the operating sections of this specification, is not
implied. Exposure to absolute maximum rating conditions for extended periods may affect
device reliability.
Table 4. Absolute maximum ratings
Symbol Parameter Min. Max. Unit
Ambient operating temperature –40 130 °C
TSTG Storage temperature –65 150 °C
TLEAD Lead temperature during soldering see note (1)
1. Compliant with JEDEC Std J-STD-020C (for small body, Sn-Pb or Pb assembly), the ST ECOPACK®
7191395 specification, and the European directive on Restrictions on Hazardous Substances (RoHS)
2002/95/EU.
°C
IOL DC output current (SDA = 0) - 5 mA
VIO Input or output range –0.50 6.5 V
VCC Supply voltage –0.50 6.5 V
VESD Electrostatic pulse (human body model)(2)
2. Positive and negative pulses applied on pin pairs, according to AEC-Q100-002 (compliant with JEDEC Std
JESD22-A114, C1=100 pF, R1=1500 Ω, R2=500 Ω).
- 4000 V
DC and AC parameters M24C16-125 M24C08-125 M24C04-125 M24C02-125
20/30 Doc ID 022564 Rev 1
6 DC and AC parameters
This section summarizes the operating and measurement conditions, and the DC and AC
characteristics of the device. The parameters in the DC and AC characteristic tables that
follow are derived from tests performed under the measurement conditions summarized in
the relevant tables. Designers should check that the operating conditions in their circuit
match the measurement conditions when relying on the quoted parameters.
Figure 10. AC measurement I/O waveform
Table 5. Operating conditions
Symbol Parameter Min. Max. Unit
VCC Supply voltage 2.5 5.5 V
Ambient operating temperature –40 125 °C
Table 6. AC measurement conditions
Symbol Parameter Min. Max. Unit
Cbus Load capacitance 100 pF
SCL input rise/fall time, SDA input fall time - 50 ns
Input levels 0.2 VCC to 0.8 VCC V
Input and output timing reference levels 0.3 VCC to 0.7 VCC V
!)#
6
##
6
##
6
##
6
##
)NPUTANDOUTPUT
TIMINGREFERENCELEVELS
)NPUTVOLTAGELEVELS
Table 7. Input parameters
Symbol Parameter(1) Test condition Min. Max. Unit
CIN Input capacitance (SDA) - 8 pF
CIN Input capacitance (other pins) - 6 pF
ZWCL WC input impedance VIN < 0.3 V 15 70 kΩ
ZWCH WC input impedance VIN > 0.7VCC 500 - kΩ
tNS
Pulse width ignored (input filter on
SCL and SDA) Single glitch - 100 ns
1. Characterized only.
M24C16-125 M24C08-125 M24C04-125 M24C02-125 DC and AC parameters
Doc ID 022564 Rev 1 21/30
Table 8. DC characteristics
Symbol Parameter Test condition
(in addition to those in Table 5)Min. Max. Unit
ILI
Input leakage current (SCL,
SDA, E0, E1,and E2)
VIN = VSS or VCC, device in
Standby mode -± 2µA
ILO Output leakage current SDA in Hi-Z, external voltage
applied on SDA: VSS or VCC
-± 2µA
ICC Supply current
VCC = 5 V, fC= 400 kHz
(rise/fall time < 50 ns) -3mA
VCC = 2.5 V, fC = 400 kHz
(rise/fall time < 50 ns) -3mA
ICC1 Standby supply current
Device not selected(1), VIN = VSS
or VCC, VCC = 5 V
1. The device is not selected after a power-up, after a read command (after the Stop condition), or after the
completion of the internal write cycle tW (tW is triggered by the correct decoding of a write command).
-5µA
Device not selected(1), VIN = VSS
or VCC, VCC = 2.5 V -2µA
VIL
Input low voltage (SDA,
SCL, WC)–0.45 0.3 VCC V
VIH
Input high voltage (SDA,
SCL, WC)0.7 VCC VCC+1 V
VOL Output low voltage IOL = 2.1 mA when VCC = 2.5 V or
IOL = 3 mA when VCC = 5.5 V -0.4V
DC and AC parameters M24C16-125 M24C08-125 M24C04-125 M24C02-125
22/30 Doc ID 022564 Rev 1
Table 9. AC characteristics at 400 kHz (I2C Fast mode)
Test conditions specified in Section 6: DC and AC parameters
Symbol Alt. Parameter Min.(1)
1. All values are referred to VIL(max) and VIH(min).
Max.(1) Unit
fCfSCL Clock frequency - 400 kHz
tCHCL tHIGH Clock pulse width high 600 - ns
tCLCH tLOW Clock pulse width low 1300 - ns
tQL1QL2(2)
2. Characterized only, not tested in production.
tFSDA (out) fall time 20(3)
3. With CL = 10 pF.
120 ns
tXH1XH2 tRInput signal rise time (4)
4. There is no min. or max. values for the input signal rise and fall times. It is however recommended by the
I²C specification that the input signal rise and fall times be more than 20 ns and less than 300 ns when
fC< 400 kHz.
(4) ns
tXL1XL2 tFInput signal fall time (4) (4) ns
tDXCX tSU:DAT Data in set up time 100 - ns
tCLDX tHD:DAT Data in hold time 0 - ns
tCLQX(5)
5. To avoid spurious Start and Stop conditions, a minimum delay is placed between SCL=1 and the falling or
rising edge of SDA.
tDH Data out hold time 100 - ns
tCLQV(6)
6. tCLQV is the time (from the falling edge of SCL) required by the SDA bus line to reach either 0.3VCC or
0.7VCC, assuming that Rbus × Cbus time constant is within the values specified in Figure 4.
tAA Clock low to next data valid (access time) 200 900 ns
tCHDL tSU:STA Start condition setup time 600 - ns
tDLCL tHD:STA Start condition hold time 600 - ns
tCHDH tSU:STO Stop condition set up time 600 - ns
tDHDL tBUF
Time between Stop condition and next Start
condition 1300 - ns
tWtWR Write time - 5 ms
M24C16-125 M24C08-125 M24C04-125 M24C02-125 DC and AC parameters
Doc ID 022564 Rev 1 23/30
Table 10. AC characteristics at 100 kHz (I2C Standard mode)(1)
1. Values recommended by the I2C bus Standard-mode specification for a robust design of the I2C bus
application. Note that the M24xxx devices decode correctly faster timings as specified in Table 9: AC
characteristics at 400 kHz (I2C Fast mode).
Test conditions specified in Section 6: DC and AC parameters
Symbol Alt. Parameter Min. Max. Unit
fCfSCL Clock frequency - 100 kHz
tCHCL tHIGH Clock pulse width high 4 - µs
tCLCH tLOW Clock pulse width low 4.7 - µs
tXH1XH2 t
RInput signal rise time - 1 µs
tXL1XL2 tFInput signal fall time - 300 ns
tQL1QL2(2)
2. Characterized only.
tFSDA fall time - 300 ns
tDXCX tSU:DAT Data in setup time 250 - ns
tCLDX tHD:DAT Data in hold time 0 - ns
tCLQX(3)
3. To avoid spurious Start and Stop conditions, a minimum delay is placed between SCL=1 and the falling or
rising edge of SDA.
tDH Data out hold time 200 - ns
tCLQV tAA Clock low to next data valid (access time) 200 3450 ns
tCHDX(4)
4. For a reStart condition, or following a Write cycle.
tSU:STA Start condition setup time 4.7 - µs
tDLCL tHD:STA Start condition hold time 4 - µs
tCHDH tSU:STO Stop condition setup time 4 - µs
tDHDL tBUF
Time between Stop condition and next Start
condition 4.7 - µs
tWtWR Write time - 5 ms
DC and AC parameters M24C16-125 M24C08-125 M24C04-125 M24C02-125
24/30 Doc ID 022564 Rev 1
Figure 11. AC waveforms
3#,
3$!)N
3#,
3$!/UT
3#,
3$!)N
T#(#,
T$,#,
T#($,
3TART
CONDITION
T#,#(
T$8#(T#,$8
3$!
)NPUT
3$!
#HANGE
T#($( T$($,
3TOP
CONDITION
$ATAVALID
T#,16 T#,18
T#($(
3TOP
CONDITION
T#($,
3TART
CONDITION
7RITECYCLE
T7
!)F
3TART
CONDITION
T#(#,
T8(8(
T8(8(
T8,8,
T8,8,
$ATAVALID
T1,1,
M24C16-125 M24C08-125 M24C04-125 M24C02-125 Package mechanical data
Doc ID 022564 Rev 1 25/30
7 Package mechanical data
In order to meet environmental requirements, ST offers these devices in different grades of
ECOPACK® packages, depending on their level of environmental compliance. ECOPACK®
specifications, grade definitions and product status are available at: www.st.com.
ECOPACK® is an ST trademark.
Package mechanical data M24C16-125 M24C08-125 M24C04-125 M24C02-125
26/30 Doc ID 022564 Rev 1
Figure 12. SO8 narrow – 8 lead plastic small outline, 150 mils body width, package
outline
1. Drawing is not to scale.
2. The “1” that appears in the top view of the package shows the position of pin 1 and the “N” indicates the
total number of pins.
Table 11. SO8 narrow – 8 lead plastic small outline, 150 mils body width,
package mechanical data
Symbol
millimeters inches(1)
1. Values in inches are converted from mm and rounded to 4 decimal digits.
Typ Min Max Typ Min Max
A - - 1.750 - - 0.0689
A1 - 0.100 0.250 - 0.0039 0.0098
A2 - 1.250 - - 0.0492 -
b - 0.280 0.480 - 0.0110 0.0189
c - 0.170 0.230 - 0.0067 0.0091
ccc - - 0.100 - - 0.0039
D 4.900 4.800 5 0.1929 0.1890 0.1969
E 6.000 5.800 6.200 0.2362 0.2283 0.2441
E1 3.900 3.800 4.000 0.1535 0.1496 0.1575
e 1.270 - - 0.0500 - -
h - 0.250 0.500 - 0.0098 0.0197
k-0°8°-0°8°
L - 0.400 1.270 - 0.0157 0.0500
L1 1.040 0.0409
SO-A
E1
8
ccc
b
e
A
D
c
1
E
h x 45˚
A2
k
0.25 mm
L
L1
A1
GAUGE PLANE
M24C16-125 M24C08-125 M24C04-125 M24C02-125 Package mechanical data
Doc ID 022564 Rev 1 27/30
Figure 13. TSSOP8 – 8 lead thin shrink small outline, package outline
1. Drawing is not to scale.
2. The circle in the top view of the package indicates the position of pin 1.
Table 12. TSSOP8 – 8 lead thin shrink small outline, package mechanical data
Symbol
millimeters inches(1)
1. Values in inches are converted from mm and rounded to 4 decimal digits.
Typ. Min. Max. Typ. Min. Max.
A - - 1.200 - - 0.0472
A1 - 0.050 0.150 - 0.0020 0.0059
A2 1.000 0.800 1.050 0.0394 0.0315 0.0413
b - 0.190 0.300 - 0.0075 0.0118
c - 0.090 0.200 - 0.0035 0.0079
CP - - 0.100 - - 0.0039
D 3.000 2.900 3.100 0.1181 0.1142 0.1220
e 0.650 - - 0.0256 - -
E 6.400 6.200 6.600 0.2520 0.2441 0.2598
E1 4.400 4.300 4.500 0.1732 0.1693 0.1772
L 0.600 0.450 0.750 0.0236 0.0177 0.0295
L1 1.000 - - 0.0394 - -
α-0°8°-0°8°
TSSOP8AM
1
8
CP
c
L
EE1
D
A2A
α
eb
4
5
A1
L1
Part numbering M24C16-125 M24C08-125 M24C04-125 M24C02-125
28/30 Doc ID 022564 Rev 1
8 Part numbering
For a list of available options (speed, package, etc.) or for further information on any aspect
of this device, please contact your nearest ST sales office.
Table 13. Ordering information scheme
Example: M24C16 – W DW 3 T P /S
Device type
M24 = I2C serial access EEPROM
Device Function
16 = 16 Kbit (2048 x 8)
08 = 8 Kbit (1024 x 8)
04 = 4 Kbit (512 x 8)
02 = 2 Kbit (256 x 8)
Operating voltage
W = VCC = 2.5 V to 5.5 V (400 kHz)
Package
MN = SO8 (150 mil width)
DW = TSSOP8 (169 mil width)
Device grade
3 = Automotive: device tested with high reliability certified flow over –40 to 125 °C
Option
T = Tape and reel packing
Plating technology
P = ECOPACK® (RoHS compliant)
Process
/S = Manufacturing technology code
M24C16-125 M24C08-125 M24C04-125 M24C02-125
30/30 Doc ID 022564 Rev 1
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