5555 N.E. Moore Ct. Hillsboro, Oregon 97124-6421 Phone (503) 268-8000 FAX (503) 268-8347
Internet: http://www.latticesemi.com
GAL®22V10 Device Datasheet
September 2010
All Devices Discontinued!
Product Change Notifications (PCNs) have been issued to discontinue all devices in this
data sheet.
The original datasheet pages have not been modified and do not reflect those changes.
Please refer to the table below for reference PCN and current product status.
Product Line
Ordering Part Number
Product Status
Reference PCN
GAL22V10D
GAL22V10D-7LP
Discontinued
PCN#09-10
GAL22V10D-7LPN
GAL22V10D-10LP
PCN#13-10
GAL22V10D-10LPN
GAL22V10D-15LP
GAL22V10D-15LPN
GAL22V10D-25LP
GAL22V10D-25LPN
GAL22V10D-7LPI
PCN#09-10
GAL22V10D-7LPNI
GAL22V10D-10LPI
PCN#13-10
GAL22V10D-10LPNI
GAL22V10D-15LPI
GAL22V10D-15LPNI
GAL22V10D-20LPI
GAL22V10D-20LPNI
GAL22V10D-25LPI
GAL22V10D-25LPNI
GAL22V10D-10QP
GAL22V10D-10QPN
GAL22V10D-15QP
GAL22V10D-15QPN
GAL22V10D-25QP
GAL22V10D-25QPN
GAL22V10D-10LS
PCN#06-07
GAL22V10D-15LS
GAL22V10D-25LS
GAL22V10D-4LJ
PCN#09-10
GAL22V10D-4LJN
GAL22V10D-5LJ
PCN#13-10
GAL22V10D-5LJN
5555 N.E. Moore Ct. Hillsboro, Oregon 97124-6421 Phone (503) 268-8000 FAX (503) 268-8347
Internet: http://www.latticesemi.com
Product Line
Ordering Part Number
Product Status
Reference PCN
GAL22V10D
(Cont’d)
GAL22V10D-7LJ
Discontinued
PCN#13-10
GAL22V10D-7LJN
GAL22V10D-10LJ
GAL22V10D-10LJN
GAL22V10D-15LJ
GAL22V10D-15LJN
GAL22V10D-25LJ
GAL22V10D-25LJN
GAL22V10D-7LJI
PCN#09-10
GAL22V10D-7LJNI
GAL22V10D-10LJI
GAL22V10D-10LJNI
GAL22V10D-15LJI
PCN#13-10
GAL22V10D-15LJNI
GAL22V10D-20LJI
GAL22V10D-20LJNI
GAL22V10D-25LJI
GAL22V10D-25LJNI
GAL22V10D-10QJ
GAL22V10D-10QJN
GAL22V10D-15QJ
GAL22V10D-15QJN
GAL22V10D-25QJ
GAL22V10D-25QJN
Specifications GAL22V10
1
228
NC
I/CLK
I
I
I
I
I
I
I
I
NC NC
NC
GND
I
I
I
I/O/Q
I/O/Q
I/O/Q
I/O/Q
I/O/Q
I/O/Q
I/O/Q
Vcc
I/O/Q
I/O/Q I/O/Q
426
25
19
18
21
23
161412
11
9
7
5
Features
• HIGH PERFORMANCE E2CMOS® TECHNOLOGY
— 4 ns Maximum Propagation Delay
— Fmax = 250 MHz
— 3.5 ns Maximum from Clock Input to Data Output
— UltraMOS® Advanced CMOS Technology
• ACTIVE PULL-UPS ON ALL PINS
• COMPATIBLE WITH STANDARD 22V10 DEVICES
— Fully Function/Fuse-Map/Parametric Compatible
with Bipolar and UVCMOS 22V10 Devices
• 50% to 75% REDUCTION IN POWER VERSUS BIPOLAR
— 90mA Typical Icc on Low Power Device
— 45mA Typical Icc on Quarter Power Device
•E
2 CELL TECHNOLOGY
— Reconfigurable Logic
— Reprogrammable Cells
— 100% Tested/100% Y ields
— High Speed Electrical Erasure (<100ms)
— 20 Year Data Retention
• TEN OUTPUT LOGIC MACROCELLS
— Maximum Flexibility for Complex Logic Designs
• PRELOAD AND POWER-ON RESET OF REGISTERS
— 100% Functional T estability
• APPLICATIONS INCLUDE:
— DMA Control
— State Machine Control
— High Speed Graphics Processing
— Standard Logic Speed Upgrade
• ELECTRONIC SIGNATURE FOR IDENTIFICA TION
• LEAD-FREE PACKAGE OPTIONS
ESCRIPTION
Description
The GAL22V10, at 4ns maximum propagation delay time, combines
a high performance CMOS process with Electrically Erasable (E2)
floating gate technology to provide the highest performance avail-
able of any 22V10 device on the market. CMOS circuitry allows
the GAL22V10 to consume much less power when compared to
bipolar 22V10 devices. E2 technology offers high speed (<100ms)
erase times, providing the ability to reprogram or reconfigure the
device quickly and efficiently.
The generic architecture provides maximum design flexibility by
allowing the Output Logic Macrocell (OLMC) to be configured by
the user. The GAL22V10 is fully function/fuse map/parametric com-
patible with standard bipolar and CMOS 22V10 devices.
Unique test circuitry and reprogrammable cells allow complete AC,
DC, and functional testing during manufacture. As a result, Lat-
tice Semiconductor delivers 100% field programmability and func-
tionality of all GAL products. In addition, 100 erase/write cycles and
data retention in excess of 20 years are specified.
GAL22V10
High Performance E2CMOS PLD
Generic Array Logic™
Copyright © 2006 Lattice Semiconductor Corp. All brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject
to change without notice.
LATTICE SEMICONDUCTOR CORP., 5555 Northeast Moore Ct., Hillsboro, Oregon 97124, U.S.A. December 2006
Tel. (503) 268-8000; 1-800-LATTICE; FAX (503) 268-8556; http://www.latticesemi.com
GAL22V10
Top View
PLCC
1
12 13
24
I/CLK
I
I
I
I
I
I
I
I
I
I
GND
Vcc
I/O/Q
I/O/Q
I/O/Q
I/O/Q
I/O/Q
I/O/Q
I/O/Q
I/O/Q
I/O/Q
I/O/Q
I
6
18
GAL
22V10
DIP
22v10_12
Functional Block Diagram
Pin Configuration
SOIC
GAL22V10
Top View
Lead-Free
Package
Options
Available!
1
12 13
24
I
I
I
I
I
I
I
I
I
GND
I/O/Q
I/O/Q
I/O/Q
I/O/Q
I/O/Q
I/O/Q
I/O/Q
I/O/Q
I/O/Q
I
618
I/CLK
IVcc
I/O/Q
PROGRAMMABLE
AND-ARRAY
(132X44)
I/O/Q
I/O/Q
I/O/Q
I/O/Q
I/O/Q
I/O/Q
I/O/Q
I/O/Q
I/O/Q
I/O/Q
I
I/CLK
I
I
I
I
I
I
I
I
I
I
RESET
PRESET
8
10
12
14
16
16
14
12
10
8
OLMC
OLMC
OLMC
OLMC
OLMC
OLMC
OLMC
OLMC
OLMC
OLMC
ALL DEVICES
DISCONTINUED
Specifications GAL22V10
2
Conventional Packaging
Commercial Grade Specifications
Industrial Grade Specifications
GAL22V10 Ordering Information
)sn(dpT)sn(usT)sn(ocT)Am(ccI#gniredrOegakcaP
5.755.4061 01V22LAGDIPL7- PIDcitsalPniP-42
5.45.4061 01V22LAGDIJL7- CCLPdaeL-82
0177 061 01V22LAGDIPL01- PIDcitsalPniP-42
061 01V22LAGDIJL01- CCLP
daeL-82
51018 031G IPL51-D01V22LA PIDcitsalPniP-42
031IJL51-D01V22LAG CCLPdaeL-82
024101031IPL02-D01V22LAG PIDcitsalPniP-42
031IJL02-D01V22LAG CCLPdaeL-82
525151031IPL52-D01V22LAG PIDcitsalPniP-42
031IJL52-D01V22LAG CCLPdaeL-82
)sn(dpT)sn(usT)sn(ocT)Am(ccI#gniredOr geakcaP
45.25.3041JL4-D01V22LAG CCLPdaeL-82
534 041JL5-D01V22LAG CCLPdaeL-82
5.75.45.4041PL7-D01V22LAG PIDcitsalPniP-42
5.45.4041JL7-D01V22LAG CCLPdaeL-82
017755PQ01-D0
1V22LAG PIDcitsalPniP-42
55JQ01-D01V22LAG CCLPdaeL-82
90
90
130
90
LP01-D01V22LAG PIDcitsalPniP-42
031JL01-D01V22LAG CCLPdaeL-82
03L
S
1
01-D01V22LAG CIOSniP-42
5101855PQ51-D01V22LAG PIDcitsalPniP-42
55JQ51-D01V22LAG CCLPdaeL-82
LP51-D01V22LAG PIDcitsalPniP-42
LJ51-D01V22LAG CCLPdaeL-82
LS
1
51-D01V22LAG CIOSniP-42
52515155PQ52-D01V22LAG PIDcitsalPniP-42
55JQ52-D01V22LAG CCLPdaeL-82
09PL52-D01V22LAG piDcitsalPniP-42
09JL52-D01V22LAG CCLPdaeL-82
09S
1
L52-D01V22LAG CIOSniP-42
1. Discontinued per PCN #06-07. Contact Rochester Electronics for available inventory.
ALL DEVICES
DISCONTINUED
Specifications GAL22V10
3
Part Number Description
Lead-Free Packaging
Commercial Grade Specifications
)sn(dpT)sn(usT)sn(ocT)Am(ccI#gniredrOegakcaP
45.25.3041NJL4-D01V22LAG CCLPdaeL-82eerF-daeL
534 041NJL5-D01V22LAG CCLPdaeL-82eerF-daeL
5.75.45.4041NPL7-D01V22LAG PIDcitsalPniP-42eerF-daeL
5.45.4041NJL7-D01V22LAG CCLPdaeL-82eerF-daeL
017755NPQ01
-D01V22LAG PIDcitsalPniP-42eerF-daeL
55NJQ01-D01V22LAG CCLPdaeL-82eerF-daeL
031NPL01-D01V22LAG PIDcitsalPniP-42eerF-daeL
031NJL01-D01V22LAG CCLPdaeL-82eerF-daeL
5101855NPQ51-D01V22LAG PIDcitsalPniP-42eerF-daeL
55NJQ51-D01V22LAG CCLPdaeL-82eerF-daeL
09NPL51-D01V22LAG PIDcitsalPniP-42eerF-daeL
09NJL51-D01V22LAG CCLPdaeL-82eerF-daeL
52515155NPQ52-D01V22LAG PIDcitsalPniP-42eerF-daeL
55NJQ52-D01V22LAG CCLPdaeL-82eerF-daeL
09NPL52-D01V22LAG piDcitsalPniP-42eerF-daeL
09NJL52-D01V22LAG CCLPdaeL-82eerF-daeL
Industrial Grade Specifications
)sn(dpT)sn(usT)sn(ocT)Am(ccI#gniredrOegakcaP
5.755.4061INPL7-D01V22LAG PIDcitsalPniP-42eerF-daeL
5.45.4061INJL7-D01V22LAG CCLPdaeL-82eerF-daeL
0177 061INPL01-D01V22LAG PIDcitsalPniP-42eerF-daeL
061INJL01-D01V22LAG CCLPdaeL-82eerF-daeL
51018 031INPL51
-D01V22LAG PIDcitsalPniP-42eerF-daeL
031INJL51-D01V22LAG CCLPdaeL-82eerF-daeL
024101031INPL02-D01V22LAG PIDcitsalPniP-42eerF-daeL
031INJL02-D01V22LAG CCLPdaeL-82eerF-daeL
525151031INPL52-D01V22LAG piDcitsalPniP-42eerF-daeL
031INJL52-D01V22LAG CCLPdaeL-82eerF-daeL
Blank = Commercial
I = Industrial
Grade
Package
PowerL = Low Power
Q = Quarter Power
Speed (ns)
XXXXXXXX XX X XX X
Device Name
_
P = Plastic DIP
PN = Lead-Free Plastic DIP
J = PLCC
JN = Lead-Free PLCC
S = SOIC
GAL22V10D
ALL DEVICES
DISCONTINUED
Specifications GAL22V10
4
GAL22V10 OUTPUT LOGIC MACROCELL (OLMC)
Each of the Macrocells of the GAL22V10 has two primary functional
modes: registered, and combinatorial I/O. The modes and the
output polarity are set by two bits (SO and S1), which are normally
controlled by the logic compiler. Each of these two primary modes,
and the bit settings required to enable them, are described below
and on the following page.
REGISTERED
In registered mode the output pin associated with an individual
OLMC is driven by the Q output of that OLMC’s D-type flip-flop.
Logic polarity of the output signal at the pin may be selected by
specifying that the output buffer drive either true (active high) or
inverted (active low). Output tri-state control is available as an in-
dividual product-term for each OLMC, and can therefore be defined
by a logic equation. The D flip-flop’s /Q output is fed back into the
AND array, with both the true and complement of the feedback
available as inputs to the AND array.
NOTE: In registered mode, the feedback is from the /Q output of
the register, and not from the pin; therefore, a pin defined as reg-
istered is an output only, and cannot be used for dynamic
I/O, as can the combinatorial pins.
COMBINATORIAL I/O
In combinatorial mode the pin associated with an individual OLMC
is driven by the output of the sum term gate. Logic polarity of the
output signal at the pin may be selected by specifying that the output
buffer drive either true (active high) or inverted (active low). Out-
put tri-state control is available as an individual product-term for
each output, and may be individually set by the compiler as either
“on” (dedicated output), “off” (dedicated input), or “product-term
driven” (dynamic I/O). Feedback into the AND array is from the pin
side of the output enable buffer. Both polarities (true and inverted)
of the pin are fed back into the AND array.
The GAL22V10 has a variable number of product terms per OLMC.
Of the ten available OLMCs, two OLMCs have access to eight
product terms (pins 14 and 23, DIP pinout), two have ten product
terms (pins 15 and 22), two have twelve product terms (pins 16 and
21), two have fourteen product terms (pins 17 and 20), and two
OLMCs have sixteen product terms (pins 18 and 19). In addition
to the product terms available for logic, each OLMC has an addi-
tional product-term dedicated to output enable control.
The output polarity of each OLMC can be individually programmed
to be true or inverting, in either combinatorial or registered mode.
This allows each output to be individually configured as either active
high or active low.
The GAL22V10 has a product term for Asynchronous Reset (AR)
and a product term for Synchronous Preset (SP). These two prod-
uct terms are common to all registered OLMCs. The Asynchronous
Reset sets all registers to zero any time this dedicated product term
is asserted. The Synchronous Preset sets all registers to a logic
one on the rising edge of the next clock pulse after this product term
is asserted.
NOTE: The AR and SP product terms will force the Q output of the
flip-flop into the same state regardless of the polarity of the output.
Therefore, a reset operation, which sets the register output to a zero,
may result in either a high or low at the output pin, depending on
the pin polarity chosen.
AR
SP
D
Q
QCLK
4 TO 1
MUX
2 TO 1
MUX
Output Logic Macrocell (OLMC)
Output Logic Macrocell Configurations
ALL DEVICES
DISCONTINUED
Specifications GAL22V10
5
ACTIVE HIGHACTIVE LOW
ACTIVE HIGHACTIVE LOW
S0 = 1
S1 = 1
S0 = 0
S1 = 1
S0 = 0
S1 = 0 S0 = 1
S1 = 0
AR
SP
D
Q
Q
CLK
AR
SP
D
Q
Q
CLK
Registered Mode
Combinatorial Mode
ALL DEVICES
DISCONTINUED
Specifications GAL22V10
6
DIP (PLCC) Package Pinouts
1 (2)
22 (26)
OLMC
S0
5810
S1
5811
0440
.
.
.
.
0880
2 (3)
ASYNCHRONOUS RESET
(TO ALL REGISTERS)
0 4 8 1216202428323640
SYNCHRONOUS PRESET
(TO ALL REGISTERS)
10 (12)
0000
5764
0044
.
.
.
0396
23 (27)
S0
5808
S1
5809
21 (25)
OLMC
S0
5812
S1
5813
0924
.
.
.
.
.
1452
3 (4)
4 (5)
5 (6)
20 (24)
OLMC
S0
5814
S1
5815
1496
.
.
.
.
.
.
2112
19 (23)
OLMC
S0
5816
S1
5817
2156
.
.
.
.
.
.
.
2860
18 (21)
OLMC
S0
5818
S1
5819
2904
.
.
.
.
.
.
.
3608
17 (20)
OLMC
S0
5820
S1
5821
3652
.
.
.
.
.
.
4268
OLMC
S0
5822
S1
5823
4312
.
.
.
.
.
4840
8 (10)
16 (19)
15 (18)
OLMC
S0
5824
S1
5825
4884
.
.
.
.
5324
9 (11)
5368
.
.
.
5720
14 (17)
OLMC
S0
5826
S1
5827
7 (9)
6 (7)
11 (13) 13 (16)
8
10
14
16
12
12
16
14
10
8
OLMC
Electronic Signature 5828, 5829 ... ... 5890, 5891
L
S
B
M
S
B
Byte 7 Byte 6 Byte 5 Byte 4 Byte 2 Byte 1 Byte 0Byte 3
GAL22V10 Logic Diagram / JEDEC Fuse Map
ALL DEVICES
DISCONTINUED
Specifications GAL22V10
7
Supply voltage VCC ....................................... -0.5 to +7V
Input voltage applied ........................... -2.5 to VCC +1.0V
Off-state output voltage applied........... -2.5 to VCC +1.0V
Storage Temperature..................................-65 to 150°C
Ambient Temperature with
Power Applied .........................................-55 to 125°C
1. Stresses above those listed under the “Absolute Maximum
Ratings” may cause permanent damage to the device. These
are stress only ratings and functional operation of the device
at these or at any other conditions above those indicated in
the operational sections of this specification is not implied
(while programming, follow the programming specifications).
Commercial Devices:
Ambient Temperature (TA) ............................. 0 to +75°C
Supply voltage (VCC)
with Respect to Ground ..................... +4.75 to +5.25V
Industrial Devices:
Ambient Temperature (TA) ............................-40 to 85°C
Supply voltage (VCC)
with Respect to Ground ..................... +4.50 to +5.50V
Specifications GAL22V10D
COMMERCIAL
ICC Operating Power VIL = 0.5V VIH = 3.0V L-4/-5/-7 — 90 140 mA
Supply Current ftoggle = 15MHz Outputs Open L-10 — 90 130 mA
L-15/-25 — 75 90 mA
Q-10/-15/-25 — 45 55 mA
VIL Input Low Voltage Vss – 0.5 — 0.8 V
VIH Input High Voltage 2.0 — Vcc+1 V
IIL1Input or I/O Low Leakage Current 0V ≤ VIN ≤ VIL (MAX.) — — –100 μA
IIH Input or I/O High Leakage Current 3.5V ≤ VIN ≤ VCC ——10μA
VOL Output Low Voltage IOL = MAX. Vin = VIL or VIH — — 0.4 V
VOH Output High Voltage IOH = MAX. Vin = VIL or VIH 2.4 — — V
IOL Low Level Output Current — — 16 mA
IOH High Level Output Current — — –3.2 mA
IOS2Output Short Circuit Current VCC = 5V VOUT = 0.5V TA = 25°C –30 — –130 mA
Over Recommended Operating Conditions (Unless Otherwise Specified)
SYMBOL PARAMETER CONDITION MIN. TYP.3MAX. UNITS
INDUSTRIAL
ICC Operating Power VIL = 0.5V VIH = 3.0V L-7/-10 — 90 160 mA
Supply Current ftoggle = 15MHz Outputs Open L-15/-20/-25 — 75 130 mA
1) The leakage current is due to the internal pull-up on all pins. See Input Buffer section for more information.
2) One output at a time for a maximum duration of one second. Vout = 0.5V was selected to avoid test problems caused by tester
ground degradation. Characterized but not 100% tested.
3) Typical values are at Vcc = 5V and TA = 25 °C
Absolute Maximum Ratings1Recommended Operating Conditions
DC Electrical Characteristics
ALL DEVICES
DISCONTINUED
Specifications GAL22V10
8
tpd A Input or I/O to Combinatorial Output 1 4 1 5 1 7.5 ns
tco A Clock to Output Delay 1 3.5 1 4 1 4.5 ns
tcf2— Clock to Feedback Delay — 2.5 — 3 — 3 ns
tsu — Setup Time, Input or Fdbk before Clk↑2.5 — 3 — 4.5 — ns
th — Hold Time, Input or Fdbk after Clk↑0—0—0—ns
A Maximum Clock Frequency with 167 — 142.8 — 111 — MHz
External Feedback, 1/(tsu + tco)
fmax3A Maximum Clock Frequency with 200 — 166 — 133 — MHz
Internal Feedback, 1/(tsu + tcf)
A Maximum Clock Frequency with 250 — 200 — 166 — MHz
No Feedback
twh — Clock Pulse Duration, High 2 — 2.5 — 3 — ns
twl — Clock Pulse Duration, Low 2 — 2.5 — 3 — ns
ten B Input or I/O to Output Enabled 1 5 1 6 1 7.5 ns
tdis C Input or I/O to Output Disabled 1 5 1 5.5 1 7.5 ns
tar A Input or I/O to Asynch. Reset of Reg. 1 4.5 1 5.5 1 9 ns
tarw — Asynch. Reset Pulse Duration 4.5 — 4.5 — 7 — ns
tarr — Asynch. Reset to Clk↑ Recovery Time 3 — 4 — 5 — ns
tspr — Synch. Preset to Clk↑ Recovery Time 3 — 4 — 5 — ns
Over Recommended Operating Conditions
UNITS
1) Refer to Switching Test Conditions section.
2) Calculated from fmax with internal feedback. Refer to fmax Description section.
3) Refer to fmax Description section. Characterized initially and after any design or process changes that may affect these
parameters.
PARAM TEST
COND.1 DESCRIPTION
SYMBOL PARAMETER MAXIMUM* UNITS TEST CONDITIONS
CIInput Capacitance 8 pF VCC = 5.0V, VI = 2.0V
CI/O I/O Capacitance 8 pF VCC = 5.0V, VI/O = 2.0V
*Characterized but not 100% tested.
-5
MIN. MAX.
COM/INDCOM
-7
MIN. MAX.
AC Switching Characteristics
Capacitance (TA = 25°C, f = 1.0 MHz)
Specifications GAL22V10D
COM
-4
MIN. MAX.
ALL DEVICES
DISCONTINUED
Specifications GAL22V10
9
tpd A Input or I/O to Comb. Output 1 10 3 15 3 20 3 25 ns
tco A Clock to Output Delay 1 7 2 8 2 10 2 15 ns
tcf2— Clock to Feedback Delay — 2.5 — 2.5 — 8 — 13 ns
tsu — Setup Time, Input or Fdbk before Clk↑6 — 10 — 12 — 15 — ns
th — Hold Time, Input or Fdbk after Clk↑0— 0—0—0—ns
A Maximum Clock Frequency with 83.3 — 55.5 — 41.6 — 33.3 — MHz
External Feedback, 1/(tsu + tco)
fmax3A Maximum Clock Frequency with 110 — 80 — 45.4 — 35.7 — MHz
Internal Feedback, 1/(tsu + tcf)
A Maximum Clock Frequency with 125 — 83.3 — 50 — 38.5 — MHz
No Feedback
twh — Clock Pulse Duration, High 4 — 6 — 10 — 13 — ns
twl — Clock Pulse Duration, Low 4 — 6 — 10 — 13 — ns
ten B Input or I/O to Output Enabled 1 10 3 15 3 20 3 25 ns
tdis C Input or I/O to Output Disabled 1 9 3 15 3 20 3 25 ns
tar A Input or I/O to Asynch. Reset of Reg. 1 13 3 20 3 25 3 25 ns
tarw — Asynch. Reset Pulse Duration 8 — 15 — 20 — 25 — ns
tarr — Asynch. Reset to Clk↑ Recovery Time 8 — 10 — 20 — 25 — ns
tspr — Synch. Preset to Clk↑ Recovery Time 8 — 10 — 14 — 15 — ns
Specifications GAL22V10D
-10
MIN. MAX.
-25
MIN. MAX.
-20
MIN. MAX.
-15
MIN. MAX.
Over Recommended Operating Conditions
UNITS
1) Refer to Switching Test Conditions section.
2) Calculated from fmax with internal feedback. Refer to fmax Description section.
3) Refer to fmax Description section.
SYMBOL PARAMETER MAXIMUM* UNITS TEST CONDITIONS
CIInput Capacitance 8 pF VCC = 5.0V, VI = 2.0V
CI/O I/O Capacitance 8 pF VCC = 5.0V, VI/O = 2.0V
*Characterized but not 100% tested.
PARAM. TEST
COND.1DESCRIPTION
COM / IND IND COM / INDCOM / IND
Capacitance (TA = 25°C, f = 1.0 MHz)
AC Switching Characteristics
ALL DEVICES
DISCONTINUED
Specifications GAL22V10
10
Input or I/O to Output Enable/Disable
Registered Output
Combinatorial Output
VALID INPUT
INPUT or
I/O FEEDBACK
t
pd
COMBINATORIAL
OUTPUT
INPUT or
I/O FEEDBACK
REGISTERED
OUTPUT
CLK
VALID INPUT
t
su
t
co
t
h
(external fdbk)
1/
f
max
t
en
t
dis
INPUT or
I/O FEEDBACK
OUTPUT
CLK
(w/o fdbk)
t
wh
t
wl
1/
f
max
Clock Width
REGISTERED
OUTPUT
CLK
INPUT or
I/O FEEDBACK
DRIVING SP
t
su
t
h
t
co
t
spr
REGISTERED
OUTPUT
CLK
t
arw
t
ar
t
arr
INPUT or
I/O FEEDBACK
DRIVING AR
fmax with Feedback
Asynchronous ResetSynchronous Preset
CLK
REGISTERED
FEEDBACK
t
cf t
su
1/
f
max (internal fdbk)
Switching Waveforms
ALL DEVICES
DISCONTINUED
Specifications GAL22V10
11
fmax with Internal Feedback 1/(tsu+tcf)
Note: fmax with external feedback is cal-
culated from measured tsu and tco.
fmax with External Feedback 1/(tsu+tco)
Note: tcf is a calculated value, derived by sub-
tracting tsu from the period of fmax w/internal
feedback (tcf = 1/fmax - tsu). The value of tcf is
used primarily when calculating the delay from
clocking a register to a combinatorial output
(through registered feedback), as shown above.
For example, the timing from clock to a combi-
natorial output is equal to tcf + tpd.
fmax with No Feedback
Note: fmax with no feedback may be less
than 1/(twh + twl). This is to allow for a
clock duty cycle of other than 50%.
REGISTER
LOGIC
ARRAY
t
co
t
su
CLK
REGISTER
LOGIC
ARRAY
CLK
tsu + th
CLK
REGISTER
LOGIC
ARRAY
t
cf
t
pd
fmax Descriptions
ALL DEVICES
DISCONTINUED
Specifications GAL22V10
12
GAL22V10D-4 Output Load Conditions (see figure below)
Test Condition R1CL
A50Ω50pF
B Z to Active High at 1.9V 50Ω50pF
Z to Active Low at 1.0V 50Ω50pF
C Active High to Z at 1.9V 50Ω50pF
Active Low to Z at 1.0V 50Ω50pF
Input Pulse Levels GND to 3.0V
Input Rise and D-4/-5/-7 1.5ns 10% – 90%
Fall Times D-10/-15/-20/-25 2.0ns 10% – 90%
Input Timing Reference Levels 1.5V
Output Timing Reference Levels 1.5V
Output Load See Figure
3-state levels are measured 0.5V from steady-state active
level.
TEST POINT
C *
L
FROM OUTPUT (O/Q)
UNDER TEST
+5V
*C
L
INCLUDES TEST FIXTURE AND PROBE CAPACITANCE
R
2
R
1
Output Load Conditions (except D-4) (see figure below)
Test Condition R1R2CL
A 300Ω390Ω50pF
B Active High ∞390Ω50pF
Active Low 300Ω390Ω50pF
C Active High ∞390Ω5pF
Active Low 300Ω390Ω5pF
TEST POINT
Z
0
= 50Ω, C
L
*
FROM OUTPUT (O/Q)
UNDER TEST
+1.45V
R
1
Switching Test Conditions
ALL DEVICES
DISCONTINUED
Specifications GAL22V10
13
Electronic Signature
An electronic signature (ES) is provided in every GAL22V10
device. It contains 64 bits of reprogrammable memory that can
contain user-defined data. Some uses include user ID codes,
revision numbers, or inventory control. The signature data is
always available to the user independent of the state of the se-
curity cell.
The electronic signature is an additional feature not present in
other manufacturers' 22V10 devices. To use the extra feature of
the user-programmable electronic signature it is necessary to
choose a Lattice Semiconductor 22V10 device type when com-
piling a set of logic equations. In addition, many device program-
mers have two separate selections for the device, typically a
GAL22V10 and a GAL22V10-UES (UES = User Electronic Sig-
nature) or GAL22V10-ES. This allows users to maintain compat-
ibility with existing 22V10 designs, while still having the option to
use the GAL device's extra feature.
The JEDEC map for the GAL22V10 contains the 64 extra fuses
for the electronic signature, for a total of 5892 fuses. However,
the GAL22V10 device can still be programmed with a standard
22V10 JEDEC map (5828 fuses) with any qualified device pro-
grammer.
Security Cell
A security cell is provided in every GAL22V10 device to prevent
unauthorized copying of the array patterns. Once programmed,
this cell prevents further read access to the functional bits in the
device. This cell can only be erased by re-programming the
device, so the original configuration can never be examined once
this cell is programmed. The Electronic Signature is always avail-
able to the user, regardless of the state of this control cell.
Latch-Up Protection
GAL22V10 devices are designed with an on-board charge pump
to negatively bias the substrate. The negative bias is of sufficient
magnitude to prevent input undershoots from causing the circuitry
to latch. Additionally, outputs are designed with n-channel pullups
instead of the traditional p-channel pullups to eliminate any pos-
sibility of SCR induced latching.
Device Programming
GAL devices are programmed using a Lattice Semiconductor-
approved Logic Programmer, available from a number of manu-
facturers (see the the GAL Development Tools section). Com-
plete programming of the device takes only a few seconds. Eras-
ing of the device is transparent to the user, and is done automati-
cally as part of the programming cycle.
Typical Input Current
1.0 2.0 3.0 4.0 5.0
-60
0
-20
-40
0
Input Voltage (Volts)
Input Current (uA)
Output Register Preload
When testing state machine designs, all possible states and state
transitions must be verified in the design, not just those required
in the normal machine operations. This is because certain events
may occur during system operation that throw the logic into an
illegal state (power-up, line voltage glitches, brown-outs, etc.). To
test a design for proper treatment of these conditions, a way must
be provided to break the feedback paths, and force any desired
(i.e., illegal) state into the registers. Then the machine can be
sequenced and the outputs tested for correct next state condi-
tions.
The GAL22V10 device includes circuitry that allows each regis-
tered output to be synchronously set either high or low. Thus, any
present state condition can be forced for test sequencing. If
necessary, approved GAL programmers capable of executing test
vectors perform output register preload automatically.
Input Buffers
GAL22V10 devices are designed with TTL level compatible in-
put buffers. These buffers have a characteristically high imped-
ance, and present a much lighter load to the driving logic than bi-
polar TTL devices.
The input and I/O pins also have built-in active pull-ups. As a re-
sult, floating inputs will float to a TTL high (logic 1). However,
Lattice Semiconductor recommends that all unused inputs and
tri-stated I/O pins be connected to an adjacent active input, Vcc,
or ground. Doing so will tend to improve noise immunity and
reduce Icc for the device. (See equivalent input and I/O schemat-
ics on the following page.)
ALL DEVICES
DISCONTINUED
Specifications GAL22V10
14
(Vref Typical = 3.2V)
(Vref Typical = 3.2V)
Circuitry within the GAL22V10 provides a reset signal to all reg-
isters during power-up. All internal registers will have their Q out-
puts set low after a specified time (tpr, 1μs MAX). As a result, the
state on the registered output pins (if they are enabled) will be
either high or low on power-up, depending on the programmed
polarity of the output pins. This feature can greatly simplify state
machine design by providing a known state on power-up. The
timing diagram for power-up is shown below. Because of the asyn-
chronous nature of system power-up, some conditions must be
met to guarantee a valid power-up reset of the GAL22V10. First,
the Vcc rise must be monotonic. Second, the clock input must
be at static TTL level as shown in the diagram during power up.
The registers will reset within a maximum of tpr time. As in nor-
mal system operation, avoid clocking the device until all input and
feedback path setup times have been met. The clock must also
meet the minimum pulse width requirements.
Vcc
PIN
Vcc
Vref
Active Pull-up
Circuit
ESD
Protection
Circuit
ESD
Protection
Circuit
Vcc
PIN
Vcc (min.)
t
pr
Internal Register
Reset to Logic "0"
Device Pin
Reset to Logic "1"
t
wl
t
su
Device Pin
Reset to Logic "0"
Vcc
CLK
INTERNAL REGISTER
Q - OUTPUT
ACTIVE LOW
OUTPUT REGISTER
ACTIVE HIGH
OUTPUT REGISTER
Vcc
PIN
Vref
Tri-State
Control
Active Pull-up
Circuit
Feedback
(To Input Buffer)
PIN
Feedback
Data
Output
Typical Input Typical Output
Power-Up Reset
Input/Output Equivalent Schematics
ALL DEVICES
DISCONTINUED
Specifications GAL22V10
15
Delta Tpd vs # of Outputs
Switching
-0.3
-0.2
-0.1
0
12345678910
Number of Outputs Switching
Delta Tpd (ns)
RISE
FALL
Delta Tco vs # of Outputs
Switching
-0.4
-0.3
-0.2
-0.1
0
12345678910
Number of Outputs Switching
Delta Tco (ns)Delta Tco (ns)
RISE
FALL
Delta Tpd vs Output Loading
Output Loading (pF)
Delta Tpd (ns)
RISE
FALL
Delta Tco vs Output Loading
RISE
FALL
Normalized Tpd vs Vcc
Normalized TpdNormalized Tpd
RISE
FALL
Normalized Tco vs Vcc
RISE
FALL
Normalized Tsu vs Vcc
Supply Voltage (V)Supply Voltage (V)Supply Voltage (V)
RISE
FALL
Normalized Tpd vs Temp Normalized Tco vs Temp Normalized Tsu vs Temp
1251007550250-25-55
1251007550250-25-55
300250200150100500
Output Loading (pF)
300250200150100500
Temperature (deg. C) Temperature (deg. C) Temperature (deg. C)
1251007550250-25-55
RISE
FALL
RISE
FALL
RISE
FALL
5.55.2554.754.5
0.9
1.3
1.2
1.1
1
0.9
0.8
12
8
4
0
-4
12
8
4
0
-4
1.3
1.2
1.1
1
0.9
0.8
0.9
1
1.1
1.2
0.95
1
1.05
1.1
Normalized TcoNormalized Tco
0.9
0.95
1
1.05
1.1
Normalized TNormalized T su
0.9
0.95
1
1.05
1.1
5.55.2554.754.5 5.55.2554.754.5
GAL22V10D-4/-5/-7/-10L (PLCC): Typical AC and DC Characteristic Diagrams
ALL DEVICES
DISCONTINUED
Specifications GAL22V10
16
Vol vs Iol
0
0.2
0.4
0.6
0 5 10 15 20 25 30 35 40
Iol (mA)
Vol (V)
Voh vs Ioh
0
1
2
3
4
0 5 10 15 20 25 30 35 40 45 50 55 60
Ioh(mA)
Voh (V)
Voh vs Ioh
3.15
3.25
3.35
3.45
3.55
3.65
3.75
3.85
3.95
0.00 1.00 2.00 3.00 4.00 5.00
Ioh(mA)
Voh (V)
Normalized Icc vs Vcc
0.8
0.9
1
1.1
1.2
4.5 4.75 5 5.25 5.5
Supply Voltage (V)
Normalized Icc
Normalized Icc vs Temp
0.7
0.8
0.9
1
1.1
1.2
1.3
-55 -25 0 25 50 88 100 125
Temperature (deg. C)
Normalized Icc
Normalized Icc vs Freq
0.95
1
1.05
1.1
1.15
1.2
1 15255075100
Frequency (MHz)
Normalized Icc
Input Clamp (Vik)
Vik (V)
Iik (mA)
Delta Icc vs Vin (1 input)
6
5
4
3
2
1
0
0 0.5 1 1.5 2 2.5 3 3.5 4 4.5 5 -3
100
80
60
40
20
0
-2.5 -2 -1.5 -1 -0.5 1
Vin (V)
Delta Icc (mA)
GAL22V10D-4/-5/-7/-10L (PLCC): Typical AC and DC Characteristic Diagrams
ALL DEVICES
DISCONTINUED
Specifications GAL22V10
17
GAL22V10D-7/10L (PDIP): Typical AC and DC Characteristic Diagrams
Normalized Tpd vs Vcc
0.9
0.95
1
1.05
1.1
4.5 4.75 5 5.25 5.5
Supply Voltage (V)
Normalized Tpd
RISE
FALL
Normalized Tco vs Vcc
0.95
1
1.05
1.1
4.5 4.75 5 5.25 5.5
Supply Voltage (V)
Normalized Tco
RISE
FALL
Normalized Tsu vs Vcc
0.8
0.9
1
1.1
1.2
4.5 4.75 5 5.25 5.5
Supply Voltage (V)
Normalized Tsu
RISE
FALL
Normalized Tpd vs Temp
0.8
0.9
1
1.1
1.2
1.3
-55 -25 0 25 50 75 100 125
Temperature (deg. C)
Normalized Tpd
RISE
FALL
Normalized Tsu vs Temp
0.8
0.9
1
1.1
1.2
1.3
-55 -25 0 25 50 75 100 125
Temperature (deg. C)
Normalized Tsu
RISE
FALL
Normalized Tco vs Temp
0.8
0.9
1
1.1
1.2
-55 -25 0 25 50 75 100 125
Temperature (deg. C)
Normalized Tco
RISE
FALL
Delta Tpd vs # of Outputs
Switching
-1.1
-1
-0.9
-0.8
-0.7
-0.6
-0.5
-0.4
-0.3
-0.2
-0.1
0
12345678910
Number of Outputs Switching
Delta Tpd (ns)
RISE
FALL
Delta Tco vs # of Outputs
Switching
-1.1
-1
-0.9
-0.8
-0.7
-0.6
-0.5
-0.4
-0.3
-0.2
-0.1
0
12345678910
Number of Outputs Switching
Delta Tco (ns)
RISE
FALL
Delta Tpd vs Output Loading
-4
0
4
8
12
0 50 100 150 200 250 300
Output Loading (pF)
Delta Tpd (ns)
RISE
FALL
Delta Tco vs Output Loading
-4
0
4
8
12
0 50 100 150 200 250 300
Output Loading (pF)
Delta Tco (ns)
RISE
FALL
ALL DEVICES
DISCONTINUED
Specifications GAL22V10
18
GAL22V10D-7/10L (PDIP): Typical AC and DC Characteristic Diagrams
Vol vs Iol
0
0.1
0.2
0.3
0.4
0.5
0 5 10 15 20 25 30
Iol (mA)
Vol (V)
Voh vs Ioh
0
1
2
3
4
0 5 10 15 20 25 30 35 40
Ioh (mA)
Voh (V)
Voh vs Ioh
2.8
2.9
3
3.1
3.2
3.3
3.4
3.5
3.6
3.7
3.8
0.00 1.00 2.00 3.00 4.00 5.00
Ioh (mA)
Voh (V)
Normalized Icc vs Vcc
0.85
0.9
0.95
1
1.05
1.1
1.15
4.5 4.75 5 5.25 5.5
Supply Voltage (V)
Normalized Icc
Normalized Icc vs Temp
0.7
0.8
0.9
1
1.1
1.2
1.3
-55 0 25 100
Temperature (deg. C)
Normalized Icc
Normalized Icc vs Freq
0.95
1
1.05
1.1
1.15
1.2
1 15255075100
Frequency (MHz)
Normalized Icc
Input Clamp (Vik)
0
10
20
30
40
50
60
70
80
90
100
-2.5 -2 -1.5 -1 -0.5 0
Vik (V)
Iik (mA)
Delta Isb vs Vin (1 input)
0
1
2
3
4
5
6
7
8
9
10
0 0.5 1 1.5 2 2.5 3 3.5 4 4.5 5
Vin (V)
Delta Icc (mA)
ALL DEVICES
DISCONTINUED
Specifications GAL22V10
19
Normalized Tpd vs Vcc
0.9
0.95
1
1.05
1.1
4.5 4.75 5 5.25 5.5
Supply Voltage (V)
Normalized Tpd
RISE
FALL
Normalized Tco vs Vcc
0.9
0.95
1
1.05
1.1
1.15
4.5 4.75 5 5.25 5.5
Supply Voltage (V)
Normalized Tco
RISE
FALL
Normalized Tsu vs Vcc
0.8
0.9
1
1.1
1.2
4.5 4.75 5 5.25 5.5
Supply Voltage (V)
Normalized Tsu
RISE
FALL
Normalized Tpd vs Temp
0.8
0.9
1
1.1
1.2
1.3
-55 -25 0 25 50 75 100 125
Temperature (deg. C)
Normalized Tpd
RISE
FALL
Normalized Tsu vs Temp
0.75
0.85
0.95
1.05
1.15
1.25
1.35
1.45
-55 -25 0 25 50 75 100 125
Temperature (deg. C)
Normalized Tsu
RISE
FALL
Normalized Tco vs Temp
0.8
0.9
1
1.1
1.2
1.3
-55 -25 0 25 50 75 100 125
Temperature (deg. C)
Normalized Tco
RISE
FALL
Delta Tpd vs # of Outputs
Switching
-1.2
-0.8
-0.4
0
12345678910
Number of Outputs Switching
Delta Tpd (ns)
RISE
FALL
Delta Tco vs # of Outputs
Switching
-1.2
-0.8
-0.4
0
12345678910
Number of Outputs Switching
Delta Tco (ns)
RISE
FALL
Delta Tpd vs Output Loading
-8
-4
0
4
8
12
16
20
0 50 100 150 200 250 300
Output Loading (pF)
Delta Tpd (ns)
RISE
FALL
Delta Tco vs Output Loading
-4
0
4
8
12
16
20
0 50 100 150 200 250 300
Output Loading (pF)
Delta Tco (ns)
RISE
FALL
GAL22V10D-10Q and Slower (L & Q): Typical AC and DC Characteristic Diagrams
ALL DEVICES
DISCONTINUED
Specifications GAL22V10
20
Vol vs Iol
0
0.2
0.4
0.6
0 5 10 15 20 25 30 35 40
Iol (mA)
Vol (V)
Voh vs Ioh
0
0.5
1
1.5
2
2.5
3
3.5
4
4.5
0204060
Ioh (mA)
Voh (V)
Voh vs Ioh
2.5
3
3.5
4
4.5
0.00 1.00 2.00 3.00 4.00 5.00
Ioh (mA)
Voh (V)
Normalized Icc vs Vcc
0.8
0.9
1
1.1
1.2
4.5 4.75 5 5.25 5.5
Supply Voltage (V)
Normalized Icc
Normalized Icc vs Temp
0.75
0.85
0.95
1.05
1.15
1.25
1.35
-55 -25 0 25 50 88 100 125
Temperature (deg. C)
Normalized Icc
Normalized Icc vs Freq
0.9
1
1.1
1.2
1.3
1.4
1 15255075100
Frequency (MHz)
Normalized Icc
Input Clamp (Vik)
0
10
20
30
40
50
60
70
80
90
-2.5 -2 -1.5 -1 -0.5 0
Vik (V)
Iik (mA)
Delta Icc vs Vin (1 input)
0
1
2
3
4
5
6
7
0 0.5 1 1.5 2 2.5 3 3.5 4 4.5 5
Vin (V)
Delta Icc (mA)
GAL22V10D-10Q and Slower (L & Q): Typical AC and DC Characteristic Diagrams
ALL DEVICES
DISCONTINUED
Specifications GAL22V10
21
Notes
Revision History
Date Version Change Summary
- 22v10_08 Previous Lattice release.
August 2004 22v10_09 Added lead-free package options.
July 2006 22v10_10 Corrected SOIC pin configuration diagram. Pin 13.
August 2006 22v10_11 Updated for lead-free package options.
December 2006 22v10_12 Corrected Icc in the Ordering Part Number section on pages 2-3.
ALL DEVICES
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