FEMTOCLOCKS™ CRYSTAL-TO-HCSL
CLOCK GENERATOR
ICS841608I
IDT™ / ICS™ HCSL CLOCK GENERATOR 1 ICS841608AKI REV. A JUNE 18, 2008
GENERAL DESCRIPTION
The ICS841608I is an optimized PCIe and sRIO
clock generator and member of the HiPerClocks™
family of high-performance clock solutions from IDT.
The device uses a 25MHz parallel crystal to
generate 100MHz and 125MHz clock signals,
replacing solutions requiring multiple oscillator and fanout buffer
solutions. The device has excellent phase jitter (<1ps rms)
suitable for clock components requiring precise and low-jitter
PCIe or sRIO or both clock signals. Designed for telecom,
networking and industrial applications, the ICS841608I can also
drive the high-speed sRIO and PCIe SerDes clock inputs of
communication processors, DSPs, switches and bridges.
FEATURES
• Eight HCSL outputs: configurable for PCIe (100MHz)
and sRIO (125MHz) clock signals
• Selectable crystal oscillator interface, 25MHz,
18pF parallel resonant crystal or LVCMOS/LVTTL
single-ended reference clock input
• Supports the following output frequencies:
100MHz or 125MHz
• VCO: 500MHz
• PLL bypass and output enable
• PCI Express (2.5Gb/s) and Gen 2 (5 Gb/s) jitter compliant
• RMS phase jitter @125MHz, using a 25MHz crystal
(1.875MHz – 20MHz): 0.37ps (typical)
• Full 3.3V power supply mode
• -40°C to 85°C ambient operating temperature
• Available in both standard and (RoHs 5) lead-free (RoHS 6)
packages
HiPerClockS™
ICS
BLOCK DIAGRAM PIN ASSIGNMENT
0
1
1
0
M = ÷20
÷N
÷4
÷5
(default)
OSC
FemtoClock
PLL
VCO = 500MHz
XTAL_IN
XTAL_OUT
REF_SEL
FSEL
MR/nOE
IREF
BYPASS
REF_IN
Pulldown
Pulldown
Pulldown
Pulldown
Pulldown
Q0
nQ0
Q1
nQ1
Q2
nQ2
Q3
nQ3
Q4
nQ4
Q5
nQ5
Q6
nQ6
Q7
nQ7
32 31 30 29 28 27 26 25
9 10 11 12 13 14 15 16
1
2
3
4
5
6
7
8
24
23
22
21
20
19
18
17
XTAL_IN
XTAL_OUT
MR/nOE
VDD
Q0
nQ0
Q1
nQ1
nQ4
Q4
VDD
nQ3
Q3
nQ2
Q2
GND
FSEL
IREF
BYPASS
VDDA
REF_SEL
REF_IN
VDD
GND
VDD
nQ7
Q7
nQ6
Q6
GND
nQ5
Q5
ICS841608I
32-Lead VFQFN
5mm x 5mm x 0.925mm
package body
K Package
Top View
IDT™ / ICS™ HCSL CLOCK GENERATOR 2 ICS841608AKI REV. A JUNE 18, 2008
ICS841608I
FEMTOCLOCKS™ CRYSTAL-TO-HCSL CLOCK GENERATOR
TABLE 1. PIN DESCRIPTIONS
TABLE 2. PIN CHARACTERISTICS
lobmySretemaraPsnoitidnoCtseTmuminiMlacipyTmumixaMstinU
C
NI
ecnaticapaCtupnI 4Fp
R
NWODLLUP
rotsiseRnwodlluPtupnI 15kΩ
rebmuNemaNepyTnoitpircseD
2,1 ,NI_LATX
TUO_LATX tupnI ,tuptuoehtsiTUO_LATX.ecafretnilatsyrctnanoserlellaraP
.t
upniehtsiNI_LATX
3EOn/RMtupnInwodlluP
eht,HGIHcigolnehW.elbanetuptuoWOLevitcA.teserretsamHGIHevitcA
.)Z-iH(
ecnadepmihgihnierastuptuoehtdnatesererasredividlanretni
.delbaneerastuptuoehtdnasredividlanretnieht,WO
LcigolnehW
.C3elbaTeeS.slevelecafretniLTTVL/SOMCVL.noitcnufsuonorhcnysA
,41,4
13,42 V
DD
rewoP.snipylppuseroC
6,50Qn,0QtuptuO.slevelecafretniLSCH.riaptuptuolaitnereffiD
8,71Qn,1QtuptuO.slevelecafretn
iLSCH.riaptuptuolaitnereffiD
23,91,9DNGrewoP.dnuorgylppusrewoP
11,012Qn,2QtuptuO.slevelecafretniLSCH.riaptupt
uolaitnereffiD
31,213Qn,3QtuptuO.slevelecafretniLSCH.riaptuptuolaitnereffiD
61,514Qn,4QtuptuO.slevelecafretni
LSCH.riaptuptuolaitnereffiD
81,715Qn,5QtuptuO.slevelecafretniLSCH.riaptuptuolaitnereffiD
12,026Qn,6QtuptuO.sl
evelecafretniLSCH.riaptuptuolaitnereffiD
32,227Qn,7QtuptuO.slevelecafretniLSCH.riaptuptuolaitnereffiD
52LES
FtupnInwodlluP .A3elbaTeeS.slevelecafretniLTTVL/SOMCVL.niptcelesycneuqerftuptuO
62FERItuptuO
rotsisernoisice
rpdexiflanretxenA.tuptuorotsiserecnerefertnerrucLSCH
574( Ωrofdesutnerrucecnereferasedivorpdnuorgotnips
ihtmorf)
.stuptuokcolcxQn/xQedom-tnerruclaitnereffid
72SSAPYBtupnInwodlluP .noitcnufsuonorhcnysA.noitarepos
sapybLLP/noitarepoLLPstceleS
.B3elbaTeeS.slevelecafretniLTTVL/SOMCVL
82V
ADD
rewoP.nipylppusgolanA
92LES_FERtupnInwodlluP .D3elbaTeeS.ecruosecnerefertupniehtstceleS.tcelesecnerefeR
.sle
velecafretniLTTVL/SOMCVL
03NI_FERtupnInwodlluP.tupnikcolcecnereferLLPLTTVL/SOMCVL
:ETON
nwodlluP
.seulavlacipytrof,scitsiretcarahCniP,2elbaTeeS.srotsisertupnilanretniotsrefer
TABLE 3D. REF_SEL FUNCTION TABLETABLE 3C. MR/nOE FUNCTION TABLE
TABLE 3B. BYPASS FUNCTION TABLE
tupnI
LES_FERecnerefeRtupnI
0)tluafed(LATX
1NI_FER
tupnI
EOn/RMnoitcnuF
0)tluafed(delbanestuptuO
1)ecnadepmi-hgih(delbasidstuptuo,tesereciveD
TABLE 3A. FSEL FUNCTION TABLE (fREF = 25MHZ)
tupnIstuptuO
LESFN 7:0Qn/7:0Q
05 )tluafed(eICP)zHM001(5/OCV
14 OIRs)zHM521(4/OCV
tupnI
SSAPYBnoitarugifnoCLLP
0)tluafed(delbaneLLP
1f(dessapybLLP
TUO
f=
FER
)N÷
IDT™ / ICS™ HCSL CLOCK GENERATOR 3 ICS841608AKI REV. A JUNE 18, 2008
ICS841608I
FEMTOCLOCKS™ CRYSTAL-TO-HCSL CLOCK GENERATOR
ABSOLUTE MAXIMUM RATINGS
Supply Voltage, V
DD 4.6V
Inputs, VI-0.5V to VDD + 0.5V
Outputs, VO-0.5V to VDD + 0.5V
Package Thermal Impedance, θJA 37°C/W (0 mps)
Storage Temperature, T
STG -65°C to 150°C
NOTE: Stresses beyond those listed under Absolute
Maximum Ratings may cause permanent damage to the
device. These ratings are stress specifications only. Functional op-
eration of product at these conditions or any conditions beyond
those listed in the
DC Characteristics
or
AC Characteristics
is not
implied. Exposure to absolute maximum rating conditions for ex-
tended periods may affect product reliability.
TABLE 5. CRYSTAL CHARACTERISTICS
retemaraPsnoitidnoCtseTmuminiMlacipyTmumixaMstinU
noitallicsOfoedoM latnemadnuF
ycneuqerF 52zHM
)RSE(ecnatsiseRs
eireStnelaviuqE 05 Ω
ecnaticapaCtnuhS 7Fp
.latsyrctnanoserlellarapFp81nagnisudeziretcarahC:ETON
TABLE 4A. POWER SUPPLY DC CHARACTERISTICS, VDD = 3.3V±5%, TA = -40°C TO 85°C
TABLE 4B. LVCMOS / LVTTL DC CHARACTERISTICS, VDD = 3.3V±5%, TA = -40°C TO 85°C
lobmySretemaraPsnoitidnoCtseTmuminiMlacipyTmumixaMstinU
V
HI
egatloVhgiHtupnI 2V
DD
3.0+V
V
LI
egatloVwoLtupnI 3.0-8.0V
I
HI
tnerruChgiHtupnI
,LES_FER,NI_FER
,EOn/RM,SSAPYB
LESF
V
DD
V=
NI
V564.3=051Aµ
I
LI
tnerruCwoLtupnI
,LES_FER,NI_FER
,EOn/RM,SSAPYB
LESF
V
DD
V,V564.3=
NI
V0=5-Aµ
lobmySretemaraPsnoitidnoCtseTmuminiMlacipyTmumixaMstinU
V
DD
egatloVylppuSeroC 531.33.3564.3V
V
ADD
egatloVylppuSgolanAV
DD
51.0–3.3V
DD
V
V
ODD
egatloVylppuStuptuO 531.33.3564.3V
I
DD
tnerruCylppuSrewoP 78Am
I
ADD
tnerruCylppuSgolanA 51Am
IDT™ / ICS™ HCSL CLOCK GENERATOR 4 ICS841608AKI REV. A JUNE 18, 2008
ICS841608I
FEMTOCLOCKS™ CRYSTAL-TO-HCSL CLOCK GENERATOR
TABLE 6. AC CHARACTERISTICS, VDD = 3.3V±5%, TA = -40°C TO 85°C
lobmySretemaraPsnoitidnoCtseTmuminiMlacipyTmumixaMstinU
f
XAM
ycneuqerFtuptuO 5/OCV001zHM
4/OCV521zHM
t
)Ø(tij1ETON;)modnaR(rettiJesahPSMR )zHM02-zHM578.1(,zHM00193.0sp
)zHM02-zHM578.1(,zHM52173.0sp
T
j
2ETON;kaeP-ot-kaePrettiJesahP
,)zHM05–zHM2.1(,zHM001
01
6
tupnilatsyrczHM52,selpmas 63.42sp
,)zHM5.26–zHM2.1(,zHM521
01
6
tupnilatsyrczHM52,selpmas 67.32sp
T
SMR_FH_KLCFER
3ETON;SMRrettiJesahP
01,zHM001
6
,selpmas
tupnilatsyrczHM52 44.2 sp
smr
01,zHM521
6
,selpmas
tupnilatsyrczHM52 73.2 sp
smr
t
)cc(tij4ETON;rettiJelcyC-ot-elcyC 05sp
t
)o(ks5,4ETON;wekStuptuO 501sp
egdEesiR
etaR 7,6ETON;etaRegdEgnisiR 6.04sn/V
etaRegdEllaF7,6ETON;etaRegdEgnillaF 6
.04sn/V
V
BR
8,6ETON;egatloVkcabgniR 001-001Vm
V
XAM
01,9ETON;egatloVtuptuO.xaMetulosbA 0511Vm
V
NIM
11,9ETON;egatloVtuptuO.niMetulosbA 003-Vm
V
SSORC
;egatloVgnissorCetulosbA
31,21,9ETON 052055Vm
ΔV
SSORC
VfonoitairaVlatoT
ssorC
;segdellarevo
41,21,9ETON 041Vm
cdo51,6ETON;elcyCytuDtuptuO 8425%
T
ELBATS
8,6ETON;tuptuOkcolCelbatSpu-rewoP 005sp
t
L
emiTkcoLLLP 09sm
.zHM521dnazHM001tanekaterasnoitacificepsllA:ETON
.tolPesioNesahPehtotreferesaelP:1ETON
,etoNnoitacilppA
TDIeeS.noitcnufrefsnartmetsysgniylpparetfarettijSMR:2ETON
.stnemeriuqeRkcolCecnerefeRsserpxEICP
mumixaM
.kaep-ot-kaepsp68sisserpxEICProftimil
.zHM61-5dnazHM61-8era2neGeICProf2Hdna1Hrofseicneuqerfelop
ehT.noitcnufrefsnartmetsysgniylpparetfarettijSMR:3ETON
,etoNnoitacilppATDIeeS
.stnemeriuqeRkcolCecnerefeRsserpxEICP
.smrsp1.3si2noitareneGsserpxEICProftimilmumixaM
.56dradnatSCEDEJhtiwecnadroccanidenifedsiretemarapsihT
:4ETON
.snoitidnocdaollauqehtiwdnaegatlovylppusemasehttastuptuoneewtebwekssadenifeD:5ETON
.stniopssorcl
aitnereffidtuptuoehttaderusaeM
.mrofevawlaitnereffidmorfnekattnemerusaeM:6ETON
.)xQnsunimxQmorfdevired(
mrofevawlaitnereffidehtnoVm051+otVm051-morftnemerusaeM:7ETON
ehtnoderetnecsiwodniwtnemerusaemVm003ehT.
emitllafdnaesirrofnoigertnemerusaemehthguorhtcinotonomebtsumlangisehT
.noitceSnoitamrofnItnemerusaeMre
temaraPeeS.gnissorcorezlaitnereffid
T:8ETON
ELBATS
sitierofebsegdegnillaf/gnisirretfaegatlovlaitnereffidVm051±muminimaniatniamtsumkcolclaitnereffidehtemitehtsi
Vehtotnikcabpordotdewolla
BR
.noitceSnoitamrofnItnemerusaeMretemaraPeeS.egnarlaitnereffid001±
.mrofevawdedneelgnismorfnekattnemerus
aeM:9ETON
.noitceSnoitamrofnItnemerusaeMretemaraPeeS.toohsrevognidulcniegatlovsuoenatnatsnimumixamehts
adenifeD:01ETON
.noitceSnoitamrofnItnemerusaeMretemaraPeeS.toohsrednugnidulcniegatlovsuoenatnatsnimumi
nimehtsadenifeD:11ETON
.xQnfoegdegnillafehtslauqexQfoegdegnisirehtfoeulavegatlovsuoenatnatsniehterehwt
niopgnissorctaderusaeM:21ETON
.noitceSnoitamrofnItnemerusaeMretemaraPeeS
.gnissorcsiegdehcihwfosseldrag
er,tsehgihehtottniopgnissorctsewolehtmorfnoitairavlatotehtotsrefeR:31ETON
.noitceSnoitamrofnItnemerusa
eMretemaraPeeS.tnemerusaemsihtrofstniopgnissorcllaotsrefeR
VehtniecnairavdewollamumixamehtsisihT.xQngn
illafdnaxQgnisirfoegatlovgnissorcllafonoitairavlatotehtsadenifeD:41ETON
SSORC
.noitceSnoitamrofnItnemerusaeMretemaraPeeS.metsysralucitrapynarof
.%05ebtsumelcycytudtupnI:51ETON
IDT™ / ICS™ HCSL CLOCK GENERATOR 5 ICS841608AKI REV. A JUNE 18, 2008
ICS841608I
FEMTOCLOCKS™ CRYSTAL-TO-HCSL CLOCK GENERATOR
TYPICAL PHASE NOISE AT 100MHZ
100MHz
RMS Phase Jitter (Random)
1.875MHz to 20MHz = 0.39ps (typical)
OFFSET FREQUENCY (HZ)
NOISE POWER dBc
Hz
➤
➤
➤
125MHz
RMS Phase Jitter (Random)
1.875MHz to 20MHz = 0.37ps (typical)
OFFSET FREQUENCY (HZ)
NOISE POWER dBc
Hz
TYPICAL PHASE NOISE AT 125MHZ
Filter
Raw Phase Noise Data
Phase Noise Result by adding
Filter to raw data
➤
➤
➤
Filter
Raw Phase Noise Data
Phase Noise Result by adding
Filter to raw data
IDT™ / ICS™ HCSL CLOCK GENERATOR 6 ICS841608AKI REV. A JUNE 18, 2008
ICS841608I
FEMTOCLOCKS™ CRYSTAL-TO-HCSL CLOCK GENERATOR
PARAMETER MEASUREMENT INFORMATION
OUTPUT SKEW
3.3V HCSL OUTPUT LOAD AC TEST CIRCUIT3.3V HCSL OUTPUT LOAD AC TEST CIRCUIT
RMS PHASE JITTER
Phase Noise Mas
k
Offset Frequency
f
1
f
2
Phase Noise Plot
RMS Jitter = Area Under the Masked Phase Noise Plot
Noise Power
tsk(o)
Qy
Qx
nQy
nQx
DIFFERENTIAL MEASUREMENT POINTS FOR RISE/FALL TIME
475Ω
Measurement
Point
33Ω100Ω
100Ω
33Ω
Measurement
Point
49.9Ω
49.9Ω
HCSL
GND
2pF
2pF
0V
IREF
3.3V±5%
VDD
3.3V±5%,
VDDA
DIFFERENTIAL MEASUREMENT POINTS FOR RINGBACK
Q - nQ
-150mV
+150mV
0.0V
Fall Edge RateRise Edge Rate
TSTABLE
TSTABLE
VRB
VRB
Q - nQ
-150mV
V
RB
= -100mV
V
RB
= +100mV
+150mV
0.0V
This load condition is used for IDD,
t
sk(o), and
t
jit measurements.
475Ω
50Ω
50Ω
HCSL
GND
0V
SCOPE
IREF
3.3V±5%
VDD
3.3V±5%,
VDDA
IDT™ / ICS™ HCSL CLOCK GENERATOR 7 ICS841608AKI REV. A JUNE 18, 2008
ICS841608I
FEMTOCLOCKS™ CRYSTAL-TO-HCSL CLOCK GENERATOR
PARAMETER MEASUREMENT INFORMATION, CONTINUED
DIFFERENTIAL MESUREMENT POINTS FOR DUTY CYCLE PERIOD
SINGLE-ENDED MEASUREMENT POINTS FOR
ABSOLUTE CROSS POINT/SWING
SINGLE-ENDED MEASUREMENT POINTS FOR DELTA CROSS POINT
nQ
Q
V
CROSS_MAX
= 550mV
V
CROSS_MIN
= 250mV
V
MAX
= 1.15V
V
MIN
= -0.30V
Q
nQ
V
CROSS_DELTA
= 140mV
Clock Period (Differential)
Positive Duty
Cycle (Differential)
Negative Duty
Cycle (Differential)
Q - nQ
0.0V
COMPOSITE PCIe TRANSFER FUNCTION
20
-20
-40
-60
-80
-100
0
10
4
10
5
10
6
10
7
10
8
-3dB
1.2MHz
-3dB
21.9MHz
Frequency (Hz)
Mag (dB)
H3(s) * (H1(s) – H2(s))
IDT™ / ICS™ HCSL CLOCK GENERATOR 8 ICS841608AKI REV. A JUNE 18, 2008
ICS841608I
FEMTOCLOCKS™ CRYSTAL-TO-HCSL CLOCK GENERATOR
APPLICATION INFORMATION
As in any high speed analog circuitry, the power supply pins
are vulnerable to random noise. To achieve optimum jitter
performance, power supply isolation is required. The ICS841608I
provides separate power supplies to isolate any high switching
noise from the outputs to the internal PLL. VDD and VDDA should
be individually connected to the power supply plane through
vias, and 0.01µF bypass capacitors should be used for each
pin.
Figure 1
illustrates this for a generic VDD pin and also shows
that VDDA requires that an additional10Ω resistor along with a
10µF bypass capacitor be connected to the VDDA pin.
POWER SUPPLY FILTERING T ECHNIQUES
FIGURE 1. POWER SUPPLY FILTERING
10Ω
VDDA
10μF
.01μF
3.3V
.01μF
VDD
FIGURE 2. P.C.ASSEMBLY FOR EXPOSED PAD T HERMAL RELEASE PATH –SIDE VIEW (DRAWING NOT TO SCALE)
VFQFN EPAD THERMAL RELEASE PAT H
In order to maximize both the removal of heat from the package
and the electrical performance, a land pattern must be
incorporated on the Printed Circuit Board (PCB) within the footprint
of the package corresponding to the exposed metal pad or
exposed heat slug on the package, as shown in
Figure 2.
The
solderable area on the PCB, as defined by the solder mask, should
be at least the same size/shape as the exposed pad/slug area on
the package to maximize the thermal/electrical performance.
Sufficient clearance should be designed on the PCB between the
outer edges of the land pattern and the inner edges of pad pattern
for the leads to avoid any shorts.
While the land pattern on the PCB provides a means of heat
transfer and electrical grounding from the package to the board
through a solder joint, thermal vias are necessary to effectively
conduct from the surface of the PCB to the ground plane(s). The
land pattern must be connected to ground through these vias.
The vias act as “heat pipes”. The number of vias (i.e. “heat pipes”)
are application specific and dependent upon the package power
dissipation as well as electrical conductivity requirements. Thus,
thermal and electrical analysis and/or testing are recommended
to determine the minimum number needed. Maximum thermal
and electrical performance is achieved when an array of vias is
incorporated in the land pattern. It is recommended to use as
many vias connected to ground as possible. It is also
recommended that the via diameter should be 12 to 13mils (0.30
to 0.33mm) with 1oz copper via barrel plating. This is desirable to
avoid any solder wicking inside the via during the soldering process
which may result in voids in solder between the exposed pad/
slug and the thermal land. Precautions should be taken to
eliminate any solder voids between the exposed heat slug and
the land pattern. Note: These recommendations are to be used
as a guideline only. For further information, refer to the Application
Note on the
Surface Mount Assembly
of Amkor’s Thermally/
Electrically Enhance Leadfame Base Package, Amkor Technology.
THERMAL VIA
LAND PATTERN
SOLDER PIN
SOLDER
PIN PADPIN PAD
PIN
GROUN D PLANE
EXPOSED HEAT SLUG
(GROUND PAD)
IDT™ / ICS™ HCSL CLOCK GENERATOR 9 ICS841608AKI REV. A JUNE 18, 2008
ICS841608I
FEMTOCLOCKS™ CRYSTAL-TO-HCSL CLOCK GENERATOR
LVCMOS TO XTAL INTERFACE
The XTAL_IN input can accept a single-ended LVCMOS
signal through an AC couple capacitor. A general interface
diagram is shown in
Figure 3.
The XTAL_OUT pin can be left
floating. The input edge rate can be as slow as 10ns. For
LVCMOS inputs, it is recommended that the amplitude be
reduced from full swing to half swing in order to prevent signal
interference with the power rail and to reduce noise. This
configuration requires that the output impedance of the driver
(Ro) plus the series resistance (Rs) equals the transmission
line impedance. In addition, matched termination at the crystal
input will attenuate the signal in half. This can be done in one of
two ways. First, R1 and R2 in parallel should equal the
transmission line impedance. For most 50Ω applications, R1
and R2 can be 100Ω. This can also be accomplished by remov-
ing R1 and making R2 50Ω.
FIGURE 3. GENERAL DIAGRAM FOR LVCMOS DRIVER TO XTAL INPUT INTERFACE
XTA L_I N
XTA L_O U T
VCC
R2
Ro
R1
Zo = 50
Rs
VCC
.1uf
VDD VDD
Zo = Ro + Rs
CRYSTAL INPUT INTERFACE
The ICS841608I has been characterized with 18pF parallel
resonant crystals. The capacitor values shown in
Figure 4
below
FIGURE 4. CRYSTAL INPUt INTERFACE
were determined using a 25MHz, 18pF parallel resonant crystal
and were chosen to minimize the ppm error.
C1
27p
X1
18pF Parallel Crystal
C2
27p
XTAL_OUT
XTAL_IN
IDT™ / ICS™ HCSL CLOCK GENERATOR 10 ICS841608AKI REV. A JUNE 18, 2008
ICS841608I
FEMTOCLOCKS™ CRYSTAL-TO-HCSL CLOCK GENERATOR
FIGURE 5. ICS841608I SCHEMATIC EXAMPLE
SCHEMATIC EXAMPLE
Figure 5
shows an example of ICS841608I application
schematic. In this example, the device is operated at VDD = 3.3V.
The 18pF parallel resonant 25MHz crystal is used. The C1 =
27pF and C2 = 27pF are recommended for frequency accuracy.
For different board layout, the C1 and C2 may be slightly
adjusted for optimizing frequency accuracy. Two examples of
HCSL terminations are shown in this schematic. The decoupling
capacitors should be located as close as possible to the power
pin.
INPUTS:
CRYSTAL INPUTS
For applications not requiring the use of the crystal oscillator input,
both XTAL_IN and XTAL_OUT can be left floating. Though not
required, but for additional protection, a 1kΩ resistor can be tied
from XTAL_IN to ground.
REF_IN INPUT
For applications not requiring the use of the reference clock,
it can be left floating. Though not required, but for additional
protection, a 1kΩ resistor can be tied from the REF_IN to ground.
LVCMOS CONTROL PINS
All control pins have internal pulldowns; additional resistance is
not required but can be added for additional protection. A 1kΩ
resistor can be used.
RECOMMENDATIONS FOR UNUSED INPUT AND OUTPUT PINS
OUTPUTS:
HCSL OUTPUTs
All unused HCSL outputs can be left floating. We recommend
that there is no trace attached. Both sides of the differential output
pair should either be left floating or terminated.
C3
0.1u
+
-
R8
50
VD D
X1
25MHz
TL4
Zo = 50
VD D
Set Logic
Input to
'0'
RD2
1K
TL3
Zo = 50
To Logic
Input
pins
C1
27pF U1
ICS841608I
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
32
31
30
29
28
27
26
25
XTA L _ I N
XTA L _ O U T
MR/nOE
VDD
Q0
nQ0
Q1
nQ1
GND
Q2
nQ2
Q3
nQ3
VDD
Q4
nQ4
Q5
nQ5
GND
Q6
nQ6
Q7
nQ7
VDD
GND
VDD
REF_IN
REF_SEL
VD D A
BYPASS
IREF
FSEL
+
-
R6
50
MR / n O E
FSEL
Recommended for PCI
Express Point-to-Point
Connec tion
VDD=3.3V
VDD
Set Logic
Input to
'1'
REF_SEL
R4 33
VDD
RD1
Not Install
R1
10
R7
50
VDD
VD D
VD D A
C2
27pF
(U1:6)
RU1
1K
Logic Control Input Examples
(U1:14)
VDD
TL2
Zo = 50
To Logic
Input
pins
VDD
C7
.1uf
VD D
TL1
Zo = 50
18pF
VDD
R3 33
(U1:31)
R5
50
BYPASS
Recommended for
PCI Express Add-In
Card
VD D
RU2
Not Install
C6
.1uf
C8
.1uf
C4
10u
C5
0.1u
HCSL Termination
(U1:24)
R2
475
VDD
IDT™ / ICS™ HCSL CLOCK GENERATOR 11 ICS841608AKI REV. A JUNE 18, 2008
ICS841608I
FEMTOCLOCKS™ CRYSTAL-TO-HCSL CLOCK GENERATOR
RECOMMENDED T ERMINATION
Figure 6A
is the recommended termination for applications
which require the receiver and driver to be on a separate PCB.
All traces should be 50Ω impedance.
FIGURE 6A. RECOMMENDED TERMINATION
Figure 6B
is the recommended termination for applications
which require a point to point connection and contain the driver
FIGURE 6B. RECOMMENDED TERMINATION
and receiver on the same PCB. All traces should all be 50Ω
impedance.
0.7V Differential HCSL
Clock Driver
0.7V Differential HCSL
Clock Driver
0.7V Differential HCSL
Add-In Card
IDT™ / ICS™ HCSL CLOCK GENERATOR 12 ICS841608AKI REV. A JUNE 18, 2008
ICS841608I
FEMTOCLOCKS™ CRYSTAL-TO-HCSL CLOCK GENERATOR
POWER CONSIDERATIONS
This section provides information on power dissipation and junction temperature for the ICS841608I.
Equations and example calculations are also provided.
1. Power Dissipation.
The total power dissipation for the ICS841608I is the sum of the core power plus the analog power plus the power dissipated in the
load(s). The following is the power dissipation for VDD = 3.3V + 5% = 3.465V, which gives worst case results.
NOTE: Please refer to Section 3 for details on calculating power dissipated in the load.
•Power (core)MAX = VDD_MAX * (IDD_MAX + IDDA_MAX) = 3.465V * (87mA + 15mA) = 353.43mW
•Power (outputs)MAX = 44.5mW/Loaded Output pair
If all outputs are loaded, the total power is 8 * 44.5mW = 356mW
Total Power_MAX (3.465V, with all outputs switching) = 353.43mW + 356mW =709.43mW
2. Junction Temperature.
Junction temperature, Tj, is the temperature at the junction of the bond wire and bond pad and directly affects the reliability of the
device. The maximum recommended junction temperature for HiPerClockSTM devices is 125°C.
The equation for Tj is as follows: Tj = θJA * Pd_total + TA
Tj = Junction Temperature
θJA = Junction-to-Ambient Thermal Resistance
Pd_total = Total Device Power Dissipation (example calculation is in Section 1 above)
TA = Ambient Temperature
In order to calculate junction temperature, the appropriate junction-to-ambient thermal resistance θJA
must be used. Assuming no air
flow and a multi-layer board, the appropriate value is 37°C/W per Table 7 below.
Therefore, Tj for an ambient temperature of 85°C with all outputs switching is:
85°C + 0.709W * 37°C/W = 111.2°C. This is well below the limit of 125°C.
This calculation is only an example. Tj will obviously vary depending on the number of loaded outputs, supply voltage, air flow,
and the type of board (single layer or multi-layer).
TABLE 7. THERMAL RESISTANCE θθ
θθ
θJA FOR 32-PIN VFQFN, FORCED CONVECTION
θθ
θθ
θJA vs. Air Flow (Meters per Second)
0 1 2.5
Multi-Layer PCB, JEDEC Standard Test Boards 37.0°C/W 32.4°C/W 29.0°C/W
IDT™ / ICS™ HCSL CLOCK GENERATOR 13 ICS841608AKI REV. A JUNE 18, 2008
ICS841608I
FEMTOCLOCKS™ CRYSTAL-TO-HCSL CLOCK GENERATOR
3. Calculations and Equations.
The purpose of this section is to calculate power dissipation on the IC per HCSL output pair.
HCSL output driver circuit and termination are shown in
Figure 7.
HCSL is a current steering output which sources a maximum of 17mA of current per output. To calculate worst case on-chip power
dissipation, use the following equations which assume a 50Ω load to ground.
The highest power dissipation occurs when VDD is HIGH.
Power = (VDD_HIGH – VOUT
) * IOUT, since VOUT = IOUT * RL
= (VDD_HIGH – IOUT *
RL) * IOUT
= (3.465V – 17mA * 50Ω) * 17mA
Total Power Dissipation per output pair = 44.5mW
FIGURE 7. HCSL DRIVER CIRCUIT AND TERMINATION
V
DD
V
OUT
R
L
50Ω
IC
➤
I
OUT = 17mA
R
REF =
475
Ω
± 1%
IDT™ / ICS™ HCSL CLOCK GENERATOR 14 ICS841608AKI REV. A JUNE 18, 2008
ICS841608I
FEMTOCLOCKS™ CRYSTAL-TO-HCSL CLOCK GENERATOR
RELIABILITY INFORMATION
TRANSISTOR COUNT
The transistor count for ICS841608I is: 2785
TABLE 8. θJAVS. AIR FLOW TABLE FOR 32 LEAD VFQFN
θθ
θθ
θJA vs. Air Flow (Meters per Second)
0 1 2.5
Multi-Layer PCB, JEDEC Standard Test Boards 37.0°C/W 32.4°C/W 29.0°C/W
IDT™ / ICS™ HCSL CLOCK GENERATOR 15 ICS841608AKI REV. A JUNE 18, 2008
ICS841608I
FEMTOCLOCKS™ CRYSTAL-TO-HCSL CLOCK GENERATOR
PACKAGE OUTLINE - K SUFFIX FOR 32 LEAD VFQFN
TABLE 9. PACKAGE DIMENSIONS
Reference Document: JEDEC Publication 95, MO-220
NOITAIRAVCEDEJ
SRETEMILLIMNISNOISNEMIDLLA
LOBMYS
2-DHHV
MUMINIMLANIMONMUMIXAM
N23
A08.0--00.1
1A 0--50.0
3A .feR52.0
b81.052.003.0
N
D
8
N
E
8
DCISAB00.5
2D 52.152.252.3
ECISAB00.5
2E 52.152.252.3
eCISAB05.0
L03.004.005.0
NOTE: The following package mechanical drawing is a generic
drawing that applies to any pin count VFQFN package. This draw-
ing is not intended to convey the actual pin count or pin layout of
this device. The pin count and pinout are shown on the front page.
The package dimensions are in Table 8 below.
IDT™ / ICS™ HCSL CLOCK GENERATOR 16 ICS841608AKI REV. A JUNE 18, 2008
ICS841608I
FEMTOCLOCKS™ CRYSTAL-TO-HCSL CLOCK GENERATOR
TABLE 10. ORDERING INFORMATION
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IKA806148IA806148SCINFQFVdaeL23yartC°58otC°04-
TIKA8
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FLIKA806148LIA80614SCINFQFV"eerF-daeL"daeL23yartC°58otC°04
-
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While the information presented herein has been checked for both accuracy and reliability, Integrated Device Technology, Incorporated (IDT) assumes no responsibility for either its use or for
infringement of any patents or other rights of third parties, which would result from its use. No other circuits, patents, or licenses are implied. This product is intended for use in normal commercial and
industrial applications. Any other applications such as those requiring high reliability or other extraordinary environmental requirements are not recommended without additional processing by IDT. IDT
reserves the right to change any circuitry or specifications without notice. IDT does not authorize or warrant any IDT product for use in life support devices or critical medical instruments.
ICS841608I
FEMTOCLOCKS™ CRYSTAL-TO-HCSL CLOCK GENERATOR
Innovate with IDT and accelerate your future networks. Contact:
www.IDT.com
For Sales
800-345-7015 (inside USA)
+408-284-8200 (outside USA)
Fax: 408-284-2775
www.IDT.com/go/contactIDT
For Tech Support
netcom@idt.com
+480-763-2056
Corporate Headquarters
Integrated Device Technology, Inc.
6024 Silver Creek Valley Road
San Jose, CA 95138
United States
800-345-7015 (inside USA)
+408-284-8200 (outside USA)
© 2008 Integrated Device Technology, Inc. All rights reserved. Product specifications subject to change without notice. IDT, the IDT logo, ICS and HiPerClockS are trademarks
of Integrated Device Technology, Inc. Accelerated Thinking is a service mark of Integrated Device Technology, Inc. All other brands, product names and marks are or may be
trademarks or registered trademarks used to identify products or services of their respective owners.
Printed in USA
