MR0A16A FEATURES * * * * * * * * * 64K x 16 MRAM Memory 3.3 Volt power supply Fast 35ns read/write cycle SRAM compatible timing Unlimited read & write endurance Commercial, Industrial, and Extended Temperatures Data non-volatile for >20 years at temperature RoHS-compliant TSOP2 and BGA packages available All products meet MSL-3 moisture sensitivity level Automotive AEC-Q100 Grade 1 option available 44-pin TSOP2 BENEFITS * * * One memory replaces FLASH, SRAM, EEPROM and BBSRAM in system for simpler, more efficient designs Improves reliability by replacing battery-backed SRAM Automatic data protection on power loss 48-ball BGA RoHS INTRODUCTION The MR0A16A is a 1,048,576-bit magnetoresistive random access memory (MRAM) device organized as 65,536 words of 16 bits. The MR0A16A offers SRAM compatible 35 ns read/write timing with unlimited endurance. Data is always non-volatile for greater than 20 years. Data is automatically protected on power loss by low-voltage inhibit circuitry to prevent writes with voltage out of specification. MR0A16A is the ideal memory solution for applications that must permanently store and retrieve critical data and programs quickly. The MR0A16B is available in a small footprint 48-pin ball grid array (BGA) package and a 44-pin thin small outline package (TSOP Type 2). These packages are compatible with similar low-power SRAM products and other nonvolatile RAM products. The MR0A16A provides highly reliable data storage over a wide range of temperatures. The product is available with commercial temperature (0 to +70 C), industrial temperature (-40 to +85 C), extended temperature (-40 to +105 C), and Automotive AEC-Q100 Grade 1 (-40 to +125) temperature range options. Copyright (c) 2018 Everspin Technologies 1 MR0A16A Rev. 8.3 3/2018 MR0A16A TABLE OF CONTENTS FEATURES..............................................................................................................................................1 BENEFITS................................................................................................................................................1 INTRODUCTION....................................................................................................................................1 BLOCK DIAGRAM AND PIN ASSIGNMENTS........................................................................................4 Figure 1 - Block Diagram............................................................................................................................................ 4 Table 1 - Pin Functions................................................................................................................................................ 4 Figure 2 - MR0A16A Package Pinouts................................................................................................................... 5 OPERATING MODES..............................................................................................................................5 Table 2 - Operating Modes........................................................................................................................................ 5 ABSOLUTE MAXIMUM RATINGS..........................................................................................................6 Table 3 - Absolute Maximum Ratings.................................................................................................................... 6 OPERATING CONDITIONS....................................................................................................................7 Table 4 - Operating Conditions................................................................................................................................ 7 Power Up and Power Down Sequencing........................................................................................8 Figure 3 - Power Up and Power Down Timing.................................................................................................. 8 DC CHARACTERISTICS..........................................................................................................................9 Table 5 - DC Characteristics....................................................................................................................................... 9 Table 6 - Power Supply Characteristics................................................................................................................. 9 TIMING SPECIFICATIONS.................................................................................................................. 10 Table 7 - Capacitance................................................................................................................................................10 Table 8 - AC Measurement Conditions...............................................................................................................10 Figure 4 - Output Load Test Low and High........................................................................................................10 Figure 5 - Output Load Test All Others................................................................................................................10 Table 9 - Read Cycle Timing....................................................................................................................................11 Figure 6 - Read Cycle 1..............................................................................................................................................12 Copyright (c) 2018 Everspin Technologies 2 MR0A16A Rev. 8.3 3/2018 MR0A16A TABLE OF CONTENTS - continued Figure 7 - Read Cycle 2..............................................................................................................................................12 Table 10 - Write Cycle Timing 1 (W Controlled) ...............................................................................................13 Figure 8 - Write Cycle Timing 1 (W Controlled)................................................................................................14 Table 11 - Write Cycle Timing 2 (E Controlled)................................................................................................15 Figure 9 - Write Cycle Timing 2 (E Controlled).................................................................................................15 Table 12 - Write Cycle Timing 3 (LB/UB Controlled)......................................................................................16 Figure 10 - Write Cycle Timing 3 (UB/LB Controlled)....................................................................................16 ORDERING INFORMATION................................................................................................................ 17 Table 13 - Part Numbering System.......................................................................................................................17 Table 14 - MR0A16A Ordering Part Numbers...................................................................................................18 PACKAGE OUTLINE DRAWINGS........................................................................................................ 19 Figure 11 - 44-pin TSOP2..........................................................................................................................................19 Figure 12 - 48-ball FBGA...........................................................................................................................................20 REVISION HISTORY............................................................................................................................ 21 HOW TO CONTACT US........................................................................................................................ 22 Copyright (c) 2018 Everspin Technologies 3 MR0A16A Rev. 8.3 3/2018 MR0A16A BLOCK DIAGRAM AND PIN ASSIGNMENTS Figure 1 - Block Diagram OUTPUT ENABLE BUFFER G A[15:0] UPPER BYTE OUTPUT ENABLE LOWER BYTE OUTPUT ENABLE 8 ADDRESS BUFFER 16 8 ROW DECODER CHIP ENABLE BUFFER E BYTE ENABLE BUFFER LB SENSE AMPS 64K x 16 BIT MEMORY ARRAY FINAL WRITE DRIVERS UPPER BYTE WRITE ENABLE LB LOWER BYTE OUTPUT BUFFER 8 8 16 UB UB 8 16 WRITE ENABLE BUFFER W COLUMN DECODER UPPER BYTE OUTPUT BUFFER 8 UPPER BYTE WRITE DRIVER LOWER BYTE WRITE DRIVER 8 8 8 8 DQU[15:8] DQL[7:0] LOWER BYTE WRITE ENABLE Table 1 - Pin Functions Signal Name Function A Address Input E Chip Enable W Write Enable G Output Enable UB Upper Byte Enable LB Lower Byte Enable DQ Data I/O VDD Power Supply VSS Ground DC Do Not Connect NC No Connection Copyright (c) 2018 Everspin Technologies 4 MR0A16A Rev. 8.3 3/2018 MR0A16A Figure 2 - MR0A16A Package Pinouts 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 A A A A A E DQL0 DQL1 DQL2 DQL3 VDD VSS DQL4 DQL5 DQL6 DQL7 W A A A A A A A A G UB LB DQU15 DQU14 DQU13 DQU12 VSS VDD DQU11 DQU10 DQU9 DQU8 DC VDD VSS A A A 1 2 3 4 5 6 LB G A0 A1 A2 NC A DQU8 UB A3 A4 E DQL0 B DQU9 DQU10 A5 A6 DQL1 DQL2 C VSS DQU11 A15 VSS DQL3 VDD D VDD DQU12 NC A14 DQL4 VSS E DQU14 DQU13 A12 A13 DQL5 DQL6 F DQU15 NC A10 A11 W DQL7 G NC A7 A8 A9 VDD DC H 44-Pin TSOP Type 2 48-Pin BGA OPERATING MODES Table 2 - Operating Modes E1 G1 W1 LB 1 UB 1 Mode VDD Current DQL[7:0] 2 DQU[15:8] 2 H X X X X Not selected ISB1, ISB2 Hi-Z Hi-Z L H H X X Output disabled IDDR Hi-Z Hi-Z L X X H H Output disabled IDDR Hi-Z Hi-Z L L H L H Lower Byte Read IDDR DOut Hi-Z L L H H L Upper Byte Read IDDR Hi-Z DOut L L H L L Word Read IDDR DOut DOut L X L L H Lower Byte Write IDDW Din Hi-Z L X L H L Upper Byte Write IDDW Hi-Z Din L X L L L Word Write IDDW Din Din Notes: 1. H = high, L = low, X = don't care 2. Hi-Z = high impedance Copyright (c) 2018 Everspin Technologies 5 MR0A16A Rev. 8.3 3/2018 MR0A16A ABSOLUTE MAXIMUM RATINGS This device contains circuitry to protect the inputs against damage caused by high static voltages or electric fields; however, normal precautions should be taken to avoid application of any voltage greater than maximum rated voltages to these highimpedance (Hi-Z) circuits. The device also contains protection against external magnetic fields. Precautions should be taken to avoid application of any magnetic field more intense than the maximum field intensity specified in the maximum ratings. Permanent device damage may occur if absolute maximum ratings are exceeded. Functional operation should be restricted to recommended operating conditions. Exposure to excessive voltages or magnetic fields could affect device reliability. 1 Table 3 - Absolute Maximum Ratings Symbol Parameter Temp Range Package Value Unit VDD Supply voltage 2 - - -0.5 to 4.0 V VIN Voltage on any pin 2 - - -0.5 to VDD + 0.5 V IOUT Output current per pin - - 20 mA PD Package power dissipation 3 - Note 3 0.600 W TBIAS Temperature under bias Commercial - -10 to 85 Industrial - -45 to 95 Extended - -45 to 110 AEC Q-100 Grade 1 - -45 to 130 C Tstg Storage Temperature - - -55 to 150 C TLead Lead temperature during solder (3 minute max) - - 260 C Commercial TSOP2, BGA 2,000 BGA 2,000 TSOP2 10,000 TSOP2 2,000 TSOP2, BGA 8,000 BGA 8,000 TSOP2 10,000 TSOP2 8,000 Hmax_write Maximum magnetic field during write Industrial, Extended AEC-Q100 Grade 1 Commercial Hmax_read Maximum magnetic field during read or standby Industrial, Extended AEC-Q100 Grade 1 A/m A/m Notes appear on the next page. Copyright (c) 2018 Everspin Technologies 6 MR0A16A Rev. 8.3 3/2018 MR0A16A Notes: for MR0A16A Absolute Maximum Ratings: 1. Permanent device damage may occur if absolute maximum ratings are exceeded. Functional operation should be restricted to recommended operating conditions. Exposure to excessive voltages or magnetic fields could affect device reliability. 2. All voltages are referenced to VSS. 3. Power dissipation capability depends on package characteristics and use environment. OPERATING CONDITIONS Table 4 - Operating Conditions Symbol Parameter Temp Range Min Typical Max Unit VDD Power supply voltage 1 All 3.0 3.3 3.6 V VWI Write inhibit voltage All 2.5 2.7 3.0 1 V VIH Input high voltage All 2.2 - VDD + 0.3 2 V VIL Input low voltage All -0.5 3 - 0.8 V TA Ambient Temperature under bias Commercial 0 70 Industrial -40 85 Extended -40 105 AEC Q-100 Grade 1 4 -40 125 C Notes: 1. There is a 2 ms startup time once VDD exceeds VDD,(min). See Power Up and Power Down Sequencing below. 2. VIH(max) = VDD + 0.3 VDC ; VIH(max) = VDD + 2.0 VAC (pulse width 10 ns) for I 20.0 mA. 3. VIL(min) = -0.5 VDC ; VIL(min) = -2.0 VAC (pulse width 10 ns) for I 20.0 mA. 4. AEC-Q100 Grade 1 temperature profile assumes 10% duty cycle at maximum temperature (2 years out of 20 years life.) Copyright (c) 2018 Everspin Technologies 7 MR0A16A Rev. 8.3 3/2018 MR0A16A Power Up and Power Down Sequencing The MRAM is protected from write operations whenever VDD is less than VWI. As soon as VDD exceeds VDD(min), there is a startup time of 2 ms before read or write operations can start. This time allows memory power supplies to stabilize. The E and W control signals should track VDD on power up to VDD- 0.2 V or VIH (whichever is lower) and remain high for the startup time. In most systems, this means that these signals should be pulled up with a resistor so that signal remains high if the driving signal is Hi-Z during power up. Any logic that drives E and W should hold the signals high with a power-on reset signal for longer than the startup time. During power loss or brownout where VDD goes below VWI, writes are protected and a startup time must be observed when power returns above VDD(min). Figure 3 - Power Up and Power Down Timing VWI VDD BROWNOUT or POWER LOSS 2 ms STARTUP READ/WRITE INHIBITED 2 ms RECOVER NORMAL OPERATION READ/WRITE INHIBITED NORMAL OPERATION VIH VIH E W Copyright (c) 2018 Everspin Technologies 8 MR0A16A Rev. 8.3 3/2018 MR0A16A DC CHARACTERISTICS Table 5 - DC Characteristics Symbol Parameter Condition Min Max Unit Ilkg(I) Input leakage current All - 1 A Ilkg(O) Output leakage current All - 1 A - 0.4 VOL Output low voltage VOH Output high voltage IOL = +4 mA V IOL = +100 A VSS + 0.2 IOH = -4 mA 2.4 IOH = -100 A VDD - 0.2 V Table 6 - Power Supply Characteristics Symbol Parameter IDDR AC active supply current - read modes 1 IDDW AC active supply current - write modes1 Condition IOUT= 0 mA, VDD= max VDD= max Temp Range Typical Max Unit All 55 80 mA Commercial 105 155 Industrial 105 165 mA Extended 105 165 AEC-Q100 Grade 1 105 165 All 18 28 mA 9 12 mA VDD= max, E = VIH ISB1 ISB2 AC standby current CMOS standby current No other restrictions on other inputs E VDD - 0.2 V and VIn VSS + 0.2 V or VDD - 0.2 V VDD = max, f = 0 MHz Notes: 1. All active current measurements are measured with one address transition per cycle and at minimum cycle time. Copyright (c) 2018 Everspin Technologies 9 MR0A16A Rev. 8.3 3/2018 MR0A16A TIMING SPECIFICATIONS Table 7 - Capacitance Symbol Parameter 1 Typical Max Unit CIn Address input capacitance - 6 pF CIn Control input capacitance - 6 pF CI/O Input/Output capacitance - 8 pF Notes: 1. f = 1.0 MHz, dV = 3.0 V, TA = 25 C, periodically sampled rather than 100% tested. Table 8 - AC Measurement Conditions Parameter Value Unit Logic input timing measurement reference level 1.5 V Logic output timing measurement reference level 1.5 V 0 or 3.0 V 2 ns Logic input pulse levels Input rise/fall time Output load for low and high impedance parameters See Figure 4 Output load for all other timing parameters See Figure 5 Figure 4 - Output Load Test Low and High ZD= 50 Output RL = 50 VL = 1.5 V Figure 5 - Output Load Test All Others 3.3 V 590 Output 5 pF 435 Copyright (c) 2018 Everspin Technologies 10 MR0A16A Rev. 8.3 3/2018 MR0A16A Table 9 - Read Cycle Timing Symbol Parameter 1 Min Max Unit tAVAV Read cycle time 35 - ns tAVQV Address access time - 35 ns tELQV Enable access time 2 - 35 ns tGLQV Output enable access time - 15 ns tBLQV Byte enable access time - 15 ns tAXQX Output hold from address change 3 - ns tELQX Enable low to output active 3 3 - ns tGLQX Output enable low to output active 3 0 - ns tBLQX Byte enable low to output active 3 0 - ns tEHQZ Enable high to output Hi-Z 3 0 15 ns tGHQZ Output enable high to output Hi-Z3 0 10 ns tBHQZ Byte high to output Hi-Z3 0 10 ns Notes: 1. W is high for read cycle. Power supplies must be properly grounded and decoupled, and bus contention conditions must be minimized or eliminated during read or write cycles. 2. Addresses valid before or at the same time E goes low. 3. This parameter is sampled and not 100% tested. Transition is measured 200 mV from the steady-state voltage. Copyright (c) 2018 Everspin Technologies 11 MR0A16A Rev. 8.3 3/2018 MR0A16A Figure 6 - Read Cycle 1 t AVAV A (ADDRESS) t AXQX Q (DATA OUT) Previous Data Valid Data Valid t AVQV Note: Device is continuously selected (EVIL, GVIL). Figure 7 - Read Cycle 2 t AVAV A (ADDRESS) t AVQV E (CHIP ENABLE) t ELQV t EHQZ t ELQX G (OUTPUT ENABLE) t GHQZ t GLQV t GLQX LB, UB (BYTE ENABLE) Q (DATA OUT) Copyright (c) 2018 Everspin Technologies t BHQZ t BLQV t BLQX Data Valid 12 MR0A16A Rev. 8.3 3/2018 MR0A16A Table 10 - Write Cycle Timing 1 (W Controlled) Symbol Parameter 1 Min Max Unit tAVAV Write cycle time 2 35 - ns tAVWL Address set-up time 0 - ns tAVWH Address valid to end of write (G high) 18 - ns tAVWH Address valid to end of write (G low) 20 - ns Write pulse width (G high) 15 - ns Write pulse width (G low) 15 - ns tDVWH Data valid to end of write 10 - ns tWHDX Data hold time 0 - ns tWLQZ Write low to data Hi-Z 3 0 12 ns tWHQX Write high to output active 3 3 - ns tWHAX Write recovery time 12 - ns tWLWH tWLEH tWLWH tWLEH Notes: 1. All write occurs during the overlap of E low and W low. Power supplies must be properly grounded and decoupled and bus contention conditions must be minimized or eliminated during read and write cycles. If G goes low at the same time or after W goes low, the output will remain in a high impedance state. After W or E has been brought high, the signal must remain in steady-state high for a minimum of 2 ns. The minimum time between E being asserted low in one cycle to E being asserted low in a subsequent cycle is the same as the minimum cycle time allowed for the device. 2. All write cycle timings are referenced from the last valid address to the first transition address. 3. This parameter is sampled and not 100% tested. Transition is measured 200 mV from the steady-state voltage. At any given voltage or temperate, tWLQZ(max) < tWHQX(min) Copyright (c) 2018 Everspin Technologies 13 MR0A16A Rev. 8.3 3/2018 MR0A16A Figure 8 - Write Cycle Timing 1 (W Controlled) t AVAV A (ADDRESS) t AVWH t WHAX E (CHIP ENABLE) t WLEH t WLWH W (WRITE ENABLE) t AVWL UB, LB (BYTE ENABLED) t DVWH D (DATA IN) t WHDX DATA VALID t WLQZ Q (DATA OUT) Hi -Z Hi -Z t WHQX Copyright (c) 2018 Everspin Technologies 14 MR0A16A Rev. 8.3 3/2018 MR0A16A Table 11 - Write Cycle Timing 2 (E Controlled) Symbol Parameter 1 Min Max Unit tAVAV Write cycle time 2 35 - ns tAVEL Address set-up time 0 - ns tAVEH Address valid to end of write (G high) 18 - ns tAVEH Address valid to end of write (G low) 20 - ns Enable to end of write (G high) 15 - ns Enable to end of write (G low) 3 15 - ns tDVEH Data valid to end of write 10 - ns tEHDX Data hold time 0 - ns tEHAX Write recovery time 12 - ns tELEH tELWH tELEH tELWH Notes: 1. All write occurs during the overlap of E low and W low. Power supplies must be properly grounded and decoupled and bus contention conditions must be minimized or eliminated during read and write cycles. If G goes low at the same time or after W goes low, the output will remain in a high impedance state. After W or E has been brought high, the signal must remain in steady-state high for a minimum of 2 ns. The minimum time between E being asserted low in one cycle to E being asserted low in a subsequent cycle is the same as the minimum cycle time allowed for the device. 2. All write cycle timings are referenced from the last valid address to the first transition address. 3. If E goes low at the same time or after W goes low, the output will remain in a high-impedance state. If E goes high at the same time or before W goes high, the output will remain in a high-impedance state. Figure 9 - Write Cycle Timing 2 (E Controlled) t AVAV A (ADDRESS) t EHAX t AVEH t ELEH E (CHIP ENABLE) t AVEL t ELWH W (WRITE ENABLE) UB, LB (BYTE ENABLE) t DVEH D (DATA IN) Q (DATA OUT) Copyright (c) 2018 Everspin Technologies t EHDX Data Valid Hi-Z 15 MR0A16A Rev. 8.3 3/2018 MR0A16A Table 12 - Write Cycle Timing 3 (LB/UB Controlled) Symbol Parameter 1 Min Max Unit tAVAV Write cycle time 2 35 - ns tAVBL Address set-up time 0 - ns Address valid to end of write (G high) 18 - ns Address valid to end of write (G low) 20 - ns Write pulse width (G high) 15 - ns Write pulse width (G low) 15 - ns tDVBH Data valid to end of write 10 - ns tBHDX Data hold time 0 - ns tBHAX Write recovery time 12 - ns tAVBH tBLEH tBLWH tBLEH tBLWH Notes: 1. All write occurs during the overlap of E low and W low. Power supplies must be properly grounded and decoupled and bus contention conditions must be minimized or eliminated during read and write cycles. If G goes low at the same time or after Wgoes low, the output will remain in a high impedance state. After W, E or UB/LB has been brought high, the signal must remain in steady-state high for a minimum of 2 ns. If both byte control signals are asserted, the two signals must have no more than 2 ns skew between them. The minimum time between E being asserted low in one cycle to E being asserted low in a subsequent cycle is the same as the minimum cycle time allowed for the device. 2. All write cycle timings are referenced from the last valid address to the first transition address. Figure 10 - Write Cycle Timing 3 (UB/LB Controlled) t AVAV A (ADDRESS) t AVEH t BHAX E (CHIP ENABLE) W (WRITE ENABLE) t AVBL t BLEH t BLWH UB, LB (BYTE ENABLED) t DVBH D (DATA IN) Q (DATA OUT) t BHDX Data Valid Hi -Z Copyright (c) 2018 Everspin Technologies Hi -Z 16 MR0A16A Rev. 8.3 3/2018 MR0A16A ORDERING INFORMATION Table 13 - Part Numbering System Copyright (c) 2018 Everspin Technologies 17 MR0A16A Rev. 8.3 3/2018 MR0A16A Table 14 - MR0A16A Ordering Part Numbers Temp Grade Temp Package Shipping 44-TSOP2 Commercial 0 to +70 C 48-BGA 44-TSOP2 Industrial -40 to +85 C 48-BGA 44-TSOP2 Extended -40 to +105 C 48-BGA AEC-Q100 Grade 1 -40 to 125 C Copyright (c) 2018 Everspin Technologies 44-TSOP2 18 Ordering Part Number Tray MR0A16AYS35 Tape and Reel MR0A16AYS35R Tray MR0A16AMA35 Tape and Reel MR0A16AMA35R Tray MR0A16ACYS35 Tape and Reel MR0A16ACYS35R Tray MR0A16ACMA35 Tape and Reel MR0A16ACMA35R Tray MR0A16AVYS35 Tape and Reel MR0A16AVYS35R Tray MR0A16AVMA35 Tape and Reel MR0A16AVMA35R Tray MR0A16AMYS35 Tape and Reel MR0A16AMYS35R MR0A16A Rev. 8.3 3/2018 MR0A16A PACKAGE OUTLINE DRAWINGS Figure 11 - 44-pin TSOP2 Notes: 1. Dimensions and tolerances per ASME Y14.5M - 1994. 2. Dimensions in Millimeters. 3. Dimensions do not include mold protrusion. 4. Dimension does not include DAM bar protrusions. 5. DAM Bar protrusion shall not cause the lead width to exceed 0.58. Copyright (c) 2018 Everspin Technologies 19 MR0A16A Rev. 8.3 3/2018 MR0A16A Figure 12 - 48-ball BGA Package Outline Notes: 1. Dimensions in Millimeters. 2. Dimensions and tolerances per ASME Y14.5M - 1994. 3. Maximum solder ball diameter measured parallel to DATUM A 4. DATUM A, the seating plane is determined by the spherical crowns of the solder balls. 5. Parallelism measurement shall exclude any effect of mark on top surface of package. Copyright (c) 2018 Everspin Technologies 20 MR0A16A Rev. 8.3 3/2018 MR0A16A REVISION HISTORY Date Description of Change 0 Jun 18, 2007 Initial Advanced Information Release 1 Sept 21, 2007 Table 6, Applied Values to TBD's in IDD Specifications 2 Nov 12, 2007 Table 2, Changed IDDA to IDDR or IDDW 3 Sep 12, 2008 Reformat Datasheet for EverSpin, Add BGA Packaging Information, Add Tape & Reel Part Numbers, Add Power Sequencing Info, Correct IOH spec of VOH to -100 uA, Correct ac Test Conditions. 4 Feb 28, 2011 Add TSOPII Lead Cross-Section, Add Production Note. Converted to new document format. 5 Dec 9, 2011 Figure 2.1 cosmetic update. Figure 5.2 BGA package outline drawing revised for ball size. Updated logo and contact information. 6 August 6, 2012 Revised Table 1 and Figure 1 to be correct for x16 device. Revised magnetic immunity ratings for TSOP2 Industrial Grade. Revised figure 3. Complete document reformat and restructure. 7 October 14, 2013 Added AEC-Q100 Grade 1 product option. 8 February 19, 2015 Revised package outline for BGA. Ball size to 0.25 / 0.35 mm. 8.1 May 19, 2015 Revised contact information on Contact Us page. 8.2 June 11, 2015 Correction to Japan Sales Office telephone number. 8.3 March 23, 2018 Revised contact information on Contact Us page. Revision Copyright (c) 2018 Everspin Technologies 21 MR0A16A Rev. 8.3 3/2018 MR0A16A HOW TO CONTACT US How to Reach Us: Everspin Technologies, Inc. Home Page: Information in this document is provided solely to enable system and software implementers to use Everspin Technologies products. There are no express or implied licenses granted hereunder to design or fabricate any integrated circuit or circuits based on the information in this document. Everspin Technologies reserves the right to make changes without further notice to any products herein. Everspin makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does Everspin Technologies assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation consequential or incidental damages. "Typical" parameters, which may be provided in Everspin Technologies data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters including "Typicals" must be validated for each customer application by customer's technical experts. Everspin Technologies does not convey any license under its patent rights nor the rights of others. Everspin Technologies products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the Everspin Technologies product could create a situation where personal injury or death may occur. Should Buyer purchase or use Everspin Technologies products for any such unintended or unauthorized application, Buyer shall indemnify and hold Everspin Technologies and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that Everspin Technologies was negligent regarding the design or manufacture of the part. EverspinTM and the Everspin logo are trademarks of Everspin Technologies, Inc. www.everspin.com World Wide Information Request WW Headquarters - Chandler, AZ 5670 W. Chandler Blvd., Suite 100 Chandler, Arizona 85226 Tel: +1-877-480-MRAM (6726) Local Tel: +1-480-347-1111 Fax: +1-480-347-1175 support@everspin.com orders@everspin.com sales@everspin.com Europe, Middle East and Africa Everspin Europe Support support.europe@everspin.com Japan Everspin Japan Support support.japan@everspin.com Asia Pacific Everspin Asia Support support.asia@everspin.com All other product or service names are the property of their respective owners. Copyright (c) Everspin Technologies, Inc. 2018 Filename: EST00354_MR0A16A_Datasheet_Rev8.3 032318 Copyright (c) 2018 Everspin Technologies 22 MR0A16A Rev. 8.3 3/2018