1
Microsemi Corporation
Copyright 2012, Microsemi Corporation. All Rights Reserved.
Features
Inputs/Outputs
• Accepts differential or single-ended input
• LVPECL, LVDS, CML, HCSL, LVCMOS
• On-chip input termination resistors and biasing for
AC coupled inputs
• Six precision LVPECL outputs
• Operating frequency up to 750 MHz
Power
• Options for 2.5 V or 3.3 V power supply
• Core current consumption of 110 mA
• On-chip Low Drop Out (LDO) Regulator for superior
power supply rejection
Performance
• Ultra low additive jitter of 36 fs RMS
Applications
• General purpose clock distribution
• Low jitter clock trees
• Logic translation
• Clock and data signal restoration
• Wired communications: OTN, SONET/SDH, GE,
10 GE, FC and 10G FC
• Wireless communications
• High performance microprocessor clock
distribution
February 2013
Figure 1 - Functional Block Diagram
clk_p
clk_n
ctrl
vt
Termination
and Bias
out5_p
out5_n
out4_p
out4_n
out3_p
out3_n
out2_p
out2_n
out1_p
out1_n
out0_p
out0_n
Buffer
ZL40205
Precision 1:6 LVPECL Fanout Buffer
with On-Chip Input Termination
Data Sheet
Ordering Information
ZL40205LDG1 32 Pin QFN Trays
ZL40205LDF1 32 Pin QFN Tape and Reel
Matte Tin
Package Size: 5 x 5 mm
-40oC to +85oC
ZL40205 Data Sheet
Table of Contents
2
Microsemi Corporation
Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
Inputs/Outputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
Power . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
Performance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
1.0 Package Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
2.0 Pin Description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
3.0 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
3.1 Clock Inputs. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
3.2 Clock Outputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
3.3 Device Additive Jitter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
3.4 Power Supply . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
3.4.1 Sensitivity to power supply noise . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
3.4.2 Power supply filtering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
3.4.3 PCB layout considerations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
4.0 AC and DC Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
5.0 Performance Characterization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
6.0 Typical Behavior . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
7.0 Package Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
8.0 Mechanical Drawing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
ZL40205 Data Sheet
List of Figures
3
Microsemi Corporation
Figure 1 - Functional Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
Figure 2 - Pin Connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
Figure 3 - Simplified Diagram of input stage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Figure 4 - Clock Input - LVPECL - DC Coupled . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Figure 5 - Clock Input - LVPECL - AC Coupled . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Figure 6 - Clock Input - LVDS - DC Coupled . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Figure 7 - Clock Input - LVDS - AC Coupled . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Figure 8 - Clock Input - CML- AC Coupled . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Figure 9 - Clock Input - HCSL- AC Coupled . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Figure 10 - Clock Input - AC-coupled Single-Ended . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Figure 11 - Clock Input - DC-coupled 3.3V CMOS. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Figure 12 - Simplified Output Driver. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Figure 13 - LVPECL Basic Output Termination . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Figure 14 - LVPECL Parallel Output Termination. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Figure 15 - LVPECL Parallel Thevenin-Equivalent Output Termination . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Figure 16 - LVPECL AC Output Termination . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Figure 17 - LVPECL AC Output Termination for CML Inputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Figure 18 - Additive Jitter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Figure 19 - Decoupling Connections for Power Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Figure 20 - Differential and Single-Ended Output Voltages Parameter Definitions . . . . . . . . . . . . . . . . . . . . . . . . 17
Figure 21 - Input To Output Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
ZL40205 Data Sheet
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Microsemi Corporation
1.0 Package Description
The device is packaged in a 32 pin QFN
26
28
30
32
12
10
8
64
2
NC
out5_p
out4_n
out5_n
NC
gnd
clk_p
VDD_core
out1_n
NC
out0_n
out1_p
gnd
out3_n
vdd
gnd
out2_p
14
16
18
2224 20
vdd
NC
out0_p
NC
clk_n
out2_n
gnd out3_p
vdd
ctrl
NC
VDD_core
out4_p
vdd
vt
gnd (E-pad)
vt
Figure 2 - Pin Connections
ZL40205 Data Sheet
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Microsemi Corporation
2.0 Pin Description
Pin # Name Description
3, 6 clk_p, clk_n, Differential Input (Analog Input). Differential (or single ended) input signals.
For all input configurations see “Clock Inputs” on page 6
28, 27,
26, 25,
24, 23,
18, 17,
16, 15,
14, 13
out0_p, out0_n
out1_p, out1_n
out2_p, out2_n
out3_p, out3_n
out4_p, out4_n
out5_p, out5_n
Differential Output (Analog Output). Differential outputs.
9, 19,
22, 32
vdd Positive Supply Voltage. 2.5 VDC or 3.3 VDC nominal.
1, 8 vdd_core Positive Supply Voltage. 2.5 VDC or 3.3 VDC nominal.
2, 7,
20, 21
gnd Ground. 0 V.
4vtOn-Chip Input Termination Node (Analog). Center tap between internal 50 Ohm
termination resistors.
The use of this pin is detailed in section 3.1, “Clock Inputs“, for various input signal types.
5ctrlDigital Control for On-Chip Input Termination (Input). Selects differential input mode;
0: DC coupled LVPECL or LVDS modes
1: AC coupled differential modes
This pin are internally pulled down to GND. The use of this pin is detailed in section 3.1,
“Clock Inputs“, for various input signal types.
10, 11,
12, 29,
30, 31
NC No Connection. Leave unconnected.
ZL40205 Data Sheet
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Microsemi Corporation
3.0 Functional Description
The ZL40205 is an LVPECL clock fan out buffer with six output clock drivers capable of operating at frequencies up
to 750MHz.
The ZL40205 provides an internal input termination network for DC and AC coupled inputs; optional input biasing
for AC coupled inputs is also provided. The ZL40205 can accept DC or AC coupled LVPECL and LVDS input
signals, AC coupled CML or HCSL input signals, and single ended signals. A pin compatible device with external
termination is also available.
The ZL40205 is designed to fan out low-jitter reference clocks for wired or optical communications applications
while adding minimal jitter to the clock signal. An internal linear power supply regulator and bulk capacitors
minimize additive jitter due to power supply noise. The device operates from 2.5V+/-5% or 3.3V+/-5% supply. Its
operation is guaranteed over the industrial temperature range -40°C to +85°C.
The device block diagram is shown in Figure 1; its operation is described in the following sections.
3.1 Clock Inputs
The device has a differential input equipped with two on-chip 50 Ohm termination resistors arranged in series with a
center tap. The input can accept many differential and single-ended signals with AC or DC coupling as appropriate.
A control pin is available to enable internal biasing for AC coupled inputs. A block diagram of the input stage is in
Figure 3.
Receiver
clk_n
50
clk_p
Vt
50
Bias
ctrl
Figure 3 - Simp lified Diagram of Input Stage
This following figures give the components values and configuration for the various circuits compatible with the
input stage and the use of the Vt and ctrl pins in each case.
In the following diagrams were the ctrl pin is logically one and the Vt pin is not connected, the Vt pin can be instead
connected to VDD with a capacitor. A capacitor can also help in Figure 4 between Vt and VDD. This capacitor will
minimize the noise at the point between the two internal termination resistors and improve the overall performance
of the device.
LVPECL
Driver
R
VDD_driver VDD
Z
o
= 50 Ohms
Z
o
= 50 Ohms
clk_p
clk_n
Vt
Ctrl
“0”
For 3.3 V: R= 50 Ohms
For 2.5 V: R= 22 Ohms
22 Ohms
22 Ohms
Not recommended for VDD_driver=2.5V
LVPECL
Driver
VDD_driver VDD
Zo= 50 Ohms
Zo= 50 Ohms
clk_p
clk_n
Vt
Ctrl
“1”
For 3.3 V: R= 150 Ohms
For 2.5 V: R= 85 Ohms
NC
RR
22 Ohms
22 Ohms
ZL40205 Data Sheet
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Microsemi Corporation
Figure 4 - Clock Input - LVPECL - DC Coupled
Figure 5 - Clock Input - LVPECL - AC Coupled
LVDS
Driver
VDD_driver VDD
Z
o
= 50 Ohms
Z
o
= 50 Ohms
clk_p
clk_n
Vt
Ctrl
“0”
NC
LVDS
Driver
VDD_driver VDD
Zo= 50 Ohms
Zo= 50 Ohms
clk_p
clk_n
Vt
Ctrl
“1”
NC
R
For VDD_driver = 3.3 V: R= 900 Ohms
For VDD_driver = 2.5 V: R = 680 Ohms
Note: R is only needed to provide a DC path for the
LVDS driver. See driver data sheet for more information.
ZL40205 Data Sheet
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Microsemi Corporation
Figure 6 - Clock Inpu t - LVDS - DC Coupled
Figure 7 - Clock Inpu t - LV DS - AC Coupled
CML
Driver
VDD_driver VDD
Zo= 50 Ohms
Zo= 50 Ohms
clk_p
clk_n
Vt
Ctrl
“1”
R= 50 Ohms
NC
RR
HCSL
Driver
VDD_driver VDD
Zo= 50 Ohms
Zo= 50 Ohms
clk_p
clk_n
Vt
Ctrl
“1”
R= 50 Ohms
NC
RR
ZL40205 Data Sheet
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Microsemi Corporation
Figure 8 - Clock Input - CML- AC Coupled
Figure 9 - Clock Input - HCSL- AC Coupled
CMOS
Driver
VDD_driver
VDD
Z
o
= 50 Ohms clk_p
clk_n
Vt
Ctrl
“1”
CMOS
Driver
VDD_driver
VDD
Z
o
= 50 Ohms clk_p
clk_n
Vt
Ctrl
“1”
NC
ZL40205 Data Sheet
10
Microsemi Corporation
Figure 10 - Clock Input - AC-coupled Single-Ended
Figure 11 - Clock Input - DC-coupled 3. 3V CMOS
ZL40205 Data Sheet
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Microsemi Corporation
3.2 Clock Outputs
LVPECL has a very low output impedance and a differential signal swing between 1V and 1.6 V. A simplified
diagram for the output stage is shown in Figure 12.The LVPECL to LVDS output termination is not shown since
there is a different device with the same inputs and LVDS outputs.
Figure 12 - Simplified Output Driver
out_p
out_n
The methods to terminate the ZL40205 LVPECL drivers are shown in the following figures.
LVPECL
Receiver
50
Ohms
50
Ohms
VDD VDD
Zo= 50 Ohms
Zo= 50 Ohms
ZL40205
clk_p
clk_n
VDD - 2
Figure 13 - LVPEC L Basic Output Termination
LVPECL
Receiver
50
Ohms
50
Ohms
VDD VDD_Rx
Zo= 50 Ohms
Zo= 50 Ohms
ZL40205
clk_p
clk_n
R
For VDD = 2.5 V: R = 20 Ohms
For VDD = 3.3 V: R = 50 Ohms
Figure 14 - LVPECL Paral lel Output Termination
ZL40205 Data Sheet
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Microsemi Corporation
R2 R2
VDD VDD_Rx
Zo= 50 Ohms
Zo= 50 Ohms
ZL40205
clk_p
clk_n
For VDD = 2.5 V: R1 = 250 Ohms, R2 = 62.5 Ohms
For VDD = 3.3 V: R1 = 127 Ohms, R2 = 82 Ohms
VDD_Rx
R1 R1
LVPECL
Receiver
Figure 15 - LVPECL Parallel Thevenin-Equivalent Output Termination
R2 R2
VDD VDD_Rx
Zo= 50 Ohms
Zo= 50 Ohms
ZL40205
clk_p
clk_n
For VDD_Rx = 2.5 V: R1 = 250 Ohms,
R2 = 62.5 Ohms
For VDD_Rx = 3.3 V: R1 = 127 Ohms,
R2 = 82 Ohms
VDD_Rx
R1 R1
LVPECL
Receiver
RR
For VDD = 2.5 V: R = 60 Ohms
For VDD = 3.3 V: R = 120 Ohms
100 nF
100 nF
Figure 16 - LVPECL AC Output Termination
ZL40205 Data Sheet
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Microsemi Corporation
VDD VDD_Rx
Zo= 50 Ohms
Zo= 50 Ohms
ZL40205
clk_p
clk_n
100 nF
100 nF
50
CML
Receiver
50
R
For VDD = 2.5 V: R = 60 Ohms
For VDD = 3.3 V: R = 120 Ohms
R
Figure 17 - LV PECL AC Output Termination for CML Inputs
ZL40205 Data Sheet
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Microsemi Corporation
3.3 Device Addi tive Ji tter
The ZL40205 clock fanout buffer is not intended to filter clock jitter. The jitter performance of this type of device is
characterized by its additive jitter. Additive jitter is the jitter the device would add to a hypothetical jitter-free clock as
it passes through the device. The additive jitter of the ZL40205 is random and as such it is not correlated to the jitter
of the input clock signal.
The square of the resultant random RMS jitter at the output of the ZL40205 is equal to the sum of the squares of the
various random RMS jitter sources including: input clock jitter; additive jitter of the buffer; and additive random jitter
due to power supply noise. There may be additional deterministic jitter sources, but they are not shown in Figure
18.
+
Jin
2Jout
2= Jin
2+Jadd
2+Jps
2
Jadd
2Jps
2
Jin = Random input clock jitter (RMS)
Jadd = Additive jitter due to the device (RMS)
Jps = Additive jitter due to power supply noise (RMS)
Jout = Resultant random output clock jitter (RMS)
+
Figure 18 - Additive Jitter
ZL40205 Data Sheet
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Microsemi Corporation
3.4 Power Supply
This device operates employing either a 2.5V supply or 3.3V supply.
3.4.1 Sensitivity to power supply noise
Power supply noise from sources such as switching power supplies and high-power digital components such as
FPGAs can induce additive jitter on clock buffer outputs. The ZL40205 is equipped with a low drop out (LDO)
regulator and on-chip bulk capacitors to minimize additive jitter due to power supply noise. The on-chip regulation,
recommended power supply filtering, and good PCB layout all work together to minimize the additive jitter from
power supply noise.
3.4.2 Power supply filtering
Jitter levels may increase when noise is present on the power pins. For optimal jitter performance, the device
should be isolated from the power planes connected to its power supply pins as shown in Figure 19.
• 10 µF capacitors should be size 0603 or size 0805 X5R or X7R ceramic, 6.3 V minimum rating
• 0.1 µF capacitors should be size 0402 X5R ceramic, 6.3 V minimum rating
• Capacitors should be placed next to the connected device power pins
• a 0.3 ohm resistor is recommended
Figure 19 - Decoupling Connections for Power Pins
3.4.3 PCB layout considerations
The power nets in Figure 19 can be implemented either as a plane island or routed power topology without
changing the overall jitter performance of the device.
ZL40205
1
8
9
19
22
32
0.1 µF
0.1 µF
vdd_core
10 µF
0.1 µF
0.15 Ω
vdd
0.1 µF
10 µF
Absolute Maximum Ratings*
Parameter Sym. Min. Max. Units
1Supply voltage VDD_R -0.5 4.6 V
2Voltage on any digital pin VPIN -0.5 VDD V
4LVPECL output current Iout 30 mA
5Soldering temperature T260 °C
6Storage temperature TST -55 125 °C
7Junction temperature Tj125 °C
8Voltage on input pin Vinput VDD V
9Input capacitance each pin Cp500 fF
ZL40205 Data Sheet
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Microsemi Corporation
4.0 AC and DC Electrical Characteristics
* Exceeding these values may cause permanent damage. Functional operation under these conditions is not implied.
* Voltages are with respect to ground (GND) unless otherwise stated
Recommended Operating Conditions*
Characteristics Sym. Min. Typ. Max. Units
1Supply voltage 2.5 V mode VDD25 2.375 2.5 2.625 V
2Supply voltage 3.3 V mode VDD33 3.135 3.3 3.465 V
3Operating temperature TA-40 25 85 °C
* Voltages are with respect to ground (GND) unless otherwise stated
DC Electrical Chara cte ri st ic s - C urrent Con s um pt io n
Characteristics Sym. Min. Typ. Max. Units Notes
1Supply current LVPECL drivers -
unloaded
Idd_unload 110 mA Unloaded
2Supply current LVPECL drivers -
loaded (all outputs are active)
Idd_load 209 mA Including power
to RL = 50Ω
DC Electrical Characteristics - Inputs and Outputs - for 3.3 V Supply
Characteristics Sym. Min. Typ. Max. Units Notes
1CMOS control logic high-level input
voltage
VCIH 0.7*VDD V
2CMOS control logic low-level input
voltage
VCIL 0.3*VDD V
3CMOS control logic Input leakage
current
IIL 1µA VI = VDD or 0 V
4Differential input common mode
voltage
VCM 1.1 2.0 V
5Differential input voltage difference VID 0.25 1 V
6Differential input resistance VIR 80 100 120 ohm
ZL40205 Data Sheet
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Microsemi Corporation
* This parameter was measured from 125 MHz to 750 MHz.
* This parameter was measured from 125 MHz to 750 MHz.
Figure 20 - Differential and Single-Ended Output Voltages Parameter Definitions
* Supply voltage and operating temperature are as per Recommended Operating Conditions
7LVPECL output high voltage VOH VDD -
1.40
V
8LVPECL output low voltage VOL VDD -
1.62
V
9LVPECL output differential voltage* VOD 0.5 0.9 V
DC Electrical Characteristics - Inputs and Outputs - for 2.5 V Supply
Characteristics Sym. Min. Typ. Max. Units Notes
1Differential input common mode
voltage
VCM 1.1 1.6 V
2Differential input voltage difference VID 0.25 1 V
3Differential input resistance VIR 80 100 120 ohm
4LVPECL output high voltage VOH VDD -
1.40
V
5LVPECL output low voltage VOL VDD -
1.62
V
6LVPECL output differential voltage* VOD 0.4 0.9 V
2*VOD
VOD
AC Electrical Characteristics* - Inputs and Outputs (see Figure 21) - for 2.5/3.3 V supply.
Characteristics Sym. Min. Typ. Max. Units Notes
1Maximum Operating Frequency 1/tp750 MHz
2Input to output clock propagation delay tpd 0 1 2 ns
3Output to output skew tout2out 50 100 ps
4Part to part output skew tpart2part 80 300 ps
5Output clock Duty Cycle degradation tPWH/ tPWL -2 0 2 Percent
6LVPECL Output clock slew rate rSL 0.75 1.2 V/ns
DC Electrical Characteristics - Inputs and Outputs - for 3.3 V Supply
Characteristics Sym. Min. Typ. Max. Units Notes
Input
tP
tPWL
tpd
tPWH
Output
ZL40205 Data Sheet
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Microsemi Corporation
Figure 21 - Input To Output Timing
Additive Jitter at 2.5 V*
Output Frequency (MHz) Jitter
Measurement
Filter
Typical
RMS (fs) Notes
1125 12 kHz - 20 MHz 139
2212.5 12 kHz - 20 MHz 109
3311.04 12 kHz - 20 MHz 85
4425 12 kHz - 20 MHz 57
5500 12 kHz - 20 MHz 50
6622.08 12 kHz - 20 MHz 40
7750 12 kHz - 20 MHz 36
Additive Jitter at 3.3 V*
Output Frequency (MHz) Jitter
Measurement
Filter
Typical
RMS (fs) Notes
1125 12 kHz - 20 MHz 115
2212.5 12 kHz - 20 MHz 85
3311.04 12 kHz - 20 MHz 72
4425 12 kHz - 20 MHz 55
5500 12 kHz - 20 MHz 48
6622.08 12 kHz - 20 MHz 41
7750 12 kHz - 20 MHz 39
ZL40205 Data Sheet
19
Microsemi Corporation
5.0 Performance Characterization
*The values in this table were taken with an approximate slew rate of 0.8 V/ns.
*The values in this table were taken with an approximate slew rate of 0.8 V/ns.
Additive Jitter from a Power Supply Tone*
Carrier
frequency Parameter Typical Units Notes
125MHz 25 mV
at 100 kHz
115 fs RMS
750MHz 25 mV
at 100 kHz
59 fs RMS
* The values in this table are the additive periodic jitter caused by an interfering tone typically caused by a switching power supply. For this test,
measurements were taken over the full temperature and voltage range for VDD = 2.5 V. The magnitude of the interfering tone is measured at the
DUT.
ZL40205 Data Sheet
20
Microsemi Corporation
6.0 Typical Behavior
Typical Phase Noise at 622.08 MHz Typical Waveformat 155.52 MHz
VOD versus Frequency Propagation Delay versus Temperature
Note: This is for a single device. For more details see the
-0.5
-0.4
-0.3
-0.2
-0.1
0
0.1
0.2
0.3
0.4
0.5
0 5 10 15 20
Voltage
Time (ns)
0.6
0.65
0.7
0.75
0.8
0 100 200 300 400 500 600 700 800
Voltage
Frequency (MHz)
0.7
0.75
0.8
0.85
0.9
0.95
1
-60 -40 -20 0 20 40 60 80 100
Propagation Delay (ns)
Temperature (°C)
ZL40205 Data Sheet
21
Microsemi Corporation
Power Supply Tone Frequency (at 25 mV) versus
PSRR at 125 MHz
Power Supply Tone Frequency (at 25 mV) versus
Additive Jitter at 125 MHz
Power Supply Tone Magnitude (at 100 kHz) versus
PSRR at 125 MHz
Power Supply Tone Magnitude (at 100 kHz) versus
Additive Jitter at 125 MHz
-105
-100
-95
-90
-85
-80
-75
100 150 200 250 300 350 400 450 500
PSRR (dBc)
Power Supply Noise Frequency (kHz)
with 25 mV magnitude
10
15
20
25
30
35
40
45
50
55
60
100 150 200 250 300 350 400 450 500
Addivite Jitter (fs RMS)
Power Supply Noise Frequency (kHz) with 25 mV
magnitude
-90
-88
-86
-84
-82
-80
-78
-76
-74
20 40 60 80 100
PSRR (dBc)
Power Supply Tone Magnitude at 100 kHz (mV)
0
50
100
150
200
250
300
20 30 40 50 60 70 80 90 100
Additive Jitter (fs RMS)
Power Supply Tone Magnitude at 100 kHz (mV)
ZL40205 Data Sheet
22
Microsemi Corporation
7.0 Package Characteristics
Thermal Data
Parameter Symbol Test Condition Value Unit
Junction to Ambient Thermal Resistance ΘJA Still Air
1 m/s
2 m/s
37.4
33.1
31.5
oC/W
Junction to Case Thermal Resistance ΘJC 24.4 oC/W
Junction to Board Thermal Resistance ΘJB 19.5 oC/W
Maximum Junction Temperature* Tjmax 125 oC
Maximum Ambient Temperature TA85 oC
ZL40205 Data Sheet
23
Microsemi Corporation
8.0 Mechanical Drawing
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