215NQA6VA12FG - Advanced Micro Devices, Inc.

AMD RS690

Databook

Technical Reference Manual

Rev. 3.03

P/N: 41977_rs690_ds_nda_3.03

Please note that in this databook, references to "DVI" and "HDMI" may refer to: (1) the function of the integrated DVI/HDMI interface described in details in section 2.2.1 and

3.7, as well as in other sections; or (2) the capability of the TMDS interface, multiplexed on the PCI-E external graphics interface, to enable DVI or HDMI through passive

enabling circuitries. Any statement in this databook on any DVI or HDMI-related functionality must be understood to apply to (1), (2), or both, according to the immediate

context of the reference.

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Committee (ATSC) standard and related technologies; or (iii) the High Definition Multimedia Interface (HDMI) standard and related technologies; or

(b) Audio and/or video codecs or any industry standard technology (e.g., technology or specifications promulgated by any standards development organization, consortium,

trade association, special interest group or like entity).

This device is protected by U.S. patent numbers 4,631,603, 4,577,216 and 4,819,098 and other intellectual property rights. The use of Macrovision's copy protection technology

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Proprietary and Confidential Table of Contents-1

Table of Contents

Chapter 1: Overview

1.1 Introducing the RS690 ........................................................................................................................................................1-1

1.2 RS690C...............................................................................................................................................................................1-2

1.3 RS690 Features ...................................................................................................................................................................1-2

1.3.1 CPU HyperTransport Interface.............................................................................................................................1-2

1.3.2 ATI HyperMemory™...........................................................................................................................................1-2

1.3.3 PCI Express Interface...........................................................................................................................................1-2

1.3.4 A-Link Express II Interface..................................................................................................................................1-2

1.3.5 2D Acceleration Features.....................................................................................................................................1-2

1.3.6 3D Acceleration Features.....................................................................................................................................1-3

1.3.7 Motion Video Acceleration Features....................................................................................................................1-4

1.3.8 Multiple Display Features ....................................................................................................................................1-4

1.3.9 DVI/HDMI (Not applicable to the RS6 90C)........................................................................................................1-5

1.3.10 Power Management Features ...............................................................................................................................1-6

1.3.11 PC Design Guide Compliance..............................................................................................................................1-6

1.3.12 Test Capability Features.......................................................................................................................................1-6

1.3.13 Packaging .............................................................................................................................................................1-6

1.4 Software Features................................................................................................................................................................1-6

1.5 Branding Diagrams .............................................................................................................................................................1-7

1.5.1 Branding Diagrams for ASIC Revision A11........................................................................................................1-7

1.5.2 Branding Diagrams for ASIC Revision A12 and After........................................................................................1-8

1.6 Part Number Legend...........................................................................................................................................................1-9

1.7 Conventions and Notations...............................................................................................................................................1-10

1.7.1 Pin Names...........................................................................................................................................................1-10

1.7.2 Pin Types............................................................................................................................................................1-10

1.7.3 Numeric Representation.....................................................................................................................................1-10

1.7.4 Register Field......................................................................................................................................................1-11

1.7.5 Hyperlinks ..........................................................................................................................................................1-11

1.7.6 Acronyms and Abbreviations.............................................................................................................................1-11

Chapter 2: Functional Descriptions

2.1 Host Interface......................................................................................................................................................................2-2

2.2 DVI/HDMI (Not Applicable to the RS690C).....................................................................................................................2-4

2.2.1 DVI/HDMI Data Transmission Order an d Signal Mapping ................................................................................2-4

2.2.2 Support for HDMI Packet Types..........................................................................................................................2-7

2.3 VGA DAC Characteristics..................................................................................................................................................2-8

2.4 External Clock Chip............................................................................................................................................................2-8

Chapter 3: Pin Descriptions and Strap Options

3.1 Pin Assignment Top View..................................................................................................................................................3-2

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3.2 Interface Block Diagram.................................................................................................................................................... 3-4

3.3 CPU HyperTransport Interface ........................................................................................................................................ 3-5

3.4 PCI Express Interfaces ....................................................................................................................................................... 3-5

3.4.1 1 x 16 Lane Interface for External Graphics ....................................................................................................... 3-5

3.4.2 A-Link Express II to Southbridge........................................................................................................................ 3-5

3.4.3 4 x 1 Lane Interface for General Purpose External Devices .............................................................................. 3-6

3.4.4 Miscellaneous PCI Express Si gnals..................................................................................................................... 3-6

3.5 Clock Interface................................................................................................................................................................... 3-6

3.6 CRT and TV Interface........................................................................................................................................................ 3-6

3.7 Integrated DVI/HDMI Interface......................................................................................................................................... 3-7

3.8 TMDS Interface Multiplexed on the PCI-E Graphics Lanes (Not Applicable to the RS690C) ........................................ 3-8

3.9 Power Management Pins................................................................................................................................................... 3-9

3.10 Miscellaneous Pins........................................................................................................................................................... 3-9

3.11 Power Pins...................................................................................................................................................................... 3-10

3.12 Ground Pins.....................................................................................................................................................................3-11

3.13 Debug Port Signals..........................................................................................................................................................3-11

3.14 Strapping Options........................................................................................................................................................... 3-12

Chapter 4: Timing Specifications

4.1 HyperTransport Bus Timing .............................................................................................................................................. 4-1

4.2 HyperTransport Reference Clock Timing Parameters....................................................................................................... 4-1

4.3 PCI-E Differential Clock AC Specifications ..................................................................................................................... 4-1

4.4 OSCIN Timing................................................................................................................................................................... 4-1

4.5 Power Rail Power Up Sequence......................................................................................................................................... 4-3

Chapter 5: Electrical Characteristics and Physical Data

5.1 Electrical Characteristics.................................................................................................................................................... 5-1

5.1.1 Maximum and Minimum Ratings ........................................................................................................................ 5-1

5.1.2 DC Characteristics............................................................................................................................................... 5-2

5.2 RS690 Thermal Characteristics.......................................................................................................................................... 5-5

5.2.1 RS690 Thermal Limits ........................................................................................................................................ 5-5

5.2.2 Other Thermal Parameters................................................................................................................................... 5-5

5.3 Package Information .......................................................................................................................................................... 5-6

5.3.1 Physical Dimensions............................................................................................................................................ 5-6

5.3.2 Pressure Specification.......................................................................................................................................... 5-8

5.3.3 Board Solder Reflow Process Recommendations ............................................................................................... 5-8

5.4 Thermal Diode Characteristics......................................................................................................................................... 5-10

Chapter 6: Power Management and ACPI

6.1 ACPI Power Management Implementation ....................................................................................................................... 6-1

6.2 Power Management for the Graphics Controller ............................................................................................................... 6-2

6.2.1 PCI Function Power States.................................................................................................................................. 6-2

6.2.2 PCI Power Management Interface....................................................................................................................... 6-2

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6.2.3 Capabilities List Data Structure in PCI Configuration Space..............................................................................6-2

6.2.4 Register Block Definition.....................................................................................................................................6-3

6.2.5 Capability Identifier: Cap_ID (Offset = 0)...........................................................................................................6-4

6.2.6 Next Item Pointer .................................................................................................................................................6-5

6.2.7 PMC - Power Management Capabilities (Offset = 2) ..........................................................................................6-5

Chapter 7: Testability

7.1 Test Capability Features ......................................................................................................................................................7-1

7.2 Test Interface.......................................................................................................................................................................7-1

7.3 XOR Tree............................................................................................................................................................................7-1

7.3.1 Brief Description of an XOR Tree .......................................................................................................................7-1

7.3.2 Description of the XOR Tree for the RS690........................................................................................................7-2

7.3.3 XOR Tree Activation ...........................................................................................................................................7-2

7.3.4 XOR Chain for the RS690....................................................................................................................................7-2

7.3.5 Unused Pins..........................................................................................................................................................7-4

7.4 VOH/VOL Test...................................................................................................................................................................7-4

7.4.1 Brief Description of a VOH/VOL Tree................................................................................................................7-4

7.4.2 VOH/VOL Tree Activation..................................................................................................................................7-4

7.4.3 VOH/VOL pin list................................................................................................................................................7-5

Appendix A: Pin Listings

A.1 RS690 Pin List Sorted by Ball Reference......................................................................................................................... 1-2

A.2 RS690 Pin List Sorted by Pin Name................................................................................................................................. 1-6

Appendix B: Revision History

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List of Figures-1 Proprietary and Confidential

List of Figures

Figure 1-1: RS690-variant Branding Diagrams for ASIC Revision A11 ........................................................................................1-8

Figure 1-2: RS690-variant Branding Diagrams for ASIC Revision A12 ........................................................................................1-9

Figure 1-3: The RS690-Family ASIC Part Number Legend ...........................................................................................................1-9

Figure 2-1: RS690 Internal Block Diagram .....................................................................................................................................2-1

Figure 2-2: Host Interface Block Diagram ......................................................................................................................................2-2

Figure 2-3: RS690 Host Bus Interface Signals ...............................................................................................................................2-3

Figure 2-4: Data Transmission Ordering for the Integrated DVI/HDMI and TMDS Interfaces ..................................................... 2-4

Figure 3-1: RS690 Pin Assignment Top View (Left) ......................................................................................................................3-2

Figure 3-2: RS690 Pin Assignment Top View (Right) ....................................................................................................................3-3

Figure 3-3: RS690 Interface Block Diagram ...................................................................................................................................3-4

Figure 4-1: Power Rail Power Up Sequence for the RS690 ........................................................................................................... 4-3

Figure 5-1: DC Characteristics of the Integrated DVI/HDMI and the TMDS Interface .................................................................5-4

Figure 5-2: RS690 Package Outline ................................................................................................................................................5-6

Figure 5-3: RS690 Ball Arrangement ..............................................................................................................................................5-7

Figure 5-2: Stencil Opening Recommendations .............................................................................................................................. 5-9

Figure 5-4: RoHS/Lead-Free Solder (SAC305/405 Tin-Silver-Copper) Reflow Profile ..............................................................5-10

Figure 6-1: Linked List for Capabilities ..........................................................................................................................................6-5

Figure 7-1: An Example of a Generic XOR Tree ............................................................................................................................7-2

Figure 7-2: Sample of a Generic VOH/VOL Tree ...........................................................................................................................7-4

List of Figures-2 Proprietary and Confidential

This page is left blank intenti onall y.

List of Tables-1 Proprietary and Confidential

List of Tables

Table 1-1: RS690-Family ASIC Part Numbers ............................................................................................................................1-10

Table 1-2: Pin Type Code s ...........................................................................................................................................................1-10

Table 1-3: Acronyms and Abbreviations ......................................................................................................................................1-11

Table 2-1: Single Link Signal Mapping for DVI/HDMI ...............................................................................................................2-5

Table 2-2: Dual-Link Signal Mapping for DVI ..............................................................................................................................2-6

Table 2-3: Support for HDMI Packet Type ....................................................................................................................................2-7

Table 2-4: VGA DAC Characteristics ............................................................................................................................................2-8

Table 3-1: CPU HyperTransport Interface .....................................................................................................................................3-5

Table 3-2: 1 x 16 Lane PCI Express Interface for External Graphics ............................................................................................3-5

Table 3-3: 1 x 4 Lane A-Link Express II Interface for Southbridge ..............................................................................................3-5

Table 3-4: 4 x 1 Lane PCI Express Interface for General Purpose External Devices .................................................................... 3-6

Table 3-5: PCI Express Interface for Miscellaneous PCI Express Signals ....................................................................................3-6

Table 3-6: Clock Interface ..............................................................................................................................................................3-6

Table 3-7: CRT and TV Interface ...................................................................................................................................................3-6

Table 3-8: Integrated DVI/HDMI Interface ....................................................................................................................................3-7

Table 3-9: TMDS Interface Multiplexed on the PCI-E Graphics Interface ....................................................................................3-8

Table 3-10: Power Management Pins .............................................................................................................................................3-9

Table 3-11: Miscellaneous Pins ......................................................................................................................................................3-9

Table 3-12: Power Pins .................................................................................................................................................................3-10

Table 3-13: Ground Pins ...............................................................................................................................................................3-11

Table 3-14: RS690 Debug Po rt Signals ........................................................................................................................................3-11

Table 3-15: Strap Definitions for the RS690 ................................................................................................................................3-12

Table 3-16: Strap Definition for GPPSB_LINK_CONFIG ..........................................................................................................3-13

Table 4-1: HTREFCLK Pad (66.66MHz) Timing Parameters .......................................................................................................4-1

Table 4-2: PCI-E Differential Clock (GFX_CLK, SB_CLK) AC Characteristics .........................................................................4-1

Table 4-3: Timing Requirements for the OSCIN Pad ....................................................................................................................4-1

Table 4-4: RS690 Power Rail Power Up Sequence Requirements .................................................................................................4-3

Table 5-1: Maximum and Minimum Ratings .................................................................................................................................5-1

Table 5-2: DC Characteristics for 3.3V TTL Signals .....................................................................................................................5-2

Table 5-3: DC Characteristics for 1.8V TTL Signals .....................................................................................................................5-2

Table 5-4: DC Characteristics for the HTREFCLK Pad (66.66MHz) ............................................................................................5-2

Table 5-5: DC Characteristics for the OSCIN Pad (14.3181818 MHz) ..........................................................................................5-2

Table 5-6: DC Characteristics for the Integrated DVI/H DMI (Not Appli cable to the RS690C) ...................................................5-3

Table 5-7: DC Characteristics for the TMDS Int erface Multiplexed on the PCI-E Gfx Lanes (Not App licable to the RS690C) .5-3

Table 5-8: RS690 Thermal Limits .................................................................................................................................................. 5-5

Table 5-9: Thermal Parameters for the RS690 ...............................................................................................................................5-5

Table 5-10: RS690 465-Pin FCBGA Package Physical Dimensi ons .............................................................................................5-6

Table 6-1: ACPI States Supported by the RS690 ...........................................................................................................................6-1

Table 6-2: ACPI Signal Definitions ................................................................................................................................................6-1

Table 6-3: Standard PCI Configuration Space Header Type 0 .......................................................................................................6-2

Table 6-4: PCI Status Register ........................................................................................................................................................6-3

Table 6-5: Capabilities Pointer (CAP_PTR) ...................................................................................................................................6-3

Table 6-6: Power Management Register Block ..............................................................................................................................6-3

Table 6-7: Power Management Control/Status Register (PMCSR) ...............................................................................................6-4

Table 6-8: Capability Identifier (Cap_ID) ......................................................................................................................................6-4

Table 6-9: Next It em Pointer (NEXT_ ITEM_PTR) .......................................................................................................................6-5

Table 6-10: Power Management Capabilities – PMC ....................................................................................................................6-5

Table 7-1: Pins on the Test Interface ..............................................................................................................................................7-1

Table 7-2: Example of an XOR Tree .............................................................................................................................................. 7-2

List of Tables-2 Proprietary and Confidential

Table 7-3: RS690 XOR Tree .......................................................................................................................................................... 7-2

Table 7-4: Trut h Table for the VOH/VOL Tree Outputs ............................................................................................................... 7-4

Table 7-5: RS690 VOH/VOL Tree ................................................................................................................................................ 7-5

Proprietary and Confidential 1-1

Chapter 1

Overview

1.1 Introducing the RS690

The RS690 is a seventh generation Integrated Graphics Processor (IGP) that integrates a DirectX 9.0 compliant 2D/3D

graphics core and a system controller in a single chip. It supports the AMD Athlon 64, Athlon 64 FX, Athlon 64 X2, and

Sempron processors, including AM2 socket CPUs. All CPUs are supported on bo th high performance and value

platforms.

The RS690 integrates an ATI Radeon™ X700-based graphics engine, dual display, a TV encoder, an integrated

DVI/HDMI interface, an integrated TMDS controller, and Northbridge functionality in a single BGA package. This high

level of integration and scalability enables manufacturers to offer enthusiast level capabilities and performance while

minimizing board space and system cost.

The RS690 is pin-compatible with AMD's RS485, allowing existing RS485 platforms to easily migrate to the RS690.

Comparing with the RS485, th e RS690 provides additional features with reduced overall system power.

Robust and Flexible Core Logic Features

The RS690 combines graphics and system logic functions in a single chip using a 21mm-body FCBGA package, reducing

overall solution area. For optimal system and graphics performance, the RS690 supp orts a high speed Hyp erTransport

interface to the AMD processor , running at a data rate of up to 2GT/s and supporting the new generation of AM2 socket

processors. The RS690 is ideally suited to 64-bit operating system s, and supports platform config urat ions with greater

than 4GB of system memory. The rich PCI Express expansion capabilities of RS690, including support for PCI Express

external graphics and up to four other PCI Express pe ripherals (or five, when using only 8 lanes for external graphics), are

complemented by the advanced I/O features of AMD's SB600 Southb ridge.

Best for Windows Vista

The RS690 delivers the best Windo ws Vista experience of any integrated graphics and core logic product for the AMD

platform. It incorporates an ATI Radeon™ X700-based graphics core, which provides the 3D rendering power needed to

generate the Windows Vista desktop even under the most demanding circumstances. In addition, dedicated hardware

acceleration is provided for key new Windows Vista features such as ClearType. This ATI Radeon X700-based graphics

technology also enables great 3D application perfor mance through technologies such as SmartShader™ HD,

SmoothVision™ HD, and 3Dc.

Leading Multimedia Capabilities

The RS690 incorporates the innovat ive ATI Avivo™* display architecture, prov idi ng users with visual quality which is

second to none. Advanced scaling and color correction capabilities, along wi th increased precision through the entire

display pipeline, ensure an optimal image on CRT monitors, LCD panel s, and any other display devices. A new TV

encoder , based on designs used in ATI's Xilleon™ products, provides unequalled quality, and fully integrated DVI/HDMI

and HDCP support allows compatibility with even the most modern high definition televisions without the additional cost

of external components.

*Note: ATI Avivo™ is a technology platform that includ es a bro a d set of capabil ities offered by certain ATI Radeon

products. Full enablement of som e ATI Avivo™ capabilities may require complementary products.

Low Power Consumption and Industry Leading Power Management

The RS690 is manufactured using a power efficient 80nm technology, and it supports a whole range of industry standards

and all new proprietary power management features. It provides comprehensive support fo r the ACPI specificati on and

AMD power management features such as PowerNow. The RS690 family inclu des va ri ants with support for dedicated

local display cache memory, which further reduces system power consumption.

Software Compatibility

The graphics driver for the RS690 is fully compatible with all other ATI Radeon class graphics controllers from AMD. A

single driver can support mult ipl e graphics config urations across AMD's product lines, including the ATI Radeon family

1-2 Proprietary and Confidential

RS690C

and the AMD chipset family. In addition, this driver compatibility allows the RS690 to benefit immediately fr om AMD's

software optimization and from the advanced Windows XP and Windows Vista support available in the ATI Radeon

family drivers.

1.2 RS690C

The RS690C is a special variant of the RS690 that supports neither a DVI/HDMI interface nor a TMDS interface that

enables DVI/HDMI. Beyond the difference, all other in format ion in this document applies to both the RS690 and

RS690C, unless otherwise specified.

1.3 RS690 Features

1.3.1 CPU HyperTransport Interface

•Supports the mobile and desktop Athlo n 64/Athlon 64 FX/Athlon X2/Sem pron processors, including AM2 socket

CPUs.

•Supports 200, 400, 600, 800, and 1000MHz HyperTransport (HT) interface speeds.

•Supports LDTSTP interface, CPU throttling, and stutter mode.

1.3.2 ATI HyperMemory™

•Supports ATI HyperMemory™*.

* Note: The amount of HyperMemory available includes both dedicated and shared memory and is determined by various

factors. For details, please refer to the product advisory numbered PA_IGPGenC5, availa ble on AMD ’s OEM Resource

Center or from you AMD CSS representative.

1.3.3 PCI Express Interface

•Compliant with the PCI Express 1.1a Specifications.

•Highly flexible PCI Express implementation to suit a variety of platform needs

•A dual-port, x16 graphics interface, configurable to any of the following modes of support:

•An external graphics device utilizing all 16 lanes.

•[Not applicable to the RS690C] An external graphics device on 8 lane s, and utilizing simultaneously the

remaining 8 lanes to support a TMDS interface, enabling DVI/HDMI (see section 1.3.9, “DVI/HDMI (Not

applicable to the RS690C)” below for details).

•An external graphics device on 8 lanes, and utilizing simultaneously the remaining lanes as a single x1, x2, or x4

general purpose PCI-E link.

•A four-port, x4 PCI Express general purpose interface, configurable to one of the following modes of support:

•Four x1 links.

•Two x2 links.

•One x2 and two x1 links.

•One x4 link.

1.3.4 A-Link Express II Interface

•One x4 A-Link Express II interface (PCI Express 1.1 compliant) for connection to an AMD Southbridge, providing

more bandwidth than the older A-Link Express interface.

1.3.5 2D Acceleration Features

•Highly-optimized 128-bi t engine, capable of processing multiple pixels per clock.

•Hardware acceleration of Bitblt, Line Draw, Polygon / Rectangle Fill, Bit Masking, Monochrome Expansion,

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Panning/Scrolling, Scissoring, and full ROP support (including R OP3).

•Optimized handling of fonts and text using AMD proprietary techniqu es.

•Hardware acceleration for ClearType font rendering.

•Game acceleration including support for Microsoft's DirectDraw: Double Buffering, Virtual Sprites, T ransparent Blit,

and Masked Blit.

•Supports a maximum resol ution of 2048x1536 @ 32bp p for a maximum pixel clock speed of 400MHz

(driver-limited).

•Acceleration in 1/8/15/16/32 bpp modes:

•ClearType mode for 1bpp

•Pseudocolor mode for 8bp p

•ARGB1555 and RGB565 modes for 16bpp

•ARGB8888 mode for 32bpp

•Significant increase in the High-End Graphi cs WinBench score due to capability for C18 color expansion.

•Setup of 2D polygons and lines.

•Support for new GDI extensions in Windows 2000 and Windows XP: Alpha BLT, Transparent BLT, Gradient Fill.

•Hardware cursor (up to 64x64x32bpp), with alpha channel for direct support of Windows 2000 and Windows XP

alpha cursor.

1.3.6 3D Acceleration Features

•Multi-texturing via one texture blending unit per pixel pipes, allowing up to 512 texel reads per pixel in a single pass.

•3D Texture support, including projective 3D textures.

•Comprehensive support for bump mapping: emboss, dot-produ ct, and environment bump maps.

•Improved precision in anisotropic filtering and bilinear filtering.

•Supports a maximum resol ution of 2048x1536 @ 32bp p for a maximum pixel clock speed of 400MHz

(driver-limited).

•Complete 3D primitive supp ort: points, lines, triangles, lists, strips and quadrilaterals and BLTs with Z compare.

•Improved texture compositing.

•Hidden surface removal using 16, 24, or 32-bit Z-buffering (maximum Z-buffer depth is 24 bits when stencil buffer

enabled) and Early Z hardware.

•8-bit stencil buffer.

•Bilinear and trilinear texture filtering.

•Full support of Direct3D texture ligh ting.

•Dithering support in 16 bpp for near 24 bpp quality in less memory.

•Extensive 3D mode support.

•Anti-aliasing using multi-sampling algorithm with supp ort for 2, 4, and 6 sam ples.

•Optimized for full performance in true color triple buffered 32bpp acceleration modes.

•New generation rendering engine provides top 3D performance.

•Support for OpenGL format for Indirect Vertices in Vertex Walker.

•Full DirectX 9.0 support (Vertex Shader version 2.0 and Pi xel Shader version 2.0):

•Full precision floating point pixel pipeline.

•Support for up to 4 MRTs (Multiple-Render-Targets).

•Support for writing all texture formats from render pipe in floating points (including cube mapes and 3D

textures).

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RS690 Features

•Support for up to 512b per pixel form ats (4 color case).

•Advanced setup engine, capable of processing 1 pol ygon (lit and textured) per cycle

1.3.7 Motion Video Acceleration Features

•Enhanced MPEG-2 hardware decode acceleration, including support for:

•Integrated general purpose iDCT engine for MPEG2 and DV decode acceleration.

•Integrated MPEG motion comp ensation engine for decode acceleration.

•Parallel operation of the iDCT and MC and high pro cessing rates with minimal soft ware overhead.

•Provides dramatically reduced CPU utilization without incurring the cost of a full MPEG-2 decod er.

•MPEG-4 simple profile support.

•Hardware acceleration for WMV9 playback.

•Supports top quality DVD with low CPU usage.

•Hardware-based adaptive de-interlacing filter and scaler provide high quality full-screen and full-speed video

playback. Minimizes the aliasing artifacts along edges usually caused by a conventional deinterlacer/scaler.

1.3.8 Multiple Display Features

General

•[Not applicable to the RS690C] Dual independe nt displays. Possible configurations include:

•CRT and DVI/HDMI

•TV (component, composite, or S-Video) and DVI/HDMI

•DVI and DVI*

•DVI and HDMI*

Note: * The options require implementation of th e TMDS interface that is multiplexed on the PCI-E external

graphics interface; see section 1.3.9, “DVI/HDMI (Not applicable to the RS690C),” on page 5.

•[Not applicable to the RS690C] Resolution, refresh rates, and display data can be completely independent for the two

display paths.

•Each display controller supports true 30 b its per pixel throughout the display pipe .

•Each display path supports VGA and accelerated modes, video overlay, hardware cursor, hardware icon, and palette

gamma correction.

•Supports both interlaced and non-interlaced displays.

•Support for display modes up to 2880 pixels/line per display.

•Full ratiometric expansion ability is supported for source desktop modes up to 1920 pixels/line.

•HD TV support (with underscan) for display modes of 1920 or less pixels/line.

•SD TV support (with underscan) for display modes of 1024 or less pixels/ line.

•Maximum DAC frequency of 400 MHz.

•Supports 8, 16, 32 & 64-bpp depths for the main graphics layer:

•For 32-bpp depth, supports xRGB 8:8:8:8, xRGB 2:10:1 0:10, sCrYCb 8:8:8:8, and xCrYCb 2:10:10:10 data

formats.

•For 64-bpp depth, supports xRGB 16:16:16:16 data format.

•Independent gamma, color conversion and corr ecti on controls for main graphics layer.

•Supports display resolutions beyond 2560x1600.

•Support for DDC1 and DDC2B+ for plug and play moni tors.

•8-bit alpha blending of graphics and video overlay.

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•Hardware cursor up to 64x64 pixels in 2bpp, full color AND/XOR mix, and full col or 8-bit alpha blend.

•Hardware icon up to 128x128 pixels in 2bpp, with two colors, transparent, and inverse transparent. AND/XOR

mixing. Supports 2x2 icon magnification.

•Virtu a l desktop support.

•Support for flat panel di splays via VGA, DVI (not appl icable to the RS690C), or HDMI (not applicable to the

RS690C).

•[Not applicable to the RS690C] Integrated HD Audi o Cont roller for HDMI audio data.

•Support for stereoscopic monitors.

TV Out

•An integrated TV encoder from AMD’s Xilleon™ products, with an on-chip DAC (shared with the CRT analog

output) (Note: Simultaneous output for TV and CRT is not supported).

•10-bit DAC with 10-tap filter producing scaled, flicker removed, artifact suppressed display on a PAL or NTSC TV

with composite, S-Video, component, and RGB output.

•W ith the proper BIOS implementation, supports different TV standards including NTSC, NTSC-J, PAL-M, PAL-CN,

PAL-B, PAL-G, PAL-D, PAL-H, PAL-I, PAL-K, and PAL- N.

•Supports Macrovision 7.1 copy protection standard (required by DVD players).

•Supports a maximum resol ution of 1024x768.

•Supports the following formats of YPbPr component output: 480i, 480p, 576i, 576p, 720p, and 1080 i.

•Internal adaptive flicker filtering available on both display paths for interlaced TV outputs.

•Supports fully-programmabl e 2D, adaptive comb filter for composite output.

•TV-out power management support.

•Line 21 Closed Caption and Extended Data Service support for encoding in Vertical Blanking Interval (VBI) of TV

signal.

•CGMS copy management support in VBI through Line-20 and/or Extended Data Service (Line-21 Field 2) for

NTSC, and through Wide Screen Signaling data (WSS) for PA L.

SURROUNDVIEW

•RS690’s SURROUNDVIEW™ feature allows support for up to three independent monitors for systems equipped

with an additional ATI discrete graphics card (require s special BIOS and displa y driver support).

1.3.9 DVI/HDMI (Not applicable to the RS690C)

•Integrated DVI or HDMI interface: single-link support only for HDMI‡, 30-bit dual-link support for DVI.

•Also supports a TMDS interface, enabling DVI or HDMI, which is multiplexed on the PCI-E external graphics

interface (only available if no external graphics card, or only a x8 one, is attached to the PCI-E external graphics

interface).‡

•1650 Mbps/channel† with 165 MHz† pi xel clock rate per link.

•Supports industry standard EVA-861B video modes incl uding 480p, 720p, and 1080i. For a full list of currently

supported modes, contact your AMD CSS representative.

•HDMI basic audio support at 32, 44.1, and 48 kHz. Supports two-channel uncom presse d audio and multi-channel

audio compressed to two channels like 5.1 AC3 and DTS. HD Au dio device compatible with Microsoft HD audio

drivers.

•HDCP support on data stream for single-link transmission, with on-chip key storage (available only on either one of

the integrated DVI/HDMI interface or the TMDS interface (multiplexed on the PCI-E graphics lanes) at any time).**

Notes: * CEC is not supported.

† To be qualified.

1-6 Proprietary and Confidential

Software Features

** HDCP content protection is only available to licensed buyers of the technology and can only be enabled when

connected to an HDCP-capable receiver.

‡ The TMDS interface multiplexed on the PCI-E graphics lanes cannot enable HDMI when the integrated

DVI/HDMI interface is supporting HDMI, and vice versa.

1.3.10 Power Management Features

•Fully supports ACPI states S1, S3, S4, and S5.

•The Chip Power Management Support logic supports four device power states defined for the OnNow Architecture—

On, Standby, Susp end, and Off. Each power state can be achieved by software control bits.

•Hardware control led int e lli gent clock gating enables clocks only to active functional blocks, and is complet e ly

transparent to software.

•Support for Cool'n'Quiet™ via FID/VID change.

•Support for PowerNow™.

•Clocks to every major functional bl ock are cont rolled by a unique dynamic clock switching technique that is

completely transparent to the software. By turning off the clock to the block that is idle or not used at that point, the

power consumption is significantly reduced during normal operati on.

•Supports .

•Support dynamic lane reduction for the PCI-E interfaces, adjusting lane width according to required bandwidth.

1.3.11 PC Design Guide Compliance

The RS690 complies with all relevan t Win dows Logo Program (WLP) requirements from Microsoft for WHQL

certification.

1.3.12 Test Capa bility Features

The RS690 has a variety of test modes and capabilities that provide a very high fault coverage and low DPM (Defect Per

Million) ratio:

•Full scan implementation on the di gital core logic through ATPG (Automatic Test Pattern Generation Vectors).

•Dedicated test logic for the on-chip custom memory macros to provide complete coverage on these modules.

•A JTAG test mode to allow board level testing of neighboring devices.

•An EXOR tree test mode on all the digital I/O's to allow for proper soldering verification at the board level.

•A VOH/VOL test mode on all digital I/O’s to allow for proper verification of output high and output low values at the

board level.

•Improved access to the analog modules to allow full evaluation and characterization.

•Improved IDDQ mode support to allow chip evaluati on through current leakage measurements.

These test modes can be accessed through the settings on the instruction register of the JTAG circuitry.

1.3.13 Packaging

•Single chip solution in 80nm , 1.2V low power CMOS technology.

•465-FCBGA package, 21mm x21mm.

1.4 Software Features

•Supports Microsoft Windows 2000, XP, and Vista.

•BIOS ability to read EDID 1.1, 1.2, and 1.3.

•Ability to selectively enable and disab le several devices including CRT, LCD, TV, and DFP.

•Register-compatible with VGA standards, BIOS-compatible with VESA VBE2.0.

Branding Diagram s

Proprietary and Confidential 1-7

•Supports corporate manageability requirements such as DMI.

•ACPI support.

•Full Writ e Combining support for maximum performance of the CPU.

•Full-featured, yet simple Windows utilities:

•Calibration utility fo r WYSIWYG color

•Independent brightness control of desktop and overlay

•End user diagnostics

•Drivers meet Microsoft's rigorous WHQL criteria and are suitable for systems with the "Designed for Windows"

logos.

•Comprehensive OS and API support.

•Hot-key support (Windows ACPI 1.0b or AMD Event Handler Utility where appropriate).

•Extensive power management support.

•Rotation mode support in software.

•Dual CRTC, simultaneous view, extended desktop support (Win98, Win XP)

•DirectX 9.0 support.

•Switchable overlay support.

•H.264 playback support.

1.5 Branding Diagrams

1.5.1 Branding Diagrams for ASIC Revision A11

GGGGG

YYWWXXV

215RQA6AVA11FG

TAIWAN

RS690

* YY - Assembly Star t Year

WW - Assembly Start Week

XX - Assembly Location

V - Substrate Vendor Code

Part Number (for ASIC revision A11)

Country of Origin

Date and Other Codes*

Wafer Foundry’s Lot Number

AMD Code Name

Artwork

1-8 Proprietary and Confidential

Branding Diagrams

Figure 1-1 RS690-variant Branding Diagrams for ASIC Revision A11

1.5.2 Branding Diagrams for ASIC Revision A12 and After

GGGGG

YYWWXXV

215CQA6AVA11FG

TAIWAN

RS690C

* YY - Assembly Start Year

WW - Assembly Start Week

XX - Assembly Location

V - Substrate Vendor Code

Part Number (for ASIC revision A11)

Country of Origin

Date and Other Codes*

Wafer Foundry’s Lot Number

AMD Code Name

Artwork

RS690

215RQA6AVA12FG

XXXXXX.XX.XXX

YYWWSSV

TAIWAN

* YY - Assembly S ta rt Ye ar

WW - Assembly Start Week

SS - Assembly Loc ation

V - Substrate Vendor Code

Part Number (for ASIC revision A12)

Country of Origin

Date and Other Codes*

Wafer Foundry’s Lot Number

AMD Code Name

AMD Logo

Part Number Legend

Proprietary and Confidential 1-9

Note: The branding diagrams above do not necessarily contain the latest ASCI revision numbers for the IGPs. Unless specified otherwise, no

information in this databook is specific to the ASIC revision numbers given in the diagrams.

Figure 1-2 RS690-variant Branding Diagrams for ASIC Revision A12

1.6 Part Number Legend

Figure 1-3 The RS690-Family ASIC Part Number Legend

RS690C

215CQA6AVA12FG

XXXXXX.XX.XXX

YYWWSSV

TAIWAN

* YY - Assembly Start Year

WW - Assembly Start Week

SS - Assembly Location

V - Substrate Vendor Code

Part Number (for ASIC revision A12)

Country of Origin

Date and Other Codes*

Wafer Foundry’s Lot Number

AMD Code Name

AMD Logo

TSMC Fab

215 RQA6 AVA12 FG

215 – Desktop

216 – Mobile

Product Type

TQA6 -RS690T

Marketing

Brand Name

Substrate

Revision

N – UMC Fab 8F

M – IBM

C 3

S TSMC Fab 4

F TSMC Fab5

G TSMC Fab6

K TSMC Fab12

L TSMC Fab14

W TSMC WSMC

Q TSMC WSMC ( 8B)

T TSMC Wafer Tech

Foundry Code

ASIC

Revision

Blank – No

F –Yes

Flip Chip

K – High Temp

G – Lead Free

Package BOM

–

NQA6 -RX690

LQA6 -RS690MC

RQA6 -RS690

V –

–

UMC Fab 12A

MQA6 -RS690M

CQA6 -RS690C

1-10 Proprietary and Confidential

Conventions and Notations

1.7 Conventions and Notations

The following conventions are used throughout this manual.

1.7.1 Pin Names

Pins are identified by their pin names or ball references. Multiplexed pins assume alternate “functional names” when they

perform their alternate functions, and these “functional names” are given in Chapter 3, “Pin Descri ptions and Strap

Options.”

All active-low signal s are identified by the suffix ‘# ’ in their names (e.g., MEM_RAS#).

1.7.2 Pin Types

The pins are assigned different codes according to their operational characteristics. These codes are listed in Table 1-2.

1.7.3 Numeric Representation

Hexadecimal numbers are appended with “h” (Intel assembly-style notation) whenever there is a risk of ambiguity. Other

numbers are in decimal.

Pins of identical functions but different trailing integers (e.g., “CPU_D0, CPU_D1,... CPU_D7”) are referred to

collectively by specifying their integers in square brackets and with colons (i.e., “CPU_D[7:0]”). A similar short-hand

notation is used to indicate bi t occupat ion in a register. For example, NB_COMMAND[15:10 ] refers to the bit positions

10 through 15 of the NB_COMMAND register.

Table 1-1 RS690-Family ASIC Part Numbers

Code Name Part Number

RS690 215RQA6AVA12FG

RS690C 215CQA6AVA12FG

RS690M 216MQA6AVA12FG

RS690MC 216LQA6AVA12FG

RS690T 216TQA6AVA12FG

RX690 215NQA6AVA12FG

Table 1-2 Pin Type Codes

Code Pin Type

I Digital Input

O Digital Output

OD Open Drain

I/O Bi-Directional Digital Input or Output

M Multifunctional

Pwr Power

Gnd Ground

A-O Analog Output

A-I Analog Input

A-I/O Analog Bi-Directional Input/Output

A-Pwr Analog Power

A-Gnd Analog Ground

Other Pin types not included in any of the categories above

Conventions and Notations

Proprietary and Confidential 1-11

1.7.4 Register Field

A field of a register is referred to by the f orm at of [Register Name].[Register.Field]. For example,

“NB_MC_CNTL.DISABLE_BYPASS” is the “DISABLE_BYPASS” field of the register “NB_MC_CNTL.”

1.7.5 Hyperlinks

Phrases or sentences in blue italic font are hyperlinks to other parts of the manual. Users of the PDF version of this manual

can click on the links to go directly to the referenced sections, tables, or figures.

1.7.6 Acronyms and Abbreviations

The following is a list of the acronyms and abbreviations used in this manual.

Table 1-3 Acronyms and Abbreviations

Acronym Full Expression

ACPI Advanced Configuration and Power Interface

A-Link-E II A-Link Express II interface between the IGP and the Southbridge.

BGA Ball Grid Array

BIOS Basic Input Output System. Initialization code stored in a ROM or Flash RAM used to start up a

system or expansion card.

BIST Built In Self Test.

BLT Blit

bpp bits per pixel

CEC Consumer Electronic Control

CPIS Common Panel Interface Specification

CRT Cathode Ray Tube

CSP Chip Scale Package

DAC Digital to Analog Converter

DBI Dynamic Bus Inversion

DDC Display Data Channel. A VESA standard for communicating between a computer system and

attached display devices.

DDR Double Data Rate

DFP Digital Flat Panel. Monitor connection standard from VESA.

DPM Defects per Million

DTV Digital TV

DVD Digital Video Disc

DVI Digital Video Interface. Monitor connection standard from the DDWG (Digital Display Work

Group).

DVS Digital Video Stream

EPROM Erasable Programmable Read Only Memory

FIFO First In, First Out

FPDI Flat Panel Display Interface

GDI Graphics Device Interface

GND Ground

GPIO General Purpose Input/Output

GTL+ Gunning Transceiver Logic

HDCP High-Bandwidth Digital Content Protection

HDMI High Definition Multimedia Interface

HDTV High Definition TV. The 1920x1080 and the 1280x720 modes defined by ATSC.

HPD Hot Plug Detect

iDCT inverse Discrete Cosine Transform

IDDQ Direct Drain Quiescent Current

1-12 Proprietary and Confidential

Conventions and Notations

IGP Integrated Graphics Processor. A single device that integrates a graphics processor and a

system controller.

JTAG Joint Test Access Group. An IEEE standard.

MB Mega Byte

MPEG Motion Pictures Experts Group. Refers to compressed video image streams in either MPEG-1

or MPEG-2 formats.

NTSC National Television Standards Committee. The standard definition TV system used in North

America and other areas.

PAL Phase Alternate Line. The standard definition TV system used in Europe and other areas.

PCI Peripheral Component Interface

PCI-E PCI Express

PCMCIA Personal Computer Memory Card International Association. It is also the name of a standard

for PC peripherals promoted by the Association.

PLL Phase Locked Loop

POST Power On Self Test

PD Pull-down Resistor

PU Pull-up Resistor

ROP Raster Operation

SDRAM Synchronous Dynamic RAM

TMDS Transition Minimized Differential Signaling

UMA Unified Memory Architecture

UV Chrominance (also CrCb). Corresponds to the color of a pixel.

UXGA Ultra Extended Graphics Array

VBI Vertical Blank Interval

VESA Video Electronics Standards Association

VGA Video Graphics Adapter

VRM Voltage Regulation Module

Table 1-3 Acronyms and Abbreviations (Continued)

Acronym Full Expression

Proprietary and Confidential 2-1

Chapter 2

Functional Descriptions

This chapter describes the functional operation of the major interfaces of the RS690 system logic chip. Figure 2-1,

“RS690 Internal Block Diagram,” illustrates the RS690 internal bl ocks and interfaces.

Figure 2-1 RS690 Internal Block Diagram

Hyper-

Transport

Unit

CPU

Interface

iDCT Setup

Engine 2D

Engine

Overlay

Root

MUX

Display 1& 2

Integrated DVI/HDMI*

TV-Out

TMDS, enabling DVI/HDMI

CRT

Memory Controller

CPU

BIF

External

Graphics Complex

A-Link-E II Gfx Interf ace

PCI-E

Interface

(1 x 16 Lanes)

GPP Interface

PCI-E

(4 x 1 Lanes)

Expansion

Slots or

On-board

Devices

(1 x 4 Lanes)

(Multiplexed on PCI-E Gfx Lanes)*

* Not applicable to the RS690C.

2-2 Proprietary and Confidential

Host Interface

2.1 Host Interface

The RS690 is optimized to interface with the AMD Athlon 64/Athlon 64 FX/Athlon X2/Sempron processors, including

AM2 socket CPUs. This section presents an overview of the HyperTransport interface. For a detailed description of the

interface, please refer to the HyperTransport I/O Link Specification from the HyperTransport Consortium. Figure 2-2,

“Host Interface Block Diagram,” illustrates the basic blocks of the host bus interface of the RS690.

Figure 2-2 Host Interface Block Diagram

The HyperTransport (HT) Interface, formerly known as the LDT (Lightning Data Transport) interface, is a high speed,

packet-based link implemented on two unidirectional buses. It is a point-to-point interface where data can flow both

upstream and downstream at the same time. The commands, addresses, and data travel in packets on the Hy perTran s port

link. Lengths of packets are in mult ipl e s of four bytes. The HT li nk consist s of three parts: the physical layer (PHY), th e

data link layer, and the protocol/transaction layer. The PHY is the physical interface between the RS690 and the CPU.

The data link layer includes the initialization and configuration sequences, periodic redundancy checks,

connect/disconnect sequences, and information packet flow controls. The protocol layer is responsible for maintain ing

strict ordering rules defined by the HT protocol.

The RS690 HyperTransport bus interface consists of seventeen unidirectional differential data/control pairs and two

differential clock pairs in each of the upstream and downstream direction. On power up, the HT link is 8-bit wide and runs

at a default speed of 200MT/s. After negotiation, carried out by the HW and SW together, the link wid th can be bro ught

up to 16-bit and the interface can run up to 2GT/s. The interface is illustrated below in Figure 2-3, “RS690 Host Bus

Interface Signals.” The signal name and direction for each signal is shown with respect to the processor. Please note that

the signal names may be different from those used in the pin listing of the RS690. Detailed descriptions of the signals are

given in section 3.3, “CPU HyperTransport Interface‚’ on page 3-5.

HT Interface to CPU (PHY)

Configuration

Registers

Root Complex Memory Controller

LTA LRA

SCH

Data Link La ye r

Protoco l/ T r a nsaction Laye r

Host Interface

Proprietary and Confidential 2-3

Figure 2-3 RS690 Host Bus Interface Signals

HT_RXCADN

RS690

AMD CPU

HT_TXCALP

HT_RXCALN

HT_RXCALP

VDD_HT

HT_TXCALN

HT_RXCADP

HT_RXCTLN

HT_RXCTLP

HT_RXCLKN

HT_RXCLKP

HT_TXCADN

HT_TXCADP

HT_TXCTLN

HT_TXCTLP

HT_TXCLKN

HT_TXCLKP

2-4 Proprietary and Confidential

DVI/HDMI (Not Applicable to the RS690C)

2.2 DVI/HDMI (Not Applicable to the RS690C)

2.2.1 DVI/HDMI Data Transmission Order and Signal Mapping

The RS690 contains an integrated DVI/HDMI interface and a TMDS interface (multiplexed on the PCI-E graphics lanes),

both supporting clock frequencies of up to 165 MHz for each signal link. Figure 2-4 below shows the transmission

ordering of the signals on both interfaces in single-link mode.

Figure 2-4 Data Transmission Ordering for the Integrated DVI/HDMI and TMDS Interfaces

For dual-link mode, which is for DVI only, the same transmissio n order applies to data channels on the second link, with

the first link transmitting data for even pixels and the second lin k for odd pi xels. See Table 2-2 below for details.

The signal mapping for the transmission is shown in Table 2-1 (single link) and Table 2-2 (dual-link DVI) below.

TX0P

TX0M

TX1P

TX1M

TX2P

TX2M

TXCP

TXCM

TG9TG8TG7TG6TG5TG4TG3TG2TG1TG0

Depending upon state of HSYNC and VSYNC

Depending upon encoded Green channel pixel dataDepending upon state of PLL_SYNC and CTL1

Depending upon sta te of CTL2 a nd CTL3

TR1TR0 TR2 TR3 TR4 TR5 TR6 TR7 TR8 TR9

Depending upon encoded Red channel p ixel data

TB0 TB1 TB2 TB3 TB4 TB5 TB6 TB7 TB8 TB9

Depending upon encoded Blue channel pixel data

Various control and audio (for HDMI only) signals

Various control and audio (for HDMI only) s ignals

Encoded Red Channel Pixel Data

Encoded Green Channel Pixel Data

Encoded Blue Chan ne l Pi xel Da ta

DVI/HDMI (Not Applicable to the RS690C)

Proprietary and Confidential 2-5

Table 2-1 Single Link Signal Mapping for DVI/ HDMI

DVI/HDMI

Functional Name Data Phase Signal

TX0M/P Phase 1 B0

Phase 2 B1

Phase 3 B2

Phase 4 B3

Phase 5 B4

Phase 6 B5

Phase 7 B6

Phase 8 B7

Phase 9 B8

Phase 10 B9

TX1M/P Phase 1 G0

Phase 2 G1

Phase 3 G2

Phase 4 G3

Phase 5 G4

Phase 6 G5

Phase 7 G6

Phase 8 G7

Phase 9 G8

Phase 10 G9

TX2M/P Phase 1 R0

Phase 2 R1

Phase 3 R2

Phase 4 R3

Phase 5 R4

Phase 6 R5

Phase 7 R6

Phase 8 R7

Phase 9 R8

Phase 10 R9

Note: H/VSYNC are transmitte d on TX0M /P(Blue) cha nnel d urin g blan k.

2-6 Proprietary and Confidential

DVI/HDMI (Not Applicable to the RS690C)

Table 2-2 Dual-Link Signal Mapping for DVI

Link 1 Link 2

DVI Functional

Name Data Phase Signal DVI Functional

Name Data Phase Signal

TX0M/P Phase 1 EVEN_B0 TX3M/P Phase 1 ODD_B0

Phase 2 EVEN_B1 Phase 2 ODD_B1

Phase 3 EVEN_B2 Phase 3 ODD_B2

Phase 4 EVEN_B3 Phase 4 ODD_B3

Phase 5 EVEN_B4 Phase 5 ODD_B4

Phase 6 EVEN_B5 Phase 6 ODD_B5

Phase 7 EVEN_B6 Phase 7 ODD_B6

Phase 8 EVEN_B7 Phase 8 ODD_B7

Phase 9 EVEN_B8 Phase 9 ODD_B8

Phase 10 EVEN_B9 Phase 10 ODD_B9

TX1M/P Phase 1 EVEN_G0 TX4M/P Phase 1 ODD_G0

Phase 2 EVEN_G1 Phase 2 ODD_G1

Phase 3 EVEN_G2 Phase 3 ODD_G2

Phase 4 EVEN_G3 Phase 4 ODD_G3

Phase 5 EVEN_G4 Phase 5 ODD_G4

Phase 6 EVEN_G5 Phase 6 ODD_G5

Phase 7 EVEN_G6 Phase 7 ODD_G6

Phase 8 EVEN_G7 Phase 8 ODD_G7

Phase 9 EVEN_G8 Phase 9 ODD_G8

Phase 10 EVEN_G9 Phase 10 ODD_G9

TX2M/P Phase 1 EVEN_R0 TX5M/P Phase 1 ODD_R0

Phase 2 EVEN_R1 Phase 2 ODD_R1

Phase 3 EVEN_R2 Phase 3 ODD_R2

Phase 4 EVEN_R3 Phase 4 ODD_R3

Phase 5 EVEN_R4 Phase 5 ODD_R4

Phase 6 EVEN_R5 Phase 6 ODD_R5

Phase 7 EVEN_R6 Phase 7 ODD_R6

Phase 8 EVEN_R7 Phase 8 ODD_R7

Phase 9 EVEN_R8 Phase 9 ODD_R8

Phase 10 EVEN_R9 Phase 10 ODD_R9

Notes:

- H/VSYNC are transmitt ed o n TX0 M/P(Blue) ch annel d uring b la nk.

- For DVI dual-link mode, the first active d ata pixel is defined as pixel#0 (an even pixel), as op posed t o t he DVI spe cifications.

DVI/HDMI (Not Applicable to the RS690C)

Proprietary and Confidential 2-7

2.2.2 Support for HDMI Packet Types

Table 2-3 Support for HDMI Packet Type

Packet

Value Packet Type Supported

or Not Source Comment

0x00 Null Yes Inserted by hardware if no packets in

horizontal active on line 2 (can be disabled

by software).

Sent when required to m eet

maximum time between data island

specification.

0x01 Audio Clock

Regeneration Yes

Inserted by hardware or video driver.

Contents from re gist er bits or combination

of register bits a nd h ardware contro l.

Inserted in horizont al b lank.

—

0x02 Audio Sample Yes

Audio samples come from HD audio DMA.

Channel status from HD a udio a nd video

registers.

Inserted in horizont al blank whenever audio

FIFO contains dat a.

—

0x03 General Control No

Sending and contents controlled by video

driver.

Inserted (on even frames only in inte rla ced

mode) when requested by software or

whenever AVMUTE st atus cha nges.

Inserted in horizont al active on line selected

by software.

—

0x04 ACP Packet Yes* — Audio content protection information.

0x05 ISRC1 Packet Yes Controlled by video driver.

Inserted in horizont al active on line selected

by software. For transmitting UPC or ISRC cod es.

0x06 ISRC2 Packet Yes Software controlled.

Inserted in horizont al active on line selected

by software. Implement if ISRC1 is used.

0x07 Reserved N/A N/A N/A

InfoFrame Packet Type

HDMI ID EIA-861B

0x80 0x00 Vendor-Specific Yes* — —

0x81 0x01 AVI Yes Controlled by video driver.

Inserted in horizont al active on line selected

by software.

For colorimetry, repetit io n coun t,

video format, picture form atting .

0x82 0x02 Source Product

Descriptor Yes* — —

0x83 0x03 Audio Yes

Inserted in horizont al active on line selected

by software.

Contents from re gist ers written by video

and HD audio drivers.

Sent only when HD au dio en ables au dio

(video driver can also disable).

For channel counts, sampling

frequency, etc.

0x84 0x04 MPEG Source Yes Software controlled.

Inserted in horizont al active on line selected

by software. For bit rate, field repeat, f rame type

* Note: These packet type s are sup porte d using g eneric packet types. A maximum of two of the m can be sup ported simultaneously.

2-8 Proprietary and Confidential

VGA DAC Characteristics

2.3 VGA DAC Characteristics

Notes:

1 - Tested over the operating temperature range at nominal supply voltage, with an Iref of -1.50mA (Iref is the level of the current flowing

out of the RSET resistor).

2 - Tested over the operating temperature range at reduced supply voltage, with an Iref of -1.50mA (Iref is the level of the current flowing

out of the Rset resistor).

3 - Full scale error from the value predicted by the design equations.

4 - About the mid-point of the distribution of the three DACs measured at full scale deflection.

5 - Linearity measured from the best fit line through the DAC characteristics. Monotonicity guaranteed.

6 - Load = 37.5Ω + 20 pF with Iref = -1.50 mA (Iref is the current flowing out of the Rset resistor).

7 - Measured from the end of the overshoot to the point where the amplitude of the video ringing is down to +/-5% of the final steady state

value.

8 - This parameter is sampled, not 100% tested.

9 - Monotonicity is guaranteed.

10 - Levels are 7.8% higher with setup pedestal enabled.

2.4 External Clock Chip

On the RS690 platform, an external cloc k chip provi des the reference clock to the CPU (for generatin g the CPU internal

clocks) and a reference clock to the RS690 (for generating the HyperTransport, PC I Express, and A-Link Express II

clocks). For more information abo ut supported clock chips, please consul t you r AMD CSS representative.

Table 2-4 VGA DAC Characteristics

Parameter Min Typ Max Notes

Resolution 10 bits - - 1

Maximum PS/2 setting Output Voltage - 0.7V - 1, 10

Maximum PS/2 setting Output Current - 18.7mA - 1, 10

Full Scale Error +8% / -3% - +10% 2, 3

DAC to DAC Correlation -2% - +2% 1, 4

Differential Linearity -2 LSB - +2 LSB 1, 5

Integral Linearity -2 LSB - +2 LSB 1, 5

Rise Time (10% to 90%) 0.58ns - 1.7ns 1, 6

Full Scale Settling Time - TBA - 1, 7, 8

Glitch Energy - TBA - 1, 8

Monotonicity - - - 9

Proprietary and Confidential 3-1

Chapter 3

Pin Descriptions and Strap Options

This chapter gives the pin descriptions and the strap options for the RS690. To jump to a to pic of interest, use the

following list of hyperlinked cross references:

“Pin Assignment Top View” on page 3-2

“Interface Block Diagram” on page 3-4

“CPU HyperTransport Interface” on page 3-5

“PCI Express Interfaces” on page 3-5:

“1 x 16 Lane Interface for External Graphics” on page 3-5

“A-Link Express II to Southbridge” on page 3-5

“4 x 1 Lane Interface for General Purpose External Devices” on page 3-6

“Miscellaneous PCI Express Signals” on page 3-6

“Clock Interface” on page 3-6

“CRT and TV Interface” on page 3-6

“Integrated DVI/HDMI Interface” on page 3-7

“TMDS Interface Multiplexed on the PCI-E Graphics La nes (Not Applicab le to the RS690C)” on page 3-8

“Power Management Pins” on pa ge 3-9

“Miscellaneous Pins” on page 3-9

“Power Pins” on page 3-10

“Ground Pins” on page 3-11

“Debug Port Signals” on page 3-1 1

“Strapping Options” on page 3-12

3-2 Proprietary and Confidential

Pin Assignment Top View

3.1 Pin Assignment Top V iew

The figures below only represent the relative ball posi tions. For the actual physical layout of the balls, please refer to

Figure 5-3, “RS690 Ball Arrangement,” on page 5- 7.

Figure 3-1 RS690 Pin Assignment Top View (Left)

12345678910111213

AVSSA I2C_CLK STRP_DATA VDD_CORE DACHSYNC DACSDA VDD_CORE DFT_GPIO5 VDD_CORE PLLVDD18 PLLVDD12 LVDDR18D TXOUT_L1N

BVDDA_12 BMREQ# DDC_DATA I2C_DATA ALLOW_LDTSTOP DACSCL VSS DFT_GPIO4 VDD_CORE PLLVSS OSCIN LVDDR18D TXOUT_L1P

CVDDA_12 TVCLKIN TESTMODE VSS LDTSTOP# DACVSYNC DFT_GPIO3 DFT_GPIO2 VDD_CORE SYSRESET# POWERGOOD LVDDR33 LVDDR33

DVDDA_12 VDDA_12 VDDA_12 VSS DFT_GPIO0 DFT_GPIO1 VDD_CORE VDDR3 LVSSR

EGFX_CLKN VDDA_12 VDDA_12 VDDA_12 VDD_PLL VSS VDDR3 GPIO3

FVSSA GFX_CLKP VSSA VDDA_12 VDD_PLL VSS_PLL VSS GPIO4

GSB_CLKP SB_CLKN VSSA GFX_RX0N GFX_RX0P VSSA VDDA_12 VSS_PLL VSS GPIO2

HVSSA GFX_TX0N VSSA VDD_CORE VSS

JGFX_TX0P VSSA VSSA GFX_RX2P GFX_RX2N VSSA GFX_RX1N GFX_RX1P VDD_CORE VSS

KGFX_TX1N GFX_TX1P GFX_TX2P

LGFX_TX3P GFX_TX3N GFX_TX2N GFX_RX4P GFX_RX4N VSSA GFX_RX3N GFX_RX3P VDDA_12 VDD_CORE VSS VDD_CORE

MVDDA_12_PKG VSSA VSSA GFX_RX6P GFX_RX6N VSSA GFX_RX5N GFX_RX5P VDDA_12 VSS VDD_CORE VSS

NGFX_TX4N GFX_TX4P VSSA VDD_CORE VSS VDD_CORE

PGFX_TX5N GFX_TX5P GFX_TX6P GFX_RX8P GFX_RX8N VSSA GFX_RX7N GFX_RX7P VSSA VSS VDD_CORE VSS

RGFX_TX7P GFX_TX7N GFX_TX6N GFX_RX9P GFX_RX9N VSSA GFX_RX10P GFX_RX10N VSSA VDD_CORE VSS VDD_CORE

TVSSA GFX_TX8P VSSA

UGFX_TX8N VSSA VSSA GFX_RX11P GFX_RX11N VSSA VDDA_12 VDD_CORE VDD_CORE

VGFX_TX9N GFX_TX9P GFX_TX10P GFX_RX14P VSSA VSSA

WGFX_TX11P GFX_TX11N GFX_TX10N GFX_RX12P GFX_RX12N VSSA VDDA_12 GFX_RX14N SB_RX2P SB_RX2N

YVSSA GFX_TX12P VSSA GFX_RX13P GFX_RX13N GPP_RX2P VSSA VSSA VSSA

AA GFX_TX12N GFX_TX13P VSSA GPP_RX2N GPP_RX3N SB_RX3P SB_RX1N

AB GFX_TX14P GFX_TX13N VDDA_12 VDDA_12 GFX_RX15N GFX_RX15P GPP_RX3P SB_RX3N SB_RX1P

AC GFX_TX14N VSSA VDDA_12 VSSA VSSA VSSA VSSA SB_TX1P VSSA VSSA VDDA_12_PKG VDDR DEBUG2

AD VSSA VDDA_12 VSSA GPP_TX2P GPP_TX3P GPP_TX3N SB_TX3P SB_TX2P SB_TX1N SB_TX0N PCE_CALRP VDDR DEBUG0

AE VDDA_12 VDDA_12 GFX_TX15P GFX_TX15N GPP_TX2N VSSA SB_TX3N SB_TX2N SB_TX0P VSSA PCE_CALRN VDDR DEBUG1

12345678910111213

CPU Interface

A-Link Express II interface

Clock Interface

CRT and TV Int er face

External grap hics In te rfa c e

Integrated DVI/HDMI Int er face

General Purpose Exte r nal De vice In terfa c e

Power Management Interface

Powers

Grounds

Others

Pin Assignment Top View

Proprietary and Confidential 3-3

Figure 3-2 RS690 Pin Assignment Top View (Right)

14 15 16 17 18 19 20 21 22 23 24 25

LVSSR TXOUT_U0P LVSSR TXOUT_U2N TXOUT_U3P VDD_CORE AVDDDI AVDDQ AVSSQ VSS HT_RXCALP VSS A

TXOUT_L0P TXOUT_L0N TXOUT_U0N TXOUT_U2P TXOUT_U3N VDD_CORE AVSSDI RSET AVDD HTREFCLK HTPVDD HTPVSS B

TMDS_HPD LVSSR LVSSR TXOUT_U1P TXOUT_U1N LVSSR Y C AVDD HTTSTCLK HT_RXCALN HT_TXCALP C

LPVDD TXCLK_LN TXOUT_L3P COMP VDD_CORE VDD_HT_PKG VSS HT_TXCALN VSS D

LPVSS TXCLK_LP TXOUT_L3N RED HT_TXCAD1P HT_TXCAD0P HT_TXCAD0N E

LVSSR LVSSR VSS GREEN HT_TXCAD8P HT_TXCAD8N HT_TXCAD1N HT_TXCAD2N HT_TXCAD2P F

TXOUT_L2N TXCLK_UN AVSSN BLUE VDD_CORE HT_TXCAD10N HT_TXCAD10P VSS VSS HT_TXCAD3P G

TXOUT_L2P TXCLK_UP AVSSN VSS HT_TXCAD3N VSS H

VDD_18 VDD_18 VDD_CORE HT_TXCAD9P HT_TXCAD9N VSS HT_TXCAD4P HT_TXCLK0P HT_TXCLK0N J

HT_TXCAD4N HT_TXCAD5N HT_TXCAD5P K

VSS VDD_CORE VDD_CORE HT_TXCAD11P HT_TXCAD11N VSS HT_TXCLK1P HT_TXCLK1N VSS VSS HT_TXCAD6P L

VDD_CORE VSS VSS HT_TXCAD12P HT_TXCAD12N VSS HT_TXCAD13N HT_TXCAD13P VSS HT_TXCAD6N VSS M

VSS VDD_CORE HT_TXCTLP HT_TXCAD7P HT_TXCAD7N N

VDD_CORE VSS VDD_CORE HT_TXCAD14P HT_TXCAD14N VSS HT_TXCAD15P HT_TXCAD15N HT_TXCTLN HT_RXCTLP HT_RXCTLN P

VSS VDD_CORE VSS HT_RXCAD15N HT_RXCAD15P VSS HT_RXCAD14P HT_RXCAD14N VSS VSS HT_RXCAD7N R

VSS HT_RXCAD7P VSS T

VDD_CORE VDD_CORE HT_RXCAD12P HT_RXCAD12N VSS HT_RXCAD13N HT_RXCAD13P HT_RXCAD5N HT_RXCAD6N HT_RXCAD6P U

VSSA VSSA HT_RXCAD5P HT_RXCAD4P HT_RXCAD4N V

SB_RX0P SB_RX0N VDD_HT HT_RXCAD11P HT_RXCAD11N HT_RXCLK1P HT_RXCLK1N VSS VSS HT_RXCLK0N W

VSSA VSSA VDD_HT HT_RXCAD8N VSS VSS HT_RXCLK0P VSS Y

NC THERMALDIODE_

PVDD_HT HT_RXCAD8P HT_RXCAD9N HT_RXCAD2N HT_RXCAD3N HT_RXCAD3P AA

NC THERMALDIODE_

NVDD_HT VDD_HT HT_RXCAD9P HT_RXCAD10N HT_RXCAD2P HT_RXCAD1P HT_RXCAD1N AB

VSS VSS VSS DEBUG9 VDD_HT VDD_HT VDD_HT HT_RXCAD10P VSS VSS HT_RXCAD0P HT_RXCAD0N AC

GPP_TX0P GPP_TX0N GPP_RX0P DEBUG13 DEBUG10 GPP_TX1P GPP_RX1P VDD_HT VDD_HT VDD_HT VDD_HT VSS AD

VSS DEBUG6 GPP_RX0N DEBUG14 VSS GPP_TX1N GPP_RX1N DEBUG15 VSS VDD_HT VDD_HT VDD_HT AE

14 15 16 17 18 19 20 21 22 23 24 25

CPU Interface

A-Link Express interface

Clock Interface

CRT and TV Interface

External graphics Interface

Integrated DVI/HDMI I nte rface

General Purpose Extern al Device Int erface

Power Manage ment Inte rface

Powers

Grounds

Others

3-4 Proprietary and Confidential

Interface Block Diagram

3.2 Interface Block Diagram

The figure below shows the different interfaces on the RS690. Interface names in blue are hyperlinks to the corresponding

sections in this chapter.

Figure 3-3 RS690 Interface Block Diagram

HT_RXCAD[15:0]P, HT_RXCAD[15:0]N

HT_RXCLK[1:0]P, HT_RXCLK[1:0]N

HT_RXCTLP, HT_RXCTLN

HT_TXCTLP, HT_TXCTLN

HT_RXCALP, HT_RXCALN

HT_TXCALP , HT_TXCALN

HT_TXCLK[1:0]P, HT_TXCLK[1:0]N

HT_TXCAD[15:0]P, HT_TXCAD[15:0]N

SB_TX[3:0]P, SB_TX[3:0]N

SB_RX[3:0]P, SB_RX[3:0]N

SB_CLKP, SB_CLKN

TXOUT_U0 N, TXOUT_U0P

TXOUT_U1 N, TXOUT_U1P

TXOUT_U2 N, TXOUT_U2P

TXCLK_LN, TXCLK _ LP

TXOUT_L0 N, TXOUT_L0P

TXCLK_UN, TXCLK_UP

TXOUT_L1 N, TXOUT_L1P

TXOUT_L2 N, TXOUT_L2P

GFX_TX[15:0]P, GFX_TX[15:0]N

GFX_RX[15:0]P, GFX_RX[15:0]N

GFX_CLKP, GFX_CLKN

VSSA

AVSSN

LPVSS

LVSSR

AVSSQ

TESTMODE

THERMALDIDOE_N,

TVCLKIN

OSCIN

SYSRESET#

POWERGOOD

VDD_18

VDDR3

PLLVDD18

VDD_CORE

VDDA_12

PLLVSS

COMP

RSET

RED

GREEN

DACSCL

DACSDA

DACHSYNC

DACVSYNC

BLUE

THERMALDIODE_P

HyperTransport

Interface

Integrated

DVI/HDMI

Interface

A-Link Express

II Interface

Power

Management

Interface

Misc. Signals

PCI-E

External

Graphics or

TMDS

[RS690 only]

Interface

CRT and

TV-out

Interface

Clock

Interface

Power

Grounds VDD_HT

AVSSDI

PCI-E

Interface

for General

Purpose

External

Devices

GPP_TX[3:0]P, GPP_TX[3:0]N

GPP_RX[3:0]P, GFX_RX[3:0]N

PCE_CALRP

Misc. PCI-E

Signals PCE_CALRN

VSS

HTREFCLK

LDTSTOP#

ALLOW_LDTSTOP

I2C_CLK

BMREQ#

DDC_DATA

I2C_DATA

STRP_DATA

DFT_GPIO[5:0]

TMDS_HPD

HTTSTCLK

PLLVDD12

VDD_PLL

VSS_PLL

HTPVSS

AVDD

AVDDDI

LVDDR33

LPVDD

HTPVDD

LVDDR18D

AVDDQ

VDD_HT_PKG

VDDA_12_PKG

VDDR

GPIO[4:2]

CPU HyperTransport Interface

Proprietary and Confidential 3-5

3.3 CPU HyperTransport Interface

3.4 PCI Express Interfaces

3.4.1 1 x 16 Lane Interface for External Graphics

3.4.2 A-Link Express II to Southbridge

Table 3-1 CPU HyperT ransport Interface

Pin Name Type Power

Domain Ground

Domain Functional Description

HT_RXCAD[15:0]P,

HT_RXCAD[15:0]N I VDDHT VSS Receiver Command, Address, and Da ta Differential Pairs

HT_RXCLK[1:0]P,

HT_RXCLK[1:0]N I VDDHT VSS Receiver Clock Signal Differential Pair. Forwarded clock signal. Ea ch byte of

RXCAD uses a dif feren t clock signa l. Data is transferred on each clock ed ge.

HT_RXCTLP,

HT_RXCTLN I VDDHT VSS Receiver Control Differential Pa ir. For d istinguishing con trol p ackets from data

packets.

HT_TXCAD[15:0]P,

HT_TXCAD[15:0]N O VDDHT VSS Transmitter Command, Address, and Data Differential Pairs

HT_TXCLK[1:0]P,

HT_TXCLK[1:0]N O VDDHT VSS Transmitte r Clock Signal Different ial Pair . Each byte of TXCAD uses a different

clock signal. Data is transferred on each clock edge.

HT_TXCTLP,

HT_TXCTLN O VDDHT VSS Transmitter Control Differential Pair. Forwarded clock signal. For

distinguishing control p ackets from data packets.

HT_RXCALN Other VDDHT VSS Receiver Calibration Resistor to VDD_HT power rail.

HT_RXCALP Other VDDHT VSS Receiver Calibration Resistor to Ground

HT_TXCALP Other VDDHT VSS Transmitter Calibration Resistor to HTTX_CALN

HT_TXCALN Other VDDHT VSS Transmitter Calibration Resistor to HTTX_CALP

HTREFCLK I HTPVDD HTPVSS HyperTransport 66 MHz reference clock from extern al clock source

HTTSTCLK I HTPVDD HTPVSS HyperTransport Bus Test Clock. Drives test clock in test mo de. Con nect t o

ground in functional mode .

Table 3-2 1 x 16 Lane PCI Express Interface for External Graphic s

Pin Name Type Power

Domain Ground

Domain Integrated

Termination Functional Description

GFX_TX[15:0]P,

GFX_TX[15:0]N O VDD_PCIE VSS_PCIE 50Ω between

complements Transmit Dat a D ifferential Pairs. Connect to external conne ct or fo r

an external graphics card on the motherboard (if implemented).

GFX_RX[15:0]P,

GFX_RX[15:0]N I VDD_PCIE VSS_PCIE 50Ω between

complements Receive Data Differential Pairs. Connect to external conne ctor for an

external graphics card on the m othe rboard (if implem ente d).

GFX_REFCLKP,

GFX_REFCLKN I VDD_PCIE VSS_PCIE 50Ω between

complements Clock Differential Pairs. Con nect t o exte rnal clock g enera tor w hen

an external graphics card is implemented.

Table 3-3 1 x 4 Lane A-Link Express II Interface for Southbridge

Pin Name Type Power

Domain Ground

Domain In tegrated

Termination Functional Description

SB_TX[3:0]P,

SB_TX[3:0]N O VDD_PCIE VSS_PCIE 50Ω between

complements Transmit Dat a Differential Pairs. Connect to the corre spo nding

Receive Data Differential pairs on the Southbridge.

SB_RX[3:0]P,

SB_RX[3:0]N I VDD_PCIE VSS_PCIE 50Ω between

complements Receive Data Differential Pa ir s. Conne ct to the correspondin g

Transmit Data Differ ential pairs on the Southbridge.

SB_CLKP,

SB_CLKN I VDD_PCIE VSS_PCIE 50Ω between

complements Clock Differential Pair. Connect to an external clo ck ge nerat or on

the motherboard.

3-6 Proprietary and Confidential

Clock Interface

3.4.3 4 x 1 Lane Interface for General Purpose External Devices

3.4.4 Miscellaneous PCI Express Signals

3.5 Clock Interface

3.6 CRT and TV Interface

Table 3-4 4 x 1 Lane PCI Express Interface for General Purpose External Devices

Pin Name Type Power

Domain Ground

Domain Integrated

Termination Functional Descripti on

GPP_TX[3:0]P,

GPP_TX[3:0]N O VDD_PCIE VSS_PCIE 50Ω between

complements T ransmit Data Dif ferential Pairs. Connect to external connectors on

the motherboard for a dd-in card or E xpr essCa rd suppo rt.

GPP_RX[3:0]P,

GPP_RX[3:0]N I VDD_PCIE VSS_PCIE 50Ω between

complements Receive Data Dif ferential Pairs. Connect to external connectors on

the motherboard for a dd-in card or E xpr essCa rd suppo rt.

Table 3-5 PCI Express Interface for Miscellaneous PCI Express Signals

Pin Name Type Power

Domain Ground

Domain Functional Descript ion

PCE_CALRN Other VDD_PCIE VSS_PCIE RX Imped ance Ca libra tion. Conne ct to VDD_ PCIE on the mo therb oard w ith an

external resistor of an appropriate value.

PCE_CALRP Other VDD_PCIE VSS_PCIE TX Impeda nce Calibrat ion. Co nnect to GND on t he m oth erboard with an e xt ernal

resistor of an appropriate value.

Table 3-6 Clock Interface

Pin Name Type Power

Domain Ground

Domain Integrated

Termination Functional Description

TVCLKIN I VDDR3 VSS – Input pin for reference clock for external TV-out support (3.3V

signaling).

OSCIN I VDDR3 VSS Disabled 14.3181818 MHz Reference clock input from the External Clock chip

(3.3 volt signaling).

Table 3-7 CRT and TV Inter fa ce

Pin Name Type Power

Domain Ground

Domain Integrated

Termination Fu nctional Desc ription

RED A-O AVDD AVSSN – Red for CRT monito r out put, or Pr fo r compo nent vid eo TV ou tput

GREEN A-O AVDD AVSSN – Green for CR T monitor output, or Y for component video TV out put

BLUE A-O AVDD AVSSN – Blue fo r CRT monitor output, or Pb for com pone nt video TV o utpu t

Y A-O AVDD A VSSN – SVID luminance output for TV out, or Y for comp onent video TV output

CA-OAVDDAVSSN–

SVID chrominance out put for TV ou t, o r Pr for com pone nt video TV

output

COMP A-O AVDD AVSSN – Composite video TV outp ut, or P b fo r compo nent vid eo TV ou tput

DACHSYNC A-O VDDR3 VSS 50kΩ

programmable:

PU/PD/none Display Horizont al Sync

DACVSYNC A-O VDDR3 VSS 50kΩ

programmable:

PU/PD/none Display Vertical Sync

RSET Other N/A AVSSQ – DAC internal ref erence t o set full sca le DA C current thro ugh 1%

resistor to AVSS

Integrated DVI/HDMI Interface

Proprietary and Confidential 3-7

3.7 Integrated DVI/HDMI Interface

Note: The RS690C does not contain an integrated DVI/HDMI interface. The following pins should be treated as reserved

for the RS690C.

DACSDA I/O VDDR3 VSS 50kΩ

programmable:

PU/PD/none I2C dat a for disp lay (t o video monit or)

DACSCL I/O VDDR3 VSS 50kΩ

programmable:

PU/PD/none I2C clock for disp la y (to video mon it or)

Table 3-8 Integrated DVI/HDMI Interface

Pin Name DVI/HDMI

Functional

Name Type Power

Domain Ground

Domain Integrated

Termination Functio nal Descripti on

TXOUT_L0N TX0M O VDDLT33

VDDLT18 VSSLT None DVI /HDM I d ata channel 0 (-)

TXOUT_L0P TX0P O VDDLT33

VDDLT18 VSSLT None DVI/HDMI dat a channel 0 (+)

TXOUT_L1N TX1M O VDDLT33

VDDLT18 VSSLT None DVI/HDMI data cha nnel 1 (-)

TXOUT_L1P TX1P O VDDLT33

VDDLT18 VSSLT None DVI/HDMI dat a channel 1 (+)

TXOUT_L2N TX2M O VDDLT33

VDDLT18 VSSLT None DVI/HDMI data cha nnel 2 (-)

TXOUT_L2P TX2P O VDDLT33

VDDLT18 VSSLT None DVI/HDMI dat a channel 2 (+)

TXOUT_L3N TX3M O VDDLT33

VDDLT18 VSSLT None DVI data channel 3 (-). The channel is only used in