TS80002
Final Datasheet Rev 1.0
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TS80002
TRIUNE PRODUCTS
High Eciency Transmitter Controller
for Wireless Power Systems
Description
The TS80002 is a power transmitter communications and
control unit for wireless charging applications. The TS80002
can support systems up to 5W and proprietary applications.
The TS80002 performs the necessary coding of protocol to
send commands to the transmitter to adjust the power level
accordingly.
Specications
• RISC-based controller core with ash and SRAM memory
• 10-bit A/D converter
• Two 16-bit timers, advanced control and general purpose
• 8-bit timer
• Auto-wakeup and watchdog timers
• 4 congurable general purpose IOs
• I2C interface
• 20 pin 3x3 QFN
Typical Application Circuit
Load
Receiver
TS51221
Transmitter
TS80002
+
TS51231
DC
Supply
Application
Processor
Features
• Supports portable wireless charging applications
• Wireless power systems up to 5W
• Integrated controller and FLASH for communications and
control
• High precision data converter
• Low external component count
Applications
• Low-power wireless chargers for:
Smart Watches
Wearables
Toys
Portable Lighting
Medical Devices
TS80002
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Pinout (Top View)
I_DC
V_AC
GPIO4
VREF
V_DC
SCL
PMW1_L
SDA
ALERT
VDD
VSS
LDO
GPIO2
GPIO1
NRST
GPIO3
PMW2_L
PMW1_H
PMW2_H
DEBUG
PIN 1
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Pin Description
Pin # Pin Name Pin Function Description
1 NRST Reset Reset input
2 GPIO1 GPIO GPIO 1
3 GPIO2 GPIO GPIO 2
4 VSS Power GND Power GND
5 LDO Filter Internal LDO lter capacitor
6 VDD Input power Input power supply
7 ALERT I2C Alert I2C Alert signal
8SDA I2C Serial Data I2C Serial Data
9 SCL I2C Serial Clock I2C Serial Clock
10 PWM1_L PWM output PWM1 low-side control
11 PWM2_L PWM output PWM2 low-side control
12 GPIO3 GPIO GPIO 3
13 PWM1_H PWM PWM1 high-side control
14 PWM2_H PWM PWM2 high-side control
15 DEBUG Debug Debug interface
16 V_AC Analog GPIO AC voltage measurement
17 I_DC Analog GPIO DC current measurement
18 GPIO4 GPIO GPIO 4
19 VREF Analog GPIO Voltage reference input
20 V_DC Analog GPIO DC voltage measurement
TS80002
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Functional Block Diagram
VDD
CONTROLLER
I2C / UART
ADC1
V_AC
GPIO Controller
Timers
Power On
Reset
System
Supervisor
Oscillator
Voltage
Reference
SDA
SCL
GND
ALERT
V_DC
PWM1_H
AGPIO Interface
IO Buffers
PWM1_L
PWM2_H
PWM
Control
AGPIOx
I_DC
PWM2_L
V_AC
V_DC
I_DC
GPIO1
GPIO4
GPIO Interface
Memory
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Absolute Maximum Rating
Over operating free–air temperature range unless otherwise noted(1, 2, 3)
Parameter Min Max Unit
VDD, VSS -0.3 6.5 V
GPIO1, GPIO2, VSS, VDD, ALERT, SDA, SCL, PWM1_L,
PWM2_L, GPIO3, PWM1_H, PWM2_H, DEBUG, V_AC,
I_DC, GPIO4, VREF, V_DC
VSS - 0.3 6.5 V
NRST, LDO VSS - 0.3 VDD + 0.3 V
Operating Junction Temperature Range, TJ -40 125 °C
Storage Temperature Range, TSTG -65 150 °C
Electrostatic Discharge – Human Body Model ±2k V
Lead Temperature (soldering, 10 seconds) 260 °C
Notes:
(1) Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute–maximum–rated conditions for extended periods may affect device reliability.
(2) All voltage values are with respect to network ground terminal.
(3) ESD testing is performed according to the respective JESD22 JEDEC standard.
Recommended Operating Conditions
Symbol Parameter Min Typ Max Unit
VDD Input Operating Voltage 2.95 5.5 V
FMCU Operating Frequency 0 16 MHz
VDD Decoupling capacitor value 1 uF
LDO Decoupling capacitor value 1 uF
TAOperating Free Air Temperature -40 85 °C
TJOperating Junction Temperature -40 105 °C
The Applications Processor can interrogate the TS80002 using the I2C interface. The TS80002 acknowledges its I2C Slave Address
only if it is powered. No ACK from the TS80002 after its slave address means that power is not applied to the TS80002.
Communication Interfaces
TS80002
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I2C
I2C Signal Pins
ALERT pin (GPIO pin) - optional:
• Driven high when an event is active in the internal STATUS
register
• Driven low when all the internal events are cleared
Note: The ALERT pin is provided to help with I2C
communication, i.e. to signal events to the EC so the EC can
interrogate the TS80002 via I2C. The use of the ALERT pin is
not mandatory in the application.
SCL pin:
• Clock pin for the I2C interface.
• True open-drain. Needs external pull-ups.
SDA pin:
• Data pin for the I2C interface.
• True open-drain. Needs external pull-ups.
I2C Protocol
The TS80002 Wireless Power Receiver acts as an I2C slave
peripheral to allow communication with an application
microcontroller. The slave address (7 bit) is 0x51. The
Embedded Controller is an I2C master and initiates every data
transfer.
The TS80002 implements a set of registers available from the
I2C bus. It also implements a set of API functions that receive
parameters and return values using the I2C bus. Four transfer
types are possible:
• Write Register
• Read Register
• Run API Function
• Read API Function Return Buer
START Start of the I2C transfer.
M[SSlave Address (7 bits) 0 (1 bit) Slave ACK Slave address + R/nW bit (0x92 as 8-bit).
M[SRegister n address (8 bits) Slave ACK Address of the rst register
M[SRegister n Data (8 bits) Slave ACK Write the rst register
M[SRegister n+1 Data (8 bits) Slave ACK Optionally write the following registers
...
M[SRegister n+k Data (8 bits) Slave ACK
STOP Stop of the I2C transfer
Write Register Operations Description
START Start of the I2C transfer.
M[SSlave Address (7 bits) 0 (1 bit) Slave ACK Slave address + 0 as R/nW bit (0x92 as 8-bit).
M[SRegister n address (8 bits) Slave ACK Address of the rst register
START Repeated Start
M[SSlave Address (7 bits) 1 (1 bit) Slave ACK Slave address + 1 as R/nW bit (0x93 as 8-bit).
S[MRegister n Data (8 bits) Master ACK Read the rst register
S[MRegister n+1 Data (8 bits) Master ACK Optionally read the following registers
...
S[MRegister n+k Data (8 bits) Master nACK The master should send a nACK after the last data byte was
received.
STOP Stop of the I2C transfer
Read Register Operations
TS80002
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START Start of the I2C transfer
M[SSlave Address (7 bits) 0 (1 bit) Slave ACK Slave address + R/nW bit (0x92 as 8-bit).
M[SAPI number (8 bits) Slave ACK API number
M[SAPI input buer length m (8 bits) Slave ACK API input buer length. Equal to 0 if no input buer data is
required by the API
M[SInput buer data[0] (8 bits) Slave ACK First byte of the input buer (optional)
M[SInput buer data[1] (8 bits) Slave ACK Second byte of the input buer (optional)
...
M[SInput buer data[m-1] (8 bits) Slave ACK Last byte of the input buer (optional)
STOP Stop of the I2C transfer and execute the API function
Run API Function Description
START Start of the I2C transfer.
M[SSlave Address (7 bits) 0 (1 bit) Slave ACK Slave address + 0 as R/nW bit (0x92 as 8-bit).
M[SAPI number (8 bits) Slave ACK API number.
START Repeated Start
M[SSlave Address (7 bits) 1 (1 bit) Slave ACK Slave address + 1 as R/nW bit (0x93 as 8-bit).
S[MAPI number (8 bits) Master ACK API number for the following return buer
S[MAPI return buer length n (8 bits) Master ACK API return buer length
S[MOutput buer data[0] (8 bits) Master ACK Read the rst byte in the output buer
S[MOutput buer data[1] (8 bits) Master ACK Optionally read the following bytes
...
S[MOutput buer data[n-1] (8 bits) Master nACK The master should send a nACK after the last data byte was
received.
STOP Stop of the I2C transfer
Read API Function Return Buer Description
TS80002
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Internal Registers
Addresss Name Type Description
General Registers
0x00 BOOTFW_REV_L R/W Bootloader Firmware Revision Low Register
0x01 BOOTFW_REV_H R/W Bootloader Firmware Revision High Register
0x02 FW_REV_L R/W Firmware Revision Low Register
0x03 FW_REV_H R/W Firmware Revision High Register
0x04 MODE_L R/W Operating Mode Low Register
0x05 MODE_H R/W Operating Mode High Register
0x06 RESET_L R/W Reset Low Register
0x07 RESET_H R/W Reset High Register
0x08 STATUS R Main Status Register
0x09 STATUS0 R Status0 Register
0x0A STATUS1 R Status1 Register
0x0B STATUS2 R Status2 Register
0x0C STATUS3 R Status3 Register
0x0D-0x7F RESERVED. Will be dened later.
Bootloader Firmware Revision Low Register (BOOTFW_REV_L)
Address: 0x00
Reset value: Minor version number of the bootloader rmware
Bits 7:0 REV_L[7:0]: Bootloader Firmware Revision Low
These bits contain the minor version number of the bootloader rmware.
Bootloader Firmware Revision High Register (BOOTFW_REV_H)
Address: 0x01
Reset value: Major version number of the bootloader rmware
Bits 7:0 REV_H[7:0]: Bootloader Firmware Revision High
These bits contain the major version number of the bootloader rmware.
76543210
REV_L[7:0]
rrrrrrrr
76543210
REV_H[7:0]
rrrrrrrr
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Firmware Revision Low Register (FW_REV_L)
Address: 0x02
Reset value: Minor version number of the user rmware
Bits 7:0 REV_L[7:0]: Firmware Revision Low
These bits contain the minor version number of the user rmware.
76543210
REV_L[7:0]
rrrrrrrr
Firmware Revision High Register (BOOTFW_REV_H)
Address: 0x03
Reset value: Major version number of the user rmware
Bits 7:0 REV_H[7:0]: Bootloader Firmware Revision High
These bits contain the major version number of the user rmware.
76543210
REV_H[7:0]
rrrrrrrr
Operating Mode Low Register (MODE_L)
Address: 0x04
Reset value: Depends on the bootloader mode and the rmware type
Bits 7:1 Reserved
Bit 0 BOOTLDR: Bootloader mode
0: The user rmware is running
1: The controller is in bootloader mode
76543210
Res BOOTLDR
r
Operating Mode High Register (MODE_H)
Address: 0x05
Reset value: Depends on the bootloader mode and the rmware type
Bits 7:0 Reserved
76543210
Res
Reset Low Register (RESET_L)
Address: 0x06
Reset value: 0x00
Bits 7:0 RESET_KEY_L[7:0]: Reset Key
0x55: generate a system reset. Both the RESET_L and the RESET_H registers have to be written
with the correct key to generate a reset.
Any other value: a system reset is not generated.
76543210
RESET_KEY_L[7:0]
wwwwwwww
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Reset High Register (RESET_H)
Address: 0x07
Reset value: 0x00
Bits 7:0 RESET_KEY_H[7:0]: Reset Key
0xAA: generate a system reset. Both the RESET_L and the RESET_H registers have to
be written with the correct key to generate a reset.
Any other value: a system reset is not generated.
76543210
RESET_KEY_H[7:0]
wwwwwwww
Main Status Register (STATUS)
Address: 0x08
Reset value: 0xC0
Bit 7 CTS: Clear To Send
This bit indicates if a new command can be issued to the controller.
0: The controller is busy processing a previous command. New commands should
not be sent to the controller.
1: The controller can accept a new command over the communication interface.
Bit 6 CTS_API: Clear to Send for API
This bit indicates if a new API call can be issued to the controller.
0: The controller is busy processing a previous API call. New API calls should not be
sent to the controller.
1: The controller can accept a new API call over the communication interface.
Bits 5:4 Reserved
Bit 3 STATUS3: STATUS3 Event Flag
0: No event is signaled in the STATUS3 register
1: An event is signaled in the STATUS3 register
Bit 2 STATUS2: STATUS2 Event Flag
0: No event is signaled in the STATUS2 register
1: An event is signaled in the STATUS2 register
Bit 1 STATUS1: STATUS1 Event Flag
0: No event is signaled in the STATUS1 register
1: An event is signaled in the STATUS1 register
Bit 0 STATUS0: STATUS0 Event Flag
0: No event is signaled in the STATUS0 register
1: An event is signaled in the STATUS0 register
76543210
CTS CTS_API Res STATUS3 STATUS2 STATUS1 STATUS0
rw rw rw rw rw rw
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API Functions
API Number API Name Description
0x80 BOOTLOADER_UNLOCK_FLASH Allow changes to the FLASH memory
0x81 BOOTLOADER_WRITE_BLOCK Write a page into the FLASH memory
0x82 BOOTLOADER_CRC_CHECK Check the CRC of the user rmware
0x83-0xFE RESERVED. Will be dened later.
0xFF API_ERROR
Value returned in the API eld when a Read API Function
Return Buer command is issued and the API function called
previously has generated an error.
Bootloader Unlock Flash (BOOTLOADER_UNLOCK_FLASH)
API number: 0x80
Input buer size: TBD
Output buer size: 1
Buer Parameter Length (bytes) Description
Input buer TBD
Return data buer ERROR_CODE 1
Bootloader Write Block (BOOTLOADER_WRITE_BLOCK)
API number: 0x81
Input buer size: 66
Output buer size: 1
Buer Parameter Length (bytes) Description
Input buer Block Number 2 Block index. The rst block has an index of 0.
Block Data 64 Data to be written to the FLASH page.
Return data buer ERROR_CODE 1
Bootloader CRC Check (BOOTLOADER_CRC_CHECK)
API number: 0x82
Input buer size: 0
Output buer size: 1
Buer Parameter Length (bytes) Description
Return data buer ERROR_CODE 1
API Error Codes
Error Code Error Code Name Description
0x00 ERROR_GENERIC Generic error.
0x01 ERROR_OK Operation succeeded. This is not indicating an error.
0x02 ERROR_INVALID_CRC CRC error.
0x03 ERROR_FLASH_UNLOCK_FAILED FLASH unlocking has failed.
0x04 ERROR_API_NOT_IMPLEMENTED The API number is not implemented.
0x05 ERROR_API_DATA_OVERFLOW The API input buer has been lled with more data than
its length.
0x06 ERROR_API_INVALID_PARAMETERS At least one of the API parameters is invalid.
0x07-0xFF RESERVED. Will be dened later.
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Application Schematic
Figure 1: TS80002 Application Schematic
1
1
2
2
3
3
4
4
D D
C C
B B
A A
1
681 N. Plano Road
Suite 121
Richardson, Texas 75081
1
Wireless Power TX
1.0
8/12/2014 10:13:27 AM
Title
Size: Number:
Date:
Revision:
Sheet ofTime:
Letter
3V-4.2V Low Power
Triune Systems Proprietary and Confidential Information
NRST
1
GPIO1
2
GPIO2
3
VSS
4
LDO
5VDD
6
ALERT 7
SDA 8
SCL 9
PWM1_L 10
PWM2_L 11
GPIO3
12
PWM1_H 13
PWM2_H 14
DEBUG
15
V_AC 16
I_DC 17
GPIO4 18
VREF 19
V_DC 20
U1
TS80002
1uF
6.3V
C5
GND
VCC5V
1uF
6.3V
C3
GND
10nF
10V
C4
GND
RESET
SCL
SDA
DEBUG
TP1
TP2
TP3
TP4
TP5
TP6
GND
VCC5V
RESET
DEBUG
SCL
SDA
SW 11
VIN 15
PGND 5
GND
8
EN
1
nFLT
4
VDD
7
HSON
6
VIN 16
SCL
3
SDA
2
SW 12
PGND 13
PGND 14
PAD 17
PGND 9
BOOT 10
U2
TS51231
VCC5V
10K
R3
10K
R4
VCC5V 100nF
10V
C2
10uF
10V
C1
GND
100nF
10V
C7
GND AC
1
AC
2COIL
J1
3.0uH TX Coil
4.7nF
50V
C6
GND
GND
GND GND
1nF
100V
C9
330K
R7
22K
R8
D1
100nF
10V
C8
VBAT 1
VBAT 2
VBAT 3
GND 4
GND 5
GND 6
ENABLE 7
DONE 8
SDA 9
SCL 10
NC 11
J2
BATT DC IN
GND
CHG_EN
Coil Feedback
1K
R9
4.7nF
100V
C10
1K
R11
10K
R10
10K
R12
1nF
10V
C11
GND GND
RX -> TX Communication
VOUT 1
VOUT 2
VOUT 3
ISEN 4
FB 5
GND
6
EN
7PG 8
NC
9
NC
10
VIN
11 VSW 12
PGND
13
VSW 14
PGND
15
VOUT 16
PAD
17
U3
TS32101
1uH
1.1A
L1
BATT
22uF
6.3V
C13
22pF
25V
C15
1.2M
R13
380K
R14
22uF
6.3V
C14
100nF
10V
C12
BATT
VCC5V
RESETCHG_EN
GNDGND
GND
DONE
SMB_SDA
SMB_SCL
SCL
SDA
DONE
22uF
6.3V
C17
GND
22nF
10V
C18
4.7nF
50V
C16
NP
C19
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Package Dimensions
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QFN Package (Top marking)
Legend:
Line 1 Marking: S033 Internal part code
Line 2 Marking: SS Assembly site identier
LL Lot trace code
Line 3 Marking: D Assembly year
WW Assembly week
Y Additional marking
o Pin 1 Identier
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Ordering Information
Part Number Description
TS80002-QFNR Boot Loader Device
RoHS and Reach Compliance
Triune Systems is fully committed to environmental quality.
All Triune Systems materials and suppliers are fully compliant
with RoHS (European Union Directive 2011/65/EU), REACH
SVHC Chemical Restrictions (EC 1907/2006), IPC-1752 Level
3 materials declarations, and their subsequent amendments.
Triune Systems maintains certied laboratory reports for
all product materials, from all suppliers, which show full
compliance to restrictions on the following:
• Cadmium (Cd)
• Chlorouorocarbons (CFCs)
• Chlorinate Hydrocarbons (CHCs)
• Halons (Halogen free)
• Hexavalent Chromium (CrVI)
• Hydrobromouorocarbons (HBFCs)
• Hydrochlorouorocarbons (HCFCs)
• Lead (Pb)
• Mercury (Hg)
• Peruorocarbons (PFCs)
• Polybrominated biphenyls (PBB)
• Polybrominated Diphenyl Ethers (PBDEs)
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Contact Information
Semtech Corporation
200 Flynn Road, Camarillo, CA 93012
Phone: (805) 498-2111, Fax: (805) 498-3804
www.semtech.com
IMPORTANT NOTICE
Information relating to this product and the application or design described herein is believed to be reliable, however such information is provided as a
guide only and Semtech assumes no liability for any errors in this document, or for the application or design described herein. Semtech reserves the right
to make changes to the product or this document at any time without notice. Buyers should obtain the latest relevant information before placing orders
and should verify that such information is current and complete. Semtech warrants performance of its products to the specications applicable at the time
of sale, and all sales are made in accordance with Semtech’s standard terms and conditions of sale.
SEMTECH PRODUCTS ARE NOT DESIGNED, INTENDED, AUTHORIZED OR WARRANTED TO BE SUITABLE FOR USE IN LIFE-SUPPORT APPLICATIONS, DEVICES
OR SYSTEMS, OR IN NUCLEAR APPLICATIONS IN WHICH THE FAILURE COULD BE REASONABLY EXPECTED TO RESULT IN PERSONAL INJURY, LOSS OF LIFE
OR SEVERE PROPERTY OR ENVIRONMENTAL DAMAGE. INCLUSION OF SEMTECH PRODUCTS IN SUCH APPLICATIONS IS UNDERSTOOD TO BE UNDERTAKEN
SOLELY AT THE CUSTOMER’S OWN RISK. Should a customer purchase or use Semtech products for any such unauthorized application, the customer shall
indemnify and hold Semtech and its ocers, employees, subsidiaries, aliates, and distributors harmless against all claims, costs damages and attorney
fees which could arise.
The Semtech name and logo are registered trademarks of the Semtech Corporation. Triune Systems, L.L.C. is now a wholly-owned subsidiary of Semtech
Corporation. The Triune Systems® name and logo, MPPT-lite™, and nanoSmart® are trademarks of Triune Systems, LLC. in the U.S.A. All other trademarks
and trade names mentioned may be marks and names of Semtech or their respective companies. Semtech reserves the right to make changes to, or
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