MOSEL VITELIC V53C104F HIGH PERFORMANCE, LOW POWER 256K X 4 BIT FAST PAGE MODE CMOS DYNAMIC RAM HIGH PERFORMANCE V53C104F 60/60L 70/70L 80/80L Max. RAS Access Time, (ta 4) 60 ns 70 ns 80 ns Max. Column Address Access Time, {t, AA) 30 ns 35 ns 40 ns Min. Fast Page Mode Cycle Time, (tag) 40 ns 45 ns 50 ns Min. Read/Write Cycle Time, (tac) 120 ns 130 ns 150 ns LOW POWER V53C104FL 60L 70L 80L Max. CMOS Standby Current, (Ing) 200pA 200A 200pA | Features Description | a 256K x 4 Organization s RAS access time: 60,70,80 ns u Low power dissipation for V53C104F-80 Operating Current 70 mA max. * TTL Standby Current 2.0 mA max. a Low CMOS Standby Current V53C104F - 1.0 mA max. * V53C104FL 0.2 mA max. = Read-Modify-Write, RAS-Only Refresh, CAS-Before-RAS Refresh capability. a Common I/O capability Refresh interval V53C104F 512 cycles/8ms * V53C104FL 512 cycles/64ms a Fast Page Mode for a sustained data rate greater than 25 MHz = Standard packages are 20 pin Plastic DIP and 26/20 pin SOJ a Low Battery Back-up Current * V53C104FL 300 pA max. * 200 LA max. available on request The V53C104F is a high speed 262,144 x 4 bit CMOS dynamic random access memory. The V53C104F offers a combination of features: Fast Page Mode for high data bandwidth, fast usable speed, CMOS standby current and, on request, extended refresh for very low data retention power (V53C104FL). All inputs and outputs are TTL compatible. Input and output capacitances are significantly lowered to allow increased system performance. Fast Page Mode operation allows random access of up to 512 (x4) bits within a row with cycle times as short as 40 ns. Because of static circuitry, the CAS clock is not in the critical timing path. The flow-through column address latches allow address pipelining while relax- ing many critical system timing requirements for fast usable speed. These features make the V53C104F ideally suited for graphics, digital signal processing and high performance computing systems. The V53C104FL offers a maximum data retention power of 1.65 mW when operating in CMOS standby mode and performing CAS-before-RAS refresh cycles. Device Usage Chart Operating Package Outline Access Time (ns) Power Temperature Temperature | Range P K 60 70 80 Low Std. Mark | OC to 70 C . . . . . Blank | V53C104F Rev. 1.0 January 1995 2-70 mm 639533991 Gooe74O LAT =MOSEL VITELIC FAMILY Description Pkg. | Pin Count Plastic DIP P 20 SOJ K 26/20 26/20 Lead SOJ Package PIN CONFIGURATION Top View vOo1 C1 26 Vss vo2 C2 2 4 WE 3 24 WO3 RAS Cy 4 23 CAS xcs vv 2h aw wx ho QO - 409 8 1 Ag Ay 10 17 A? Ao it teh AS Ag C12 16 As Vpp Cj 13 144 Ag Absolute Maximum Ratings* Ambient Temperature Under Bias .0... ee 10C to +80C Storage Temperature (plastic) ....-55C to +125C Voltage Relative to V.. -1.0Vto+7.0V Voltage on V_,, relative to Veg ...... 1.0 V to +7.0 V Data Output Current .......... cesses cece 50 mA Power Dissipation ...........cccccseseeeeeeees 1.0W Note: Operation above Absolute Maximum Ratings can adversely affect device reliability. V53C104F Rev. 1.0 January 1995 MM 63553591 oo02e741 Ob V53C104F DEVICE PKG SPEED TEMP. t Z (tac) pwr LL BLANK {0C to 70C) P (PLASTIC DIP) K (Sv) BLANK (NORMAL) L (LOW POWER) 60 (60 ns) 70 (70 ns) 80 (80 ns) 20 Lead Plastic DIP PIN CONFIGURATION Top View vo, 01 ~~ 0H Veg vO2 q 2 9 Wy Wwe G3 2 18 ff vo msds & 7b cas ngs 2 6h & Ao G6 Y 15 f Ag A, G7 14 Ay Ap ds 7 3B Ag 43 a9 12 Ag Vpp 4 10 1 Ag Pin Names ASA, Address Inputs RAS Row Address Strobe CAS Column Address Strobe WE Write Enable OE Output Enable Vo,-VO, Data Input, Output bp +5V Supply ss OV Supply NC No Connect Capacitance* T, = 25C, Vip = 5 V + 10%, Veg = OV Symbol! Parameter Typ. | Max. | Unit Cy Address Input 6 pF Cio RAS, CAS, WE, OE | 7 | pF Cour Data Input/Output _ 7 pF * Note: Capacitance is sampled and not 100% tested 2-71MOSEL VITELIC V53C104F Block Diagram 256K x 4 OE o WE o oS RAS RAS CLOCK CAS CLOCK WE CLOCK OE CLOCK GENERATOR | GENERATOR | GENERATOR | GENERATOR VoD > Vgg oe { DATA /O BUS ? 14 > BUFFER _ oe 7 COLUMN DECODERS VOg pO VO, YoYs H | SENSE AMPLIFIERS REFRESH COUNTER $12 x4 SZ 9 AO oe 2 fe uj WW At oe i a Xo Xx 8 te 512 MO . Oo MEMORY a Sa - ARRAY . an LO e LJ Az o>] Fd c a A ae 8 oe < S V58C104F Rev. 1.0 January 1995 2-72 WE 6353391 O00e74e TheMOSEL VITELIC V53C104F DC and Operating Characteristics (1-2) T, = 0C to 70C, Vop =5V+ 10%, Veg = 0 V, unless otherwise specified. V53C104F V53C104FL Access Symbol | Parameter Time Min. Max. Min. Max. | Unit) Test Conditions | Notes ly input Leakage Current -10 10 -10 10 BA | Veg 5 Vy S Vop (any input pin) lo Output Leakage Current 10 10 -10 10 HA | Vegs Vour Vop (for High-Z State) RAS, CAS at Vig 60 90 90 l Vi Supply Current, al oo SEPP 70 80 80 MA | tag = tae (min.) 1,2 Operating aa 70 70 lope Vop Supply Current, RAS, CAS at Vig TTL Standby 2.0 2.0 mA | other inputs > V5g 60 90 90 Vop Supply Current, lnpg =| RAS-Only Refresh 70 80 80 MA | tao = tag (min.) 2 80 70 70 Vop Supply Current, 60 80 80 loo, | Fast Page Mode 70 70 70 _| mA | Minimum Cycle 1,2 Operation 80 60 60 loos Standby, Output Enabied 3.0 2.0 mA RAS-=V,,,, CAS=V,, 4 other inputs 2 V,. loos Vpp Supply Current RAS 2 Vp, -0.2 V, CMOS Standby 1.0 0.2 mA | CAS > Vop 0.2 V other input > V., Vie Input Low Voltage -1.0 0.8 -1.0 0.8 Vv 3 Vi Input High Voltage 2.4 Vop+1 2.4 Voptt Vv 3 Vor Output Low Voltage 0.4 0.4 V | ly=42ma Von Output High Voltage 24 2.4 Vi tig, =-5mA VS3C104F Rev. 1.0 January 1995 ME 6353391 0002743 999 278MOSEL VITELIC V53C104F AC Characteristics T,= 0C to 70C, Von = 5V 10%, Veg = OV unless otherwise noted AC Test conditions, input pulse levels 0 to 3V JEDEC 60/L 7O/L 80/L # | Symbol | Symbol Parameter Unit | Notes Min. | Max.| Min. | Max. | Min. | Max. 1 | the seus tars RAS Pulse Width 60 | 75K | 70 | 75K ) 80 | 75K | ns 2 | toons tac Read or Write Cycle Time 120 130 150 ns 3 | toate tap RAS Precharge Time 50 50 60 ns 4 | torso logy CAS Hold Time 60 70 80 ns 5 | toc tons CAS Pulse Width 15 20 20 ns 6 | tare trop RAS to CAS Delay 20 46 20 50 20 60 ns 4 7 | Awepcre tacs Read Command Setup Time 0 0 0 ns 8 | tives lisa Row Address Setup Time 0 0 0 ns 9 | tar ax than Row Address Hold Time 10 10 10 ns 10 | tavcre tasc Column Address Setup Time 0 0 0 ns 17 | terrax toa Column Address Hold Time 16 15 15 ns 12 | tor yany tasy R) RAS Hold Time (Read Cycle) 15 20 20 ns 13 | toes tore CAS to RAS Precharge Time 5 5 5 ns 14 | topewx tach Read Command Hold Time 0 0 0 ns 5 Referenced to CAS 15 | tarowx tany Read Command Hold Time 0 0 0 ns 5 Referenced to RAS 16 | toctiane trou RAS Hold Time 10 10 10 ns Referenced to OE 17 | tesoy toac Access Time from OE 15 20 20 ns 18 | teuav toac Access Time from CAS 15 20 20 ns 6,7 19 | toiiev toac Access Time from RAS 60 70 80 ns | 6,8,9 20 | tayey tena Access Time from Column 30 35 40 ns 6,7, Address 10 V53C104F Rev. 1.0 January 1995 me 6353391 op0e744 bes = 2-74MOSEL VITELIC V53C104F AC Characteristics (Cont'd.) JEDEC 60/L 7O/L 80/L # | Symbol | Symbol Parameter Unit | Notes Min. | Max. | Min. | Max. | Min.| Max. 21 | to ox ty OE or CAS to Low-Z Output 0 0 0 ns 16 22 | topaz tuz OE or CAS to High-Z Output 0 20 0 20 0 20 ns 16 23 | te ax tan Column Address Hold Time 50 55 60 ns from RAS 24 | taay toap RAS to Column Address 15 30 15 35 15 40 ns 14 Delay Time 2 25 toLinni tas w RAS or CAS Hold Time 15 20 20 ns in Write Cycle 28 | twice: tow. Write Command to CAS 15 20 20 ns Lead Time 27 | tunes twos Write Command Setup Time 0 0 0 ns | 12,13 28 town twou Write Command Hold Time 10 15 15 ns 29 | ty away tye Write Pulse Width 10 15 15 ns 30 | taiwan twor Write Command Hold Time 50 55 60 ns from RAS 31 | twee tawe Write Command to RAS 15 20 20 ns Lead Time 92 | tows tos Data in Setup Time 0 0 0 ns 14 33 | twripx tow Data in Hold Time 15 15 15 ns 14 34 | twats twou Write to OE Hold Time 15 20 20 ns 14 35 | taonx lop OE to Data Delay Time 15 20 20 ns 14 36 | to ope tawe Read-Modify-Write 170 185 205 ns (RMW) Cycle Time 87 1 tar seen taaw Read-Modify-Write Cycie 105 125 135 ns (RMW) RAS Pulse Width 38 | to wie town CAS to WE Delay 40 50 50 ns 12 V53C104F Rev. 1.0 January 1995 BS 6353391 0002745 7bl 2-75MOSEL VITELIC V53C 104F AC Characteristics (Cont'd.) JEDEC 60/L 7O/L 80/L # | Symbol | Symbol Parameter Unit | Notes Min. | Max. | Min. | Max. | Min. |Max. 39 | ter wee tawo RAS to WE Delay in 85 100 110 ns | 12 Read-Modify-Write Cycle 40 | toricun toaw CAS Pulse Width (RMW) 65 75 75 ns 41 | taywee tawp Col. Address to WE Delay 60 65 70 ns 12 42 | tose too Fast Page Mode 40 45 50 ns Read or Write Cycle Time 43 | topecte top CAS Precharge Time 10 10 10 ns 44 | tava loan Column Address to RAS 30 35 45 ns Setup Time 45 | towav toap Access Time from 36 40 45 ns 7 Column Precharge 46 | ta ipx tour Data in Hold Time 50 55 60 ns Referenced to RAS 47 | torte tosr CAS Setup Time 10 10 10 ns CAS-before-RAS Refresh 48 | trrcie tapc RAS to CAS Precharge Time 10 10 10 ns 49 | taicus tour CAS Hold Time 30 30 30 ns CAS-before-RAS Refresh 50 | torsere toom Fast Page Mode Read- 85 95 100 ns (RMW) Modify-Write Cycle Time t Transition Time 3 50 3 50 3 50 ns 15 (Rise and Fall) ter Refresh Interval 8 8 8 ms 17 (512 Cycles) ther Refresh Interval 64 64 64 ms | 17,18 V53C104FL Only (612 Refresh cycles, t,=125 1s) V5SC104F Rev.1.0 January 1995 M 6353391 0002746 bTa 21%MOSEL VITELIC V53C 104F 2 ND Oo 10. 11. 12. 13. 14, 15. 16. 18. Ip is dependent on output loading when the device output is selected. Specified \pp (max.) is measured with the output open. top is dependent upon the number of address transitions. Specified lop (Max.) is Measured with a maximum of two transitions per address cycle in Fast Page Mode. Specified V,_ (min.) is steady state operating. During transitions, V,, (min.) may undershoot to -1.0 V for a period not to exceed 20 ns. All AC parameters are measured with V,, (min.) 2 Vg, and V,,, (max.) < Vop: tacp (Max.) is specified for reference only. Operation within trop (max.) limits insures that trac (Max.) andt,,, (max.) can be met. If tacp iS greater than the specified tacp (max.), the access time is controlled by tong and trae Either tony, OF tao, must be satisified for a Read Cycle to occur. Measured with a load equivalent to two TTL inputs and 100 pF. Access time is determined by the longest of tomar tong ANd toap. Assumes thatt, ., Strap (Max.). Ift,,,, is greater than trap (Max.), t.,,- will increase by the amount that taap exceeds taap (max.). Assumes that trop <taep (Max.). IFt,,, is greater than trop (Max.), t, 4, Will increase by the amount thatt,, exceeds tren (max.). RCD zt Assumes that trap 2 pap (max.). Operation within thet, ,, (max.) limit ensures thatt, ,. (max.) can be met. taap (Max.) is specified as a reference point only. If tz, iS greater than the specified trap (Max.) limit, the access time is controlled by toa, ANd toao- twos? 'rwo: fawn 2N9 top are not restrictive operating parameters. twes (min.) must be satisfied in an Early Write Cycte. tpg and t,,, are referenced to the latter occurrence of CAS or WE. t, is measured between V,,, (min.) and Vi (max.). AC-measurements assume t= Sns. Assumes a three-state test load (5 pF and a 380 Ohm Thevenin equivalent). An initial 200 ys pause and 8 RAS-containing cycles are required when exiting an extended period of bias without clocks. An extended period of time without clocks is defined as one that exceeds the specitied Refresh Interval. This is battery backup data retention mode under CAS before RAS refresh cycles. tac = 125 ps (125 us x 512 = 64 ms) tras = brag (min) to 1 ps input voltages : RAS and CAS Vin > Yop - 0-2 V Vi <02V WE and OF Vin? Vpn - 0-2 All other inputs at stable V,,, or Vi V53C104F Rev. 1.0 January 1995 6353391 0002747? 534 2-77MOSEL VITELIC V53C104F Waveforms of Read Cycle RAS CAS ADDRESS vo Vin Vit Vi Vi Min Vit Vin Viv i) Vib Vou Vou tar (23) Tes (4) RSH (F(12) torp (13) CAS (5) torp (13) Trop @) leap (2a) TRaH (9) toaH (11) TaSR (8) tase (10) ROW ADDRESS COLUMN ADDRESS tear (44) tacH (14) tres 7) tRRH (15) [+ trow (16) toma 20) t CAC (18) tz ea) trac (19) VALID DATA-OUT tLz @1) Waveforms of Early Write Cycle ADDRESS vO Vin Vie V53C104F Rev. 1.0 Me 6353391 0002748 470 Ea 2-78 tac 2) tras (1) tan (23) TosH (a) ; tRsH wes) TCRP (13) teas (5) torp 13) taco (6) toan (44) ToaH (11) 'RAH (9) base (10) ROW ADDRESS COLUMN ADDRESS trap wou (28) To Sow es) Uwe (29) twes (27) wore, en RWL (31) toHA (4s) tos (a2) Re Ty (39) $$ $$$ $f wuooanin HIGH-Z 676 02 January 1995MOSEL VITELIC V53C104F Waveforms of OE Controlled Write Cycle tre @) tras (1) RP (gy _ yee F*E Ot far 2) RAS N Ke iL tesu (4) = lorp (13) i trop 6) lasy wy) k ' onp 13) as Viq \ tcas (5) vir w- _S \ | I trap (aay ef Kan | a tRAH (9) Lo 1 (CAH (11) lasr @) ~ Tasc (10) Vv ADDRESS ve ROW ADDRESS KX COLUMN ADDRESS MKAKXXK KKK KK Lo -! Cw (26) bet awe (91) >4 bt typ (29y| Vin we wh LLLLLL. LLLLLLL LX ITLL LLL LL LAL LL. tWor (aa) _ Vig me LILLLLLLL LLL LA NLLLLLLLL LLL LLL LLL. L loen (as) re tbw (33) *| Ds (82) Vie ik we Wo) RRR momo NX XKKKKKKKRRRRRERED ve X 676 03 Waveforms of Read-Modify-Write Cycle trwe (36) tRRW (a7) trp (a) RAS CAS ADDRESS vO V53C104F Rev. 1.0 January 1995 Vin Vit Vi Vit Vin Vit Vie Vit Vin Vit Vin Vit _ TAR (23) tes (4) 0 pen na Corp (13) trep 6) Trash (wyi25) toRP (13) _ CRW (40) tran (9) toaH (a) tase (10) COLUMN Taw (41) Lowe 26) trap (2a) jt wo (38) Tawe (31) 'Rwn (39) t we (29) a tena eo) toac (17) YoeED (as) 'oH (33) tcac (18) trac (19) Vou VALID Vor DATA-QUT tizen M@ 6353391 0002749 30? 2-79MOSEL VITELIC V53C104F Waveforms of Fast Page Mode Read Cycle VH RAS Vi Vy IH CAS Yi Vig appRess 4 vi VYu WE Vi Va OE Vin Vou OH vo Yor t FP (3) tar (23) {be (42) trsH(Ry(12) icp (a3) CAS (6) then ) top (13) tore teas (6) cas tesH ~toAR (44) tasc tRaH (9) ToaH (11) ASC Tasn (a) ToaH (11) COLUMN COLUMN TRH (14) tRoH (14) tres 7) lt oaH (1) tres (7) acs 7) tona (20) : tena (eo) , CAP (45) RBH (15} toac (17) oac (17) toac tz (22) t Rac (19) Voac (18) t cac (18) tiz ery tz (22) HZ (22) toac a8) Wen tHz (22) bz (22) wen tz (22) VALID OUT. 676 05 Waveforms of Fast Page Mode Write Cycle Vu Ras vu Vay cas vi ADDRESS Va WE iH Vi Vig 1H OE Vi Vn vo vi tar (233 | bap (3 +} tras (1) N | . \ | "| ht bore (13) + Pc (42) URsH (wy(25) | e- tRoD (6) | top cay tas (5) tcas ey I st test (4) hy t Sop (ia) teas (5) > * RAH (9) Su tar (44) I tascia| "asc (10) t GAH (11) et CAH (11) jet oet-t oa (11 Ht + COLUMN COLUMN COLUMN ADDRESS ADDRESS h ADDRESS rt he t ewr (26) ht owi (26) it teewr (26) I twos (27) twes (27) ft twes (27) two (2a) t twou (2a) 9 _ 'Rw. 31) 4 | + tor (28) we twp (29) 4 twp (ea) twe (29) TTETTTTNATTTT TTT NETTIE Tos (a2) "ps (32) tos (ay DH (33) tH (33) tn (33) VALID y VALID VALID { DATAIN b OPEN { DATAIN p { DATAIN OPEN 676 06 V53C104F Rav. 1.0 January 1995 BH 6353391 0002750 029 ey MOSEL VITELIC Waveforms of Fast Page Mode Read-Write Cycle ye Ras to CAS v IL appress 4 to _ {dq WE | = ik OE iL Viog vO OH Vyo. V53C 104F \ tras a1) y test (4) trp (a) htacp (6) | 'pom (50) k tray cwy(25) top (43) oRP (13) h+ teas (6) H+ tons s) p+ tcas (5) __ TRaD (24) | \ M N I ~ tRAH (9) bt tar (44) >| L wm int- tase (10) tase (19) tase ( 0) bae- + tasR (a) t CAH (11) poet ba (44) oan (11) COLUMN X COLUMN) M COLUMN XXX KY ADDRESS ADDRESS DDRESS tres 7) twp (33) l. town on) tcwo penn 8) fem1t RWI (31) - (26) plcwo (38) + tow (26) eon (26) t f Taw (41) h tawn (41) iy AWD (41) > teaa 20) 4 WP (28) twe! (28) | twp (29) toac (a7} he ToED (a5) ft cep (5) beoac (18) tcac val he t Rac (193 >! tuz (22) fm pe tDH (33) I*'on ay tos (aa) S (32) tiz (at) Waveforms of RAS-Only Refresh Cycle RAS CAS ADDRESS 676 07 tre (a) i! RP (3) >4 Va taas (1) F vu Nn t CRP (13) Via Yy%- tasn (s) URAH (9) Yu ROW Vi ADDRESS 1579 OB NOTE: WE, OE = Don't care V59C104F Rev.1.0 January 1995 BE 6353391 0002751 TLSMOSEL VITELIC Waveforms of CAS-before-RAS Refresh Cycle V53C104F Re @) h+ trp (3) } t Ras (1) Upp (a) ] S Ss VKe } ras N \ vi m tape 4s) top ay toHR (49) leet osR (47) Vya cs OM / / vi "yz (22) 0 vo OH b Yo7- 675 07 NOTE: WE, OE, Ag-A7 = Don't care Waveforms of Hidden Refresh Cycle (Read) tac {2} tro (2) rt tras (4) tap (ay] +t ras (1) | Uap (3) __ va OT bt ag (23 | RAS N \ \ poe tcre (13) metro (6) TASH (R)(12) ke toHR (49) ft orp (13) *I oe NT N Po NL trap (24) tasn@y >| bet tase (10) TRaH (gy fe Tr toan (1) Vig '4 ROW COLUMN ADDRESS Vir OOO] ADDRESS tacs a fh $}- TRRH (15) we YM V/f NLL LLL LLL LL LLL LLL. he- loa, (20) lowe (17) me LTT) LMLLLLLLLLLLLLLL bet cac (18) iz 17 rt th2 (22) | tuz (aay T pac (18) Vou vo VALID DATA Vor _ V53C104F Rev. 1.0 January 1995. MH 6353391 0002752 5Tl 2-82 676 10MOSEL VITELIC V53C 104F Waveforms of Hidden Refresh Cycle (Write) tre (2) TRAS (1) trp (3) RAS ViH lar (23) vit treo RSH (12) top (13) Corp (13) __ Vig CAS V L TRAD (24) tasr (a) tase (10) tRAH @) toaH (1) ADDRESS H ~~ ROW COLUMN L twes (27) t we (28) _ Ve WE I vi OE Vin Yin tos (32) to (a3) Vig IL ToHR (48) 676 11 V53C104F Rev. 1.0 January 1995 2-83 Fg 6353391 0002753 438MOSEL VITELIC V53C104F Waveforms of CAS-before-RAS Refresh Counter Test Cycle RAS CAS ADDRESS vo vO thas (1) tour (49) top Y asH (wes) tos (47) CAS Viq Yum tase (10) boa (11) Vin COLUMN ADDRESS Vi tRRH (15) tRCH (14) READ CYCLE t RCS {7} Vy vii ROH (16) Yoac (17) Vin Vi Vin Vit RWL (31) Cwr (26) wou (28) WRITE CYCLE t wes (27) Viq Vin Via vi bs (a2) Vw Vi 1486 12 V53C104F Rev. 1.0 January 1995 MB 63539391] 0002754 774 me 2-84MOSEL VITELIC Functional Description The V53C104F is a CMOS dynamic RAM opti- mized for high data bandwidth, low power applica- tions. Itis functionally similar to a traditional dynamic RAM. The V53C104F reads and writes data by multiplexing an 18-bit address into a 9-bit row and a 9-bit column address. The row address is latched by the Row Address Strobe (RAS). The column address flows through an internal address buffer and is latched by the Column Address Strobe (CAS). Be- cause access time is primarily dependent on a valid column address rather than the precise time that the CAS edge occurs, the delay time from RAS to CAS has little effect on the access time. Memory Cycle A memory cycle is initiated by bringing RAS tow. Any memory cycle, once initiated, mustnot be ended or aborted before the minimumt, ,. time has expired. This ensures proper device operation and data integ- rity. A new cycle must not be initiated until the minimum precharge time t.,,/t,, has elapsed. Read Cycle A Read cycle is performed by holding the Write Enable (WE) signal High during a RAS/CAS opera- tion. The column address must be held for a mini- mum specified by t,,. Data Out becomes valid only when toro: trac toaa and toa, are all satisifed. As a result, the access time is dependent on the timing relationships between these parameters. For ex- ample, the access time is limited by t,,, when t loac aNd toa, are all satisfied. RAC Write Cycle AWrite Cycle is performed by taking WE and CAS low during a RAS operation. The column address is latched by CAS. The Write Cycle can be WE con- trolled or CAS controlled depending on whether WE. or CAS falls later. Consequently, the input data must be valid at or before the falling edge of WE or CAS, whichever occurs last. In the CAS-controlled Write Cycle, when the leading edge of WE occurs prior to the CAS low transition, the I/O data pins will be in the High-Z state at the beginning of the Write function. V53C104F Rev. 1.0 January 1995 WM 6353391 0002755 00 V53C104F Ending the Write with RAS or CAS will maintain the output in the High-Z state. In the WE controlled Write Cycle, OE must be in the high state and t,,,, must be satisfied. Refresh Cycle To retain data, 512 Refresh Cycies are required in each 8 ms period. There are two ways to refresh the memory: 1. By clocking each of the 512 row addresses (A, through A,) with RAS at least once every 8 ms. Any Read, Write, Read-Modify-Write or RAS-only cycle refreshes the addressed row. 2. Using a CAS-before-RAS Refresh Cycle. If CAS makes a transition from low to high to low after the previous cycle and before RAS falls, CAS-before- RAS refresh is activated. The V53C104F uses the output of an internal 9-bit counter as the source of row addresses and ignore external address _ in- puts. CAS-before-RAS is a refresh-only mode and no data access or device selection is allowed. Thus, the output remains in the High-Z state during the cycle. ACAS-before-RAS counter test mode is provided to ensure reliable operation of the internal refresh counter. Data Retention Mode The V53C104F offers a CMOS standby mode that is entered by causing the RAS clock to swing be- tween a valid V, and an extra high V,,, within 0.2 V of V,,- While the RAS clock is at the extra high level, the V53C104F power consumption is reduced to the low I... level. Overall |, consumption when DDE operating in this mode can be calculated as follows: (tac) * (lppy) + (taxvtac) * (lope) i= tax Where: t,,,. = Refresh Cycle Time tay = Refresh Interval / 512MOSEL VITELIC Fast Page Mode Operation Fast Page Mode operation permits all 512 col- umns within a selected row of the device to be randomly accessed at a high data rate. Maintaining RAS tow while performing successive CAS cycles retains the row address internally and eliminates the need to reapply itfor each cycle. The column address buffer acts as a transparent or flow-through latch while CAS is high. Thus, access begins from the occurrence of a valid column address rather than from the falling edge of CAS, eliminating t,,, and t, from the critical timing path. CAS latches the address into the column address buffer and acts as an output enable. During Fast Page Mode operation, Read, Write, Read-Modify-Write or Read-Write-Read cycles are possible at random addresses within a row. Following the initial entry cycle into Fast Page Mode, accessist,,, ort,,, controlled. if the column address is valid prior to the rising edge of CAS, the access time is referenced to the CAS rising edge and is specified byt, ap: Ifthe column address is valid after the rising CAS edge, access is timed fromthe occurrence of a valid address and is specified by toga: In both cases, the falling edge of CAS latches the address and enables the output. Fast Page Mode provides a sustained data rate of 25 MHz for applications that require high data rates such as bit-mapped graphics or high-speed signal processing. The following equation can be used to calculate the maximum data rate: 512 Data Rate= tag + OTT X tag Data Output Operation The V53C104F Input/Output is controlled by OE, CAS, WE and RAS. ARAS low transition enables the transfer of data to and from the selected row address in the Memory Array. A RAS high transition disables data transfer and latches the output data if the output is enabled. After a memory cycle is initiated with a RAS low transition, a CAS low transition or CAS low level enables the internal /O path. A CAS high transition or a CAS high level disables the I/O path and the output driver if it is enabled. A CAS low transition while RAS is high has no effect on the I/O data path or on the output drivers. The output drivers, when otherwise enabled, can be disabled by holding V53C104F Rev, 1.0 January 1995 M 63533591 0002756 Su? ama a V53C104F OE high. The OE signal has no effect on any data stored in the output latches. A WE low level can also disable the output drivers when CAS is low. During a Write cycle, if WE goes low at a time in relationship to CAS that would normally cause the outputs to be active, itis necessary to use OE to disable the output drivers prior to the WE Jow transition to allow Data In Setup Time (t,,) to be satisfied. Power-On 2-86 After application of the V,,, supply, an initial pause of 200 is is required followed by a minimum of 8 initialization cycles (any combination of cycles con- taining a RAS clock). Eight initialization cycles are required after extended periods of bias without clocks (greater than the Refresh Interval). During Power-On, the V,,, current requirement of the V53C104F is dependent on the input levels of RAS and CAS. If RAS is low during Power-On, the device will go into an active cycle and I,,,, will exhibit current transients. It is recommended that RAS and CAS track with V,,, or be held at a valid V,,, during Power-On to avoid current surges. Table 1. V53C104F Data Output Operation for Various Cycle Types Cycle Type VO State Read Cycles Data from Addressed Memory Cell CAS-Controlled Write High-Z Cycle (Early Write) WE-Controlled Write OE Controlied. High Cycle (Late Write) OE = High-Z I/Os Read-Modity-Write Data from Addressed Cycles Memory Cell Fast Page Mode Data from Addressed Read Memory Cell Fast Page Mode Write High-Z Cycle (Early Write) Data from Addressed Memory Cell Fast Page Mode Read- Modify-Write Cycle RAS-only Refresh High-Z CAS-before-RAS Refresh Cycle Data remains as in previous cycle CAS-only Cycles High-Z