Rate Conversion/Jitter Attenuation Products System clock trees are becoming more complex often requiring rate conversion with jitter attenuation at very low bandwidth frequencies and distribution of several clock frequencies to multiple loads. Rate conversion/ jitter attenuation devices from Microsemi(R) can lock to input clock signals and filter jitter starting at 30 mHz. These devices lower bill of material costs, simplify design, and improve performance by replacing external components traditionally used to build timing clock trees with a fully integrated single chip-solution. Clock Fanout Buffer Clock Synthesis Rate Conversion * Providing spec-compliant timing for multigigabit PHYs is difficult * Adding external jitter cleaning circuitry to provide PHYs with spec-compliant timing is costly and complex High Integration PHYs NPU Clock Rate Conversion Solutions Address Key Customer Pains SRAM DRAM FPGA * Up to 2 independent programmable synthesizers replace competing multi-chip single channel solutions * Integrated fanout buffers with up to 20 output clock signals in two frequency families Industry Leading Ultra-low Jitter * Ultra-low 160 fs jitter on all outputs Bridge Applications * Timing generation for enterprise routers and switches, storage area network equipment, servers, communications equipment. and broadcast video applications * Processor, processor bus, SDRAM, and DDR clocks * Timing for 10 Gigabit CDRs, Rapid-IO, PCIe, Serial MII, Star Fabric, Fibre Channel, XAUI Availability and Support Microsemi Clock Management products are in volume production. To learn more about Microsemi's clock products, visit www.microsemi. com/products/timing-and-synchronization/frequency-conversion. Full information, including complete data sheets and design manuals, is available to registered MyMicrosemi customers. To register for a MyMicrosemi account, visit www.microsemi.com/create-an-account. * Low bandwidth jitter filtering on input clock signals starting at 30 mHz Wide Frequency Range * Output clock frequencies from <1 Hz to 1035 MHz * Fractional synthesizers support any-to-any clock synthesis Highly Programmable Outputs * Control of each output clock's signal format, voltage, drive strength, frequency divider, and phase * Replace external support components such as fanout buffers and format converters Custom Configuration * Clock signals available at power-up with integrated EEPROM; easily configurable with hardware pins Microsemi makes no warranty, representation, or guarantee regarding the information contained herein or the suitability of its products and services for any particular purpose, nor does Microsemi assume any liability whatsoever arising out of the application or use of any product or circuit. The products sold hereunder and any other products sold by Microsemi have been subject to limited testing and should not be used in conjunction with mission-critical equipment or applications. Any performance specifications are believed to be reliable but are not verified, and Buyer must conduct and complete all performance and other testing of the products, alone and together with, or installed in, any end-products. Buyer shall not rely on any data and performance specifications or parameters provided by Microsemi. It is the Buyer's responsibility to independently determine suitability of any products and to test and verify the same. The information provided by Microsemi hereunder is provided "as is, where is" and with all faults, and the entire risk associated with such information is entirely with the Buyer. Microsemi does not grant, explicitly or implicitly, to any party any patent rights, licenses, or any other IP rights, whether with regard to such information itself or anything described by such information. Information provided in this document is proprietary to Microsemi, and Microsemi reserves the right to make any changes to the information in this document or to any products and services at any time without notice. Rate Conversion/Jitter Attenuation Products Featured Products ZL30253 ic1_p/n ZL30252, ZL30253, and ZL30254 Input Block Divider, Monitor ic2_p/n DIV DPLL APLL ic3_gpio3 xout DIV Crystal Driver DIV oc1_p/n DIV oc2_p/n DIV oc3_p/n x2 EEPROM Configuration and Status SPI/I2C Slave GPIO/ Alarms Control Interface or EEPROM (optional) GPIO Input Block Divider, Monitor ic2_p/n * Up to 6 output clock signals * Control over each output clock's signal format, voltage, and drive strength * Frequency divider and phase adjustment per output * Numerically Controlled Oscillator mode DPLL APLL1 mclk_p/n xout Crystal Driver xin If XO input ~200 MHz APLL2 Master Clock APLL SPI Master Configuration and Status EEPROM (Optional) SPI Slave GPIO Alarms JTAG Control Interface GPIO JTAG DIV oc2_p/n * Small 5 mm x 5 mm QFN DIV oc3_p/n DIV oc4_p/n DIV oc5_p/n DIV oc6_p/n DIV oc7_p/n DIV oc8_p/n DIV oc9_p/n DIV oc10_p/n MAX24605 and MAX24610 * Ultra-low jitter provides spec-compliant timing for multi-gigabit interfaces * Any-to-any frequency conversion / jitter attenuation. Output frequencies from <1Hz to 750 MHz with ultra-low 180 fs RMS jitter * Low-bandwidth DPLL * Precision synthesizer generates any clock rate from 1 Hz to 177.5 MHz with jitter below 1 ps OSCi Clock Generation0 Precision Synthesizer 0 DPLL0 SPI/I2C Slave Control Interface Microsemi Corporate Headquarters One Enterprise, Aliso Viejo, CA 92656 USA Within the USA: +1 (800) 713-4113 Outside the USA: +1 (949) 380-6100 Fax: +1 (949) 215-4996 Email: sales.support@microsemi.com www.microsemi.com * Spread Spectrum mode PCIe(R) compliant ZL30159 Master Clock Reference Monitoring oc1_p/n * Up to 20 output clock signals in two frequency families * Control over each output clock's signal format, voltage, and drive strength * Frequency divider and phase adjustment per output * 10 mm x 10 mm CSBGA OSCo Configuration and Status DIV * 4 Hz to 400 Hz programmable bandwidth, attenuates low frequency jitter * On-chip fanout buffers with flexible output configuration ZL30159 ref0 * Any-to-any frequency conversion / jitter attenuation. Output frequencies from <1 Hz to 1035 MHz with ultra-low 160 fs RMS jitter * Low-bandwidth DPLL * 14 Hz to 500 Hz programmable bandwidth, attenuates low frequency jitter * Universal Outputs MAX24610 ic1_p/n * Ultra-low jitter provides spec-compliant timing for multi-gigabit interfaces JTAG GPIO/ Alarms JTAG GPIO hpoutclk0 hpoutclk1 * Programmable digital PLL synchronizes to any clock rate from 1 Hz to 750 MHz Flexible output configuration * 30 mHz to 896 Hz programmable bandwidth, attenuates low frequency jitter * Two LVCMOS outputs * 9 mm x 9 mm LBGA Microsemi Corporation (Nasdaq: MSCC) offers a comprehensive portfolio of semiconductor and system solutions for aerospace & defense, communications, data center and industrial markets. Products include high-performance and radiation-hardened analog mixed-signal integrated circuits, FPGAs, SoCs and ASICs; power management products; timing and synchronization devices and precise time solutions, setting the world's standard for time; voice processing devices; RF solutions; discrete components; enterprise storage and communication solutions, security technologies and scalable anti-tamper products; Ethernet solutions; Power-over-Ethernet ICs and midspans; as well as custom design capabilities and services. Microsemi is headquartered in Aliso Viejo, California and has approximately 4,800 employees globally. Learn more at www.microsemi.com. (c)2018 Microsemi Corporation. All rights reserved. Microsemi and the Microsemi logo are registered trademarks of Microsemi Corporation. All other trademarks and service marks are the property of their respective owners. MSCC-0105-PB-01001-1.00-0118