Enpirion(R) Power Datasheet EN2360QI 6A PowerSoC Voltage Mode Synchronous Buck With Integrated Inductor Not Recommended for New Designs Description Features The EN2360QI is a Power System on a Chip (PowerSoC) DC-DC converter. It integrates MOSFET switches, small-signal control circuits, compensation and an integrated inductor in an advanced 8x11x3mm QFN module. It offers high efficiency, excellent line and load regulation over temperature. The EN2360QI operates over a wide input voltage range and is specifically designed to meet the precise voltage and fast transient requirements of high-performance products. The EN2360QI features frequency synchronization to an external clock, power OK output voltage monitor, programmable soft-start along with thermal and short circuit protection. The device's advanced circuit design, ultra high switching frequency and proprietary integrated inductor technology delivers high-quality, ultra compact, nonisolated DC-DC conversion. The Altera Enpirion solution significantly helps in system design and productivity by offering greatly simplified board design, layout and manufacturing requirements. In addition, overall system level reliability is improved given the small number of components required with the Altera Enpirion solution. All Altera Enpirion products are RoHS compliant, halogen free and are compatible with lead-free manufacturing environments. * * * * * * * * * * * * 47nF Applications * * * * * Space Constrained Applications Distributed Power Architectures Output Voltage Ripple Sensitive Applications Beat Frequency Sensitive Applications Servers, Embedded Computing Systems, LAN/SAN Adapter Cards, RAID Storage Systems, Industrial Automation, Test and Measurement, and Telecommunications Efficiency vs. Output Current 0.22F 100 RPG 560 VIN Integrated Inductor, MOSFETs, Controller Wide Input Voltage Range: 4.5V - 14V Total Solution Size Estimate: 185mm2 Frequency Synchronization (External Clock) 1% Initial VOUT Accuracy Output Enable Pin and Power OK signal Programmable Soft-Start Time Can be Pin Compatible with the EN2340QI (4A) Under Voltage Lockout Protection (UVLO) Short Circuit Protection Thermal Shutdown Protection RoHS Compliant, MSL Level 3, 260oC Reflow VOUT PG BTMP VDDB BGND VOUT 90 PVIN ON ENABLE OFF 22F 1206 2x 47F 0805 RA CA AVINO AVIN 1F 1F RCA VFB SS EFFICIENCY (%) EN2360QI RVB 4.75k 80 70 60 50 40 30 20 47nF PGND PGND FQADJ AGND RCLX VOUT = 3.3V 10 RB 0 0 RFS 100k Figure 1. Simplified Applications Circuit (Footprint Optimized) CONDITIONS VIN = 12.0V AVIN = 3.3V Dual Supply 0.5 1 1.5 2 2.5 3 3.5 4 4.5 5 OUTPUT CURRENT (A) 5.5 6 Figure 2. Highest Efficiency in Smallest Solution Size www.altera.com/enpirion Page 1 07514 June 2, 2015 Rev D EN2360QI Ordering Information Part Number EN2360QI EVB-EN2360QI Package Markings EN2360QI EN2360QI TAMBIENT Rating (C) -40 to +85 Package Description 68-pin (8mm x 11mm x 3mm) QFN T&R QFN Evaluation Board Packing and Marking Information: www.altera.com/support/reliability/packing/rel-packing-and-marking.html NC NC NC NC NC NC(SW) NC(SW) NC(SW) CGND NC FQADJ RCLX SS EAIN VFB AGND AGND AVIN ENABLE POK 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 Pin Assignments (Top View) 48 S_OUT NC 1 NC 2 47 S_IN NC 3 46 BGND NC 4 45 VDDB NC 5 44 BTMP NC 6 43 PG 42 AVINO 41 PVIN 40 PVIN KEEP OUT 69 PGND KEEP OUT KEEP OUT 28 29 30 31 32 33 34 NC(SW) PGND PGND PGND PGND PGND PGND VOUT VOUT 27 PVIN NC(SW) 14 NC 26 PVIN 35 NC 36 25 13 NC NC 24 PVIN VOUT 37 23 12 22 NC 21 PVIN VOUT 38 20 11 VOUT NC 19 PVIN VOUT 39 18 10 VOUT NC 17 9 VOUT NC 16 8 VOUT NC 15 7 NC NC Figure 3: Pin Out Diagram (Top View) NOTE A: NC pins are not to be electrically connected to each other or to any external signal, ground, or voltage. All pins including NC pins must be soldered to the PCB. Failure to follow this guideline may result in part malfunction or damage. NOTE B: Shaded area highlights exposed metal below the package that is not to be mechanically or electrically connected to the PCB. Refer to Figure 14 for details. NOTE C: White `dot' on top left is pin 1 indicator on top of the device package. Pin Description I/O Legend: PIN 1-15, 25-26, 59, 6468 16-24 P=Power G=Ground NC=No Connect I=Input O=Output I/O=Input/Output NAME I/O FUNCTION NC NC NO CONNECT - These pins may be internally connected. Do not connect them to each other or to any other electrical signal. Failure to follow this guideline may result in device damage. VOUT O Regulated converter output. Connect these pins to the load and place output capacitor www.altera.com/enpirion Page 2 07514 June 2, 2015 Rev D EN2360QI PIN NAME I/O 27-28, 61-63 NC(SW) NC 29-34 PGND G 35-41 PVIN P 42 AVINO O 43 PG I/O 44 BTMP I/O 45 VDDB O 46 BGND G 47 S_IN I 48 S_OUT O 49 POK O 50 ENABLE I 51 AVIN P 52, 53 AGND G 54 VFB I/O 55 EAIN I 56 SS I/O 57 RCLX I/O 58 FQADJ I/O 60 CGND 69 PGND FUNCTION between these pins and PGND pins 29-31. NO CONNECT - These pins are internally connected to the common switching node of the internal MOSFETs. They are not to be electrically connected to any external signal, ground, or voltage. Failure to follow this guideline may result in damage to the device. Input/Output power ground. Connect these pins to the ground electrode of the input and output filter capacitors. See VOUT and PVIN pin descriptions for more details. Input power supply. Connect to input power supply. Decouple with input capacitor to PGND pins 32-34. Internal 3.4V linear regulator output. Connect this pin to AVIN (Pin 51) for applications where operation from a single input voltage (PVIN) is required. If AVINO is being used, place a 1F, X5R, capacitor between AVINO and AGND as close as possible to AVINO. PMOS gate. Place a 47nF, X5R/X7R, capacitor between this pin and BTMP. A 560 resistor must be connected from PVIN to PG to support monotonic shut down. Bottom plate ground. See pin 43 description. Internal regulated voltage used for the internal control circuitry. Place a 0.22F, X5R/X7R, capacitor between this pin and BGND. Ground for VDDB. See pin 45 description. Do not connect BGND to any other ground. Digital synchronization input. This pin accepts either an input clock to phase lock the internal switching frequency or a S_OUT signal from another EN2360QI. Leave this pin floating if not used. Digital synchronization output. Can be used to synchronize the internal clock with another device switching at a similar frequency. Leave this pin floating if not used. Power OK is an open drain transistor (pulled up to AVIN or similar voltage) used for power system state indication. POK is logic high when VOUT is above 90% of VOUT nominal. Leave this pin floating if not used. Output enable. Applying a logic high to this pin enables the output and initiates a soft-start. Applying a logic low disables the output. ENABLE logic cannot be higher than AVIN (refer to Absolute Maximum Ratings). Do not leave floating. See Power Up/Down Sequencing section for details. Input power supply for the controller. Place a 1F, X5R/X7R, capacitor between AVIN and AGND. Analog ground. This is the ground return for the controller. All AGND pins need to be connected to a quiet ground. External feedback input. The feedback loop is closed through this pin. A voltage divider at VOUT is used to set the output voltage. The mid-point of the divider is connected to VFB. A phase lead network from this pin to VOUT is also required to stabilize the loop. Optional error amplifier input. Allows for customization of the control loop for performance optimization. Leave this pin floating if not used. Soft-start node. The soft-start capacitor is connected between this pin and AGND. The value of this capacitor determines the startup time. See Soft-Start Operation in the Functional Description section for details. Short circuit protection. Connect a 100k resistor from RCLX to ground. Adding a resistor (RFS) to this pin will adjust the switching frequency of the EN2360QI. See Table 1 for suggested resistor values on RFS for various PVIN/VOUT combinations to maximize efficiency. Do not leave this pin floating. Test pin. For Altera Internal Use Only. Connect to GND plane at all times. Not a perimeter pin. Device thermal pad to be connected to the system GND plane for heatsinking purposes. www.altera.com/enpirion Page 3 07514 June 2, 2015 Rev D EN2360QI Absolute Maximum Ratings CAUTION: Absolute Maximum ratings are stress ratings only. Functional operation beyond the recommended operating conditions is not implied. Stress beyond the absolute maximum ratings may impair device life. Exposure to absolute maximum rated conditions for extended periods may affect device reliability. PARAMETER SYMBOL MIN MAX UNITS VIN -0.5 15 V Voltages on: ENABLE, POK -0.3 AVIN+0.3 V Pin Voltages - AVINO, AVIN, S_IN, S_OUT 2.5 6.0 V Pin Voltages - VFB, SS, EAIN, RCLX, FQADJ , VDDB, BTMP -0.5 2.75 V Dual Supply PVIN Rising and Falling Slew Rate (Note 1) 0.3 25 V/ms Single Supply PVIN Rising and Falling Slew Rate (Note 1) 0.3 6 V/ms 9 A 150 C 150 C Reflow Temp, 10 Sec, MSL3 JEDEC J-STD-020A 260 C ESD Rating - all pins (based on Human Body Model) 2000 V ESD Rating (based on CDM) 500 V Voltages on - PVIN, VOUT, PG Maximum Continuous Output Current IOUT_CONT_MAX Storage Temperature Range TSTG Maximum Operating Junction Temperature -65 TJ-ABS Max Recommended Operating Conditions SYMBOL MIN MAX UNITS PVIN: Input Voltage Range PARAMETER PVIN 4.5 14.0 V AVIN: Controller Supply Voltage AVIN 2.5 5.5 V Output Voltage Range (Note 2) VOUT 0.75 5.0 V Output Current IOUT 0 6.0 A Operating Ambient Temperature TA - 40 +85 C Operating Junction Temperature TJ - 40 +125 C Thermal Characteristics SYMBOL TYP UNITS Thermal Resistance: Junction to Ambient (0 LFM) (Note 3) PARAMETER JA 16 C/W Thermal Resistance: Junction to Case (0 LFM) JC 2 C/W Thermal Shutdown TSD 160 C Thermal Shutdown Hysteresis TSDH 35 C Note 1: PVIN rising and falling slew rates cannot be outside of specification. For accurate power up sequencing, use a fast ENABLE logic (>1V/100s) after both AVIN and PVIN are high. Note 2: Dropout: Maximum VOUT VIN - 2.5V Note 3: Based on 2oz. external copper layers and proper thermal design in line with EIJ/JEDEC JESD51-7 standard for high thermal conductivity boards. www.altera.com/enpirion Page 4 07514 June 2, 2015 Rev D EN2360QI Electrical Characteristics NOTE: VIN=12V, Minimum and Maximum values are over operating ambient temperature range (-40C TA +85C) unless otherwise noted. Typical values are at TA = 25C. PARAMETER MAX UNITS Operating Input Voltage SYMBOL PVIN TEST CONDITIONS MIN 4.5 TYP 14.0 V Controller Input Voltage AVIN 2.5 5.5 V AVIN Under Voltage Lock-out rising AVINUVLOR Voltage above which UVLO is not asserted 1.7 2.2 2.4 V AVIN Under Voltage Lock-out falling AVINOVLOF Voltage below which UVLO is asserted 1.7 2.1 2.3 V AVIN Pin Input Current Internal Linear Regulator Output Voltage Shut-Down Supply Current IAVIN 7 mA AVINO 3.4 V IPVINS PVIN=12V, AVIN=3.4V, ENABLE=0V 500 A IAVINS PVIN=12V, AVIN=3.4V, ENABLE=0V Feedback node voltage at: VIN = 12V, ILOAD = 0, TA = 25C Only 100 A Feedback Pin Voltage VFB Feedback Pin Voltage VFB Feedback node voltage at: 4.5V VIN 14V; 0A ILOAD 6A Feedback pin Input Leakage Current IFB VFB pin input leakage current (Note 4) VOUT Rise Time tRISE Soft Start Capacitor Range CSS_RANGE Continuous Output Current IOUT_CONT ENABLE Logic High VENABLE_HIGH ENABLE Logic Low VENABLE_LOW ENABLE Lockout Time TENLOCKOUT ENABLE pin Input Current Switching Frequency IENABLE FSW 0.60 0.606 0.588 0.60 0.612 -5 5 CSS = 47nF (Note 4, Note 5 and Note 6) 2.8 10 V nA ms nF 0 6 A 4.5V VIN 14V; 1.25 AVIN V 4.5V VIN 14V; 0 0.95 V Subject to thermal derating 47 V 68 370k pull down (Note 4) RFS = 3.01k External SYNC Clock Frequency Lock Range FPLL_LOCK Range of SYNC clock frequency (See Table 1) S_IN Threshold - Low VS_IN_LO S_IN Clock Logic Low Level (Note 4) S_IN Threshold - High VS_IN_HI S_IN Clock Logic High Level (Note 4) S_OUT Threshold - Low VS_OUT_LO S_OUT Clock Logic Low Level (Note 4) S_OUT Threshold - High VS_OUT_HI S_OUT Clock Logic High Level (Note 4) POKLT Percentage of Nominal Output Voltage for POK to be Low POK Lower Threshold 0.594 POK Output low Voltage VPOKL With 4mA current sink into POK POK Output Hi Voltage VPOKH PVIN range: 4.5V VIN 14V 8 ms 4 A 1.0 MHz 0.8 1.8 1.8 1.8 MHz 0.8 V 2.5 V 0.8 V 2.5 V 90 % 0.4 V AVIN V www.altera.com/enpirion Page 5 07514 June 2, 2015 Rev D EN2360QI PARAMETER POK Pin VOH leakage Current SYMBOL IPOKL TEST CONDITIONS POK High (Note 4) MIN TYP MAX UNITS 1 A Note 4: Parameter not production tested but is guaranteed by design. Note 5: Rise time calculation begins when AVIN > VUVLO and ENABLE = HIGH. Note 6: VOUT Rise Time Accuracy does not include soft-start capacitor tolerance. www.altera.com/enpirion Page 6 07514 June 2, 2015 Rev D EN2360QI Typical Performance Curves Efficiency vs. Output Current 100 100 90 90 80 80 EFFICIENCY (%) EFFICIENCY (%) Efficiency vs. Output Current 70 60 50 VOUT = 5.0V 40 VOUT = 3.3V VOUT = 2.5V 30 VOUT = 1.8V 20 VOUT = 1.2V 10 VOUT = 1.0V CONDITIONS VIN = 12.0V AVIN = 3.3V Dual Supply 70 60 VOUT = 5.0V 50 VOUT = 3.3V 40 VOUT = 2.5V 30 VOUT = 1.8V 20 VOUT = 1.2V 10 VOUT = 1.0V 0 0 0 0.5 1 1.5 2 2.5 3 3.5 4 4.5 OUTPUT CURRENT (A) 5 5.5 0 6 0.5 MAXIMUM OUTPUT CURRENT (A) MAXIMUM OUTPUT CURRENT (A) 7.0 6.0 5.0 VOUT = 2.5V VOUT = 3.3V 4.0 VOUT = 5.0V 3.0 CONDITIONS VIN = 12V TJMAX = 125C JA = 16C/W 8x11x3mm QFN No Air Flow 2.0 1.0 1 1.5 2 2.5 3 3.5 4 4.5 OUTPUT CURRENT (A) 5 5.5 6 Output Current De-rating Output Current De-rating 7.0 6.0 5.0 VOUT = 2.5V VOUT = 3.3V 4.0 VOUT = 5.0V 3.0 CONDITIONS VIN = 10V TJMAX = 125C JA = 16C/W 8x11x3mm QFN No Air Flow 2.0 1.0 0.0 0.0 68 70 72 74 76 78 80 82 AMBIENT TEMPERATURE (C) 84 68 86 MAXIMUM OUTPUT CURRENT (A) 7.0 6.0 VOUT = 3.3V 5.0 VOUT = 5.0V 4.0 3.0 CONDITIONS VIN = 12V TJMAX = 125C JA = 13C/W 8x11x3mm QFN Air Flow (200fpm) 2.0 1.0 70 72 74 78 80 82 76 AMBIENT TEMPERATURE (C) 84 86 De-rating with Air Flow (200fpm) De-rating with Air Flow (200fpm) MAXIMUM OUTPUT CURRENT (A) CONDITIONS VIN = 10.0V AVIN = 3.3V Dual Supply 7.0 6.0 VOUT = 3.3V 5.0 VOUT = 5.0V 4.0 3.0 CONDITIONS VIN = 10V TJMAX = 125C JA = 13C/W 8x11x3mm QFN Air Flow (200fpm) 2.0 1.0 0.0 0.0 75 76 77 78 79 80 81 82 83 AMBIENT TEMPERATURE (C) 84 85 75 76 77 78 79 80 81 82 83 AMBIENT TEMPERATURE (C) 84 85 www.altera.com/enpirion Page 7 07514 June 2, 2015 Rev D EN2360QI Typical Performance Curves Output Voltage vs. Output Current Output Voltage vs. Output Current 1.205 1.004 VIN = 8V 1.003 VIN = 10V 1.002 VIN = 12V OUTPUT VOLTAGE (V) OUTPUT VOLTAGE (V) 1.005 1.001 1.000 0.999 0.998 0.997 VIN = 8V 1.203 VIN = 10V 1.202 VIN = 12V 1.201 1.200 1.199 1.198 1.197 CONDITIONS VOUT_NOM = 1.0V 0.996 1.204 0.995 1.195 0 0.5 1 1.5 2 2.5 3 3.5 4 4.5 5 5.5 6 OUTPUT CURRENT (A) 0 0.5 1 1.5 2 2.5 3 3.5 4 4.5 5 5.5 6 OUTPUT CURRENT (A) Output Voltage vs. Output Current Output Voltage vs. Output Current 2.505 1.804 VIN = 8V 1.803 VIN = 10V 1.802 VIN = 12V OUTPUT VOLTAGE (V) 1.805 OUTPUT VOLTAGE (V) CONDITIONS VOUT_NOM = 1.2V 1.196 1.801 1.800 1.799 1.798 1.797 VIN = 8V 2.503 VIN = 10V 2.502 VIN = 12V 2.501 2.500 2.499 2.498 2.497 CONDITIONS VOUT_NOM = 1.8V 1.796 2.504 CONDITIONS VOUT_NOM = 2.5V 2.496 2.495 1.795 0 0.5 1 1.5 2 2.5 3 3.5 4 4.5 5 5.5 6 OUTPUT CURRENT (A) 0 0.5 1 1.5 2 2.5 3 3.5 4 4.5 5 5.5 6 OUTPUT CURRENT (A) Output Voltage vs. Temperature Output Voltage vs. Temperature 1.204 CONDITIONS VIN = 8V VOUT_NOM = 1.2V 1.203 1.202 OUTPUT VOLTAGE (V) OUTPUT VOLTAGE (V) 1.204 1.201 1.200 LOAD = 0A 1.199 LOAD = 1A LOAD = 2A 1.198 LOAD = 4A 1.197 CONDITIONS VIN = 10V VOUT_NOM = 1.2V 1.203 1.202 1.201 1.200 LOAD = 0A 1.199 LOAD = 1A LOAD = 2A 1.198 LOAD = 4A 1.197 LOAD = 6A 1.196 LOAD = 6A 1.196 -40 -15 10 35 60 AMBIENT TEMPERATURE ( C) 85 -40 -15 10 35 60 AMBIENT TEMPERATURE ( C) 85 www.altera.com/enpirion Page 8 07514 June 2, 2015 Rev D EN2360QI Typical Performance Curves Output Voltage vs. Temperature Output Voltage vs. Temperature 1.204 CONDITIONS VIN = 12V VOUT_NOM = 1.2V 1.203 1.202 OUTPUT VOLTAGE (V) OUTPUT VOLTAGE (V) 1.204 1.201 1.200 LOAD = 0A 1.199 LOAD = 1A LOAD = 2A 1.198 LOAD = 4A 1.197 LOAD = 6A CONDITIONS VIN = 14V VOUT_NOM = 1.2V 1.203 1.202 1.201 1.200 LOAD = 0A 1.199 LOAD = 1A 1.198 LOAD = 2A 1.197 LOAD = 4A LOAD = 6A 1.196 1.196 -40 -15 10 35 60 AMBIENT TEMPERATURE ( C) 85 -40 -15 10 35 60 AMBIENT TEMPERATURE ( C) 85 www.altera.com/enpirion Page 9 07514 June 2, 2015 Rev D EN2360QI Typical Performance Characteristics Enable Startup/Shutdown Waveform (0A) Enable Startup/Shutdown Waveform (2A) ENABLE ENABLE VOUT VOUT POK POK LOAD LOAD CONDITIONS VIN = 12V, VOUT = 3.3V, Load = 0A, Css = 47nF CIN = 22F(1206), COUT = 2x47F(1206)+100F(1206) CONDITIONS VIN = 12V, VOUT = 3.3V, Load = 2A, Css = 47nF CIN = 22F(1206), COUT = 2x47F(1206)+100F(1206) Enable Startup/Shutdown Waveform (4A) Enable Startup/Shutdown Waveform (6A) ENABLE ENABLE VOUT VOUT POK POK LOAD LOAD CONDITIONS VIN = 12V, VOUT = 3.3V, Load = 4A, Css = 47nF CIN = 22F(1206), COUT = 2x47F(1206)+100F(1206) CONDITIONS VIN = 12V, VOUT = 3.3V, Load = 6A, Css = 47nF CIN = 22F(1206), COUT = 2x47F(1206)+100F(1206) Power Up Waveform (0A) Power Up Waveform (6A) PVIN PVIN VOUT VOUT POK POK LOAD LOAD CONDITIONS VIN = 12V, VOUT = 3.3V, Load = 0A, Css = 47nF CIN = 22F(1206), COUT = 2x47F(1206)+100F(1206) CONDITIONS VIN = 12V, VOUT = 3.3V, Load = 6A, Css = 47nF CIN = 22F(1206), COUT = 2x47F(1206)+100F(1206) www.altera.com/enpirion Page 10 07514 June 2, 2015 Rev D EN2360QI Typical Performance Characteristics Output Ripple at 20MHz Bandwidth VOUT = 1V (AC Coupled) Output Ripple at 20MHz Bandwidth VOUT = 1V (AC Coupled) LOAD = 0A VOUT = 1.8V (AC Coupled) VOUT = 1.8V (AC Coupled) VOUT = 3.3V (AC Coupled) VOUT = 3.3V (AC Coupled) 20mV / DIV 20mV / DIV CONDITIONS VIN = 12V, CIN = 22F (1206), COUT = 2x47F + 100F (1206) CONDITIONS VIN = 12V, CIN = 22F (1206), COUT = 2x47F + 100F (1206) Output Ripple at 500MHz Bandwidth Output Ripple at 500MHz Bandwidth LOAD = 0A VOUT = 1V (AC Coupled) LOAD = 6A VOUT = 1V (AC Coupled) VOUT = 1.8V (AC Coupled) VOUT = 1.8V (AC Coupled) VOUT = 3.3V (AC Coupled) VOUT = 3.3V (AC Coupled) 20mV / DIV 20mV / DIV CONDITIONS VIN = 12V, CIN = 22F (1206), COUT = 2x47F + 100F (1206) CONDITIONS VIN = 12V, CIN = 22F (1206), COUT = 2x47F + 100F (1206) Load Transient from 0 to 3A (VOUT =1V) Load Transient from 0 to 6A (VOUT =1V) VOUT (AC Coupled) LOAD LOAD = 6A VOUT (AC Coupled) CONDITIONS VIN = 12V, VOUT = 1.0V CIN = 22F (1206) COUT = 2x47F (1206) + 100F (1206) Using Best Performance Configuration LOAD CONDITIONS VIN = 12V, VOUT = 1.0V CIN = 22F (1206) COUT = 2x47F (1206) + 100F (1206) Using Best Performance Configuration www.altera.com/enpirion Page 11 07514 June 2, 2015 Rev D EN2360QI Typical Performance Characteristics Load Transient from 0 to 3A (VOUT =1.2V) Load Transient from 0 to 6A (VOUT =1.2V) VOUT (AC Coupled) LOAD VOUT (AC Coupled) CONDITIONS VIN = 12V, VOUT = 1.2V CIN = 22F (1206) COUT = 2x47F (1206) + 100F (1206) Using Best Performance Configuration LOAD Load Transient from 0 to 3A (VOUT =1.8V) Load Transient from 0 to 6A (VOUT =1.8V) VOUT (AC Coupled) LOAD VOUT (AC Coupled) CONDITIONS VIN = 12V, VOUT = 1.8V CIN = 22F (1206) COUT = 2x47F (1206) + 100F (1206) Using Best Performance Configuration LOAD CONDITIONS VIN = 12V, VOUT = 1.8V CIN = 22F (1206) COUT = 2x47F (1206) + 100F (1206) Using Best Performance Configuration Load Transient from 0 to 6A (VOUT =3.3V) Load Transient from 0 to 3A (VOUT =3.3V) VOUT (AC Coupled) VOUT (AC Coupled) LOAD CONDITIONS VIN = 12V, VOUT = 1.2V CIN = 22F (1206) COUT = 2x47F (1206) + 100F (1206) Using Best Performance Configuration CONDITIONS VIN = 12V, VOUT = 3.3V CIN = 22F (1206) COUT = 2x47F (1206) + 100F (1206) Using Best Performance Configuration LOAD CONDITIONS VIN = 12V, VOUT = 3.3V CIN = 22F (1206) COUT = 2x47F (1206) + 100F (1206) Using Best Performance Configuration www.altera.com/enpirion Page 12 07514 June 2, 2015 Rev D EN2360QI Functional Block Diagram S_OUT S_IN UVLO Digital I/O BTMP PVIN PG Linear Regulator To PLL AVINO Thermal Limit Current Limit NC(SW) Gate Drive VOUT BGND (-) PWM Comp (+) PGND PLL/Sawtooth Generator FQADJ VDDB Compensation Network EAIN Compensation Network (-) Error Amp (+) Power Good Logic SS Soft Start ENABLE VFB POK 300k Voltage Reference Generator 370k Band Gap Reference EN2360QI AVIN AGND Figure 4: Functional Block Diagram Functional Description small size input and output filter capacitors, as well as a wide loop bandwidth within a small foot print. Synchronous Buck Converter The EN2360QI is a highly integrated synchronous, buck converter with integrated controller, power MOSFET switches and integrated inductor. The nominal input voltage (PVIN) range is 4.5V to 14V and can support up to 6A of continuous output current. The output voltage is programmed using an external resistor divider network. The control loop utilizes a Type IV Voltage-Mode compensation network and maximizes on a low-noise PWM topology. Much of the compensation circuitry is internal to the device. However, a phase lead capacitor is required along with the output voltage feedback resistor divider to complete the Type IV compensation network. The high switching frequency of the EN2360QI enables the use of Protection Features: The power supply has the following protection features: * Short Circuit Protection * Thermal Shutdown with Hysteresis. * AVIN Under-Voltage Lockout Protection Additional Features: * * * Switching Frequency Synchronization. Programmable Soft-Start Power OK Output Monitoring www.altera.com/enpirion Page 13 07514 June 2, 2015 Rev D EN2360QI Power Up Sequence The EN2360QI is designed to be powered by either a single input supply (PVIN) or two separate supplies: one for PVIN and the other for AVIN. The EN2360QI is not "hot pluggable." Refer to the PVIN Slew Rate specification on page 4. then to ground can be used to enable and disable the device at a programmed PVIN voltage level. The lower resistor (4.02k) can be adjusted to set startup and shutdown at a specific PVIN voltage level. See ENABLE and DISABLE thresholds in the Electrical Characteristics table. Dual Input Supply Application (PVIN and AVIN): Single Input Supply Application (PVIN): 47nF 47nF RPG 560 VIN EN2360QI ENABLE 4.02k 22F 1206 VOUT PG BTMP VDDB BGND VOUT PVIN 10k RVB 4.75k RPG 560 VIN EN2360QI 2x 47F 0805 RA CA 1F ENABLE 22F 1206 1F 47nF VFB PGND RCLX RCA PGND FQADJ AGND RCLX RB RB RFS RFS CA VFB SS PGND 47nF FQADJ AGND RA AVINO VAVIN RCA PGND 2x 47F 0805 AVIN AVIN SS VOUT PG BTMP VDDB BGND VOUT PVIN AVINO 1F 0.22F 0.22F 100k 100k Figure 7: Dual Input Supply Schematic Figure 5: Single Input Supply Schematic The EN2360QI has an internal linear regulator that converts PVIN to 3.4V. The output of the linear regulator is provided on the AVINO pin once the device is enabled. AVINO should be connected to AVIN on the EN2360QI. In this application, the following external components are required: Place a 1F, X5R/X7R capacitor between AVINO and AGND as close as possible to AVINO. Place a 1F, X5R/X7R capacitor between AVIN and AGND as close as possible to AVIN. In addition, place a resistor (RVB) between VDDB and AVIN, as shown in Figure 5. Altera recommends RVB=4.75k. In this application, ENABLE cannot be asserted before PVIN. See diagram below for a recommended startup and shutdown sequencing. In this application, place a 1F, X5R/X7R, capacitor between AVIN and AGND as close as possible to AVIN. Refer to Figure 7 for a recommended schematic for a dual input supply application. For dual input supply applications, the sequencing of the two input supplies, PVIN and AVIN, is very important. There are two common acceptable turnon sequences for the device. AVIN can always come up before PVIN. If PVIN comes up before AVIN, then ENABLE must be toggled last, after AVIN is asserted. Do not turn off AVIN before PVIN and ENABLE during shutdown. Doing so will disable the internal controller while there may still be energy in the system. The device will not softshutdown properly and damage may occur. See diagram below for a recommended startup and shutdown sequencing. 12V PVIN 0V 12V PVIN slew rate limitations as per datasheet PVIN PVIN - Recommended to be ramped down after the Vout softshutdown occurs 0V PVIN slew rate limitations as per datasheet PVIN powered down before AVIN 3.3V AVIN AVIN powered up before PVIN 0V 3.3V ENABLE 0V Delay from ENABLE rising edge to soft start begin ~ 1ms VOUT Delay from ENABLE falling edge to soft shutdown begin ~ 1.5ms Soft Start Time 2ms w/Css=47nF 3.3V ENABLE Soft Shutdown Time 1.3ms w/Css=47nF 0V Delay from ENABLE rising edge to soft start begin ~ 1ms VOUT Figure 6: Single Supply Startup/Shutdown Sequence Delay from ENABLE falling edge to soft shutdown begin ~ 1.5ms Soft Start Time 2ms w/Css=47nF PVIN/AVIN - Recommended to be ramped down after the Vout softshutdown occurs Soft Shutdown Time 1.3ms w/Css=47nF Figure 8: Dual Supply Startup/Shutdown Sequencing If no external enable signal is used, a resister divider (see Figure 5) from PVIN to ENABLE and www.altera.com/enpirion Page 14 07514 June 2, 2015 Rev D EN2360QI Enable Operation Pre-Bias Precaution The EN2360QI is not designed to be turned on into a pre-biased output voltage. Be sure the output capacitors are not charged or the output of the EN2360QI is not pre-biased when the EN2360QI is first enabled. Frequency Synchronization Rfs vs. SW Frequency SWITCHING FREQUENCY (MHz) The ENABLE pin provides a means to enable normal operation or to shut down the device. A logic high will enable the converter into normal operation. When the ENABLE pin is asserted (high) the device will undergo a normal soft-start. A logic low will disable the converter. A logic low will power down the device in a controlled manner and the device is subsequently shut down. The ENABLE signal has to be low for at least the ENABLE Lockout Time (8ms) in order for the device to be reenabled. To ensure accurate startup sequencing the ENABLE/DISABLE signal should be faster than 1V/100s. A slower ENABLE/DISABLE signal may result in a delayed startup and shutdown response. Do not leave ENABLE floating. 1.80 1.70 1.60 1.50 1.40 1.30 1.20 1.10 1.00 0.90 0.80 0.70 0.60 0 2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 RFS RESISTOR VALUE (k) Figure 9. RFS versus Switching Frequency The efficiency performance of the EN2360QI for various VOUTs can be optimized by adjusting the switching frequency. Table 1 shows recommended RFS values for various VOUTs in order to optimize performance of the EN2360QI. PVIN The switching frequency of the EN2360QI can be phase-locked to an external clock source to move unwanted beat frequencies out of band. The internal switching clock of the EN2360QI can be phase locked to a clock signal applied to the S_IN pin. An activity detector recognizes the presence of an external clock signal and automatically phaselocks the internal oscillator to this external clock. Phase-lock will occur as long as the input clock frequency is in the range of 0.8MHz to 1.8MHz. The external clock frequency must be within 10% of the nominal switching frequency set by the RFS resistor. It is recommended to use a synchronized clock frequency close to the typical frequency recommendations in Table 1. A 3.01k resistor from FQADJ to ground is recommended for clock frequencies within 10% of 1MHz. When no clock is present, the device reverts to the free running frequency of the internal oscillator set by the RFS resistor. The efficiency performance of the EN2360QI for various PVIN/VOUT combinations can be optimized by adjusting the switching frequency. Table 1 shows recommended RFS values for various PVIN/VOUT combinations in order to optimize performance of the EN2360QI. CONDITIONS VIN = 6V to 12V VOUT = 0.8V to 5.0V 12V 5V VOUT 5.0V 3.3V 2.5V 1.8V 1.5V 1.2V <1.0V 2.5V 1.8V 1.5V 1.2V <1.0V RFS 30k 15k 10k 4.87k 3.01k 1.65k 1.3k 22.1k 10k 6.65k 4.87k 3.01k Typical fsw 1.48 MHz 1.38 MHz 1.3 MHz 1.15 MHz 1.0 MHz 0.95 MHz 0.8 MHz 1.4 MHz 1.3 MHz 1.25 MHz 1.15 MHz 1.0 MHz Table 1: Recommended RFS Values Soft-Start Operation Soft start is a means to ramp the output voltage gradually upon start-up. The output voltage rise time is controlled by the choice of soft-start capacitor, which is placed between the SS pin (pin 56) and the AGND pin (pin 52). During start-up of the converter, the reference voltage to the error amplifier is linearly increased to its final level by an internal current source of approximately 10A. The soft-start time is measured from when VIN > VUVLOR and ENABLE pin voltage crosses its logic high threshold to when VOUT reaches its programmed value. The total soft-start time can be calculated by: www.altera.com/enpirion Page 15 07514 June 2, 2015 Rev D EN2360QI Soft Start Time (ms): T SS Css [nF] x 0.06 Typical soft-start time is approximately 2.8ms with SS capacitor value of 47nF. POK Operation The POK signal is an open drain signal (requires a pull up resistor to AVIN or similar voltage) from the converter indicating the output voltage is within the specified range. Typically, a 100k or lower resistance is used as the pull-up resistor. The POK signal will be logic high (AVIN) when the output voltage is above 90% of the programmed voltage level. If the output voltage is below this point, the POK signal will be a logic low. The POK signal can be used to sequence down-stream converters by tying to their enable pins. Short Circuit Protection The short circuit protection feature will protect the device if the output is shorted to ground. Short circuit protection is achieved by sensing the current flowing through a sense PFET. When the sensed current exceeds the threshold for more than 32 cycles, both power FETs are turned off for the rest of the switching cycle. If the short circuit condition is removed, the device will reactivate soft-start and resume PWM operation. In the event the short circuit trips consistently in normal operation, the device enters a hiccup mode. While in hiccup mode, the device is disabled for a short while and restarted with a normal soft-start. The hiccup time is approximately 32ms. This cycle can continue indefinitely as long as the short circuit condition persists. Use a resistor value of 100k from the RCLX pin to ground to enable this feature. Thermal Overload Protection Thermal shutdown circuit will disable device operation when the junction temperature exceeds approximately 160C. After a thermal shutdown event, when the junction temperature drops by approx 35C, the converter will re-start with a normal soft-start. Input Under-Voltage Lock-Out (UVLO) Internal circuits ensure that the converter will not start switching until the AVIN input voltage is above the specified minimum voltage. Hysteresis, input de-glitch and output leading edge blanking ensures high noise immunity and prevents false UVLO triggers. Application Information Output Voltage Programming and Loop Compensation The EN2360QI uses a Type IV Voltage Mode compensation network. Type IV Voltage Mode control is a proprietary Altera Enpirion control scheme that maximizes control loop bandwidth to deliver excellent load transient response and maintain output regulation with pin point accuracy. For ease of use, most of this network has been optimized and is integrated within the device package. The EN2360QI output voltage is programmed using a simple resistor divider network (RA and RB). The feedback voltage at VFB is nominally 0.6V. RA is predetermined based on Table 5 and RB can be calculated based on Figure 10. The values recommended for COUT, CA, RCA and REA make up the external compensation of the EN2360QI. It will vary with each PVIN and VOUT combination to optimize on performance. The EN2360QI solution can be optimized for either smallest size or highest performance. Please see Table 5 for a list of recommended RA, CA, RCA, REA and COUT values for each solution. Since VFB is a sensitive node, do not touch the VFB node while the device is in operation as doing so may introduce parasitic capacitance into the control loop that causes the device to behave abnormally and damage may occur. VOUT VOUT COUT EAIN RA CA REA RCA VFB VFB = 0.6V PGND RB = EN2360QI VFB x RA VOUT - VFB Figure 10: VOUT Resistor Divider & Compensation Components. See Table 5 for details. www.altera.com/enpirion Page 16 07514 June 2, 2015 Rev D EN2360QI Input Capacitor Selection The EN2360QI requires a 22F/1206 input capacitor. Low-cost, low-ESR ceramic capacitors should be used as input capacitors for this converter. The dielectric must be X5R or X7R rated. Y5V or equivalent dielectric formulations must not be used as these lose too much capacitance with frequency, temperature and bias voltage. In some applications, lower value capacitors are needed in parallel with the larger, capacitors in order to provide high frequency decoupling. Table 2 contains a list of recommended input capacitors. Recommended Input Capacitors Description 22F, 16V, X5R, 10%, 1206 22F, 16V, X5R, 20%, 1206 MFG P/N Murata GRM31CR61C226ME15 Taiyo Yuden EMK316ABJ226ML-T maintained. Table 3 shows the recommended compensation components for applications that require bulk capacitance at the load. PVIN (V) VOUT (V) Min. ESR 4.5 to 14 0.6 to 5.0 4m Com pensation COUT = 2x47F/1206 Bulk Cap 1000F CA = 18pF RA = 200k RCA = 0 REA = 56k Table 3: Minimum ESR for Bulk Capacitance at Load Output ripple voltage is determined by the aggregate output capacitor impedance. Capacitor impedance, denoted as Z, is comprised of capacitive reactance, effective series resistance, ESR, and effective series inductance, ESL reactance. Placing output capacitors in parallel reduces the impedance and will hence result in lower ripple voltage. Table 2: Recommended Input Capacitors 1 Z Total Output Capacitor Selection As seen from Table 5, the EN2360QI has been optimized for use with one 100F/1206 plus two 47F/1206 output capacitors for best performance. For the smallest solution size configuration see Table 5. Low ESR ceramic capacitors are required with X5R or X7R rated dielectric formulation. Y5V or equivalent dielectric formulations must not be used as these lose too much capacitance with frequency, temperature and bias voltage. Table 4 contains a list of recommended output capacitors. In some applications, extra bulk capacitance is required at the load. In this case, up to 1000F of bulk capacitance may be used at the load as long as the minimum ESR between the device output and the bulk capacitance is = 1 1 1 + + ... + Z1 Z 2 Zn Recommended Output Capacitors Description MFG P/N 47F, 6.3V, X5R, 20%, 1206 Murata GRM31CR60J476ME19L 47F, 10V, X5R, 20%, 1206 Taiyo Yuden LMK316BJ476ML- T 22F, 10V, X5R, 20%, 0805 Panasonic ECJ-2FB1A226M 47F, 6.3V, X5R, 20%, 0805 Taiyo Yuden JMK212BBJ476MG-T 22F, 10V, X5R, 20%, 0805 Taiyo Yuden LMK212BJ226MG- T Table 4: Recommended Output Capacitors www.altera.com/enpirion Page 17 07514 June 2, 2015 Rev D EN2360QI Best Performance Smallest Solution Size CIN = 22F/1206 CIN = 22F/1206 V OUT 1.8V, COUT = 2x47F/0805 1.8V V OUT 3.3V, COUT = 2x47F/1206 COUT = 100F/1206 + 2x47F/1206, RA = 200k PVIN (V) 14V 12V 10V 8V 6.6V 5V VOUT (V) CA (pF) RCA (k) REA (k) Ripple (mV) Dev iation (mV) 0.9V 15 8.2 0 5.29 1.2V 12 8.2 0 1.5V 12 12 0 PVIN (V) VOUT (V) RA (k) CA (pF) RCA (k) REA (k) Ripple (mV) Dev iation (mV) 26 0.9V 200 10 0.2 Open 15 51 6.6 22 1.2V 200 10 0.2 Open 19 68 8.39 24 1.5V 200 10 0.2 Open 24 66 1.8V 10 12 0 9.7 28 1.8V 200 8.2 0.2 Open 24 66 2.5V 10 12 56 18.8 54 14V 2.5V 120 8.2 15 Open 43 86 3.3V 8.2 18 56 28.8 54 3.3V 120 6.8 15 Open 52 106 5.0V 6.8 12 56 52.1 66 5.0V 120 5.6 0.2 Open 66 152 0.9V 15 8.2 0 5.22 28 0.9V 200 12 0.2 Open 17 57 1.2V 15 8.2 0 6.51 22 1.2V 200 12 0.2 Open 18 70 1.5V 12 12 0 7.5 28 1.5V 200 12 0.2 Open 24 70 1.8V 10 12 0 9 34 1.8V 200 10 0.2 Open 26 80 2.5V 12 12 56 16.8 50 2.5V 120 10 15 Open 39 94 3.3V 10 18 56 27.3 54 3.3V 120 10 15 Open 45 114 5.0V 8.2 12 56 48.5 74 5.0V 120 6.8 0.2 Open 56 164 0.9V 18 8.2 0 5.01 28 0.9V 200 18 0.2 Open 15 69 1.2V 18 8.2 0 6.11 26 1.2V 200 18 0.2 Open 19 67 1.5V 15 12 0 7.3 28 1.5V 200 15 0.2 Open 23 78 1.8V 12 12 0 8.13 32 1.8V 200 12 0.2 Open 29 94 2.5V 15 12 56 16.8 44 2.5V 120 15 15 Open 29 98 3.3V 12 18 56 27.2 68 3.3V 120 12 15 Open 44 128 5.0V 10 12 56 42 84 5.0V 120 10 0.2 Open 52 192 0.9V 22 8.2 0 4.92 26 0.9V 200 27 0.2 Open 16 68 1.2V 18 8.2 0 5.41 32 1.2V 200 22 0.2 Open 19 75 1.5V 15 12 0 6.48 32 1.5V 200 22 0.2 Open 23 82 1.8V 15 12 0 7.32 36 1.8V 200 18 0.2 Open 27 104 12V 10V 8V 2.5V 18 12 56 16.1 64 2.5V 120 27 6.8 Open 36 124 3.3V 15 18 56 24 72 3.3V 120 22 6.8 Open 36 152 5.0V 12 12 56 31.4 102 5.0V 120 12 0.2 Open 40 236 0.9V 22 8.2 0 4.6 30 0.9V 200 33 0.2 Open 14 70 1.2V 22 8.2 0 5.59 32 1.2V 200 33 0.2 Open 17 80 1.5V 18 12 0 5.88 36 1.5V 200 27 0.2 Open 21 96 1.8V 18 12 0 7.12 38 1.8V 200 27 0.2 Open 24 110 2.5V 3.3V 0.9V 22 18 27 12 18 8.2 56 56 0 15.4 21.6 3.93 56 78 32 2.5V 3.3V 0.9V 120 120 200 39 27 68 4.3 4.3 0.2 Open Open 29 28 13 140 184 80 1.2V 22 8.2 0 4.4 38 1.2V 200 56 0.2 Open 15 92 1.5V 22 12 0 5.91 38 1.5V 200 47 0.2 Open 17 106 1.8V 22 12 0 6.91 42 1.8V 200 39 0.2 Open 19 124 2.5V 27 12 56 13.6 76 2.5V 120 68 0.2 Open 21 172 6.6V 5V Open Table 5: RA, CA, RCA and REA Values for Various PVIN/VOUT Combinations: Smallest Solution Size vs. Best Performance. See Figure 10. Use the equation in Figure 10 to calculate RB. Note 7: Nominal Deviation is for a 6A load transient step. Note 8: For compensation values of output voltage in between the specified output voltages, choose compensation values of the lower output voltage setting. www.altera.com/enpirion Page 18 07514 June 2, 2015 Rev D EN2360QI Thermal Considerations Thermal considerations are important power supply design facts that cannot be avoided in the real world. Whenever there are power losses in a system, the heat that is generated by the power dissipation needs to be accounted for. The Altera Enpirion PowerSoC helps alleviate some of those concerns. The Altera Enpirion EN2360QI DC-DC converter is packaged in an 8x11x3mm 68-pin QFN package. The QFN package is constructed with copper lead frames that have an exposed thermal pad. The exposed thermal pad on the package should be soldered directly on to a copper ground pad on the printed circuit board (PCB) to act as a heat sink. The recommended maximum junction temperature for continuous operation is 125C. Continuous operation above 125C may reduce long-term reliability. The device has a thermal overload protection circuit designed to turn off the device at an approximate junction temperature value of 160C. The following example and calculations illustrate the thermal performance of the EN2360QI. Example: VIN = 12V VOUT = 3.3V PIN = POUT / PIN 19.8W / 0.87 22.76W The power dissipation (PD ) is the power loss in the system and can be calculated by subtracting the output power from the input power. PD = PIN - POUT 22.76W - 19.8W 2.96W With the power dissipation known, the temperature rise in the device may be estimated based on the theta JA value (JA). The JA parameter estimates how much the temperature will rise in the device for every watt of power dissipation. The EN2360QI has a JA value of 16 C/W without airflow. Determine the change in temperature (T) based on PD and JA. T = PD x JA T 2.96W x 16C/W = 47.36C 47C The junction temperature (T J ) of the device is approximately the ambient temperature (T A) plus the change in temperature. We assume the initial ambient temperature to be 25C. T J = T A + T T J 25C + 47C 72C IOUT = 6A First calculate the output power. POUT = 3.3V x 6A = 19.8W Next, determine the input power based on the efficiency () shown in Figure 11. Efficiency vs. Output Current 100 The maximum operating junction temperature (T JMAX) of the device is 125C, so the device can operate at a higher ambient temperature. The maximum ambient temperature (T AMAX) allowed can be calculated. T AMAX = T JMAX - PD x JA 125C - 47C 78C The maximum ambient temperature the device can reach is 78C given the input and output conditions. Note that the efficiency will be slightly lower at higher temperatures and this calculation is an estimate. 90 80 EFFICIENCY (%) = POUT / PIN = 87% = 0.87 70 60 50 40 30 20 VOUT = 3.3V 10 CONDITIONS VIN = 12.0V AVIN = 3.3V Dual Supply 0 0 0.5 1 1.5 2 2.5 3 3.5 4 4.5 5 OUTPUT CURRENT (A) 5.5 6 Figure 11: Efficiency vs. Output Current For VIN = 12V, VOUT = 3.3V at 6A, 87% www.altera.com/enpirion Page 19 07514 June 2, 2015 Rev D EN2360QI Engineering Schematic A single through-hole via connects these AGND pins to the GND plane. An optional resistor (Rea) may be connected from VFB to EAIN for control loop optimization Css 0402 47n X7R EAIN 49 PVIN EN2360QI NC9 PVIN NC10 PVIN NC11 PVIN NC12 PGND PVIN Cb 0.22u 0402 X5R 47 46 45 44 Cpg 47n 0402 X5R 43 42 Cav ino 1u 0402 X7R 40 39 38 37 36 Rpg 560 35 0402 { Cout1--Cout2: 47u 1206 X5R 0201 0402 0402 Rb 26.7k PVIN = 12V Rca 15k Rv b 4.75k 41 Ca 10p Ra 120k Choose RPOK so that the max sink current is not exceeded. 34 PGND 33 PGND PGND 32 31 PGND 30 PGND NC(SW)28 PVIN 29 27 NC25 NC26 26 VOUT 24 25 VOUT VOUT 23 VOUT NC14 28 NC(SW)27 PVIN NC13 48 0402 POK 51 52 50 ENABLE AVIN AGND 53 54 VFB AGND EAIN 55 56 SS 58 57 RCLX FQADJ 59 NC59 61 60 CGND NC(SW)61 62 NC(SW)62 63 64 NC64 NC(SW)63 65 66 NC66 NC65 NC67 U1 NC8 15 14 AVINO 21 VOUT NC7 22 13 S_IN PG VOUT 12 S_OUT NC6 VOUT 11 0402 100K BTMP 19 10 RPOK NC5 20 9 POK EN VDDB VOUT 8 AGND BGND 18 7 15k NC4 VOUT 6 Rf s NC3 VOUT 5 100k 0402 NC2 17 4 NC68 68 3 NC1 NC15 2 16 1 67 Rfs value is chosen for 12Vin/3.3Vout Rclx Enable can also be driven with an external logic signal Cav in 1u 0402 X7R Compensation network optimized for 12Vin / 3.3Vout. See datasheet for other Vin/Vout cases. Cin Cout1 Cout2 Output capacitors chosen for small footprint. For lower Vout ripple option, see the datasheet. Cin: 22u 1206 25V X5R PVIN Connect input and output caps to GND plane through mulitple vias. (See the Gerber files.) Figure 12: Engineering Schematic with Engineering Notes www.altera.com/enpirion Page 20 07514 June 2, 2015 Rev D EN2360QI Layout Recommendation Figure 13: Top Layer Layout with Critical Components (Top View). See Figure 12 for corresponding schematic. This layout only shows the critical components and top layer traces for minimum footprint in singlesupply mode. Alternate circuit configurations & other low-power pins need to be connected and routed according to customer application. Please see the Gerber files at www.altera.com/enpirion for details on all layers. Recommendation 1: Input and output filter capacitors should be placed on the same side of the PCB, and as close to the EN2360QI package as possible. They should be connected to the device with very short and wide traces. Do not use thermal reliefs or spokes when connecting the capacitor pads to the respective nodes. The +V and GND traces between the capacitors and the EN2360QI should be as close to each other as possible so that the gap between the two nodes is minimized, even under the capacitors. Recommendation 2: The PGND connections for the input and output capacitors on layer 1 need to have a slit between them in order to provide some separation between input and output current loops. Recommendation 3: The system ground plane should be the first layer immediately below the surface layer. This ground plane should be continuous and un-interrupted below the converter and the input/output capacitors. Recommendation 4: The thermal pad underneath the component must be connected to the system ground plane through as many vias as possible. The drill diameter of the vias should be 0.33mm, and the vias must have at least 1 oz. copper plating on the inside wall, making the finished hole size around 0.20-0.26mm. Do not use thermal reliefs or spokes to connect the vias to the ground plane. This connection provides the path for heat dissipation from the converter. Recommendation 5: Multiple small vias (the same size as the thermal vias discussed in recommendation 4) should be used to connect ground terminal of the input capacitor and output capacitors to the system ground plane. It is preferred to put these vias along the edge of the GND copper closest to the +V copper. These vias connect the input/output filter capacitors to the GND plane, and help reduce parasitic inductances in the input and output current loops. If vias cannot be placed under the capacitors, then place them on both sides of the slit in the top layer PGND copper. Recommendation 6: AVIN is the power supply for the small-signal control circuits. AVINO powers AVIN in single supply mode. AVIN and AVINO should have a decoupling capacitor close to each of their pins. Refer to Figure 13. Recommendation 7: The layer 1 metal under the device must not be more than shown in Figure 13. Refer to the section regarding Exposed Metal on Bottom of Package. As with any switch-mode DC/DC converter, try not to run sensitive signal or control lines underneath the converter package on other layers. Recommendation 8: The VOUT sense point should be just after the last output filter capacitor. Keep the sense trace short in order to avoid noise coupling into the node. Contact Altera MySupport for any remote sensing applications. Recommendation 9: Keep RA, CA, RB, and RCA close to the VFB pin (Refer to Figure 13). The VFB pin is a high-impedance, sensitive node. Keep the trace to this pin as short as possible. Whenever possible, connect RB directly to the AGND (pin 52, 53) instead of going through the GND plane. Recommendation 10: Follow all the layout recommendations as close as possible to optimize performance. Altera provides schematic and layout reviews for all customer designs. Contact Altera MySupport for detailed support (www.altera.com/mysupport). www.altera.com/enpirion Page 21 07514 June 2, 2015 Rev D EN2360QI Design Considerations for Lead-Frame Based Modules Exposed Metal on Bottom of Package Lead-frames offer many advantages in thermal performance, in reduced electrical lead resistance, and in overall foot print. However, they do require some special considerations. In the assembly process lead frame construction requires that, for mechanical support, some of the lead-frame cantilevers be exposed at the point where wire-bond or internal passives are attached. This results in several small pads being exposed on the bottom of the package, as shown in Figure 14. Only the thermal pad and the perimeter pads are to be mechanically or electrically connected to the PC board. The PCB top layer under the EN2360QI should be clear of any metal (copper pours, traces, or vias) except for the thermal pad. The "shaded-out" area in Figure 14 represents the area that should be clear of any metal on the top layer of the PCB. Any layer 1 metal under the shaded-out area runs the risk of undesirable shorted connections even if it is covered by soldermask. The solder stencil aperture should be smaller than the PCB ground pad. This will prevent excess solder from causing bridging between adjacent pins or other exposed metal under the package. Please consult the EN2360QI QFN Package Soldering Guidelines for more details and recommendations. Figure 14: Lead-Frame exposed metal (Bottom View) Shaded area highlights exposed metal that is not to be mechanically or electrically connected to the PCB. www.altera.com/enpirion Page 22 07514 June 2, 2015 Rev D EN2360QI Recommended PCB Footprint Figure 15: EN2360QI PCB Footprint (Top View) The solder stencil aperture for the thermal pad (shown in blue) is based on Altera's manufacturing recommendations. www.altera.com/enpirion Page 23 07514 June 2, 2015 Rev D EN2360QI Package and Mechanical Figure 17: EN2360QI Package Dimensions (Bottom View) Packing and Marking Information: www.altera.com/support/reliability/packing/rel-packing-and-marking.html Contact Information Altera Corporation 101 Innovation Drive San Jose, CA 95134 Phone: 408-544-7000 www.altera.com (c) 2013 Altera Corporation--Confidential. All rights reserved. ALTERA, ARRIA, CYCLONE, ENPIRION, HARDCOPY, MAX, MEGACORE, NIOS, QUARTUS and STRATIX words and logos are trademarks of Altera Corporation and registered in the U.S. Patent and Trademark Office and in other countries. All other words and logos identified as trademarks or service marks are the property of their respective holders as described at www.altera.com/common/legal.html. Altera warrants performance of its semiconductor products to current specifications in accordance with Altera's standard warranty, but reserves the right to make changes to any products and services at any time without notice. Altera assumes no responsibility or liability arising out of the application or use of any information, product, or service described herein except as expressly agreed to in writing by Altera. Altera customers are advised to obtain the latest version of device specifications before relying on any published information and before placing orders for products or services. www.altera.com/enpirion Page 24 07514 June 2, 2015 Rev D