TPS43337-Q1 www.ti.com SLVSBC2A - AUGUST 2013 - REVISED SEPTEMBER 2013 LOW IQ, SINGLE-BOOST, FIXED-VOLTAGE DUAL SYNCHRONOUS BUCK CONTROLLER Check for Samples: TPS43337-Q1 FEATURES 1 * * 2 * * * * * * * * * * * * * Qualified for Automotive Applications AEC-Q100 Qualified With the Following Results: - Device Temperature Grade 1: -40C to +125C Ambient Operating Temperature - Device HBM ESD Classification Level H2 - Device CDM ESD Classification Level C2 Two Synchronous Buck Controllers BuckA: Fixed Output Voltage of 3.4 V BuckB: Fixed Output Voltage of 1.235 V One Pre-Boost Controller Input Range up to 40 V, (Transients up to 60 V), Operation Down to 2 V When Boost Is Enabled Low-Power Mode IQ: 34 A (One Buck On), 43 A (Two Bucks On) Low Shutdown Current Ish < 4 A Boost Output Selectable: 7 V, 8.85 V, or 10 V Programmable Frequency and External Synchronization Range: 150 to 600 kHz Separate Enable Inputs (ENA, ENB, ENC) Selectable Forced Continuous Mode or Automatic Low-Power Mode at Light Loads Sense Resistor or Inductor DCR Sensing for Buck Controllers Out-of-Phase Switching Between Buck Channels * * Peak Gate Drive Current 1.5 A Thermally Enhanced 38-Pin HTSSOP (DAP) PowerPADTM Package APPLICATIONS * * Automotive Start-Stop, Infotainment, Navigation Instrument Cluster Systems Industrial and Automotive Multi-Rail DC Power-Distribution Systems and Electronic Control Units DESCRIPTION The TPS43337-Q1 includes two current-mode synchronous buck controllers and a voltage-mode boost controller. The device is ideally suited as a preregulator stage with low IQ requirements and for systems that must survive supply drops due to cranking events. The integrated boost controller allows the device to operate down to 2 V at the input without seeing a drop on the buck regulator output stages. At light loads, the buck controllers enable to operate automatically in low power-mode, consuming just 34 A of quiescent current. The buck controllers have independent soft-start capability and power-good indicators. Current foldback in the buck controllers and cycle-by-cycle current limitation in the boost controller provide external MOSFET protection. The switching frequency is programable over 150 to 600 kHz or is synchronized to an external clock in the same range VBAT V BUCK A VBuckA V BA T TPS43337-Q1 VBUCKB C VBuckB 2V Figure 1. Typical Application Diagram 1 2 Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. PowerPAD is a trademark of Texas Instruments. PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of the Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. Copyright (c) 2013, Texas Instruments Incorporated TPS43337-Q1 SLVSBC2A - AUGUST 2013 - REVISED SEPTEMBER 2013 www.ti.com These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam during storage or handling to prevent electrostatic damage to the MOS gates. space ABSOLUTE MAXIMUM RATINGS (1) Voltage MIN MAX Input voltage: VIN, VBAT -0.3 60 V Enable inputs: ENA, ENB -0.3 60 V Bootstrap inputs: CBA, CBB -0.3 68 V Phase inputs: PHA, PHB -0.7 60 V Phase inputs: PHA, PHB (for 150 ns) Voltage (buck function: BuckA and BuckB) Voltage (boost function) Voltage (PMOS driver) Temperature -1 -0.3 13 V Error amplifier outputs: COMPA, COMPB -0.3 13 V High-side MOSFET driver: GA1-PHA, GB1-PHB -0.3 8.8 V Low-side MOSFET drivers: GA2, GB2 -0.3 8.8 V Current-sense voltage: SA1, SA2, SB1, SB2 -0.3 13 V Soft start: SSA, SSB -0.3 13 V Power-good output: PGA, PGB -0.3 13 V Power-good delay: DLYAB -0.3 13 V Switching-frequency timing resistor: RT -0.3 13 V SYNC, EXTSUP -0.3 13 V Low-side MOSFET driver: GC1 -0.3 8.8 V Error amplifier output: COMPC -0.3 13 V Enable input: ENC -0.3 13 V Current-limit sense: DS -0.3 60 V Output-voltage select: DIV -0.3 8.8 V P-channel MOSFET driver: GC2 -0.3 60 V P-channel MOSFET driver: VIN-GC2 -0.3 8.8 V Gate-driver supply: VREG -0.3 8.8 V Junction temperature: TJ -40 150 C Operating temperature: TA -40 125 C Storage temperature: TS -55 165 C Charged-device model (CDM) AEC-Q100 Classification Level C2 Machine model (MM) (1) 2 V Feedback inputs: FBA, FBB Human-body model (HBM) AEC-Q100 Classification Level H2 Electrostatic discharge ratings UNIT 2 VBAT, ENC, SYNC, VIN 750 All other pins 500 PGA, PGB 150 All other pins 200 kV V Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating Conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. All voltage values are with respect to GND. Submit Documentation Feedback Copyright (c) 2013, Texas Instruments Incorporated Product Folder Links: TPS43337-Q1 TPS43337-Q1 www.ti.com SLVSBC2A - AUGUST 2013 - REVISED SEPTEMBER 2013 THERMAL INFORMATION TPS43337-Q1 THERMAL METRIC (1) HTSSOP-DAP UNIT 38 PINS Junction-to-ambient thermal resistance (2) JA (3) 27.3 C/W JCtop Junction-to-case (top) thermal resistance 19.6 C/W JB Junction-to-board thermal resistance (4) 15.9 C/W JT Junction-to-top characterization parameter (5) 0.24 C/W JB Junction-to-board characterization parameter (6) 6.6 C/W JCbot Junction-to-case (bottom) thermal resistance (7) 1.2 C/W (1) (2) (3) (4) (5) (6) (7) For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report, SPRA953. The junction-to-ambient thermal resistance under natural convection is obtained in a simulation on a JEDEC-standard, high-K board, as specified in JESD51-7, in an environment described in JESD51-2a. The junction-to-case (top) thermal resistance is obtained by simulating a cold plate test on the package top. No specific JEDECstandard test exists, but a close description can be found in the ANSI SEMI standard G30-88. The junction-to-board thermal resistance is obtained by simulating in an environment with a ring cold plate fixture to control the PCB temperature, as described in JESD51-8. The junction-to-top characterization parameter, JT, estimates the junction temperature of a device in a real system and is extracted from the simulation data for obtaining JA, using a procedure described in JESD51-2a (sections 6 and 7). The junction-to-board characterization parameter, JB, estimates the junction temperature of a device in a real system and is extracted from the simulation data for obtaining JA , using a procedure described in JESD51-2a (sections 6 and 7). The junction-to-case (bottom) thermal resistance is obtained by simulating a cold plate test on the exposed (power) pad. No specific JEDEC standard test exists, but a close description can be found in the ANSI SEMI standard G30-88. Spacer RECOMMENDED OPERATING CONDITIONS Buck function: BuckA and BuckB voltage Boost function MIN MAX Input voltage: VIN, VBAT 4 40 Enable inputs: ENA, ENB 0 40 Boot inputs: CBA, CBB 4 48 -0.6 40 Current-sense voltage: SA1, SA2, SB1, SB2 0 11 Power-good output: PGA, PGB 0 11 SYNC, EXTSUP 0 9 Enable input: ENC 0 9 0 VREG -40 125 Phase inputs: PHA, PHB Voltage sense: DS 40 DIV Operating Temperature: TA Submit Documentation Feedback Copyright (c) 2013, Texas Instruments Incorporated Product Folder Links: TPS43337-Q1 UNIT V V C 3 TPS43337-Q1 SLVSBC2A - AUGUST 2013 - REVISED SEPTEMBER 2013 www.ti.com DC ELECTRICAL CHARACTERISTICS VIN = 8 to 18 V, TJ = -40C to +150C (unless otherwise noted) NO. PARAMETER 1.0 Input Supply 1.1 VBAT 1.2 1.3 1.4 MIN Boost controller enabled, after initial start-up condition is satisfied Supply voltage Input voltage required for device on initial start-up VIN VIN TEST CONDITIONS VBOOST_UNLOCK Buck undervoltage lockout Boost unlock threshold 2 40 6.5 40 4 40 VIN falling. After a reset, initial start-up conditions may apply. (1) 3.5 VIN rising. After a reset, initial start-up conditions may apply. (1) VBAT rising 8.2 VIN = 13 V, BuckA: LPM, BuckB: off, TA = 25C 1.5 IQ_LPM LPM quiescent current: (2) VIN = 13 V, BuckB: LPM, BuckA: off, TA = 25C VIN = 13 V, BuckA, B: LPM, TA = 25C VIN = 13 V, BuckA: LPM, BuckB: off, TA = 125C 1.6 IQ_LPM LPM quiescent current: (2) MAX UNIT V V Buck regulator operating range after initial start-up UV TYP VIN = 13 V, BuckB: LPM, BuckA: off, TA = 125C VIN = 13 V, BuckA and BuckB: LPM, TA = 125C 3.6 3.8 V 3.8 4 V 8.5 8.8 V 34 46 A 43 57 A 44 56 A 53 67 A 4.85 5.3 7 7.6 5 5.5 SYNC = 5 V, TA = 25C 1.7 IQ_NRM Quiescent current: normal (PWM) mode (2) VIN = 13 V, BuckA: CCM, BuckB: off, TA = 25C VIN = 13 V, BuckB: CCM, BuckA: off, TA = 25C VIN = 13 V, BuckA and BuckB: CCM, TA = 25C mA SYNC = 5 V, TA = 125C IQ_NRM Quiescent current: normal (PWM) mode (2) VIN = 13 V, BuckA, B: CCM, TA = 125C 7.5 8 1.9 Ibat_sh Shutdown current BuckA and BuckB: off, VBat = 13 V , TA = 25C 2.5 4 A 1.10 Ibat_sh Shutdown current BuckA and BuckB: off, VBat = 13 V, TA = 125C 3 5 A 1.11 VINLPMexit VIN level to exit LPM VIN falling 7.7 8 8.3 V 1.12 VINLPMentry VIN level to enable entering LPM VIN rising 8.2 8.5 8.8 V 1.13 VINLPMhys Hysteresis VIN rising or falling 0.4 0.5 0.6 V 2.0 Input Voltage VBAT - Undervoltage Lockout VBAT falling. After a reset, initial start-up conditions may apply. (1) 1.8 1.9 2 V VBAT rising. After a reset, initial start-up conditions may apply. (1) 2.4 2.5 2.6 V 500 600 700 mV 2.1 (1) (2) 4 VIN = 13 V, BuckA: CCM, BuckB: off, TA = 125C 1.8 VBATUV Boost-input undervoltage 2.2 UVLOHys Hysteresis 2.3 UVLOfilter Filter time 3.0 Input Voltage VIN - Overvoltage Lockout 3.1 VOVLO Overvoltage shutdown 3.2 OVLOHys Hysteresis 3.3 OVLOfilter Filter time VIN = 13 V, BuckB: CCM, BuckA: off, TA = 125C 5 s VIN rising 45 46 47 VIN falling 43 44 45 1 2 3 5 mA V V s If VBAT and VREG remain adequate, the buck can continue to operate if VIN is > 3.8 V. Quiescent current specification includes the current in the internal-feedback resistor divider. Submit Documentation Feedback Copyright (c) 2013, Texas Instruments Incorporated Product Folder Links: TPS43337-Q1 TPS43337-Q1 www.ti.com SLVSBC2A - AUGUST 2013 - REVISED SEPTEMBER 2013 DC ELECTRICAL CHARACTERISTICS (continued) VIN = 8 to 18 V, TJ = -40C to +150C (unless otherwise noted) NO. PARAMETER 4.0 Boost Controller 4.1 Vboost7-VIN 4.2 4.3 4.4 Vboost7-th Vboost10-VIN Vboost10-th 4.5 Vboost8.85-VIN 4.6 Vboost8.85-th TEST CONDITIONS MIN TYP MAX Boost VOUT = 7 V DIV = low, VBAT = 2 to 7 V 6.8 7 7.3 Boost-enable threshold Boost VOUT = 7 V, VBAT falling 7.5 8 8.5 Boost-disable threshold Boost VOUT = 7 V, VBAT rising Boost hysteresis Boost VOUT = 7 V, VBAT rising or falling Boost VOUT = 10 V DIV = open, VBAT = 2 to 10 V Boost-enable threshold Boost VOUT = 10 V, VBAT falling Boost-disable threshold Boost hysteresis Boost VOUT = 8.85 V 8 8.5 9 0.4 0.5 0.6 9.7 10 10.4 10.5 11 11.5 Boost VOUT = 10 V, VBAT rising 11 11.5 12 Boost VOUT = 10 V, VBAT rising or falling 0.4 0.5 0.6 DIV = VREG, VBAT = 2 to 8.85 V 8.35 8.85 9.35 Boost-enable threshold Boost VOUT = 8.85 V, VBAT falling 9.15 9.85 10.45 Boost-disable threshold Boost VOUT = 8.85 V, VBAT rising 9.65 10.35 10.85 Boost hysteresis Boost VOUT = 8.85 V, VBAT rising or falling 0.4 0.5 0.6 0.2 0.225 UNIT V V V V V V Boost-Switch Current Limit 4.7 VDS Current-limit sensing 4.8 tDS Leading-edge blanking DS input with respect to PGNDA 0.175 200 V ns Gate Driver for Boost Controller 4.9 IGC1 4.10 rDS(on) Peak Gate-driver peak current 1.5 Source and sink driver VREG = 5.8 V, IGC1 current = 200 mA A 2 Gate Driver for PMOS 4.11 rDS(on) PMOS OFF 4.12 IPMOS_ON Gate current VIN = 13.5 V, Vgs = -5 V 10 4.13 tdelay_ON Turnon delay C = 10 nF 20 10 mA 5 10 s Boost-Controller Switching Frequency 4.14 fsw-Boost Boost switching frequency 4.15 DBoost Boost duty cycle fSW_Buck / 2 kHz 90% Error Amplifier (OTA) for Boost Converters 4.16 GmBOOST Forward transconductance 5.0 Buck Controllers 5.1a VBuckA_NRM Fixed output voltage in normal mode 5.1b VBuckA_LPM Fixed output in low-power mode 5.2a VBuckB_NRM Fixed output voltage in normal mode 5.2b VBuckB_LPM Fixed output voltage in lowpower mode VBAT = 12 V 0.8 1.35 VBAT = 5 V 0.35 0.65 Included resistor-feedback-divider, measured at FBA pin Included resistor-feedback-divider, measured at FBB pin 3.345 3.396 3.447 3.311 3.396 3.481 1.216 1.235 1.253 1.204 1.235 1.266 mS V V V sense for forward-current limit in CCM Measured across Sx1 and Sx2, FBx at 94% of typical value (low duty-cycle) 60 75 90 mV V sense for reverse-current limit in CCM Measured across Sx1 and Sx2, FBx at 125% of typical value -65 -37.5 -23 mV VI-Foldback V sense for output short Measured across Sx1 and Sx2, FBx = 0 V 17 32.5 48 mV 5.7 tdead Shoot-through delay, blanking time 5.8 DCNRM Maximum duty cycle (digitally controlled) 5.9 DCLPM Duty cycle, LPM 5.4 Vsense 5.5 5.6 High-side minimum on-time 20 ns 100 ns 98.75% 80% Submit Documentation Feedback Copyright (c) 2013, Texas Instruments Incorporated Product Folder Links: TPS43337-Q1 5 TPS43337-Q1 SLVSBC2A - AUGUST 2013 - REVISED SEPTEMBER 2013 www.ti.com DC ELECTRICAL CHARACTERISTICS (continued) VIN = 8 to 18 V, TJ = -40C to +150C (unless otherwise noted) NO. PARAMETER TEST CONDITIONS ILPM_Entry LPM entry-threshold load current as fraction of maximum set load current ILPM_Exit LPM exit-threshold load current as fraction of maximum set load current 5.10 MIN (3) TYP MAX 1% . (3) UNIT 10% High-Side External NMOS Gate Drivers for Buck Controller 5.11 IGX1_peak Gate-driver peak current 5.12 rDS(on) Source and sink driver 1.5 VREG = 5.8 V, IGX1 current = 200 mA A 2 2 Low-Side NMOS Gate Drivers for Buck Controller 5.13 IGX2_peak Gate driver peak current 5.14 RDS Source and sink driver ON 1.5 VREG = 5.8 V, IGX2 current = 200 mA A Error Amplifier (OTA) for Buck Converters GmBUCK 6.0 Digital Inputs: ENA, ENB, ENC, SYNC 6.1 VIH Higher threshold VIN = 13 V 6.2 VIL Lower threshold VIN = 13 V 6.3 RIH_SYNC Pulldown resistance on SYNC VSYNC = 5 V 500 k 6.4 RIL_ENC Pulldown resistance on ENC VENC = 5 V 500 k 6.5 IIL_ENx Pullup current source on ENA, ENB VENx = 0 V 0.5 7.0 Boost Output Voltage: DIV 7.1 VIH_DIV Higher threshold 7.2 VIL_DIV Lower threshold 7.3 Voz_DIV Voltage on DIV if unconnected 8.0 Switching Parameter - Buck DC-DC Controllers 8.1 fSW_Buck Buck switching frequency RT pin: GND 360 400 440 kHz 8.2 fSW_Buck Buck switching frequency RT pin: 60-k external resistor 360 400 440 kHz 8.3 fSW_adj Buck adjustable range with external resistor RT pin: external resistor 150 600 kHz 8.4 fSYNC Buck synchronization range External clock input 150 600 kHz 9.0 Internal Gate-Driver Supply Internal regulated supply VIN = 8 to 18 V, VEXTSUP = 0 V, SYNC = high 5.5 5.8 6.1 V 9.1 VREG Load regulation IVREG = 0 to 100 mA, VEXTSUP = 0 V, SYNC = high 0.2% 1% Internal regulated supply VEXTSUP = 8.5 V 7.5 7.8 9.2 VREG(EXTSUP) Load regulation IEXTSUP = 0 to 125 mA, SYNC = High VEXTSUP = 8.5 to 13 V 0.2% 1% 9.3 VEXTSUP-th EXTSUP switch-over voltage threshold IVREG = 0 to 100 mA, VEXTSUP ramping positive 4.6 4.8 V 9.4 VEXTSUP-Hys EXTSUP switch-over hysteresis 150 250 mV 9.5 IREG-Limit Current limit on VREG VEXTSUP = 0 V, normal mode as well as LPM 100 400 mA 9.6 IREG_EXTSUP-Limit Current limit on VREG when using EXTSUP IVREG = 0 to 100 mA, VEXTSUP = 8.5 V, SYNC = High 125 400 mA 10.0 Soft Start 10.1 ISSx Soft-start source current VSSA and VSSB = 0 V 60 A 11.0 Oscillator (RT) 11.1 VRT (3) 6 COMPA, COMPB = 0.8 V, source/sink = 5 A, test in feedback loop 5.15 Transconductance VREG = 5.8 V 0.72 1 1.35 1.7 V 0.7 2 Vreg - 0.2 Oscillator reference voltage Vreg / 2 7.2 4.4 40 V A V 0.2 Voltage on DIV if unconnected mS 50 1.2 V V V V The exit threshold specification must always higher than the entry threshold. Submit Documentation Feedback Copyright (c) 2013, Texas Instruments Incorporated Product Folder Links: TPS43337-Q1 TPS43337-Q1 www.ti.com SLVSBC2A - AUGUST 2013 - REVISED SEPTEMBER 2013 DC ELECTRICAL CHARACTERISTICS (continued) VIN = 8 to 18 V, TJ = -40C to +150C (unless otherwise noted) NO. PARAMETER 12.0 Power Good / Delay 12.1a PGthA 12.1b PGthB 12.2 PGhys Hysteresis 12.3 PGdrop Voltage drop TEST CONDITIONS Power-good threshold PGleak Power-good leakage 12.6 tdeglitch Power-good deglitch time TYP MAX FBA falling 3.09 3.158 3.226 FBB falling 1.124 1.148 1.173 UNIT V 2% 12.4 12.5 MIN IPGA = 5 mA 450 mV IPGA = 1 mA 100 mV 1 A 16 s Sx2 = PGx = 13 V 2 12.7 tdelay Reset delay External capacitor = 1 nF VBUCKx < PGthx 12.8 tdelay_fix Fixed reset delay No external capacitor, pin open 12.9 IOH Activate current source (current to charge external capacitor) 12.10 IIL Activate current sink (current to discharge external capacitor) 13.0 Overtemperature Protection 13.1 Tshutdown Junction-temperature shutdown threshold 13.2 Thys Junction-temperature hysteresis 1 ms 20 50 s 30 40 50 A 30 40 50 A 150 165 C 15 C Submit Documentation Feedback Copyright (c) 2013, Texas Instruments Incorporated Product Folder Links: TPS43337-Q1 7 TPS43337-Q1 SLVSBC2A - AUGUST 2013 - REVISED SEPTEMBER 2013 www.ti.com DEVICE INFORMATION DAP PACKAGE (TOP VIEW) VBAT 1 38 DS 2 37 GC1 3 36 DIV GC2 4 35 VREG CBA 5 34 CBB GA1 6 33 GB1 PHA 7 32 PHB GA2 8 31 9 30 SA1 10 29 SB1 SA2 11 28 SB2 FBA 12 27 13 26 SSA 14 25 SSB PGA 15 24 PGB PGNDA COMPA VIN EXTSUP GB2 PGNDB FBB COMPB ENA 16 23 AGND ENB 17 22 RT 18 21 DLYAB 19 20 SYNC COMPC ENC PIN FUNCTIONS NO. I/O AGND NAME 23 O Analog ground reference CBA 5 I A capacitor on this pin acts as the voltage supply for the high-side N-channel MOSFET gate-drive circuitry in buck controller BuckA. When the buck is in a dropout condition, the device automatically reduces the duty cycle of the high-side MOSFET to approximately 95% on every fourth cycle to allow the capacitor to recharge. CBB 34 I A capacitor on this pin acts as the voltage supply for the high-side N-channel MOSFET gate-drive circuitry in buck controller BuckB. When the buck is in a dropout condition, the device automatically reduces the duty cycle of the high-side MOSFET to approximately 95% on every fourth cycle to allow the capacitor to recharge. COMPA 13 O Error-amplifier output of BuckA and compensation node for voltage-loop stability. The voltage at this node sets the target for the peak current through the inductor of BuckA. Clamping this voltage on the upper and lower ends provides current-limit protection for the external MOSFETs. COMPB 26 O Error-amplifier output of BuckB and compensation node for voltage-loop stability. The voltage at this node sets the target for the peak current through the inductor of BuckB. Clamping this voltage on the upper and lower ends provides current-limit protection for the external MOSFETs. COMPC 18 O Error-amplifier output and loop-compensation node of the boost regulator DIV 36 I The status of this pin defines the output voltage of the boost regulator. A high input regulates the boost converter at 8.85 V, a low input sets the value at 7 V, and a floating pin sets 10 V. DLYAB 21 O The capacitor at the DLYAB pin sets the power-good delay interval used to de-glitch the outputs of the powergood comparators. Leaving this pin open sets the power-good delay to an internal default value of 20 s, typical. DS 2 I This input monitors the voltage on the external boost-converter low-side MOSFET for overcurrent protection. An alternative connection for better noise immunity is to place a sense resistor between the source of the low-side MOSFET and ground via a filter network. ENA 16 I Enable inputs for BuckA (active-high with an internal pullup current source). An input voltage higher than 1.5 V enables the controller, whereas an input voltage lower than 0.7 V disables the controller. When both ENA and ENB are low, the device shuts down and consumes less than 4 A of current. 8 DESCRIPTION Submit Documentation Feedback Copyright (c) 2013, Texas Instruments Incorporated Product Folder Links: TPS43337-Q1 TPS43337-Q1 www.ti.com SLVSBC2A - AUGUST 2013 - REVISED SEPTEMBER 2013 PIN FUNCTIONS (continued) NAME NO. I/O DESCRIPTION ENB 17 I Enable inputs for BuckB (active-high with an internal pullup current source). An input voltage higher than 1.5 V enables the controller, whereas an input voltage lower than 0.7 V disables the controller. When both ENA and ENB are low, the device shuts down and consumes less than 4 A of current. ENC 19 I This input enables and disables the boost regulator. An input voltage higher than 1.5 V enables the controller. Voltages lower than 0.7 V disable the controller. When enabled, the controller starts switching as soon as VBAT falls below the boost threshold, depending upon the programmed output voltage. EXTSUP 37 I One uses EXTSUP to supply the VREG regulator from one of the TPS43337-Q1 buck regulator rails to reduce power dissipation in cases where there is an expectation of high VIN. When EXTSUP is open or lower than 4.6 V, the regulator power comes from VIN. FBA 12 I Feedback voltage pin for BuckA. The buck controller regulates this feedback voltage to 3.4 V through the internal resistor-divider network. Connect FBA to the output voltage of BuckA. FBB 27 I Feedback voltage pin for BuckB. The buck controller regulates this feedback voltage to 1.235 V through the internal resistor-divider network. Connect FBB to the output voltage of BuckB. GA1 6 O This output drives an external high-side N-channel MOSFET for buck regulator BuckA. The output provides high peak currents to drive capacitive loads. The gate-drive reference is to a floating ground provided by PHA that has a voltage swing provided by CBA. GA2 8 O This output drives an external high-side N-channel MOSFET for buck regulator BuckA. The output provides high peak currents to drive capacitive loads. VREG provides the voltage swing on this pin. GB1 33 O This output drives an external high-side N-channel MOSFET for buck regulator BuckB. The output provides high peak currents to drive capacitive loads. The gate-drive reference is to a floating ground provided by PHB that has a voltage swing provided by CBB. GB2 31 O This output drives an external high-side N-channel MOSFET for buck regulator BuckB. The output provides high peak currents to drive capacitive loads. VREG provides the voltage swing on this pin. GC1 3 O This output drives an external low-side N-channel MOSFET for the boost regulator. This output provides high peak currents to drive capacitive loads. VREG provides the voltage swing on this pin. GC2 4 O This pin makes a floating output drive available to control the external P-channel MOSFET. This MOSFET bypasses the boost rectifier diode or a reverse-protection diode when the boost status is non-switching or disabled, and thus reduces power losses. PGA 15 O Open-drain power-good indicator pin for BuckA. An internal power-good comparator monitors the voltage at the feedback pin and pulls this output low when the output voltage falls below 93% of the set value, or if either VIN or VBAT drops below the respective undervoltage threshold. PGB 24 O Open-drain power-good indicator pin for BuckB. An internal power-good comparator monitors the voltage at the feedback pin and pulls this output low when the output voltage falls below 93% of the set value, or if either VIN or VBAT drops below the respective undervoltage threshold. PGNDA 9 O Power-ground connection to the source of the low-side N-channel MOSFETs of BuckA. PGNDB 30 O Power-ground connection to the source of the low-side N-channel MOSFETs of BuckB. PHA 7 O Switching terminal of buck regulator BuckA; provides a floating ground reference for the high-side MOSFET gatedriver circuitry and senses current reversal in the inductor when discontinuous-mode operation is desired. PHB 32 O Switching terminal of buck regulator BuckB; provides a floating ground reference for the high-side MOSFET gatedriver circuitry and senses current reversal in the inductor when discontinuous-mode operation is desired. RT 22 O Connecting a resistor to ground on this pin sets the operating switching frequency of the buck and boost controllers. A short circuit to ground on this pin defaults operation to 400 kHz for the buck controllers and 200 kHz for the boost controller. SA1 10 I SA2 11 I SB1 29 I SB2 28 I SSA SSB 14 25 High-impedance differential-voltage inputs from the current-sense element (sense resistor or inductor DCR) for each buck controller. Choose the current-sense element to set the maximum current through the inductor based on the current-limit threshold (subject to tolerances) and considering the typical characteristics across duty cycle and VIN. (SA1 positive node, SA2 negative node) High-impedance differential voltage inputs from the current-sense element (sense resistor or inductor DCR) for each buck controller. Choose the current-sense element to set the maximum current through the inductor based on the current-limit threshold (subject to tolerances) and considering the typical characteristics across duty cycle and VIN. (SB1 positive node, SB2 negative node) O Soft-start or tracking input for buck controller BuckA. The buck controller regulates the FBA voltage to the lower of 0.8 V or the SSA pin voltage. An internal pullup current source of 50 A is present at the pin. Connect an appropriate capacitor here to set the soft-start ramp interval, or connect a resistor divider connected to another supply to provide a tracking input to this pin. O Soft-start or tracking input for buck controller BuckB. The buck controller regulates the FBA voltage to the lower of 0.8 V or the SSA pin voltage. An internal pullup current source of 50 A is present at the pin. Connect an appropriate capacitor here to set the soft-start ramp interval, or connect a resistor divider connected to another supply to provide a tracking input to this pin. Submit Documentation Feedback Copyright (c) 2013, Texas Instruments Incorporated Product Folder Links: TPS43337-Q1 9 TPS43337-Q1 SLVSBC2A - AUGUST 2013 - REVISED SEPTEMBER 2013 www.ti.com PIN FUNCTIONS (continued) NAME NO. I/O DESCRIPTION SYNC 20 I If an external clock is present on this pin, the device detects it, and the internal PLL locks on to the external clock. This overrides the internal oscillator frequency. The device can synchronize to frequencies from 150 kHz to 600 kHz. A high logic level on this pin ensures forced continuous-mode operation of the buck controllers and inhibits transition to low-power mode. An open or low allows discontinuous-mode operation and entry into low-power mode at light loads. VBAT 1 I Battery input sense for the boost controller. With the boost controller enabled, if the voltage at VBAT falls below the boost threshold, the device activates the boost controller and regulates the voltage at VIN to the programmed boost output voltage. VIN 38 I Main input pin. This is the buck controller input pin as well as the output of the boost regulator. Additionally, VIN powers the internal control circuits of the device. VREG 35 O This pin requires an external capacitor to provide a regulated supply for the gate drivers of the buck and boost controllers. TI recommends a capacitance on the order of 4.7 F. Either VIN or EXTSUP can power the regulator. This pin has current-limit protection, so do not use it to drive any other loads. 10 Submit Documentation Feedback Copyright (c) 2013, Texas Instruments Incorporated Product Folder Links: TPS43337-Q1 TPS43337-Q1 www.ti.com SLVSBC2A - AUGUST 2013 - REVISED SEPTEMBER 2013 VIN EXTSUP VREG SYNC Gate Driver Supply 37 PWM Logic 5 CBA 6 GA1 7 PHA 8 GA2 9 PGNDA 10 SA1 11 SA2 12 FBA 13 COMPA 15 PGA 21 DLYAB 34 CBB 33 GB1 32 PHB 31 GB2 30 PGNDB 29 SB1 28 SB2 27 FBB 26 COMPB 24 PGB VREG 35 Internal Oscillator 22 180 deg RT Duplicate for second Buck controller channel Internal ref (Band gap) 38 Slope Comp PWM comp SYNC and LPM 20 Current sense Amp OTA GC2 Gm 0.8 V Source and Sink Logic 4 SSA FBA ENC 50 A SSA 14 ENA 16 ENA 25 ENB 17 DS 2 Filter Timer 500 nA 40 A VIN 50 A SSB VIN 40 A ENB 500 nA OCP VIN VboostxV 0.2 V COMPC 18 DIV 36 Gm Second Buck Controller Channel Ramp Vboost7V-th VBAT OTA 1 MUX Vboost8.85V-th Vboost10V-th GC1 3 ENC 19 AGND 23 VREG PWM comp PWM Logic PGNDA Figure 2. Functional Block Diagram Submit Documentation Feedback Copyright (c) 2013, Texas Instruments Incorporated Product Folder Links: TPS43337-Q1 11 TPS43337-Q1 SLVSBC2A - AUGUST 2013 - REVISED SEPTEMBER 2013 www.ti.com TYPICAL CHARACTERISTICS BuckA EFFICIENCY AND POWER LOSSES VIN = 12 V, Inductor = 10 H, Rsense = 20 m, Switching Frequency = 400 kHz, EXTSUP open 10 80 100 1 80 Power Loss (W) Efficiency (%) 70 0.1 60 50 0.01 40 30 0.001 20 10 Efficiency, SYNC=HIGH Efficiency, SYNC=LOW Power Loss, SYNC=HIGH Power Loss, SYNC=LOW 90 1 70 0.1 60 50 0.01 40 30 0.001 20 10 Power Loss (W) Efficiency, SYNC=HIGH Efficiency, SYNC=LOW Power Loss, SYNC=HIGH Power Loss, SYNC=LOW 90 Efficiency (%) 100 BuckB EFFICIENCY AND POWER LOSSES VIN = 12 V, Inductor = 4.7 H, Rsense = 10 m, Switching Frequency = 400 kHz, EXTSUP open 10 0.0001 0 1.00E-07 1.00E-05 1.00E-03 1.00E-01 I_Load (A) 0.0001 0 1.00E-07 1.00E-05 1.00E-03 1.00E-01 I_Load (A) C001 C002 Figure 3. Figure 4. BuckA LOAD STEP 1 A - 2 A VIN = 12 V, Inductor = 10 H, Rsense = 20 m, COUT = 100 F, Switching Frequency = 400 kHz BuckB LOAD STEP 1 A - 2 A VIN = 12 V, Inductor = 4.7 H, Rsense = 10 m, COUT = 320 F, Switching Frequency = 400 kHz VOUT BuckA - AC Coupled 50 mV / DIV VOUT BuckB - AC Coupled 100 mV / DIV IIND 1 A / DIV IIND 1 A / DIV 1 ms / DIV 1 ms / DIV Figure 5. Figure 6. BuckB LOAD STEP UP 0 A - 1 A VIN = 12 V, Inductor = 4.7 H, Rsense = 10 m, COUT = 320 F, Switching Frequency = 400 kHz BuckB LOAD STEP DOWN 1 A - 0 A VIN = 12 V, Inductor = 4.7 H, Rsense = 10 m, COUT = 320 F, Switching Frequency = 400 kHz IIND 50 mV / DIV VOUT BuckB - AC Coupled 50 mV / DIV VOUT BuckB - AC Coupled IIND 0.2 A / DIV 0.2 A / DIV 100 s / DIV 100 s / DIV Figure 7. 12 Figure 8. Submit Documentation Feedback Copyright (c) 2013, Texas Instruments Incorporated Product Folder Links: TPS43337-Q1 TPS43337-Q1 www.ti.com SLVSBC2A - AUGUST 2013 - REVISED SEPTEMBER 2013 TYPICAL CHARACTERISTICS (continued) SOFT-START OUTPUTS BuckA and BuckB VIN (BOOST OUTPUT) = 10 V, SWITCHING FREQUENCY = 200 kHz, INDUCTOR = 1 H, RSENSE = 7.5 mW 100 90 VOUT BuckA, 1V / DIV VBAT = 8 V Efficiency (%) 80 VOUT BuckB, 0.5 V / DIV 70 VBAT = 5 V 60 VBAT = 3 V 50 40 30 20 10 0 5 ms / DIV 0.01 1 Output Current (A) Figure 10. Figure 9. VBAT (BOOST INPUT) = 5 V, VIN (BOOST OUTPUT) = 10 V, SWITCHING FREQUENCY = 200 kHz, INDUCTOR = 1 H, RSENSE = 7.5 mW, CIN = 440 F, COUT = 660 F VIN (BOOST OUTPUT) = 10 V, BuckA = 5 V AT 1.5 A, BuckB = 3.3 V AT 3.5 A, SWITCHING FREQUENCY = 200 kHz, INDUCTOR = 1 H, RSENSE = 7.5 mW, CIN = 440 F, COUT = 660 F 5 V/DIV 500 mV/DIV 10 VBAT (BOOST INPUT) VIN (BOOST OUTPUT) AC-COUPLED 0V 200 mV/DIV 200 mV/DIV VOUT BuckA AC-COUPLED VOUT BuckB AC-COUPLED 5 A/DIV IIND 10 A/DIV IIND 0A 2 ms/DIV 20 ms/DIV Figure 11. Figure 12. VIN (BOOST OUTPUT) = 10 V, BuckA = 5 V AT 1.5 A, BuckB = 3.3V AT 3.5A, SWITCHING FREQUENCY = 200 kHz, INDUCTOR = 1 H, RSENSE = 7.5 mW, CIN = 440 F, COUT = 660 F 5 V/DIV VBAT (BOOST INPUT) = 5 V, VIN (BOOST OUTPUT) = 10 V, SWITCHING FREQUENCY = 200 kHz, INDUCTOR = 1 H, RSENSE = 7.5 mW, CIN = 440 F, COUT = 660 F VBAT (BOOST INPUT) 3-A LOAD 5 A/DIV 0V VIN (BOOST OUTPUT) 5 V/DIV 0V 10 A/DIV 0A 100-mA LOAD 5 A/DIV IIND 2 s/DIV 20 ms/DIV Figure 13. Figure 14. Submit Documentation Feedback Copyright (c) 2013, Texas Instruments Incorporated Product Folder Links: TPS43337-Q1 13 TPS43337-Q1 SLVSBC2A - AUGUST 2013 - REVISED SEPTEMBER 2013 www.ti.com TYPICAL CHARACTERISTICS (continued) Peak Current Sense Voltage (mV) 75 62.5 Sense Current (A) 50 37.5 25 12.5 SYNC = LOW 0 -12.5 -25 SYNC = HIGH -37.5 0.65 0.8 0.95 1.1 1.25 1.4 0.9 0.8 0.7 0.6 0.5 0.4 0.3 0.2 0.1 0 -0.1 -0.2 -0.3 150C 25C 0 1.55 1 2 5 7 6 8 9 10 11 12 Figure 16. 80 Peak Current Sense Voltage (mV) FOLDBACK CURRENT LIMIT (BUCK) 80 Peak Current Sense Voltage (mV) 4 Output Voltage (V) COMPx Voltage (V) Figure 15. 70 60 50 40 30 20 70 60 VIN = 8 V 50 40 VIN = 12 V 30 20 10 0 10 0 10 0 0 0.25 0.5 0.75 1 Normalized VOUT Figure 17. 14 3 20 30 40 50 60 70 80 90 100 Duty Cycle (%) Figure 18. Submit Documentation Feedback Copyright (c) 2013, Texas Instruments Incorporated Product Folder Links: TPS43337-Q1 TPS43337-Q1 www.ti.com SLVSBC2A - AUGUST 2013 - REVISED SEPTEMBER 2013 DETAILED DESCRIPTION BUCK CONTROLLERS: NORMAL-MODE PWM OPERATION Frequency Selection and External Synchronization The buck controllers operate using constant-frequency peak-current-mode control for optimal transient behavior and ease of component choices. The switching frequency is programmable between 150 kHz and 600 kHz, depending upon the resistor value at the RT pin. A short circuit to ground at this pin sets the default switching frequency to 400 kHz. the frequency is also set by a resistor at RT according to Equation 1. X fSW = (X = 24 kW MHz) RT fSW = 24 109 RT (1) For example, 600 kHz requires 40 k. 150 kHz requires 160 k. Synchronizing to an external clock at the SYNC pin in the same frequency range of 150 to 600 kHz is also possible. The device detects clock pulses at this pin, and an internal PLL locks on to the external clock within the specified range. The device also detects a loss of clock at this pin, and on detecting this loss, the device sets the switching frequency to the internal oscillator. The two buck controllers operate at identical switching frequencies, 180 degrees out of phase. Enable Inputs Independent enable inputs from the ENA and ENB pins enable the buck controllers. These are high-voltage pins, with a threshold of 1.5 V for high level, and with direct connection directly to the battery for self-bias. The low threshold is 0.7 V. Both these pins have internal pullup currents of 0.5 A (typical). As a result, an open circuit on these pins enables the respective buck controllers. When both buck controllers are disabled, the device shuts down and consumes a current less than 4 A. Feedback Inputs An internal voltage divider presets the output voltage. Connect each FBx pin to the output of the respective regulator of the pin. Soft-Start Inputs In order to avoid large inrush currents, each buck controller has an independent, programmable soft-start timer. The voltage at the SSx pins acts as the soft-start reference voltage. A 50-A pullup current available at the SSx pins, in combination with a suitably chosen capacitor, generates a ramp of the desired soft-start speed. After start-up, the pullup current ensures that this node is higher than the internal reference of 0.8 V; 0.8 V then becomes the reference for the buck controllers. Equation 2 calculates the soft-start ramp time. I SS Dt CSS = (Farads) DV where, * * * ISS = 50 A (typical) V = 0.8 V CSS is the required capacitor for t, the desired soft-start time. (2) Alternatively, the soft-start pins are used as tracking inputs. In this case, connect these pins to the supply to be tracked via a suitable resistor-divider network. Submit Documentation Feedback Copyright (c) 2013, Texas Instruments Incorporated Product Folder Links: TPS43337-Q1 15 TPS43337-Q1 SLVSBC2A - AUGUST 2013 - REVISED SEPTEMBER 2013 www.ti.com Current-Mode Operation Peak-current-mode control regulates the peak current through the inductor to maintain the output voltage at the set value. The error between the feedback voltage at FBx and the internal voltage divider produces a signal at the output of the error amplifier (COMPx), which serves as the target for the peak inductor current. The device senses the current through the inductor as a differential voltage at Sx1-Sx2 and compares the voltage with this target during each cycle. A fall or rise in load current produces a fall or rise in voltage at FBx, causing COMPx to fall or rise respectively, thus increasing or decreasing the current through the inductor until the average current matches the load. This process maintains the output voltage in regulation. The top N-channel MOSFET turns on at the beginning of each clock cycle and stays on until the inductor current reaches the peak value. When this MOSFET turns off, and after a small delay (shoot-through delay), the lower N-channel MOSFET turns on until the start of the next clock cycle. In dropout operation, the high-side MOSFET stays on continuously. In every fourth clock cycle, there is a limit on the duty cycle of 95% in order to charge the bootstrap capacitor at CBx, which allows a maximum duty cycle of 98.75% for the buck regulators. During dropout, the buck regulator switches at one-fourth of its normal frequency. Current Sensing and Current Limit With Foldback Clamping of the maximum value of COMPx is such as to limit the maximum current through the inductor to a specified value. When the output of the buck regulator (and hence the feedback value at FBx) falls to a low value due to a short-circuit or overcurrent condition, the clamped voltage at COMPx successively decreases, thus providing current foldback protection, which protects the high-side external MOSFET from excess current (forward-direction current limit). Similarly, if due to a fault condition the output is shorted to a high voltage and the low-side MOSFET turns fully on, the COMPx node drops low. A clamp is on the lower end as well, in order to limit the maximum current in the low-side MOSFET (reverse-direction current limit). An external resistor senses the current through the inductor. Choose the sense resistor such that the maximum forward-peak current in the inductor generates a voltage of 75 mV across the sense pins. This specified typical value is for low duty cycles only. At typical duty-cycle conditions around 28% (assuming 3.4 V output and 12 V input), 55 mV is a more reasonable value, considering tolerances and mismatches. The typical characteristics (see Figure 18) provide a guide for using the correct current-limit sense voltage. The current-sense pins Sx1 and Sx2 are high-impedance pins with low leakage across the entire output range, thus allowing DCR current sensing using the dc resistance of the inductor for higher efficiency. Figure 19 shows DCR sensing. Here, the series resistance (DCR) of the inductor is the sense element. Place the filter components close to the device for noise immunity. Remember that while the DCR sensing gives high efficiency, it is inaccurate due to the temperature sensitivity and a wide variation of the parasitic inductor series resistance. Hence using the more-accurate sense resistor for current sensing is advantageous. Inductor L TPS43337-Q1 VBuckX DCR R1 1 C1 1 VC 2 Sx2 Sx1 1 Figure 19. DCR Sensing Configuration 16 Submit Documentation Feedback Copyright (c) 2013, Texas Instruments Incorporated Product Folder Links: TPS43337-Q1 TPS43337-Q1 www.ti.com SLVSBC2A - AUGUST 2013 - REVISED SEPTEMBER 2013 Slope Compensation Optimal slope compensation, which is adaptive to changes in input voltage and duty cycle, allows stable operation at all conditions. For optimal performance of this circuit, choose the inductor and sense resistor according to Equation 3. L f SW = 200 RS where * * * L is the buck regulator inductor in henries. RS is the sense resistor in ohms. fsw is the buck regulator switching frequency in hertz. (3) Power-Good Outputs and Filter Delays Each buck controller has an independent power-good comparator monitoring the feedback voltage at the FBx pins and indicating whether the output voltage has fallen below a specified power-good threshold. This threshold has a typical value of 93% of the regulated output voltage. The power-good indicator is available as an opendrain output at the PGx pins. Shutdown of a buck controller causes an internal pulldown of the power-good indicator. Connecting the external pullup resistor to a rail other than the output of that particular buck channel causes a constant current flow through the external resistor during a powered-down state of the buck controller. In order to avoid triggering the power-good indicators due to noise or fast transients on the output voltage, the device uses an internal delay circuit for de-glitching. Similarly, when the output voltage returns to the set value after a long negative transient, assertiohn of the power-good indicator (release of the open-drain pin) occurs after the same delay. Use of this delay can pause the reset of circuits powered from the buck regulator rail. Program the delay of this circuit by using a suitable capacitor at the DLYAB pin according to Equation 4. tDELAY 1 msec = CDLYAB 1 nF (4) When the DLYAB pin is open, the delay is set to a default value of 20 s (typical). The power-good delay timing is common to both the buck rails, but the power-good comparators and indicators function independently. Light-Load PFM Mode An external clock or a high level on the SYNC pin results in forced continuous-mode operation of the bucks. When the SYNC pin is low or open, the buck controllers are allowed to operate in discontinuous mode at light loads by turning off the low-side MOSFET whenever a zero-crossing in the inductor current is detected. In discontinuous mode, as the load decreases, the duration of the clock-period when both the high-side as well the low-side MOSFET is turned-off, increases (deep discontinuous mode). In case the duration exceeds 60% of the clock period and VBAT > 8 V, the buck controller switches to a low-power operation mode. The design ensures that this typically occurs at 1% of the set full-load current if the inductor and the sense resistor have been chosen appropriately as recommended in the Slope Compensation section. In low-power PFM mode, the buck monitors the FBx voltage and compares it with the 0.8 V internal reference voltage through the internal voltage divider. Whenever the FBx value falls below the internal threshold, the highside MOSFET is turned on for a pulse duration inversely proportional to the difference VIN - Sx2. At the end of this on-time, the high-side MOSFET is turned off and the current in the inductor decays until it becomes zero. The low-side MOSFET is not turned on. The next pulse occurs the next time FBx falls below the threshold value which results in a constant volt-second ton hysteretic operation with a total-device quiescent-current consumption of 34 A when a single buck channel is active and 43 A when both channels are active. As the load increases, the pulses become more and more frequent and move closer to each other until the current in the inductor becomes continuous. At this point, the buck controller returns to normal fixed-frequency current-mode control. Another criterion to exit the low-power mode is when VIN falls low enough to require higher than 80% duty cycle of the high-side MOSFET. During low-power mode, the TPS43337-Q1 supports the full-current load until the transition to normal mode takes place. The design ensures the low-power-mode exit occurs at 10% (typical) of full-load current if the inductor and sense resistor have been chosen as recommended. Moreover, there is always a hysteresis between the entry and exit thresholds to avoid oscillating between the two modes. Submit Documentation Feedback Copyright (c) 2013, Texas Instruments Incorporated Product Folder Links: TPS43337-Q1 17 TPS43337-Q1 SLVSBC2A - AUGUST 2013 - REVISED SEPTEMBER 2013 www.ti.com In the event that both buck controllers are active, low-power mode is only possible when both buck controllers have light loads that are low enough for entry into low-power mode. When the boost controller is enabled, lowpower mode is possible only if VBAT is high enough to prevent the boost from switching and if DIV is open or set to GND. If DIV is high (VREG), low-power mode is inhibited. Boost Controller The boost controller has a fixed-frequency voltage-mode architecture and includes a cycle-by-cycle current-limit protection for the external N-channel MOSFET. The switching frequency is derived from and set to one-half of the buck-controller switching frequency. The output voltage of the boost controller at the VIN pin is set by an internal resistor-divider network and is programmable to 7 V, 8.85 V, and 10 V based on the low, open, and high status of the DIV pin, respectively. A change of the DIV setting is not recognized while the device is in low-power mode. The boost controller is enabled by the active-high ENC pin and is active when the input voltage at the VBAT pin has crossed the unlock threshold of 8.5 V at least once. After that, the boost controller is armed and starts switching as soon as VIN falls below the value set by the DIV pin, and regulates the VIN voltage. Thus, the boost regulator maintains a stable input voltage for the buck regulators during transient events such as a cranking pulse at VBAT. Whenever the voltage at the DS pin exceeds 200 mV, the boost-external MOSFET is turned off by pulling the CG1 pin low. By connecting the DS pin to the drain of the MOSFET or to a sense resistor between the MOSFET source and ground, cycle-by-cycle overcurrent protection for the MOSFET can be achieved. The on-resistance of the MOSFET or the value of the sense resistor must be chosen in such a way that the on-state voltage at DS does not exceed 200 mV at the maximum load and minimum input-voltage conditions. When a sense resistor is used, connecting a filter network between the DS pin and the sense resistor is recommended for better noise immunity. The boost output (VIN) is also used to supply other circuits in the system, however, they should be high-voltage tolerant. The boost output is regulated to the programmed value only when VIN is low, and so VIN can reach battery levels. Vbat VIN TPS43337-Q1 DS GC1 Figure 20. External Drain-Source Voltage Sensing Vbat VIN TPS43337-Q1 GC1 DS RIFLT CIFLT RISEN Figure 21. External Current Shunt Resistor 18 Submit Documentation Feedback Copyright (c) 2013, Texas Instruments Incorporated Product Folder Links: TPS43337-Q1 TPS43337-Q1 www.ti.com SLVSBC2A - AUGUST 2013 - REVISED SEPTEMBER 2013 Table 1. Mode Control SYNC Terminal Comments External clock Device in forced into continuous mode, internal PLL locks into the external clock between 150 kHz and 600 kHz Low or open Device can enter discontinuous mode. Automatic LPM entry and exit, depending on load conditions High Device in forced into continuous mode Table 2. Mode of Operation ENABLE AND INHIBIT PINS ENA ENB ENC Low Low Low Low High High Low Low Low SYNC X Low High Low High Low High High Low High Low Low Low Low High High X Low DRIVER STATUS BUCK CONTROLLERS BOOST CONTROLLER Shutdown Disabled BuckB running Disabled BuckA running Disabled Low High Low High High High High Shutdown Approximately 4 A BuckB: LPM enabled Approximately 34 A (light loads) BuckB: LPM inhibited mA range BuckA: LPM enabled Approximately 34 A (light loads) BuckA: LPM inhibited mA range BuckA and BuckB: LPM enabled Approximately 43 A (light loads) BuckA and BuckB: LPM inhibited mA range Disabled Shutdown Disabled Shutdown Approximately 4 A BuckB running Boost running for VIN < set boost output BuckB: LPM enabled Approximately 54 A (no boost, light loads) BuckB: LPM inhibited mA range Boost running for VIN < set boost output BuckA: LPM enabled Approximately 54 A (no boost, light loads) BuckA: LPM inhibited mA range BuckA and BuckB: LPM enabled Approximately 68 A (no boost, light loads) BuckA and BuckB: LPM inhibited mA range BuckA running High Low QUIESCENT CURRENT BuckA and BuckB running High High DEVICE STATUS BuckA and BuckB running Boost running for VIN < set boost output Gate Driver Supply (VREG, EXTSUP) The gate drivers of the buck and boost controllers are supplied from an internal linear regulator whose output (5.8 V, typical) is available at the VREG pin and requires decoupling with a ceramic capacitor in the range of 3.3 F to 10 F. This pin has internal current-limit protection and should not be used to power any other circuits. The VREG linear regulator is powered from VIN by default when the EXTSUP voltage is lower than 4.6 V (typical). In case VIN is expected to go to high levels, there can be excessive power dissipation in this regulator, especially at high switching frequencies and when using large external MOSFETs. In this case, powering this regulator from the EXTSUP pin is advantageous, which can be connected to a supply lower than VIN but high enough to provide the gate drive. When EXTSUP is connected to a voltage greater than 4.6 V, the linear regulator automatically switches to EXTSUP as its input to provide this advantage. Efficiency improvements are possible when one of the switching regulator rails from the TPS43337-Q1 or any other voltage available in the system is used to power EXTSUP. The maximum voltage that should be applied to EXTSUP is 9 V. Submit Documentation Feedback Copyright (c) 2013, Texas Instruments Incorporated Product Folder Links: TPS43337-Q1 19 TPS43337-Q1 SLVSBC2A - AUGUST 2013 - REVISED SEPTEMBER 2013 www.ti.com VIN LDO VIN typ 5.8 V EXTSUP LDO EXTSUP typ 7.5 V typ 4.6 V VREG Figure 22. Internal Gate-Driver Supply Using a voltage above 5.8 V (sourced by VIN) for EXTSUP is advantageous as it provides a large gate drive and therefore better on-resistance of the external MOSFETs. During low-power mode, the EXTSUP functionality is not available. The internal regulator operates as a shunt regulator powered from VIN and has a typical value of 7.5 V. Current-limit protection for VREG is available in low-power mode as well. If EXTSUP is unused, leave the pin open without a capacitor installed. External P-Channel Drive (GC2) and Reverse Battery Protection The TPS43337-Q1 includes a gate driver for an external P-channel MOSFET, which can be connected across the rectifier diode of the boost regulator which is useful to reduce power losses when the boost controller is not switching. The gate driver provides a swing of 6 V typical below the VIN voltage in order to drive a P-channel MOSFET. When VBAT falls below the boost enable threshold, the gate driver turns off the P-channel MOSFET, and the diode is no longer bypassed. The gate driver can also be used to bypass any additional protection diodes connected in series as shown in Figure 23. Figure 24 also shows a different scheme of reverse battery protection which may require only a smaller-sized diode to protect the N-channel MOSFET, as the diode conducts only for a part of the switching cycle. Because the diode is not always in the series path, the system efficiency improves. R10 GC2 D3 Q7 TPS43337-Q1 Q6 L3 Fuse (S1) VIN Vbat D2 C16 C17 D1 C15 C14 DS GC1 C13 COMPC R9 VBAT Figure 23. Reverse-Battery-Protection Option for Buck-Boost Configuration 20 Submit Documentation Feedback Copyright (c) 2013, Texas Instruments Incorporated Product Folder Links: TPS43337-Q1 TPS43337-Q1 www.ti.com SLVSBC2A - AUGUST 2013 - REVISED SEPTEMBER 2013 GC2 VBAT VIN Fuse TPS43337-Q1 DS GC1 COMPC VBAT Figure 24. Reverse-Battery-Protection Option for Buck-Boost Configuration Undervoltage Lockout and Overvoltage Protection The TPS43337-Q1 starts up at a VIN voltage of 6.5 V (minimum), required for the internal supply (VREG). Once the has started up, it operates down to a VIN voltage of 3.6 V; below this voltage level, the undervoltage lockout disables the device. NOTE If VIN drops, VREG drops as well, reducing the gate-drive voltage, while the digital logic remains fully functional. Even if ENC is high, exceeding the boost-unlock voltage of typically 8.5 V one time is required before boost activation takes place (see the Boost Controller section). A voltage of 46 V at VIN triggers the overvoltage comparator, which shuts down the device. In order to prevent transient spikes from shutting down the device, the undervoltage and overvoltage protection have filter times of 5 s (typical). When the voltages return to the normal-operating region, the enabled switching regulators start including a new soft-start ramp for the buck regulators. When the boost controller is enabled, a voltage less than 1.9 V (typical) on VBAT triggers an undervoltage lockout and pulls the boost gate driver (GC1) low (this action has a filter delay of 5 s, typical). As a result, VIN falls at a rate dependent on the capacitor and load, eventually triggering VIN undervoltage. A short falling transient at VBAT even lower than 2 V can thus be survived, if VBAT returns above 2.5 V before VIN is discharged to the undervoltage threshold. Thermal Protection The TPS43337-Q1 protects itself from overheating using an internal thermal shutdown circuit. If the die temperature exceeds the thermal shutdown threshold of 165C due to excessive power dissipation (for example, due to fault conditions such as a short circuit at the gate drivers or VREG), the controllers are turned off, and then restarted when the temperature has fallen by 15C. Submit Documentation Feedback Copyright (c) 2013, Texas Instruments Incorporated Product Folder Links: TPS43337-Q1 21 TPS43337-Q1 SLVSBC2A - AUGUST 2013 - REVISED SEPTEMBER 2013 www.ti.com APPLICATION INFORMATION The following example illustrates the design process and component selection for the TPS43337-Q1. The design goal parameters are given in Table 3. Table 3. Design Goal Parameters Example PARAMETER Input voltage Output voltage, VOUTx Maximum output current, IOUTx Load step output tolerance, VOUT + VOUT(Ripple) Current output load step, IOUTx Converter switching frequency, fSW VBUCKA VBUCKB BOOST VIN 6 to 30 V 12 V - typical VIN 6 to 30 V 12 V - typical VBAT = 5 (cranking pulse input) to 30 V 3.396 V 1.235 V 10 V 3A 2A 2.5 A 0.2 V 0.12 V 0.5 V 0.1 to 3 A 0.1 to 2 A 0.1 to 2.5 A 400 kHz 400 kHz 200 kHz This example is a starting point and theoretical representation of the values to be used for the application; further optimization of the components derived may be required to improve the performance of the device. Boost Component Selection A boost converter operating in continuous-conduction mode (CCM) has a right-half-plane (RHP) zero in the transfer function. The RHP zero is inversely related to the load current and inductor value and directly related to the input voltage. The RHP zero limits the maximum bandwidth achievable for the boost regulator. If the bandwidth is too close to the RHP zero frequency, the regulator may become unstable. Thus, for high-power systems with low input voltages, a low inductor value is chosen. This value increases the amplitude of the ripple currents in the N-channel MOSFET, the inductor and the capacitors for the boost regulator. They must be designed with the ripple/RHP zero trade-off in mind and considering the power dissipation effects in the components due to parasitic series resistance. A boost converter that operates in the discontinuous mode does not contain the RHP-zero in transfer function. However, designing for the discontinuous mode demands an even lower inductor value that has high ripple currents. Also, ensure that the regulator never enters the continuous-conduction mode; otherwise, the regulator becomes unstable. VIN CO 7V COMPx OTA-gmEA R ESR 8.85 V C1 + VREF C2 R3 10 V Figure 25. Boost Compensation Components This design is done assuming continuous-conduction mode. During light load conditions, the boost converter operates in discontinuous mode without affecting stability. Hence, the assumptions here cover the worst case for stability. 22 Submit Documentation Feedback Copyright (c) 2013, Texas Instruments Incorporated Product Folder Links: TPS43337-Q1 TPS43337-Q1 www.ti.com SLVSBC2A - AUGUST 2013 - REVISED SEPTEMBER 2013 Boost Maximum Input Current IIN_MAX The maximum input current is drawn at the minimum input voltage and maximum load. The efficiency for VBAT = 5 V at 2.3 A is 80%, based on the typical characteristics plot. PINmax = POUT 25 W = = 31.3 W Efficiency 0.8 (5) Hence, IINmax (at VBAT = 5 V) = 31.3 W = 6.3 A 5V (6) Boost Inductor Selection, L Allow input ripple current of 40% of IIN max at VBAT = 5 V L= VBAT t ON IINripple max = VBAT IINripple max 2 fSW = 5V 2.52 A 2 200 kHz = 4.9 mH (7) Choose a lower value of 3.9 H in order to ensure a high RHP-zero frequency while making a compromise that expects a high current ripple. This inductor selection also makes the boost converter operate in discontinuous conduction mode, where it is easier to compensate. The inductor saturation current must be higher than the peak inductor current and some percentage higher than the maximum current-limit value set by the external resistive sensing element. This rating should be determined at the minimum input voltage, maximum output current, and maximum core temperature for the application. Inductor Ripple Current, IRIPPLE Based on an Inductor value of 3.9 H, the ripple current is approximately 3.1 A. Peak Current in Low-Side FET, IPEAK I 3.1 A I PEAK = IINmax + RIPPLE = 6.3 A + = 7.85 A 2 2 (8) Based on this peak current value (see Equation 8), the external current-sense resistor RSENSE is calculated in . 0.2 V RSENSE = = 25 mW 7.85 A Select 20 m, allowing for tolerance. The filter component values RIFLT and CIFLT for current sense are 1.5 k and 1 nF, respectively, which allows for good noise immunity. Right Half-Plane Zero RHP Frequency, fRHP fRHP = VBAT min = 32 kHz 2p IIn max L (9) Submit Documentation Feedback Copyright (c) 2013, Texas Instruments Incorporated Product Folder Links: TPS43337-Q1 23 TPS43337-Q1 SLVSBC2A - AUGUST 2013 - REVISED SEPTEMBER 2013 www.ti.com Output Capacitor, CO To ensure stability, the output capacitor CO is chosen such that f LC f RHP 10 10 2p L COUTx VBAT min 2p I INmax L 2 2 ae 10 IINmax o ae 10 6.3 A o c / L = c / 3.9 mH 5V e o e VBAT min o COUTx COUTx min 635 mF (10) Select COUTx = 680 F. This capacitor is usually aluminum electrolytic with ESR in the tens-of-milliohms which is good for loop stability, because it provides a phase boost due to the ESR. The output filter components L and C create a double pole (180 degree phase-shift) at a frequency fLC, and the ESR of the output capacitor RESR creates a zero for the modulator at frequency fESR. These frequencies can be determined by Equation 11. f ESR = f ESR = f LC = 1 2p COUTx RESR Hz, 1 2p 680 mF 0.04 1 2p L COUTx assume RESR = 40 mW = 6 kHz 1 = = 3.1 kHz 2p 4 mH 680 mF (11) This satisfies fLC 0.1 fRHP. Bandwidth of Boost Converter, fC Use the following guidelines to set the frequency poles, zeroes, and crossover values for the trade-off between stability and transient response: fLC < fESR< fC< fRHP Zero fC < fRHP Zero / 3 fC < fSW / 6 fLC < fC / 3 24 Submit Documentation Feedback Copyright (c) 2013, Texas Instruments Incorporated Product Folder Links: TPS43337-Q1 TPS43337-Q1 www.ti.com SLVSBC2A - AUGUST 2013 - REVISED SEPTEMBER 2013 Output Ripple Voltage Due to Load Transients, VO Assume a bandwidth of fC = 10 kHz. DVOUTx = RESR DIOUTx + = 0.04 W 2.5 A + DIOUTx 4 COUTx f C 2.5 A 4 660 mF 10 kHz = 0.19 V (12) Because the boost converter is active only during brief events such as a cranking pulse, and the buck converters are high-voltage tolerant, a higher excursion on the boost output may be tolerable in some cases. In such cases, smaller component choices for the boost output may be used. Selection of Components for Type II Compensation The required loop gain for unity gain bandwidth (UGB) is shown in Equation 13. ae fC o ae fC - 20 log c / c f LC / c f ESR e o e G = 40 log c o // o ae 10 kHz o ae 10 kHz o / - 20 log c / = 15.9 dB 3.1kHz 6 kHz e o e o G = 40 log c (13) The boost converter error amplifier (OTA) has a Gm that is proportional to the VBAT voltage which allows a constant loop response across the input voltage range and makes it easier to compensate by removing the dependency on VBAT. R3 = C1 = C2 = 10G/20 = 7.2 kW 85 10 -6 A / V 2 VOUTx 10 2p fC R3 = 10 2p 10 kHz 7.2 kW C1 aef 2p R3 C1 c SW e 2 o / -1 o = = 22 nF 22 nF ae 200 kHz o 2p 7.2 kW 22nF c / -1 2 e o = 223 pF choose 220 pF (14) Input Capacitor, CIN The input ripple required is lower than 50 mV. IRIPPLE DVC1 = = 10 mV 8 fSW CIN CIN = IRIPPLE 8 fSW DVC1 = 194-F DVESR = IRIPPLE R ESR = 40 mV (15) Therefore, TI recommends 220 F with 10-m ESR. Submit Documentation Feedback Copyright (c) 2013, Texas Instruments Incorporated Product Folder Links: TPS43337-Q1 25 TPS43337-Q1 SLVSBC2A - AUGUST 2013 - REVISED SEPTEMBER 2013 www.ti.com Output Schottky Diode D1 Selection A Schottky diode with low forward-conducting voltage VF over temperature and fast switching characteristics is required to maximize efficiency. The reverse breakdown voltage should be higher than the maximum input voltage, and the component should have low reverse-leakage current. Additionally, the peak forward current should be higher than the peak inductor current. The power dissipation in the Schottky diode is given in Equation 16. PD = ID(PEAK ) VF (1 - D) D = 1- VINMIN 5V = 1= 0.53 VOUT + VF 10V + 0.6V PD = 7.85 A 0.6 V (1 - 0.53) = 2.2 W (16) Low-Side MOSFET (BOT_SW3) ae VI IPk o / (tr + t f ) f sw e 2 o ae V I o = (7.85 A)2 0.02 W (1 + 0.4) 0.53 + c I Pk / (20 ns + 20 ns) 200 kHz = 1.07 W e 2 o PBOOSTFET = (IPk )2 rDS(on) (1 + TC) D + c PBOOSTFET (17) The times tr and tf denote the rising and falling times of the switching node and are related to the gate-driver strength of the TPS43337-Q1 and gate Miller capacitance of the MOSFET. The first term denotes the conduction losses, which are minimized when the on-resistance of the MOSFET is low. The second term denotes the transition losses which arise due to the full application of the input voltage across the drain-source of the MOSFET as it turns on or off. They are higher at high output currents and low input voltages (due to the large input peak current) and when the switching time is low. NOTE: The on-resistance rDS(on) has a positive temperature coefficient, which produces the (TC = d x T) term that signifies the temperature dependence. (Temperature coefficient d is available as a normalized value from MOSFET data sheets and can be assumed to be 0.005 / C as a starting value.) BuckA Component Selection Minimum ON Time, tON min VO 3.4 V t ON min = = = 283 ns VIN max fSW 30 V 400 kHz (18) As shown in Equation 18, tON min is higher than the minimum duty cycle specified (100 ns, typical). Hence the minimum duty cycle is achievable at this frequency. Current-Sense Resistor RSENSE Based on the typical characteristics for VSENSE limit with VIN versus duty cycle, the sense limit is approximately 70 mV (at VIN = 12 V and duty cycle of 3.4 V / 12 V = 0.283). Allowing for tolerances and ripple currents, choose VSENSE maximum of 55 mV. 55 mV RSENSE = = 18 mW 3A Select 18 m. 26 Submit Documentation Feedback Copyright (c) 2013, Texas Instruments Incorporated Product Folder Links: TPS43337-Q1 TPS43337-Q1 www.ti.com SLVSBC2A - AUGUST 2013 - REVISED SEPTEMBER 2013 Inductor Selection L As explained in the description of the buck controllers (see Detailed Description), for optimal slope compensation and loop response, the inductor should be chosen such that: R SENSE 18 mW L = K FLR = 200 = 9.2 mH f SW 400 kHz * KFLR = Coil selection constant = 200 (19) Choose a standard value of 10 H. For the buck converter, the inductor saturation currents and core should be chosen to sustain the maximum currents. Inductor Ripple Current IRIPPLE At the nominal input voltage of 12 V, this gives a ripple current of 25% of IOUTmax 1 A. Output Capacitor CO Select an output capacitance CO of 100 F with low ESR in the range of 10 m. This gives VO(Ripple) 15 mV and V drop of 180 mV during a load step, which does not trigger the power-good comparator and is within the required limits. 2 DI OUTA 2 2.9 A COUTA = = 72.5 mF f SW DVOUTA 400 kHz 0.2 V (20) VOUTA(Ripple) = DVOUTA = I OUTA(Ripple) 8 f SW COUTA DI OUTA 4 f C COUTA + I OUTA(Ripple) ESR = + DI OUTA ESR = 1A + 1 A 10 mW = 13.1mV 8 400 kHz 100 mF 2.9 A + 2.9 A 10 mW = 174 mV 4 50 kHz 100 mF (21) (22) Bandwidth of Buck Converter fC Use the following guidelines to set frequency poles, zeroes, and crossover values for the trade-off between stability and transient response. * Crossover frequency fC between fSW / 6 and fSW / 10. Assume fC = 50 kHz. * Select the zero fz fC / 10 * Make the second pole fP2 fSW / 2 Submit Documentation Feedback Copyright (c) 2013, Texas Instruments Incorporated Product Folder Links: TPS43337-Q1 27 TPS43337-Q1 SLVSBC2A - AUGUST 2013 - REVISED SEPTEMBER 2013 www.ti.com Selection of Components for Type II Compensation VOUT FBx RESR RL GmBUCK COUT COMP VREF Type 2A R3 R0 C2 C1 Figure 26. Buck Compensation Components 2p fC VOUTA COUTA R3 = GmBUCK K CFB VREF = 2p 50 kHz 3.4 V 100 mF GmBUCK K CFB VREF = 19 kW Use standard value of R3 = 18 k where: * * * * * VO = 3.4 V CO = 100 F Gm = 1 mS VREF = 0.8 V KCFB = 0.125 / RSENSE = 6.9 (0.125 is an internal constant) (23) (24) Use standard value of 1.8 nF. C2 = C1 aef 2p R3 C1c SW e 2 o / -1 o = 1.8 nF ae 400 kHz o 2p 18 kW 1.8 nF c / -1 2 e o = 45 pF (25) Use standard value of 47 pF. The resulting bandwidth of buck converter fC fC = GmBUCK R3 K CFB VREF 2p COUTA VOUT fC = 1mS 18 kW 6.9 S 0.8 V = 46.5 kHz 2p 100 F 3.4 V (26) fC is close to the target bandwidth of 50 kHz. The resulting zero frequency fZ1 fZ1 = 1 1 = 2p R3 C1 = 4.9 kHz 2p 18 kW 1.8 nF (27) fZ1 is close to the fC / 10 guideline of 5 kHz The second pole frequency fP2 fP2 = 28 1 2p R3 C2 1 = 2p 18 kW 47 pF = 188 kHz Submit Documentation Feedback (28) Copyright (c) 2013, Texas Instruments Incorporated Product Folder Links: TPS43337-Q1 TPS43337-Q1 www.ti.com SLVSBC2A - AUGUST 2013 - REVISED SEPTEMBER 2013 fP2 is close to the fSW / 2 guideline of 200 kHz. Hence, all requirements for a good loop response are satisfied. BuckB Component Selection Using the same method as VBUCKA, the following parameters and components are realized in Equation 29. VOUTB 1.235 V t ON min = = = 103 ns VIN max fSW 30 V 400 kHz (29) This tONmin is on the edge of the minimum duty cycle specified (100 ns, typical); expect pulse-skipping at high VIN. 60 mV RSENSE = L = 200 = 30 mW 2A 30 mW 400 kHz = 15 mH choose 30 m, 15 H. * Iripple current 0.4 A (approx. 20% of IO max) Select an output capacitance CO of 100 F with low ESR in the range of 10 m. This gives VO (ripple) 7.5 mV and V drop of 120 mV during a load step. Assume fC = 50 kHz. 2 DI OUTB 2 1.9 A = = 46 mF COUTB fSW DVOUTB 400 kHz 0.12 V VOUTB(Ripple) = DVOUTB = R3 = = I OUTB(Ripple) 8 f SW COUTB DI OUTB 4 f C COUTB + I OUTB(Ripple) ESR = + DI OUTB ESR = (30) 0.4 A + 0.4 A 10 mW = 5.3 mV 8 400 kHz 100 mF 1.9 A + 1.9 A 10 mW = 114 mV 4 50 kHz 100 mF (31) (32) 2p fC VOUTB COUTB GmBUCK K CFB VREF 2p 50 kHz 1.235 V 100 mF 1mS 4.16S 0.8V = 11.7 kW (33) Use standard value of R3 = 12 k. 10 C1 = 2p R3 fC C2 = 10 = 2p 12 kW 50 kHz fC = fC = choose 2.7 nF (34) C1 ae fSW e 2 2p R3 C1 c = = 2.7 nF, o / -1 o 2.7 nF ae 400 kHz o 2p 12 kW 2.7 nF c / -1 2 e o GmBUCK R3 K CFB 2p COUTB = 68 pF, choose 68 pF (35) VREF VO 1mS 12 kW 4.16 0.8 2p 100 mF 1.235 V = 51.5 kHz (36) fC is close to the target bandwidth of 50 kHz. Submit Documentation Feedback Copyright (c) 2013, Texas Instruments Incorporated Product Folder Links: TPS43337-Q1 29 TPS43337-Q1 SLVSBC2A - AUGUST 2013 - REVISED SEPTEMBER 2013 www.ti.com The resulting zero frequency fZ1 fZ1 = 1 2p R3 C1 1 = = 4.9 kHz 2p 12 kW 2.7 nF fZ1 is close to the fC / 10 guideline of 5 kHz. The second pole frequency fP2 fP2 = 1 2p R3 C2 1 = 2p 12kW 68 pF = 195 kHz (37) fP2 is close to the fSW / 2 guideline of 200 kHz. Hence, all requirements for a good loop response are satisfied. BuckX High-Side and Low-Side N-Channel MOSFETs The gate-drive supply for these MOSFETs is supplied by an internal supply which is 5.8 V (typical) under normal operating conditions. The output is a totem pole, allowing full voltage drive of VREG to the gate with peak output current of 1.2 A. The high-side MOSFET is referenced to a floating node at the phase terminal (PHx) and the low-side MOSFET is referenced to the power ground (PGx) terminal. For a particular application, these MOSFETs should be selected with consideration for the following parameters: rds(on), gate charge Qg, drain-tosource breakdown voltage BVDSS, maximum dc current IDC(max), and thermal resistance for the package. The times tr and tf denote the rising and falling times of the switching node and are related to the gate-driver strength of the TPS43337-Q1 and gate Miller capacitance of the MOSFET. The first term denotes the conduction losses, which are minimized when the on-resistance of the MOSFET is low. The second term denotes the transition losses, which arise due to the full application of the input voltage across the drain-source of the MOSFET as it turns on or off. They are lower at low currents and when the switching time is low. ae V I o PBuckTOPFET = (IOUT )2 rDS(on) (1 + TC) D + c IN OUT / (tr + t f ) f SW 2 e o 2 PBuckLOWERFET = (IOUT ) rDS(on) (1 + TC) (1 - D) + VF IOUT (2 t d ) fSW (38) (39) In addition, during the dead time td when both the MOSFETs are off, the body diode of the low-side MOSFET conducts, increasing the losses which is denoted by the second term in the Equation 39. Using external Schottky diodes in parallel to the low-side MOSFETs of the buck converters helps to reduce this loss. Note that rDS(on) has a positive temperature coefficient which is accounted for in the TC term for rDS(on), TC = d x T[C]. The temperature coefficient, d, is available as a normalized value from MOSFET data sheets and can be assumed to be 0.005 / C as a starting value. 30 Submit Documentation Feedback Copyright (c) 2013, Texas Instruments Incorporated Product Folder Links: TPS43337-Q1 TPS43337-Q1 www.ti.com SLVSBC2A - AUGUST 2013 - REVISED SEPTEMBER 2013 Schematic The following section summarizes the previously calculated example and gives a schematic and component proposals. Table 4. Application Example PARAMETER Input voltage VBUCKA VBUCKB BOOST VIN = 6 to 30 V 12 V - typical VIN = 6 to 30 V 12 V - typical VBAT = 5 (cranking pulse input) to 30 V 3.396 V 1.235 V 10 V 3A 2A 2.5 A Output voltage, VOUTx Maximum output current, IOUTx Load-step output tolerance, VOUT + VOUT(Ripple) Current output load step, IOUTx Converter switching frequency, fSW 5 V to 30 V L1 VBAT 0.2 V 0.12 V 0.5 V 0.1 to 3 A 0.1 to 2 A 0.1 to 2.5 A 400 kHz 400 kHz 200 kHz D1 BOOST -- 10V, 25W 3.9 H 10F CIN 220 F 680 F COUT1 TOP-SW3 1k VIN VBAT EXTSUP DS BOT-SW3 1.5 k 0.025 1nF TOP-SW1 VBuckA -- 3.4 V, 10.2 W 0.018 DIV GC2 VREG CBA CBB GA1 GB1 0.1 F 0.1F L2 10 H 100F COUTA GC1 PHA PHB GA2 GB2 15 H PGNDB PGNDA SA1 SA2 FBA 1.8 nF 18 k COMPA SSA 5k 500 nF 22 nF 7.2 k TPS43337-Q1 SB1 SB2 FBB COMPB PGB ENA AGND COMPC ENC 68 pF 12 k 2.7 nF SSB PGA ENB 220 pF VBuckB -- 1.235 V, 2 W 100 F COUTB BOT-SW2 BOT-SW1 47 pF TOP-SW2 L3 0.03 500 nF 5k RT DLYAB 1 nF SYNC Figure 27. Schematic - Application Example Table 5. Application Example - Component Proposals Component Proposal Value L1 Name MSS1278T-392NL (Coilcraft) 3.9 H L2 MSS1278T-103ML (Coilcraft) 10 H L3 MSS1278T-153ML (Coilcraft) 15 H D1 SK103 (Micro Commercial Components) TOP_SW3 IRF7416 (International Rectifier) TOP_SW1, TOP_SW2 Si4840DY-T1-E3 (Vishay) BOT_SW1, BOT_SW2 Si4840DY-T1-E3 (Vishay) BOT_SW3 IRFR3504ZTRPBF (International Rectifier) COUT1 EEVFK1J681M (Panasonic) 680 F COUTA, COUTB ECASD91A107M010K00 (Murata) 100 F CIN EEVFK1J221Q (Panasonic) 220 F Submit Documentation Feedback Copyright (c) 2013, Texas Instruments Incorporated Product Folder Links: TPS43337-Q1 31 TPS43337-Q1 SLVSBC2A - AUGUST 2013 - REVISED SEPTEMBER 2013 www.ti.com Power Dissipation Derating Profile, 38-Pin HTTSOP Package With PowerPAD Package Figure 28. Power Dissipation Derating Profile Based on High-K JEDEC PCB PCB Layout Guidelines Grounding and PCB Circuit Layout Considerations Boost Converter 1. The path formed from the input capacitor to the inductor and BOT_SW3 with the low-side current-sense resistor should have short leads and PC trace lengths. The same applies for the trace from the inductor to the Schottky diode D1 to the COUT1 capacitors. The negative terminal of the input capacitor and the negative terminal of the sense resistor must be connected together with short trace lengths. 2. The overcurrent-sensing shunt resistor may require noise filtering, and this capacitor should be close to the IC pin. Buck Converter 1. Connect the drains of TOP_SW1 and TOP_SW2 together with the positive terminal of input capacitor COUT1. The trace length between these terminals should be short. 2. Connect a local decoupling capacitor between the drain of TOP_SWx and the source of BOT_SWx. 3. The Kelvin-current sensing traces for the shunt resistor should have minimum trace spacing and be routed parallel to each other. Any filtering capacitors for noise should be placed near the IC pins. 4. Connect the positive terminal of the respective output capacitor COUTA or COUTB to the respective feedback input FBA or FBB. Do not connect these traces near any switching nodes or high-current traces. Other Considerations 1. PGNDx and AGND should be shorted to the thermal pad. Use a star-ground configuration if connecting to a non-ground-plane system. Use tie-ins for the EXTSUP capacitor, compensation-network ground, and voltage-sense-feedback ground networks to this star ground. 2. Connect a compensation network between the compensation pins and IC signal ground. Connect the oscillator resistor (frequency setting) between the RT pin and IC signal ground. These sensitive circuits should not be located near nodes showing high dv/dt; these include the gate-drive outputs, phase pins, and boost circuits (bootstrap). 3. Reduce the surface area of the high-current-carrying loops to a minimum, by ensuring optimal component placement. Ensure the bypass capacitors are located as close as possible to their respective power and ground pins. 32 Submit Documentation Feedback Copyright (c) 2013, Texas Instruments Incorporated Product Folder Links: TPS43337-Q1 TPS43337-Q1 www.ti.com SLVSBC2A - AUGUST 2013 - REVISED SEPTEMBER 2013 PCB Layout POW ER IN PUT Powe r L ines Connec tion to GND P lane o fPCB th rough v ias Connec tion to top /bo ttom o fPCB th rough v ias Vo ltage Ra ilO u tpu ts V BOOST VBAT V IN EXTSUP GC1 D IV GC2 VREG CBA CBB GA1 GB1 PHA PHB GA2 GB2 PGNDA PGNDB SA1 SB1 SA2 SB2 FBA FBB COMPA COMPB SSA SSB PGA PGB ENA AGND ENB RT COMPC ENC M ic rocon tro lle r VBUCKB VBUCKA DS DLYAB Exposed Pad connec ted to GND P lane SYNC Submit Documentation Feedback Copyright (c) 2013, Texas Instruments Incorporated Product Folder Links: TPS43337-Q1 33 TPS43337-Q1 SLVSBC2A - AUGUST 2013 - REVISED SEPTEMBER 2013 www.ti.com REVISION HISTORY Changes from Original (August 2013) to Revision A * 34 Page Changed document status from Product Preview to Production Data ................................................................................. 1 Submit Documentation Feedback Copyright (c) 2013, Texas Instruments Incorporated Product Folder Links: TPS43337-Q1 PACKAGE OPTION ADDENDUM www.ti.com 10-Sep-2013 PACKAGING INFORMATION Orderable Device Status (1) TPS43337QDAPRQ1 ACTIVE Package Type Package Pins Package Drawing Qty HTSSOP DAP 38 2000 Eco Plan Lead/Ball Finish (2) Green (RoHS & no Sb/Br) MSL Peak Temp Op Temp (C) Device Marking (3) CU NIPDAU Level-3-260C-168 HR (4/5) -40 to 125 TPS43337 (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. TBD: The Pb-Free/Green conversion plan has not been defined. Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. 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Addendum-Page 1 Samples PACKAGE MATERIALS INFORMATION www.ti.com 14-Dec-2017 TAPE AND REEL INFORMATION *All dimensions are nominal Device TPS43337QDAPRQ1 Package Package Pins Type Drawing SPQ HTSSOP 2000 DAP 38 Reel Reel A0 Diameter Width (mm) (mm) W1 (mm) 330.0 24.4 Pack Materials-Page 1 8.6 B0 (mm) K0 (mm) P1 (mm) W Pin1 (mm) Quadrant 13.0 1.8 12.0 24.0 Q1 PACKAGE MATERIALS INFORMATION www.ti.com 14-Dec-2017 *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) TPS43337QDAPRQ1 HTSSOP DAP 38 2000 367.0 367.0 45.0 Pack Materials-Page 2 IMPORTANT NOTICE Texas Instruments Incorporated (TI) reserves the right to make corrections, enhancements, improvements and other changes to its semiconductor products and services per JESD46, latest issue, and to discontinue any product or service per JESD48, latest issue. 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