3342-55 - PEREGRINE SEMICONDUCTOR

Page 1 of 17

Peregrine’s PE3342 is a high performance integer-N PLL with

embedded EEPROM capable of frequency synthesis up to

2700 MHz with a speed-grade option to 3000 MHz. The

EEPROM allows designers to permanently store control bits,

allowing easy configuration of self-starting synthesizers. The

superior phase noise performance of the PE3342 is ideal for

applications such as wireless base stations, fixed wireless, and

RF instrumentation systems.

The PE3342 features a ÷10/11 dual modulus prescaler,

counters, and a phase comparator as shown in Figure 1.

Counter values are programmable through a three-wire serial

interface.

The PE3342 UltraCMOS™ Phase Locked-Loop is

manufactured in Peregrine’s patented Ultra Thin Silicon

(UTSi®) CMOS process, offering excellent RF performance

with the economy and integration of conventional CMOS.

Pro duct Specificat ion

2.7 GHz Integer-N PLL

with Field-Programmable EEPROM

Product Description

Figure 1. Block Diagram

PE3342

Features

• Field-programmable EEPROM for self-

star ting appl ic ati o ns

• Standard 2700 MHz operation,

3000 MHz speed-grade option

• ÷10/ 11 dua l modulus pres caler

• Int er nal phas e det ec t or

• Seri al pr ogramm able

• Low power — 20 mA at 3 V

• Ultra-low phase noise

• Available in 20-lead 4x4 mm QFN

package

Enhancement

(8-bit)

Prescaler

÷10/11

M Counter

÷2 to ÷512

Serial

Interface

Mux

R Counter

÷1 to ÷64

Phase

Detector

S_WR

PD_U

PD_D

EELoad

EESel

FSel

Clock

Data

20 LD

Cext

Primary

(20-bit)

Transfer

Logic

EEPROM

ENH

E_WR

Secondary

(20-bit)

Not for new design

Product Specification

PE3342

Page 2 of 17

Table 2 . Pin Descriptions

Figure 2. Pin Configuration (Top View) Figure 3. Package Type

20-lead QFN

Pin No. Pin Name Type Description

1 S_WR Input Secondary Register WRITE input. Primary Register contents are copied to the Secondary Register on

S_WR rising e dg e. Also us e d to co ntrol S er ial Por t op er a ti on and EEP RO M program m in g.

2 Data Input Binary serial data input. Input data entered LSB (B0) first.

3 Clock Input Serial clock input. Data is clocked serially into the 20-bit Primary Register, the 20-bit EE Register, or

the 8-bit Enhancement Register on the rising edge of Clock. Also used to clock EE Register data out

Dout port.

4 FSel Input Frequency Register selection control line. Internal 70 kW pull-down resistor.

5 E_WR Input Enhancement Register write enable. Also functions as a Serial Port control line. Internal 70 kW pull-

down resistor.

6 VPP Input EEPROM erase/write programming voltage supply pin. Requires a 100pF bypass capacitor connected

to GND.

7 VDD (Note 1) Power supply input. Input may range from 2.85 V to 3.15 V. Bypassing required.

8 Fin Input Prescaler input from the VCO.

9 Fin Input

Prescaler complementary input. A series 50 W resistor and DC blocking capacitor should be placed as

close as possible to this pin and connected to the ground plane.

10 CEXT Output

Logical “NAND” of PD_U and PD_D terminated through an on-chip, 2 kW series resistor. Connecting

CEXT to an external capacitor will low pass filter the input to the inverting amplifier used for driving LD.

11 EELoad Input Control line for Serial Data Port, Frequency Register selection, EE Register parallel loading, and

EEPROM programming. Internal 70 kW pull-down resistor.

12 LD Output, OD

Lock detect output, an open-drain logical inversion of CEXT. When the loop is in lock, LD is high

impedance; otherwise, LD is a logic LOW.

13 Dout Output Data out function. Dout is defined with the Enhancement Register and enabled with ENH.

14 VDD (Note 1) Same as pin 7.

19 VDD (Note 1) Same as pin 7.

20 ENH Input Enhancement mode control line. When asserted LOW, enhancement register bits are functional.

Int ern al 70 kW pu ll-up r es is t or .

15 PD_D Output Phase detector output. PD_D pulses negatively when fp leads fc.

16 PD_U Output Phase detector output. PD_U pulses negatively when fc leads fp.

17 EESel Input Control line for Frequency Register selection, EE Register parallel loading, and EEPROM

programming. Internal 70 kW pull-up resistor.

18 fr Input Reference frequency input.

EXT

20-lead QFN

4x4mm

Exposed Solder Pad

(Bottom Side)

S_WR

Data

Clock

FSel

E_WR EELoad

Dout

PD_D

PD_U

EESel

ENH

Notes 1: VDD pins 7, 14 and 19 are connected by diodes and must be supplied with the same positive voltage level.

2: Ground connections are made through the exposed solder pad. The solder pad must be soldered to the ground plane for proper operation.

Not for new design

Product Specification

PE3342

Page 3 of 17

Table 4. Operating Ranges

Table 3. Absolute Maximum Ratings

Symbol Parameter/Conditions Min Max Units

VDD Supply voltage –0.3 +4.0 V

VI Voltage on any digital

input –0.3 VDD+0.3 V

TStg Storage temperature

range –65 +85 °C

Symbol Parameter/Conditions Min Max Units

VDD Supply voltage 2.85 3.15 V

TA Operating ambient

temperature range -40 85 °C

Symbol Parameter/Conditions Min Max Units

VESD ESD volt age human bod y

model (Note 1) 1000 V

VESD

(VPP) ESD volt age human bod y

model (Note 1) 200 V

Note 1: Periodically sampled, not 100% tested. Tested per MIL-

STD-883, M3015 C2

Table 5 . ESD Rati ngs

Electrostatic Discharge (ESD) Precautions

When hand ling this UltraCMOS ™ device, obs erve

the same precautions that you would use with

o ther ES D-sens itive devi ces. Althou gh this device

contains circuitry to protect it from damage due to

ESD, precautions should be taken to avoid

exceeding the specified rating in Table 4.

Latc h-Up Avoidance

Unlike conventional CMOS devices, UltraCMOS™

devices are immune to latch-up.

Exceeding absolute maximum ratings may cause

permanent damage. Operation should be

restricted to the limits in the Operating Ranges

tabl e. Oper ation betw e en op er a ti ng ran ge

max imum and abs olute max i mum for extended

periods may redu ce reliability.

Not for new design

Product Specification

PE3342

Page 4 of 17

Table 6. DC Characteristics

VDD = 3.0 V, - 40° C < TA < 85° C, unless otherwise specif ied

Symbol Parameter Conditions Min Typ Max Units

IDD Operationa l supply current;

Pres c al er en ab le d VDD = 2.8 5 to 3. 15 V 20 30 mA

Digital Inputs: S_WR, Data, Clock

VIH High-level input voltage VDD = 2.8 5 to 3.15 V 0.7 x VDD V

VIL Low-level input voltage VDD = 2.85 to 3.15 V 0.3 x VDD V

IIH High-level input current VIH = VDD = 3.15 V +1 µA

IIL Low-level input current VIL = 0, VDD = 3.15 V -1 µA

Digital inputs: ENH, EESel (contains a 70 kΩ pull-up resistor)

VIH High-level input voltage VDD = 2.8 5 to 3.15 V 0.7 x VDD V

VIL Low-level input voltage VDD = 2.85 to 3.15 V 0.3 x VDD V

IIH High-level input current VIH = VDD = 3.15 V +1 µA

IIL Low-level input current VIL = 0, VDD = 3.15 V -100 µA

Digital inputs: FSel, EELoad, E_WR (contains a 70 kΩ pull-down resistor)

VIH High-level input voltage VDD = 2.8 5 to 3.15 V 0.7 x VDD V

VIL Low-level input voltage VDD = 2.85 to 3.15 V 0.3 x VDD V

IIH High-level input current VIH = VDD = 3.15 V +100 µA

IIL Low-level input current VIL = 0, VDD = 3.15 V -1 µA

EE Memo ry Programming Voltage and Cu rrent: VPP, IPP

VPP_WRITE EEPROM write voltage 12.5 V

VPP_ERASE EEPROM erase voltage -8.5 V

IPP_WRITE EEPROM write cycle current 30 mA

IPP_ERASE EEPROM erase cycle cu rrent -10 mA

Reference Divider input: fr

IIHR High-level input current VIH = VDD = 3.15 V +100 µA

IILR Low-level input current VIL = 0, VDD = 3.15 V -100 µA

Counter output: Do ut

VOLD Output voltage LOW Iout = 6 mA 0.4 V

VOHD Output voltage HIGH Iout = -3 mA VDD - 0.4 V

Lock detect outputs: (C EXT, LD)

VOLC Outp ut v olt ag e LO W, CEXT I

out = 0.1 mA 0.4 V

VOHC Output voltage HIGH, CEXT I

out = -0.1 mA VDD - 0.4 V

VOLLD Outp ut v olt ag e LO W, LD Iout = 1 mA 0.4 V

Not for new design

Product Specification

PE3342

Page 5 of 17

Table 7. AC Characteristics

VDD = 3.0 V, - 40° C < TA < 85° C, unless otherwise specif ied

Symbol Parameter Conditions Min Max Units

Control Interface and Registers (see Figure 4)

fClk Serial data clock frequency (Note 1) 10 MHz

tClkH Serial clock HIGH time 30 ns

tClkL Serial clock LOW time 30 ns

tDSU Data set-up time to Clock rising edge 10 ns

tDHLD Data hold time after Clock rising edge 10 ns

tPW S_WR pulse width 30 ns

tCWR Clock rising edge to S_WR rising edge 30 ns

tCE Clock falling edge to E_WR transition 30 ns

tWRC S_W R f alling edge to Clock rising edge 30 ns

tEC E_WR transition to Clock rising edge 30 ns

EEPROM Erase/Write Programming (see Figures 5 & 6)

tEESU EELoad rising edge to VPP rising edge 500 ns

tEEPW VPP pu ls e width 25 30 ms

tVPP VPP pulse rise and fall times (Note 2) 1 µs

Main D iv i der (I nc l u din g P res c aler)

FIn Operating frequency 300 2700 MHz

FIn Operating frequency Speed-grade option (Note 3) 300 3000 MHz

PFIn Input level range External AC coupling -5 5 dBm

Main Divider (Prescaler Bypassed)

FIn Operating frequency (Note 4) 50 270 MHz

PFIn Input level range External AC coupling (Note 4) -5 5 dBm

Reference Divider

fr Operating frequency (Note 5) 100 MHz

Pfr Refe rence input po wer (Note 4) Single ended inpu t -2 dBm

Phase Detector

fc Comparison frequency (Note 6) 20 MHz

SSB Phase Noise (Fin = 1. 3 GH z , fr = 1 0 MHz , fc = 1.25 MHz, LBW = 70 kHz, VDD = 3.0 V, Temp = -40° C)

100 Hz Offset -75 dBc/Hz

1 kHz Offset -85 dBc/Hz

Note 1: fClk is verified during the functional pattern test. Serial programming sections of the functional pattern are clocked at 10 MHz to verify fClk

specification.

Note 2: Rise and fall times of the VPP programmi ng voltage pulse must be grea ter than 1 µs.

Note 3: The maximum frequency of operation can be extended to 3.0 GHz by ordering a special speed-grade option. Please refer to Table 14,

Ordering Information, for ordering details.

Note 4: CMOS logic levels can be used to drive FIn input if DC coupled and used in Prescaler Bypass mode. Voltage input needs to be a minimum

of 0.5 Vp-p. For optimum phase noise performance, the reference input falling edge rate should be faster than 80 mV/ns. No minimum

frequency limit exists when operated in this mode.

Note 5: CMOS logic levels can be used to drive reference input if DC coupled. Voltage input needs to be a minimum of 0.5 Vp-p. For optimum

phase noise performance, the reference input falling edge rate should be faster than 80 mV/ns.

Note 6: Parameter is guaranteed through characterization only and is not tested.

Not for new design

Product Specification

PE3342

Page 6 of 17

Functional Description

The PE 33 42 c o ns is ts of a du al mo dul us pr es caler,

three programmable counters, a phase detector

and control logic with EEPROM memory (see

Figure 1).

The dual modulus prescaler divides the VCO

frequency by either 10 or 11, depending on the

state of the internal modulus se lect logic. The R

and M counters divide the reference and prescaler

outputs by integer values stored in one of three

selectable registers. The modulus select logic

uses th e 4- bi t A coun ter .

The ph as e- freque nc y detect or gen er ates up and

down frequency control signals and are also used

to enable a lock detect circuit.

Frequency control data is loaded into the device

via the Serial Data Port, and can be placed in

three separate frequency registers. One of these

registers (EE register) is used to load from and

write to the non-volatile 20-bit EEPROM.

Various operational and test modes are available

through the enhancement register, which is only

accessible through th e Serial Data Port (it cannot

be loaded from the EEPROM).

Main Counter Chain

The main counter chain divides the RF input

frequency, Fin, by an integer derived from the

user-defined values in the M and A counters. It

operates in two modes:

High Frequency Mode

Setting PB (prescaler bypass) LOW enables the

÷10 /1 1 pr esc aler, pr ovi di n g op er ation to 2. 7 GHz .

In this mode, the output from the main counter

chain, fp, is related to the VCO frequency, Fin, by

the following equation:

fp = Fin / [10 x (M + 1) + A] (1)

wh ere 0

≤

15 and A

≤

M + 1; 1

≤

511

When the loop is locked, Fin is related to the

reference freque nc y, fr, by the following equation:

Fin = [10 x (M + 1) + A] x (fr / (R+1)) (2)

wh ere 0

≤

15 and A

≤

M + 1; 1

≤

511

A consequence of the uppe r lim it on A is th at F in

must be greater th an or equ al to 90 x (fr / (R+1)) t o

obtain contiguous channels. Programming the M

counter with the min imum value of 1 will result in a

minimum M counter divide ratio of 2.

Programming the M and A counters with their

maximum values provides a divide ratio of 5135.

Prescaler Bypass Mode

Setti ng the PB bi t of a fr eq ue ncy re gis ter HIGH

allo ws F in to bypass the ÷10/11 prescaler. In this

mode , t he pr escaler and A co un ter ar e powered

down, and the input VCO frequency is divided by

the M counter directly. The following equation

relate s Fin to the reference freq uency fr:

Fin = (M + 1) x (fr / (R+1)) (3)

wh ere 1 ≤ M ≤ 511

Refe rence Counter

The reference counter chain divides the reference

freq ue nc y, fr, do wn to the phase detector

compar i son freq ue nc y, fc.

The output frequency of the 6-bit R Co unter is

related to the reference frequency by the following

equation:

fc = fr / (R + 1) (4)

where 0

≤

Not e that programming R with 0 will pass the

reference freque nc y, fr, directly to the phase

detector.

Phase Detector

The phase detector is triggered by rising edge s

from the main counter (fp) and the reference

co unte r (fc). It has two outputs, PD_U, and PD_D.

If the divided VCO leads the divided reference in

phase or frequency (fp leads fc), PD_D p ul ses

LOW. If the divided reference leads the divided

VCO in phase or frequency (fc leads fp), PD_U

pulses LOW. The width of either pulse is directly

prop or ti o nal to th e phas e offset betw e en th e fp an d

fc signals.

Not for new design

Product Specification

PE3342

Page 7 of 17

Lock Detect Output

A lock detect signal is provided at pin LD, via the

pin CEXT (see Figure 1). CEXT is the logical “NAND”

of PD_U and PD_D wav ef or m s , driven thro ug h a

series 2k ohm resistor. When the loop is locked,

th is ou tput will be HIGH with narrow pulses LOW.

Connecting CEXT to an exte rnal shunt capacitor

prov id es integration of this si gn al .

The CEXT signal is sent to the LD pin through an

internal inve rting comparator with an open drain

output. Thus LD is an “AND” function of PD_U

and PD_D.

Serial Data Port

The Serial Data Port allows control data to be

entered into the device. This data can be directed

into on e of thr e e re gi sters: t he En ha ncemen t

Table 7 defines the control line settings re quired

to select one of these destinations.

Input data pres ented on pi n 5 (Dat a) is cl oc ke d

serially into the designated register on the rising

edge of Clock. Data is always loaded LSB (B0)

first into the receiving register. Figure 4 defines

the timing requirements for this process .

Table 8. Serial Interface

S_WR E_WR EELoad Register Loaded

0 0 0 Primary Register

0 1 0 Enhancement Register

0 X 1 EE Register

Figure 4. Se rial Interface Timing Diagram

DHLD

DSU

ClkH

ClkL

CWR

WRC

E_WR

EELoad

Data

Clock

S_WR

Not for new design

Product Specification

PE3342

Page 8 of 17

Frequency Registers

There are three independent frequency registers,

any one of which can be selected to control the

operation of the device. Each register is 20 bits in

length, and provides data to the three counters

and t he pr escaler byp as s c on tr ol . Ta ble 8 defines

thes e bi t ass ignmen ts.

Primary Register

The Primary Register is a serial shift register,

loaded through the Serial Data Port. It can be

selected to control the PLL as shown in Table 9.

It is not buffered, thus when this register is

selected to control the PLL, its data is

continuously presented to the counters during a

load operation.

This register is also used to perform a parallel

load of da ta into the Secondary Register.

Secondary Register

The Secondary Register is a parallel-load register.

Data is copied into this register from the Primary

the timing diagrams shown in Figure 4. It ca n be

selected to control the PLL as shown in Table 9.

EE Register

The EE Register is a serial/parallel-in, serial/

parallel-out register, and provides the interface to

the EEPROM. It is loaded from the Serial Da ta

Port to provide the parallel data source when

writing to the EEPROM. It also accepts stored

data from the EEPROM for cont rolling the PLL.

Serial loading of the EE Register is done as

shown in Table 7 and Figure 4. Parallel loading of

the register from EEPROM is accomplished as

shown in Table 10.

The EE register can be selected to control the PLL

as shown in Table 9. Note that it cannot be

selected to control the PLL using data that has

been loaded serially. Th is is because it must first

go through one of the two conditions in Table 10

that causes the EEPROM data to be copied into

the EE Register. The effect of this is that only

EEPROM data is used when the EE Register is

selected.

The contents of the EE register can also be

shifte d out seri al ly through th e Do ut pin. This

mode is enabled by appropriately programming

the Enhancement Register. In this mode, data

exits the register on the rising edge of Clock, LSB

(B0) first, and is replaced with the data present on

the Data input pin. Tables 7 and 12 define the

set tings required to enable th is mode.

Table 9. Primary / Secondary / EE Register Bit Assignments

R5 R4 M8 M7 PB M6 M5 M4 M3 M2 M1 M0 R3 R2 R1 R0 A3 A2 A1 A0

B0 B1 B2 B3 B4 B5 B6 B7 B8 B9 B10 B11 B12 B13 B14 B15 B16 B17 B18 B19

Table 10. Frequency Register Selection

EESel FSel EELoad Register Selected

0 1 0 Primary Register

0 0 0 Secondary Register

1 X 0 EE Register

Table 11. EE Register Load from EEPRO M

EESel EELoad Function

_ ⁄¯ 0 EEPROM → EE Register

1 ¯\_ EEPROM → EE Register

Not for new design

Product Specification

PE3342

Page 9 of 17

Enhancement Register

The Enhancement Register is a buffered serial

shift register, loaded from the Serial Data Port. It

activates special test and operating modes in the

PLL. Th e bit assignments for these modes are

shown in Table 11.

The fu ncti o ns of the se Enhancemen t Regi st er bits

are shown in Table 12. A function becomes active

when its corresponding bit is set HIGH. Note that

bits 1, 2, 5, and 6 direct various data to the Dout

pin, an d for v ali d op er ati o n no m or e th an on e

should be set HIGH simultaneously .

The Enhancement Register is buffered to prevent

inadvertent control changes during serial loading.

Data that has been loaded into the register is cap-

tured in the buffer and made available to the PLL

on the falling edge of E_WR.

A separate control line is provided to enable and

disable the Enhancement mode. Functions are

enabled by taking the ENH control line LOW.

Note: The enhancement register bit values are

unknown during power up. To avoid enabling the

enhancement mode during power up, set the Enh

pin high (“1”) until the enhancement register bit

values are programmed to a known state.

Table 12. Enhanceme nt Register Bit Assignments

Reserved EE Reg ister

Output fp output Power

down Counter

load MSEL

output fc output Reserved

B0 B

1 B

2 B

3 B

4 B

5 B

6 B

Table 13. Enhancement Regis ter Functions

Bit Functi on Description

Bit 0 Res er v e d P rogra m to 0

Bit 1 EE Register Output Allows the contents of the EE Register to be serially shifted out Dout, LSB (B0) firs t.

Data is shifted on rising edge of Clock.

Bit 2 fp outp ut Provides the M counter output at Dout.

Bit 3 Pow er dow n P ower s do w n al l func t ions exc e pt pr o gram mi ng interf ac e .

Bit 4 Counter load Immedia te and continuous load of co unter programming.

Bit 5 MS E L outpu t Provid es the internal du al m od ulus pr es c al er modu lus se lec t (M SE L) at D out .

Bit 6 fc output Provides the R counter output at Dout.

Bit 7 Res er v e d P rogra m to 0

Not for new design

Product Specification

PE3342

Page 10 of 17

EEPROM Programming

Frequency control data that is present in the EE

EEPROM. All 20 bits are written simultaneously

in a parallel operation. The EEPROM is

guaranteed for at least 100 erase/ write cycles.

Erase Cycle

The EE PR OM sho ul d be taken thr ou gh a n er ase

cycle before writing data, since the write operation

performs a logical AND of th e EEPROM’s current

contents with the data in the EE Register. Erasing

the EEPR OM is accompl i sh ed by holdin g the

S_WR , EES el , an d EEL o ad i np uts HIGH , th en

appl y ing one ER A SE pr ogramm i ng voltage pul s e

to the VPP input (see Table 13). The voltage

source for this operation must be capable of

supplying the EEPROM era se cycle current

(IPP_ERASE, Table 5). The timing diagram is

shown in Figure 5.

Write Cycle

Using the Serial Data Port, the EE Register is first

loaded with the desired data. The EEPROM is

then pr ogramm ed wi th thi s da ta by taki n g the

S_WR input HIGH and EESel input LOW, then

applying one WRITE programming voltage pulse

to the VPP input. The voltage source for this

oper ati o n m us t be capabl e of sup pl y ing t he

EEPROM write cycle curre n t (IPP_WRITE, Table

5). T he ti m ing di a gr am of thi s operation is s h ow n

in Figure 6. Programming is comple ted by taking

the EELoad input LOW.

Note that it is possible to erroneously overwrite

the EE Register with the EEPROM contents

bef or e th e wri te c yc l e be gi ns by un ne eded

manipulation of the EELoad bit (see Table 10 ).

Table 13. EEPROM Programming

Figure 5. EEPROM Erase Timing Diagram

S_WR EESel EELoad VPP Function

1 1 1 25 ms @ −8.5V Erase cycle

1 0 1 25 ms @ +12 . 5V Wri te cycle

Figure 6. EEPROM Write Ti ming Diagram

EEPW

EELoad

S_WR

EESel

_ERASE

EESU

VPP

EEPW

S_WR

_WRITE

EESel

EESU

12.5V

EELoad

VPP

Not for new design

Product Specification

PE3342

Page 11 of 17

Gross EEPRO M Programming Timing Grid

Figure 7 shows a gross PE3342 EEPROM

programm i ng ti mi ng gr i d al th ou gh eac h individu al

step has been described thoroughly in previous

sections. It starts with EE Register load, and then

together with ot her parame ters a Vpp_ERASE

negati ve pulse is appl ied to Vp p pin to er ase t he

EEPROM contents and followed by a Vpp_WRITE

pulse for EEPROM write cycle. The separatio n

between the Vpp_ERASE and Vpp_WRITE pulse

has to be at least 100 ms if mechanical relays are

u sed to avoid bo th being on at the same ti me.

After EE programming, the contents of the

EEPROM cells can be verified by se tting

Enhancement Register Bit 1. A procedure shown

in Figure 8 is applied twice. The first time is to

load the EE Register from EEPROM and the

second time is to shift out the EE Register

contents through Dout pin.

Figure 7. Gross PE3342 EEPROM Programming Timing Grid

Data

S_WR

Vpp_ERASE

Vpp_WRITE

12.5V

-8.5V

25 ms

EE Register

load

EE PROM

Erase

EE PROM

Write

40 ms

E_WR

EELoad

EESel

Clock

Dout

>=100 ms

Rough time scale

The final set

of Dout is

EEPROM

content

Note: ENH/ (Pin 20) is at low (0) for this process.

EE Register

shifted out

through Dout

EE Programming

EE verify

CHANNEL

CODE

ENH code set's

Dout mux to EE

EE Register

load from

EEPROM

Not for new design

Product Specification

PE3342

Page 12 of 17

Figure 8. Details of EE register contents l oaded from EEPROM and then shifte d out Serially through

Dout pin - The procedure is performed twice.

In Figur e 8, th e first ste p is to pr o gram

Enhancement Register to set Bit 1 high (“1”) to

access EE Register Output Bit Function.

Subsequent action, which includes 19 Clock

pulses, allows the existing EE Register contents to

be shifted out the Dout pin and the EEPROM

contents are loaded to the EE Register. Since the

initial data existing in the EE Register could be

anything, the data must be flushed out before

clocking the contents of the EEPROM register out.

After the same procedure is duplicated, the Dout

output is th e EEPROM contents. Note that only

1 9 Clock pu lses are enough for th e 20-bit EE

present at Dout pin. Also ENH/ (Pin 3 in TSSOP

or Pin 20 in QFN) is set to low (“0”) to access the

Enhancement mo de.

Data

S_WR

Enhancement

Programming

E_WR

EELoad

EESel

Clock

Dout

(example)

EE Register

load from

EEPROM

EE Register

shifted out

through Dout

Rough time scale

0 1 0 1 0 0 1 1 1 1 1 0 0 0 1 1 1 0 0 1

20 us

Note: ENH/ (Pin 20) is at low (0) for this process.

Not for new design

Product Specification

PE3342

Page 13 of 17

Evaluation and Programming Kit Support

To provide easy evaluation of the PE3342 and to

also enable programming of small evaluation

quanti ties, Peregri n e has dev el o ped c om plete

evalua tion kits and prog ramming kits for the

PE3342 EEPR OM PLLs.

Evaluation Kits

The evaluation kits consist of an evaluation board

and support software enabling the user to

evaluate the full functionality of the part. The

EEPROM can be loaded with user specified

values and t hen placed in a self start - up mode.

Please refer to Table 14, Ordering Information, for

the specific order codes.

Programming Kits

The progra mming kits consist of a programming

board and support software that enables the user

to program smal l qu anti ties of devi ces f or

prototype evaluation and for small pre-production

runs. Please refer to Table 14, Ordering

Information , for the specific order codes

Larg e pr od uc tion quan ti ti es c a n be spec ial

programmed at Peregrine for an additional

charge. Please contact Peregrine Sales for pricing

and leadtime at sales@psemi.com.

Application Information

The PE 33 42 has b ee n design ed to allow a sel f-

starting PLL synthesizer to be built, removing the

need to have a micr o- controller or oth er

programming source load data into the device on

power - u p. It can be us e d as a rem o tely

controllable PLL as well, since the EEPROM

circuitry has been added to a complete PLL core

(PE3339).

The PE 33 42’ s EE PR OM can be pr ogr am m e d i n-

circuit, or prior to assembly using a socketed

fixture. It can be reprogrammed a minimum of

100 times, but is not designed to support constant

reprogramming of the EEPROM by an

application .

Self-Starting Mode

In self-starting applications, the EE Register is

used to control the device and must be selected

per Table 9. Additionally, the contents of the

EEPROM must be copied to the EE Register per

Table 10, and device power must be stable for this

transfer to be reliably accomplished. These

requirements can be met by connecting a

capacitor of 50pF-10uF (evaluation design uses

3.3uF) from the EESel pin to ground. The delay of

the rising edge on EESel, created by the RC time

constant of its 70k ohm internal pull-up resistor

and the external capacitor, will allow device power

to stab ilize first, ensuring proper data transfer.

This edge is adaptable by capacitor value

selection. The Vcc applied to the IC must be

settle d fir st.

Not for new design

Product Specification

PE3342

Page 14 of 17

20-lead QFN

Figure 10. Pa ckage Drawing

1.00

2.00

0.23

0.10 C A B

EXP OSED PAD

4.00

DETAIL A

115

0.50

2.00

0.55

DETAIL A

0.18

0.435

SEAT IN G

PL AN E

0.08 C

0.10 C

0.020

0.20 REF

EXPOSED PAD &

TERMINAL PADS

0.90

- C -

2.00 X 2.00

2.00

4.00

- B -

- A -

IN DE X A REA

0.25 C

2. C OPLANARITY APP LIES T O T HE EXPOS ED HE AT SIN K SLUG AS WELL

1. DIMENSION APPLIES TO METALL IZED TER MINAL AND IS MEASURED

AS THE TERMINALS.

BETWEEN 0 .25 AND 0.30 FROM TERMINA L TIP.

Not for new design

Product Specification

PE3342

Page 15 of 17

Table 15. Ordering Information

Or der Code Part Marking Description Package Shipping Method

3342-53 PE3342 PE3342G-20QFN4x4-92A Green 20-lead QFN Tape or loose

3342-54 PE3342 PE3342G-20QFN4x4-3000C Green 20-lead QFN 3000 units / T&R

3342-55 PE3342 PE3342-20QFN4x4-92A (3GHz grade) Green 20-lead QFN Tape or loose

3342-56 PE3342 PE3342-20QFN4x4-3000C (3GHz grade) Green 20-lead QFN 3000 units / T&R

3342-05 PE3342-EK PE3342-20QFN4x4-EK Evaluation Kit 1 / Box

3342-07 PE3342-PK PE3342-20QFN4x4-PK Progr a mming Kit 1 / Box

Figure 12. Tape and Re el Drawing

Figure 11. Marking Specifi cations

3342

YYWW

ZZZZZ

YYWW = Date Code

ZZZZZ = Last five digits of PSC Lot Number

Not for new design

Product Specification

PE3342

Page 16 of 17

Sales Offices

The Americas

Peregrine Semiconductor Corporation

9380 Car r oll Park Drive

San Diego, CA 92121

Tel 858-731-9400

Fax 858-731- 9499

North Asia Pacific

Peregrine Semiconductor K.K.

5A-5, 5F Im perial Tower

1-1-1 Uchisaiwaicho, Chiyoda-ku

Tokyo 100-0011 Japan

Tel: +81-3-3502-5211

Fax: +81- 3- 3502-5213

Peregrine Semiconductor, Korea

#B-2402, Kolon Tripolis, #210

Geumgok-dong, Bundang-gu, Seongnam- si

Gyeonggi-do, 463-480 S. Korea

Tel: +82-31-728-4300

Fax: +82- 31-728-4305

Europe

Peregrine Semiconductor Europe

Bâtiment Maine

13-15 rue des Quatre Vents

F- 92380 G arches, France

Tel: +33-1-47-41-91-73

Fax : +33-1 -47 -41-91-7 3

For a lis t of represent at ives in your area, please refer t o our Web site at: www.psem i.com

Data Sheet Identification

Advance Information

The product is in a formative or design stage. The data

sheet cont ains design target specifications f or product

development. Spec ifications and feat ures may change in

any manner without notice.

Preliminary Specification

The data sheet cont ains preliminar y data. Additional data

may be added at a later date. Peregrine reser ves the r ight

to change specifications at any tim e without notice in order

to supply t he best possible product.

Product Specification

The data sheet con tains final data. In the event Peregrine

dec ide s to cha nge the spe c ific ations, Pereg rine will not ify

customers of the intended changes by iss u ing a DCN

(Document Change Notice).

The inform ation in this dat a sheet is believed to be reliable.

Howeve r, Peregrine assume s no liabilit y for the use of this

information. Use shall be ent irely at the user’s own risk.

No pat ent rights or licenses t o any circuits described in this

data sheet are implied or granted to any third party.

Peregrine’s products are not designed or intended for use in

devices or syst ems intended for sur gical implant, or in other

applications int ended to support or sustain life, or in any

application in which the failure of t he Per egrine product could

create a situat ion in which per s onal injury or death m ight occur.

Peregr ine assum e s no liability for damages, including

consequential or incidental damages, arising out of t he use of

its product s in such applications.

The Per egrine name, logo, and UTSi ar e register ed trademarks

and UltraCMO S and HaRP are tr ademarks of Per egrine

Semiconduct or Corp.

South As ia Pacific

Peregrine Semiconductor, China

Shanghai, 200040, P.R. China

Tel: +86-21-5836-8276

Fax: +86- 21-5836-7652

Spa ce and De fense Products

Americas:

Tel: 505-881-0438

Fax: 505- 881-0443

Europe, Asi a Pacific:

180 Rue Jean de Guiramand

13852 Aix- En-Provence cedex 3, France

Tel: +33(0) 4 4239 3361

Fax: +33( 0) 4 4239 7227

Not for new design