1
Features
•Single 2.7V - 3.6V Supply
•Dual-interface Architecture
–RapidS
™ Serial Interface: 50 MHz Maximum Clock Frequency
(SPI Modes 0 and 3 Compatible for Frequencies up to 33 MHz)
–Rapid8
™ 8-bit Interface: 20 MHz Maximum Clock Frequency
•Page Program
– 16,384 Pages (1,056 Bytes/Page) Main Memory
•Sector Erase Architecture
– Sixty-three 270,336-byte Sectors
– One 261,888-byte Sector
– One 8,488-byte Sector
•Two 1056-byte SRAM Data Buffers – Allows Receiving of Data
while Reprogramming the Flash Array
•Continuous Read Capability through Entire Array
– Ideal for Code Shadow ing Applic ation s
•Low-power Dissipati on
– 10 mA Active Read Current Typical – Serial Interface
– 12 mA Active Read Current Typical – 8-bit Interface
– 15 µA CMOS Standby Current Typical
•Hardware Data Protection
•Security: 128-byte Security Register
– 64-by te User Programmable Space
– Unique 64-byte Device Identifier
•JEDEC Standard Manufacturer and Device ID Read
•100 Program/Erase Cycles Per Sector Minimum
•Data Retention – 10 Years
•Commercial Temperature Range
Description
The AT45CS1282 is a 2.7-volt, dual-interface sequential access Flash memory
idea lly suited for infreq uent cod e shadowing ap plica tions. Th is devic e utilize s Atmel ’s
e-STAC™ Multi-Level Cell (MLC) memory technology, which allows a single cell to
128-megabit
2.7-volt
Dual-interface
Code Shadow
DataFlash®
AT45CS1282
Preliminary
™
Note: *Optional Use – See pin description text
for connection information.
Pin Configurations
Pin Name Function
CS Chip Sele ct
SCK/CLK Serial Clock/Clock
SI Serial Input
SO Serial Output
I/O7 - I/O0 8-bit Input/Output
WP Hardware Page Write
Protect Pin
RESET Chip Reset
RDY/BUSY Ready/Busy
SER/BYTE Serial/8-bit Interface
Control
TSOP Top View: Type 1
CBGA Top View
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
22
21
NC
NC
RDY/BUSY
RESET
WP
NC
NC
NC
VCC
GND
NC
NC
NC
NC
CS
SCK
SI*
SO*
NC
NC
NC
NC
NC
NC
NC
I/O7*
I/O6*
I/O5*
I/O4*
VCCP*
GNDP*
I/O3*
I/O2*
I/O1*
I/O0*
SER/BYTE*
CLK
NC
NC
NC
A
B
C
D
E
F
G
H
J
12345
NC
I/O2
I/O1
I/O0
NC
SER/BYTE
SCK/CLK
CS
SO
GNDP
NC
GND
RDY/BUSY
SI
VCCP
I/O7
VCC
WP
RESET
NC
I/O6
I/O5
I/O4
I/O3
NC
Rev. 3447A–DF LS H– 2/0 4
2AT45CS1282 [Preliminary] 3447A–DFLSH–2/04
stor e two bits of inf ormatio n deliv ering a v ery cos t effect ive hi gh dens ity Fla sh mem-
ory. The AT45CS1282 supports RapidS serial interface and Rapid8 8-bit interface.
RapidS serial in terface is SPI com patible for freq uencies up to 33 MHz. T he dual-in ter-
face allow s a dedic ated seri al interfac e to be con nected to a DSP an d a dedica ted 8-bit
interf ace to be con nected to a mi crocon troller or vi ce versa. Ho wever, the use of either
interface is purely optional. Its 138,412,032 bits of memory are organized as 16,384
pages of 1,056 bytes each. In addition to the 132-megabit main memory, the
AT45CS1282 also contains two SRAM buffers of 1,056 bytes each. The buffers allow
the rec eiving of data whi le a page in the main Me mory is being r eprogr ammed, a s well
as writing a continuous data stream. Unlike conventional Flash memories that are
accessed randomly with multiple address lines and a parallel interface, the DataFlash
uses either a RapidS serial interface or a 8-bit Rapid8 interface to sequentially access
its data . The simp le sequen tial acce ss dram aticall y reduces active pin coun t, facilita tes
hardware layou t, increases sys tem reliability , minimizes sw itching noise, a nd reduces
package size. The device is optimized for use in many commercial applications where
high-density, low-pin count, low-voltage and low-power are essential. The device oper-
ates at clock frequencies up to 50 MHz with a typical active read current consumption of
10 mA.
To allow for simple in-system repr ogrammability, the AT45CS1282 does not require
high input voltages for programming. The device operates from a single power supply,
2.7V to 3.6V, for both the program and read operations. The AT45CS1282 is enabl ed
through the ch ip select pin ( CS) and access ed via a three-wire interface con sisting of
the Serial Input (SI), Serial Output (SO), and the Serial Clock (SCK), or an 8-bit interface
consisting of the input/output pins (I/O7 - I/O0) and the clock pin (CLK).
All programming and erase cycles are self-timed.
Block Diag ram
Memory Array To provide optimal flexibility, the memory array of the AT45CS1282 is divided into two
levels of granularity comprising of sectors, and pages. The “Memory Architecture Dia-
gram” illustrates the breakdown of each level and details the number of pages per
sector. All program operations to the DataFlash occur on a page by page basis. The
erase operations is performed at the sector level.
FLASH MEMORY ARRAY
PAGE (1056 BYTES)
BUFFER 2 (1056 BYTES)BUFFER 1 (1056 BYTES)
I/O INTERFACE
SCK/CLK
CS
RESET
VCC
GND
RDY/BUSY
SER/BYTE
WP
SOSI I/O7 - I/O0
3
AT45CS1282 [Preliminary]
3447A–DFLSH–2/04
Memory Architecture
Diagram
Device Operation The device operation is controlled by instructions from the host processor. The list of
instructions and their associated opcodes are contained in Tables 1 through 4. A valid
instr uction starts wit h the falling ed ge of CS followed by th e appropr iate 8- bit opcod e
and the desired buffer or main memory address location. While the CS pin is low, tog-
gling the SCK/CLK pin controls the loading of the opcode and the desired buffer or main
memory address location through either the SI (serial input) pin or the 8-bit input pins
(I/O7 - I/O0). All instructions, addresses, and data are transferred with the most signifi-
cant bit (MSB) first.
Buffer addressing is referenced in the datasheet using the terminology BFA10 - BFA0 to
denote the 11 addr ess bits required to designate a byte a ddress within a buffer. Main
memory addressing is referenced using the terminol ogy PA13 - PA0 and BA10 - BA0,
where PA13 - PA0 denotes the 14 address bits requi red to designate a pag e address
and BA10 - BA0 denotes the 11 address bits required to designate a byte address within
the page.
Read Commands By speci fying the appr opriate opcode, da ta can be read from the main memory or fro m
either one of the two SRAM data buffers. The DataFlash supports RapidS and Rapid8
protocols for Mode 0 and Mode 3. Please refer to the “Detailed Bit-level Read Timing”
diagrams in this datasheet for details on the clock cycle sequences for each mode.
CONTINUOUS ARRAY READ: By supplying an initial starting a ddress for the main
memory array, the Continuous Array Read command can b e utilized to sequentially
read a conti nuous stream of data from the de vice by simp ly provi ding a cl ock sig nal; no
additional addressing information or control signals need to be provided. The DataFlash
incorporates an internal address counter that will automatically increment on every clock
cycle, al lowing one con tinuous read ope ration without th e nee d of additional addr ess
sequences. To perform a continuous read, an opcode of E8H must be clocked into the
device follow ed by four address by tes ( whi ch c omp ri se s 7 don ’t c are b its pl us the 25-bit
page and byte address sequence) and a series of don’t care clock cycles (24 if using the
serial in terface or 19 if us ing the 8-bit inter face). The firs t 14 bits (PA13 - PA0 ) of the
SECTOR 0a = 8 Pages
8,448 bytes (8K + 256)
SECTOR 0b = 248 Pages
261,888 bytes (248K + 7,936)
8 Pages
Page = 1,056 bytes
(1K + 32)
PAGE 0
PAGE 1
PAGE 6
PAGE 7
PAGE 8
PAGE 9
PAGE 16,382
PAGE 16,383
PAGE 14
PAGE 15
PAGE 16
PAGE 17
PAGE 18
SECTOR ARCHITECTURE PAGE ARCHITECTURE
SECTOR 63 = 256 Pages
270,336 bytes (256K + 8K)
SECTOR 1 = 256 Pages
270,336 bytes (256K + 8K)
SECTOR 62 = 256 Pages
270,336 bytes (256K + 8K)
SECTOR 2 = 256 Pages
270,336 bytes (256K + 8K)
4AT45CS1282 [Preliminary] 3447A–DFLSH–2/04
25-bit ad dres s s eque nc e sp ecify whi ch page of the mai n me mory ar ray to r ead , and the
last 11 bits (BA10 - BA0) of the 25-bit address sequence specify the starting byte
address within the page. The 24 or 19 don’t care clock cycles that follow the four
addres s b ytes are nee ded to i ni tia li ze the re ad o perati on . Foll owi ng the d on’ t c are c lo ck
cycles, ad ditional c lock pulses on the SCK /CLK pin will result in d ata bein g output on
either the SO (serial output) pin or the eight output pins (I/O7- I/O0).
The CS pin must r emain low during the l oading of the opcode , the address bytes, the
don’t care bytes, an d the reading of data. When the end of a page in main memory is
reache d during a Con tin uous A rray Rea d, the devic e will contin ue readin g at the begin-
ning of the next page with no delays incurred during the page boundary crossover (the
crossover from the end of one page to the beginning of the next page). When the last bit
(or byte if using the 8- bit inte rface mode) in the main memory array has be en read, th e
device will continue reading back at the beginning of the first page of memory. As with
crossing over page boundaries, no delays will be incurred when wrapping around from
the end of the array to the beginning of the array.
A low-to -high tran sition o n the CS pi n will terminat e the read ope ration and tr i-state the
output pins (SO or I/O7-I/O0). The maximum SCK/CLK frequency allowable for the Con-
tinuous Array Read is defined by the fCAR specification. The Continuous Array Read
bypasses both data buffers and leaves the contents of the buffers unchanged.
MAIN MEMORY PAGE READ: A main memo ry page read allows the user to read da ta
directl y from any one of the 1638 4 pages in the ma in memory, by passing both of th e
data buffers and leaving the contents of the buffers unchanged. To start a page read, an
opcode of D2H must be clocked into the device followed by four address bytes (which
comprise 7 don’t care bits plus the 25-bit page and byte address sequence) and a series
of don’t care clock cycles (24 if usin g the seri al interface or 19 if using the 8- bit inter-
face). The firs t 14 bit s (PA13 - PA 0) of the 25 -bit a ddress seque nce s pecify th e page i n
main memory to be read, and the last 11 bits (BA10 - BA0) of the 25-bit address
sequence specify the starting byte address within that page. The 24 or 19 don’t care
clock cycles that follow the four address bytes are sent to initialize the read operation.
Following the don’t care bytes, additional pulses on SCK/CLK result in data being output
on either the SO (serial output) pin or the eight output pins (I/O7 - I/O0). The CS pin
must remain low during the loading of the opcode, the address bytes, the don’t care
bytes, and the reading of data. When the end of a page in main memory is reached, the
device will continue reading back at the beginning of the same page. A low-to-high tran-
sition on the CS pin will terminate the read operation and tri-state the output pins (SO or
I/O7 - I/O 0). The maximu m SCK/CLK f requency allowable for the Main Me mory Page
Read is defin ed by the fSCK specification. The Main Memory Page Read bypasses both
data buffers and leaves the contents of the buffers unchanged.
BUFFER READ: Data can be read from e ither one of the two bu ffers, usin g different
opcodes to specify which buffer to read from. With the serial interface, an opcode of
D4H is used to read data from buffer 1, and an opcode of D6H is used to read data from
buffer 2. Likewis e with the 8-bit interfac e an opcode of 54H is used to rea d data from
buffer 1 and an opcode of 56H is used to read data from buffer 2. To perform a buffer
read, the opcode must be clocked into the device followed by four address bytes com-
prised of 21 don ’t care bits and 11 buffer addr ess bits (BFA10 - BFA0) . Follo wing the
four address bytes, additional don’t care bytes (one byte if using the serial interface or
two bytes if using the 8- bit inter face) mus t be clocked in to initializ e the read ope ration.
Since the buffer size is 1056 bytes, 11 buffer address bits are required to specify the first
byte of dat a to be read from the buffer . The CS pi n must rema in low during the lo adin g
of the opcode, the address bytes, the don’t care bytes, and the reading of data. When
the end of a buff er is r eached, the devi ce will c ontinu e rea ding ba ck at t he begi nning of
the buffer. A low-to-high transition on the CS pin will terminate the read operation and
tri-state the output pins (SO or I/O7 - I/O0).
5
AT45CS1282 [Preliminary]
3447A–DFLSH–2/04
Program and Erase Commands
BUFFER WRIT E: Data can be c locked in from the input pins (S I or I/O7 - I/O 0) into
either buffer 1 or buffer 2. To load data into either buffer, a 1-byte opcode, 84H for buffer
1 or 87H for buffer 2, must be clocked into the device, followed by four address bytes
compri sed of 21 do n’t care bits and 11 buffer address bi ts (BFA10 - B FA0). The 11
buffer addres s bits sp ec ify the fir s t byte in the buffe r to be written. After th e last address
byte has been clocked into the device, data can then be clocked in on subsequent clock
cycles. If the end of the data bu ffer is reached, the device will wrap around back to the
beginning of the buffer . Dat a wil l co nti nue to be loa ded into the buff er unti l a lo w-to- hig h
transition is detected on the CS pin.
BUFFER T O MAIN MEMOR Y PA GE PR OGRAM: A previously-erased page within main
memory can be program med with the contents of eit her buffer 1 or buffer 2. The pro-
gramming time is selectable by the system through the use of different opcodes
between a normal mode and a fast mode (the fast program option will consume more
current). A 1-byte opcode, 88H for buffer 1 or 89H for buffer 2 (98H for buffer 1 fast pro-
gram or 99H for buffer 2 fast program), must be clocked into the device followed by four
addres s bytes consisting of 7 don’t care bits, 14- page address bi ts (PA13 - PA0) that
specify the page in the main memory to be written and 11 don’t care bits. When a low-to-
high transition occurs on the CS pin, the part will program the data stored in the buffer
into the spec ified page in th e main m em or y. It is n eces sa ry t hat the pa ge in main m em-
ory that is being programmed has been previously erased using the secto r erase
command s. The prog rammi ng of the page is interna lly self -timed and s hould tak e place
in a maximum time of tP for normal programming or tFP for fast programming. During this
time, the status register and the RDY/BUSY pin will indicate that the part is busy.
SECTOR ERASE: Th e Sector Erase comma nd can be u sed to indivi dually er ase any
sector in th e mai n memo ry. Th ere ar e 65 s ectors and o nly o ne se ctor can be eras ed at
one time. Sector 0a requires a different opcode than sectors 0b-63. To perform a sector
0a erase, an opcode of 50h must be loaded into the devic e, followed by four address
bytes comprise d of 7 don’t care bits, 11-page address bits (PA13 - PA3) and 14 don’t
care bits. To perform a sector 0b-63 erase, an opcode of 7Ch must be loaded into the
device, followed by four address bytes comprised of 7 don’t care bits, 6-page address
bits (PA13 - PA8) and 19 don’t care bits. The 6-page address bits are used to specify
which sect or is to be e rased. Refer to Sector Erase ad dressing table . When a low- to-
high transition occurs on the CS pin, the part will erase the selected sector. The erase
operation is internally self-timed and should take place in a maximum time of tSE. During
this time, the status register and the RDY/BUSY pin will indicate that the part is busy.
6AT45CS1282 [Preliminary] 3447A–DFLSH–2/04
Additional Commands MAIN MEMO RY PAGE TO BUFFER TRANSFER : A page of data can be transferred
from the main memory to either buffer 1 or buffer 2. To start the operation, a 1-byte
opcode, 53H for buffer 1 and 55H for buffer 2, must be clocked into the device, followed
by four address bytes comprised of 7 don’t care bits, 14-page address bits (PA13- PA0),
which spe cify the p age in main memory that is to be trans ferred, and 11 don’t ca re bits.
The CS pin must be low while toggling the SCK/CLK pin to load the opcode and the
address bytes from the inp ut pins (SI or I/O7 - I/O0) . The tra nsfer of the page of data
from the ma in me mor y to the buffe r will beg in whe n the CS pi n t ra nsitions f ro m a low to
a high s tat e. During th e tran sfer of a p age of dat a ( tXFR), the status register can be read
or the RDY/BUSY can be monitored to determine whether the transfer has been
completed.
MAIN MEMORY PAGE TO BUFFER COMPARE: A page of data in main memory can
be compared to the data in buffer 1 or buffer 2. To initiate the operation, a 1-byte
opcode, 60H for buffer 1 and 61H for buffer 2, must be clocked into the device, followed
by four address bytes consisting of 7 don’t care bits, 14-page address bits (PA13 - PA0)
that specify the page in the main memory that is to be compared to the buffer, and 11
don’t care bits. T he CS pin must be low whi le toggling the SCK/CLK pin to load the
opcode and the add r ess bytes fro m the inpu t pin s (SI or I/O7 - I/O 0). On the lo w-t o-hig h
transition of the CS pin, t he 1056 bytes in the selected main m emory p age wil l be c om-
pared with the 1056 byt es in buffer 1 or buffer 2. During this time (tXFR), the status
regist er and the RDY /BUSY pin will indicate that the part is busy. On comple tion of the
compare operation, bit 6 of the status register is updated with the result of the compare.
STATUS REGISTER READ: Th e sta tus regist er c an b e us ed to determi ne th e dev ice ’s
ready/busy status, the result of a Main Memory Page to Buffer Compare operation, or
the device density. To read the status register, an opcode must be loaded into the
device. After the opcode and optional dummy byte(s) is clocked in, the 1-byte status
registe r will be cloc ked out on th e output pi ns (SO or I/O 7 - I/O 0), starting with the nex t
clock c ycle. In case o f seria l int erface, opcode D7H is followed w ith an option al du mmy
byte (8 cl ocks). For Serial applications over 25 MHz, opcode must be always followed
with a dummy byte. In case of applications with 8-bit interface, opcode D7H and two
dummy clock cycles should be used. When using the serial interface, the data in the sta-
tus register, starting with the MSB (bit 7), will be cloc ked out on the SO pin during the
next eight cloc k cycles.
Sector Erase Addressing
PA13 PA12 PA11 PA10 PA9 PA8 PA7 PA6 PA5 PA4 PA3 PA2 PA1 PA0 Sector
00000000000XXX0a
000000XXXXXXXX 0b
000001XXXXXXXX 1
000010XXXXXXXX 2
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
111100XXXXXXXX 60
111101XXXXXXXX 61
111110XXXXXXXX 62
111111XXXXXXXX 63
7
AT45CS1282 [Preliminary]
3447A–DFLSH–2/04
The six most-significant bits of the status register will contain device information, while
the remaining two least-significant bits are reserved for future use and will have unde-
fined values. After the one byte of the status register has been clocked out, the
sequenc e will repeat i tself (as lon g as CS remai ns low and SCK /CLK is bein g togg led) .
The data in the status register is constantly updated, so each repeating sequence will
output new data.
Ready/busy status is indicated using bit 7 of the status register. If bit 7 is a 1, then the
device is not busy and is ready to accept the next command. If bit 7 is a 0, then the
device i s in a bus y state . Sin ce th e d ata i n th e sta tus r eg ister i s c ons tan tly upd ated , th e
user must toggl e SCK/CLK pin to check the ready/busy st atus. There are four opera-
tions th at can cause the device to be in a bu sy state: Main Memory Page to Buffer
Transfer, Main Memory Page to Buffer Compare, Buffer to Main Memory Page Program
and Sector Erase.
The result of the most recent Main Memory Page to Buffer Compare operation is indi-
cated using bit 6 of the status register. If bit 6 is a 0, then the data in the main memory
page matches the data in the buffer. If bit 6 is a 1, then at least one bit of the data in the
main memory page does not match the data in the buffer.
The devi ce densi ty is indic ated using bits 5, 4, 3, and 2 of th e status register . For the
AT45CS1282, the four bits are 0, 1, 0, 0. The decimal value of these four binary bits
does not equate to the device density; the fou r bits represent a combi national code
relating to differing densities of DataFlash devices. The device density is not the same
as the density code indicated in the JEDEC device ID information. The device density is
provided only for backward compatibility.
Status Register Format
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
RDY/BUSY COMP0100XX
8AT45CS1282 [Preliminary] 3447A–DFLSH–2/04
Manufacturer and Device ID Read
This instruction conforms to the JEDEC standard and allows the user to read the Manuf acturer ID, Device ID, and Extended
Device Inf ormation. This mode is only offered via the serial interface with clock frequencies up to 25 MHz. A 1-byte opcode,
9FH, must be clocked into the device while the CS pin is low. After the opcode is clock ed in, the Manufacturer ID, 2 bytes of
Device ID and Extended Device Information will be clock ed out on the SO pin. The fourth byte of the sequence output is the
Extended Device Inform ati on Str i ng L eng th byte. This byte is us ed to s igni fy how many bytes o f E xtende d Device Infor ma-
tion will be output.
Manufacturer and Device ID Information
Note: Based on JEDEC publication 106 (JEP106), Manufacturer ID data can be comprised of any number of bytes. Some manufacturers may have
Manufacturer ID codes that are two, three or even four bytes long with the first byte(s) in the sequence being 7FH. A system should detect code
7FH as a “Continuation Code” and continue to read Manuf act urer ID bytes. The first non-7FH byte would signify t he last byte of Manuf acturer ID
data. For Atmel (and some other manufacturers), the Manuf acturer ID data is comprised of only one byte .
Byte 1 – Manufacturer ID
Hex
Value
JEDEC Assigned Code
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
1FH00011111 Manufacturer ID 1FH = Atmel
Byte 2 – Device ID (Part 1)
Hex
Value
Family Code Density Code
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Family Code 001 = DataFlash
29H00101001 Density Code 01001 = 128-Mbit
Byte 3 – Device ID (Part 2)
Hex
Value
MLC Code Product Version Code
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 MLC Code 001 = 2-Bit/Cell Technology
20H00100000 Product Version 00000 = Initial Version
Byte 4 – Extended Device Information String Length
Hex
Value
Byte Count
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
00H00000000 Byte Count 00H = 0 Bytes of Information
9FH
Manufacturer ID
Byte n Device ID
Byte 1 Device ID
Byte 2
This information
would only be output
if the Extended Device
Information String Length
value was something
other than 00H.
Extended
Device
Information
String Length
Extended
Device
Information
Byte x
Extended
Device
Information
Byte x + 1
CS
1FH 29H 20H 00H Data Data
SI
SO
Opcode
Each transition
represents 8 bits
9
AT45CS1282 [Preliminary]
3447A–DFLSH–2/04
Security Register The AT45CS1282 contains a specialized register that can be used for security purposes
in system design. The Security Register is a unique 128-byte register that is divided into
two portions. The first 64 bytes (byte 0 to byte 63) of this register are allocated as a one-
time user programmable space. Once these 64 bytes have bee n programmed, they
should not be repr ogrammed. The remaining 64 by tes of this register (byte 64 to byte
127) are factory programmed by Atmel and will contain a unique number for each
device. The factory programmed data is fixed and cannot be changed.
The Sec urity Register can b e read by clock ing in o pcode 77H to t he d evice fo llowe d by
four address bytes (which are comprised of 21 don’t care bits plus 11 byte address bits)
and a series of don’t care clock cycles (24 if using the serial interface and 19 if using the
8-bit interface). The Security Register Read can be terminated by asserting CS low to
high after the 12 8- byte se cu ri ty regis ter has bee n r ead o ut. The c ont inu ati on of c lo ckin g
past that will result in indeterminate data on the output. See the opcode table on page
13 for this mode.
To program the first 64 bytes of the Security Register, a two step sequence must be
used. The first step requires that the user loads the desired data into Buffer 1 by using
the Buff er 1 W rite operation (opc ode 84H – see Buffer Write de scription). The u ser
should specify the starting buffer address as location zero and should write a full
64 bytes of in formation into the buffer. Otherwi se, the first 64 bytes of the buf fer may
contain data that was previously stored in the buffer. It is not necessary to fill the remain-
ing 992 by tes (b yt e lo cat ion s 6 4 thr ou gh 10 55) of the buffer wi th da ta. A fter the Buffer 1
Write op eration has been comple ted, the Secur ity Register ca n be subsequentl y pro-
grammed by reselecting the device and clocking in opcode 9AH into the device followed
by four don’t care bytes (32 clock cycles if using the serial interface and four clock
cycles if using the 8-bit interface). After the final don’t care clock cycle has been
completed, a low-to-high transition on the CS pin will cause the device to initiate an
internally self-timed program operation in which the contents of Buffer 1 will be pro-
gramm ed into the S ecurity R egister . On ly the fi rst 64 bytes of dat a in B uffer 1 will b e
programmed into the Security Register; the remaining 992 bytes of the buffer will be
ignored. The Security Register program operation should take place in a maximum time
of tP.
Operation Mode
Summary The modes d escrib ed can be separate d into two groups – mo des tha t make us e of the
Flash memory array (Group A) and modes that do not make use of the Flash memory
array (Group B).
Group A modes consist of:
1. Main Memory Page Read
2. Continuous Array Read
3. Main Memory Page to Buffer 1 (or 2) Transfer
4. Main Memory Page to Buffer 1 (or 2) Compare
5. Buffer 1 (or 2) to Main Memory Page Program
6. Secto r 0a Erase
7. Secto r 0b-63 Erase
Group B modes consist of:
1. Buffer 1 (or 2) Read
2. Buffer 1 (or 2) Write
3. Status Register Read
10 AT45CS1282 [Preliminary] 3447A–DFLSH–2/04
If a Group A mode is in progress (not fully completed), then another mode in Group A
should not be started. However, during this time in which a Group A mode is in
progress, modes in Group B can be started, except the first two Group A commands
(Memory Array Read Commands).
This give s th e DataFlash th e abi li ty to vi rtual ly ac co mmo dat e a co nti nuo us data str eam .
While data is being programmed into main memory from buffer 1, data c an be loaded
into buffer 2 (or vice versa). See application note AN-4 (“Using Atmel’s Serial
DataFlash”) for more details.
Pin Descriptions SERIAL/8-BIT INTERFACE CONTROL (SER/BYTE): The DataFlash may be config-
ured to util ize eithe r its serial port or 8-bit port th rough the us e of the serial/8 -bit contro l
pin (SER/BYTE). When the SER/BYTE pin is held high, the se rial port (SI and SO ) of
the DataFlash will be used for all data transfers, and the 8-bit port (I/O7 - I/O0) will be in
a high impedance state. Any data presented on the 8-bit port while SER/BYTE is held
high w ill be ignor ed. Wh en the S ER/B YTE is held low, the 8-bit port will be used for all
data trans fers , and the S O pin of the ser ial por t wil l b e in a hig h im ped anc e s tate . Wh il e
SER/BYTE is low, any da ta presented on the SI pin will be igno red. Switchi ng between
the serial port and 8-bit port should only be done while the CS pin is high and the device
is not busy in an internally self-timed operation.
The SER/BYTE pin is internally pulled high; therefore, if the 8-bit port is never to be
used, then connection of the SER/BYTE pin is not necessary. In addition, if the
SER/BYTE pin is not connected or if the SER/BYTE pin is always driven high externally,
then the 8- bit in put/outp ut pins ( I/O7-I/O0) , the VC CP pin, and the G NDP pin s hould b e
treated as “don’t connects”.
SERIAL INPUT (SI): The SI pin is an input-only pin and is used to shift data serially into
the device. The SI pin is used for all data input, including opcodes and address
sequences. If the SER/BYTE pin is always driven low, then the SI pin should be a “don’t
connect”.
SERIAL OUTPUT (SO): The SO pin is an outp ut-onl y pin and i s used t o shift d ata seri-
ally out from the dev ice. If the SER/BYTE pin is always driven low, then the SO pin
should be a “don’t connect”.
8-BIT INPUT/OUTPUT (I/O7-I/O0): The I/O7-I/O0 pins are bidirectional and used to
clock data into and out of the device. The I/O7-I/O0 pins are used for all data input,
including opcodes and address sequenc es. The use of these pins is optional, and the
pins should be treated as “don’t connects” if the SER/BYTE pin is not connected or if the
SER/BYTE pin is always driven high externally.
SERIAL CLOCK/CLOCK (SCK/CLK): The SCK and CLK pins are input-only pins and
are used to control the flow of data to and from the DataFlash. The SCK and CLK pins
are used for serial and 8-bit interface respectively. Data is always clocked into the
device on th e rising ed ge of SCK/CLK and c locked out of the devic e on the falling edg e
of SCK/CLK.
CHIP SELECT (CS): The DataFlash is selected when the CS pin is low. When the
device is not sele cted, da ta will n ot be accept ed on the in put pins (SI or I/O7- I/O0), an d
the output pins (SO or I/O7-I/O0) will remain in a hi gh impedance state. A high-to-low
transition on the CS pin is re quired to st art an ope ratio n, and a low-to- high trans ition on
the CS pin is required to end an operation.
HARDWARE PAGE WRITE PROTECT: If the WP pi n is held low , the firs t 256 pages
(sectors 0 and 1) of the mai n me mory can not be repro gramm ed. The only way to r epro-
gram the first 256 pages is to first drive the protect pin high and then use the program
11
AT45CS1282 [Preliminary]
3447A–DFLSH–2/04
comma nds previously mentioned. If thi s pin and fea ture are not uti lized it is r ecom-
mended that the WP pin be driven high externally.
RESET: A low state on the reset pin (RESET) will terminate the operation in progress
and res et the in terna l state machi ne to a n idle state. T he de vice will re main i n the r eset
condition as long as a low level is present on the RESET pin. Normal operation can
resume once the RESET pin is brought back to a high level.
The device incorporates an inte rnal power-on reset circuit, so there are no restrictions
on the RESET pin during power-on sequences. If this pin and feature are not utilized it is
recommended that the RESET pin be driven high e xternally.
READY/BUSY: This open drain output p in wil l be driv en low w hen the d evice i s busy i n
an internally self-timed operation. This pin, which is normally in a high state (through
an extern al pull-up res istor), will be pul led low durin g programmin g/erase opera tions,
compare operations, and page-to-buffer transfers.
The busy status indicates that the Flash memory array and one of the buffers cannot be
accessed; read and write operations to the other buffer can still be performed.
8-BIT PORT SUPPLY VOLTAGE (VCCP AND GNDP): The VCCP and GND P pins are
used to supply power for the 8- bit input/output pins (I/O7-I/O0). The VCCP and GNDP
pins need to be used if the 8-bit po rt is to be utilize d; howev er, these pins should b e
treated as “don’t connects” if the SER/BYTE pin is not connected or if the SER/BYTE pin
is always driven high externally.
Power-on/Reset State When power is first applied to the device, or when recovering from a reset condition, the
device wil l defa ult to Mode 3 . In add ition, the outp ut pin s (SO or I/O7 - I/O0) wi ll be in a
high impedance state, and a high-to-low transition on the CS pin will be required to start
a valid instruction. The mode (Mode 3 or Mode 0) will be automatically selected on every
falling edge of CS by sampling the inactive clock state. After power is applied and VCC is
at the minimum d atasheet value, the system shoul d wait 20 ms before an operational
mode is started.
System
Considerations The RapidS serial interface is controlled by the serial clock SCK, serial input SI and chip
select CS pins. The sequential 8-bit Rapid8 is controlled by the clock CLK, 8 I/Os and
chip select CS pins. These signals mu st rise and fall monotonically and be free from
noise. Excessive noise or ringing on these pins can be misinterpreted as multiple edges
and cause improper operation of the device. The PC board traces must be kept to a
minimum distance or appropri ately termi nated to ensur e prope r operatio n. If necessary ,
decoupling c apacitors can be a dded on these pins to provide filtering agai nst noise
glitches.
As system complexity continues to increase, voltage regulation is becoming more
importa nt. A key el eme nt o f a ny v ol tage r eg ula tio n s c hem e i s i ts cu rrent sou rc ing capa-
bility. Like all Flash memories, the peak current for DataFlash occur during the
progra mming and era se operation. The regu lator needs to supply thi s peak cu rrent
requirement. An under specified regulator can cause current starvation. Besides
increasing system noise, current starvation during programming or erase can lead to
improper operation and possible data corruption.
12 AT45CS1282 [Preliminary] 3447A–DFLSH–2/04
Note: 1. The Secur ity Register Program command utilizes data stored in Buffer 1. Therefore,
this command must be used in conjunction with the Buffer 1 write command. See the
Security Register description for details.
Tab le 1. Read Commands
Command Serial/8-bit Opcode
Main Memory Page Read Both D2h
Continuous Array Read Both E8h
Buffer 1 Read Serial D4h
Buffer 2 Read Serial D6h
Buffer 1 Read 8-bit 54h
Buffer 2 Read 8-bit 56h
Tab le 2. Program and Erase Commands
Command Serial/8-bit Opcode
Buffer 1 Write Both 84h
Buffer 2 Write Both 87h
Buffer 1 to Main Memory Page Program Both 88h
Buffer 1 to Main Memory Page Program,
Fast Program Both 98h
Buffer 2 to Main Memory Page Program Both 89h
Buffer 2 to Main Memory Page Program,
Fast Program Both 99h
Sector 0 a Erase Both 50h
Sector 0 b-63 Erase Both 7Ch
Tab le 3. Additional Commands
Command Serial/8-bit Opcode
Main Memory Page to Buffer 1 Transfer Both 53h
Main Memory Page to Buffer 2 Transfer Both 55h
Main Memory Page to Buffer 1 Compare Both 60h
Main Memory Page to Buffer 2 Compare Both 61h
Status Register Read Both D7h
Manufacturer and Device ID Read Serial 9Fh
Security Regi ste r Prog ra m(1) Both 9Ah
Security Registe r Read Both 77h
13
AT45CS1282 [Preliminary]
3447A–DFLSH–2/04
Notes: P = Page Address Bit
B = Byte/Buffer Address Bit
x = Don’t Care
*The number with (*) is for 8-bit interface.
Tab le 4. Detailed Bit-level Addressing Sequence
Opcode Opcode
Address Byte Address Byte Address Byte Address Byte
Additional
Don’t Care
Bytes*
50h 01010000xxxxxxxP PPPPPPPP PPxxxxxx xxxxxxxx N/A
53h 01010011xxxxxxxP PPPPPPPP PPPPPxxx xxxxxxxx N/A
54h 01010100xxxxxxxx xxxxxxxx xxxxxBBBBBBBBBBB 2*
55h 01010101xxxxxxxP PPPPPPPP PPPPPxxx xxxxxxxx N/A
56h 01010110xxxxxxxx xxxxxxxx xxxxxBBBBBBBBBBB 2*
60h 01100000xxxxxxxP PPPPPPPP PPPPPxxx xxxxxxxx N/A
61h 01100001xxxxxxxP PPPPPPPP PPPPPxxx xxxxxxxx N/A
77h 01110111xxxxxxxx xxxxxxxx xxxxxBBBBBBBBBBB 3 or 19*
7Ch 01111100 xxxxxxxP PPPPPxxx xxxxxxxx xxxxxxxx N/A
84h 10000100xxxxxxxx xxxxxxxx xxxxxBBBBBBBBBBB N/A
87h 10000111xxxxxxxx xxxxxxxx xxxxxBBBBBBBBBBB N/A
88h 10001000xxxxxxxP PPPPPPPP PPPPPxxx xxxxxxxx N/A
89h 10001001xxxxxxxP PPPPPPPP PPPPPxxx xxxxxxxx N/A
98h 10011000xxxxxxxP PPPPPPPP PPPPPxxx xxxxxxxx N/A
99h 10011001xxxxxxxP PPPPPPPP PPPPPxxx xxxxxxxx N/A
9Ah 10011010 xxxxxxxx xxxxxxxx xxxxxxxx xxxxxxxx N/A
9Fh 10011111 N/A N/A N/A N/A N/A
D2h 11010010xxxxxxxP PPPPPPPP PPPPPBBB BBBBBBBB 3 or 19*
D4h 11010100xxxxxxxx xxxxxxxx xxxxxBBBBBBBBBBB 1
D6h 11010110xxxxxxxx xxxxxxxx xxxxxBBBBBBBBBBB 1
D7h 11010111 N/A N/A N/A N/A 1/0 or 1*
E8h 11101000 xxxxxxxP PPPPPPPP PPPPPBBB BBBBBBBB 3 or 19*
PA13
PA12
PA11
PA
10
PA9
PA8
PA7
PA6
PA5
PA4
PA3
PA2
PA1
PA0
BA10
BA9
BA8
BA7
BA6
BA5
BA4
BA3
BA2
BA1
BA0
14 AT45CS1282 [Preliminary] 3447A–DFLSH–2/04
Note: 1. After power is applied and VCC is at the minimum specified datasheet value, the system should wait 20 ms before an opera-
tional mode is started.
Notes: 1. ICC1 during a buffer read is 25 mA maximum.
2. ICC2 during a buffer read is 25 mA maximum.
Absolute Maxim u m Ratings*
Temperature under Bias ............................... -55°C to +125°C*NOTICE: Stresses beyond those listed under “Absolute
Maximum Ratings” may cause permanent dam-
age to the device . This i s a stres s rat ing onl y and
funct ional ope rati on of the de vic e at these or an y
other conditions beyond those indicated in the
operational sections of this specification is not
implied. Exposure to absolute maximum rating
conditi ons for e xtended periods ma y affe ct device
reliability.
Storage Temperature.................................... -65°C to +150°C
All Input Voltages
(including NC Pins)
with Respect to Ground...................................-0.6V to +6.25V
All Output Voltages
with Respect to Ground.............................-0.6V to VCC + 0.6V
DC and AC Operating Range
AT45CS1282
Operating Temperature (C ase) Com. 0°C to 70°C
VCC Power Supply(1) 2.7V to 3.6V
DC Characteristics
Symbol Parameter Condition Min Typ Max Units
ISB Standby Current CS, RESET, WP = VIH, all
inputs at CMOS levels 15 50 µA
ICC1(1) Activ e Curren t, Read
Operation, Serial Interface f = 20 MHz; IOUT = 0 mA;
VCC = 3.6V 10 20 mA
ICC2(2) Activ e Curren t, Read
Operation, 8-bit Interface f = 10 MHz; IOUT = 0 mA;
VCC = 3.6V 12 20 mA
ICC3 Active Curren t, Program
Operation, Page Program VCC = 3.6V 50 mA
ICC4 Active Curren t, Program
Operation, Fast Page Program VCC = 3.6V 65 mA
ICC5 Active Current, Sector Erase
Operation VCC = 3.6V 50 mA
ILI Input Load Current VIN = CMOS levels 1 µA
ILO Out put Leakage Current VI/O = CMOS levels 1 µA
VIL Input Low Voltage VCC x 0.3 V
VIH Input High Voltage VCC x 0.7 V
VOL Output Low Voltage IOL = 1.6 mA; VCC = 2.7V 0.4 V
VOH Output High Volta ge IOH = -100 µA VCC - 0.2V V
15
AT45CS1282 [Preliminary]
3447A–DFLSH–2/04
AC Characteristics – RapidS Serial Interface
Symbol Parameter Min Typ Max Units
fSCK SCK Frequency 50 MHz
fCAR SCK Frequency for Continuous Array Read 40 MHz
tWH SCK High Time 9 ns
tWL SCK Low Time 9 ns
tCS Minimum CS High Time 250 ns
tCSS CS Setup Time 250 ns
tCSH CS Hold Time 250 ns
tCSB CS High to RDY/BUSY Low 150 ns
tSU Data In Setup Time 5 ns
tHData In Hold Time 7 ns
tHO Output Hold Time 2 ns
tDIS Output Disable Time 10 ns
tVOutput Valid 10 ns
tXFR Page to Buffer Transfer/Compare Time 500 µs
tPPage Programming Time 50 ms
tFP Fast Page Programming Time 15 ms
tSE0a Sector 0a Erase Time 75 200 ms
tSE0b-63 Sector 0b-63 Erase Time 2 4 s
tRST RESET Pulse Width 10 µs
tREC RESET Recover y Time 1 µs
16 AT45CS1282 [Preliminary] 3447A–DFLSH–2/04
Input Test Waveforms and Measurement Levels
tR, tF < 2 ns (10% to 90%)
Output Test Load
AC Characteristics – Rapid8 8-bit Interface
Symbol Parameter Min Typ Max Units
fSCK1 CLK Frequency 20 MHz
fCAR1 CLK Frequency for Continuous Array Read 20 MHz
tWH CLK High Time 16 ns
tWL CLK Low Time 16 ns
tCS Minimum CS High Time 250 ns
tCSS CS Setup Time 250 ns
tCSH CS Hold Time 250 ns
tCSB CS High to RDY/BUSY Low 150 ns
tSU Data In Setup Time 10 ns
tHData In Hold Time 10 ns
tHO Output Hold Time 3 ns
tDIS Output Disable Time 15 ns
tVOutput Valid 15 ns
tXFR Page to Buffer Transfer/Compare Time 500 µs
tPPage Programming Time 50 ms
tFP Fast Page Programming Time 15 ms
tSE0a Sector 0a Erase Time 75 200 ms
tSE0b-63 Sector 0b-63 Erase Time 2 4 s
tRST RESET Pulse Width 10 µs
tREC RESET Recover y Time 1 µs
AC
DRIVING
LEVELS
AC
MEASUREMENT
LEVEL
0.45V
1.5V
2.4V
DEVICE
UNDER
TEST
30 pF
17
AT45CS1282 [Preliminary]
3447A–DFLSH–2/04
AC Waveforms Six different timing waveforms are shown below. Waveform 1 shows the SCK/CLK sig-
nal being low when CS makes a high-to-low transition, and waveform 2 shows the
SCK/CLK signal being high when CS makes a high-to-low transition. In both cases, out-
put SO becomes valid while the SCK/CLK signal is still low (SCK/CLK low time is
specified as tWL). Timing waveforms 1 and 2 conform to RapidS serial interface but for
frequencies up to 33 MHz. Waveforms 1 and 2 are compatible with SPI Mode 0 and SPI
Mode 3, respectively.
Wavefor m 3 and wa veform 4 illustrate general timing diagr am for RapidS serial i nter-
face. These are similar to waveform 1 and waveform 2, except that output SO is not
restric ted to bec ome va lid duri ng the tWL period . These ti ming wa veforms are vali d over
the full frequency r ange (maximum frequency = 50 MHz) of the RapidS serial case.
Wavefor m 5 and waveform 6 are for 8-bit Rapi d8 in terfac e ov er the full frequ ency rang e
of operation (maximum frequency = 20 MHz).
Waveform 1 – SPI Mode 0 Compatible (for Frequencies up to 33 MHz)
Waveform 2 – SPI Mode 3 Compatible (for Frequencies up to 33 MHz)
CS
SCK/CLK
SI
SO
tCSS
VALID IN
tH
tSU
tWH tWL tCSH
tCS
tV
HIGH IMPEDANCE VALID OUT
tHO tDIS
HIGH IMPEDANCE
CS
SCK/CLK
SO
tCSS
VALID IN
tH
tSU
tWL tWH tCSH
tCS
tV
HIGH Z VALID OUT
tHO tDIS
HIGH IMPEDANCE
SI
18 AT45CS1282 [Preliminary] 3447A–DFLSH–2/04
Waveform 3 – RapidS Mode 0 (for all Frequencies)
Waveform 4 – RapidS Mode 3 (for all Frequencies)
Waveform 5 – Rapid8 Mode 0 (FMAX = 20 MHz)
Waveform 6 – Rapid8 Mode 3 (FMAX = 20 MHz)
CS
SCK/CLK
SI
SO
tCSS
VALID IN
tH
tSU
tWH tWL tCSH
tCS
tV
HIGH IMPEDANCE VALID OUT
tHO tDIS
HIGH IMPEDANCE
CS
SCK/CLK
SO
tCSS
VALID IN
tH
tSU
tWL tWH tCSH
tCS
tV
HIGH Z VALID OUT
tHO tDIS
HIGH IMPEDANCE
SI
CS
SCK/CLK
I/O7 - I/O0
(INPUT)
I/O7 - I/O0
(OUTPUT)
tCSS
VALID IN
tH
tSU
tWH tWL tCSH
tCS
tV
HIGH IMPEDANCE VALID OUT
tHO tDIS
HIGH IMPEDANCE
CS
SCK/CLK
I/O7 - I/O0
(OUTPUT)
tCSS
VALID IN
tH
tSU
tWL tWH tCSH
tCS
tV
HIGH Z VALID OUT
tHO tDIS
HIGH IMPEDANCE
I/O7 - I/O0
(INPUT)
19
AT45CS1282 [Preliminary]
3447A–DFLSH–2/04
Reset Timing
Note: T he CS signal should be in the high state before the RESET signal is deasserted.
Command Sequence for Read/Write Operations
(Except Status Register Read, Manufacturer and Device ID Read)
Write Operations
The following block diagram and wa veforms illustrate the various write sequences available.
CS
SCK/CLK
RESET
SO or I/O7 - I/O0
(OUTPUT)
HIGH IMPEDANCE HIGH IMPEDANCE
SI or I/O7 - I/O0
(INPUT)
tRST
tREC tCSS
SI or I/O7 - I/O0
(INPUT) CMD 8 bits 8 bits 8 bits
MSB
7 Bits Don't
Care Page Address
(PA13 - PA0)
X X X X X X X X X X X X X X X X LSB
X X X X X X X X
8 bits
X X X X X X X X
Byte/Buffer Address
(BA10 - BA0/BFA10 - BFA0)
FLASH MEMORY ARRAY
PAGE (1056 BYTES)
BUFFER 2 (1056 BYTES)BUFFER 1 (1056 BYTES)
I/O INTERFACE
SI
BUFFER 1 TO
MAIN MEMORY
PAGE PROGRAM
BUFFER 2 TO
MAIN MEMORY
PAGE PROGRAM
BUFFER 1
WRITE BUFFER 2
WRITE
I/O7 - I/O0
20 AT45CS1282 [Preliminary] 3447A–DFLSH–2/04
Buffer Write
Buffer to Main Memory Page Program (Data from Buffer Programmed into Flash Pag e)
Read Operations
The following block diagram and waveforms illustrate the various read sequences available.
SI or I/O7 - I/O0
(INPUT)
CMD
X
X···X, BFA10-8
BFA7-0
nn+1 Last Byte
· Completes writing into selected buffer
CS
X
SI or I/O7 - I/O0
(INPUT)
CMD
XXXXXXX PA13 PA12-5
CS
Starts self-timed erase/program operation
X···X
PA4-0, XXX
Each transition
represents 8 bits
FLASH MEMORY ARRAY
PAGE (1056 BYTES)
BUFFER 2 (1056 BYTES)BUFFER 1 (1056 BYTES)
I/O INTERFACE
MAIN MEMORY
PAGE TO
BUFFER 1
MAIN MEMORY
PAGE TO
BUFFER 2
MAIN MEMORY
PAGE READ
BUFFER 1
READ BUFFER 2
READ
SO I/O7 - I/O0
n = 1st byte
n+1 = 2nd byte
21
AT45CS1282 [Preliminary]
3447A–DFLSH–2/04
Main Memory Page Read
Main Memory Page to Buffer Transfer (Data from Flash Page Read into Buf fer)
Buffer Read
SI or I/O7 - I/O0
(INPUT)
CMD xxx...PA13 PA12-5 BA7-0 X
X
CS
n n+1
SO or I/O7 - I/O0
(OUTPUT)
PA4-0, BA10-8
24 Cycles for Serial
19 Cycles for Parallel
Starts reading page data into buffer
SI or I/O7 - I/O0
(INPUT)
CMD XX...PA13 PA12-5 X
CS
SO or I/O7 - I/O0
(OUTPUT)
PA4-0, XXX
I/O7-I/O0
(INPUT)
CMD X
X···X, BFA10-8 BFA7-0
CS
n n+1
I/O7-I/O0
(OUTPUT)
X
ADDR ADDR
X
1 Dummy Byte (Serial)
2 Dummy Bytes (Parallel)
Each transition
represents 8 bits
n = 1st byte read
n+1 = 2nd byte read
22 AT45CS1282 [Preliminary] 3447A–DFLSH–2/04
Detailed Bit-level Read Timing – RapidS Serial Interface Mode 0
Continuous Array Read (Opcode: E8H)
Main Memory Page Read (Opc ode: D2H)
SI
11XXX
CS
SO
SCK
12 62 63 64 65 66 67
HIGH IMPEDANCE
D7D6D5D2D1D0D7D6D5
DATA OUT
BIT 0
OF
PAGE n+1
BIT 8,447
OF
PAGE n
LSB MSB
t
SU
tV
SI 11010 XXX
CS
SO
SCK 12345 60 61 62 63 64 65 66 67
XX
HIGH IMPEDANCE
COMMAND OPCODE
t
SU
D7D6D5
DATA OUT
MSB
t
V
D4
23
AT45CS1282 [Preliminary]
3447A–DFLSH–2/04
Detailed Bit-level Read Timing – RapidS Serial Interface Mo de 0 (Continued)
Buffer Read (Opcode: D4H or D6H)
Status Register Read (Opcode: D7H)
Manufacturer and Device ID Read (Opcode: 9FH)
SI
11010 XXX
CS
SO
SCK
12345 44 45 46 47 48 49 50 51
XX
HIGH IMPEDANCE
COMMAND OPCODE
t
SU
D7D6D5
DATA OUT
MSB
t
V
D4
SI
11010111
CS
SO
SCK
12345 7891011 12 15 16
HIGH IMPEDANCE STATUS REGISTER OUTPUT
COMMAND OPCODE
MSB
t
SU
6
D1D0D7
LSB MSB
D7D6D5
t
V
D4
t
V
DON’T CARE FOR
FREQ. OVER 25 MHz
SI
10- 011111
CS
SO
SCK
12345 7891011 12 16 17
HIGH IMPEDANCE PRODUCT ID OUTPUT
COMMAND OPCODE
MSB
tSU
6
100
MSBLSB
000
tV
1
24 AT45CS1282 [Preliminary] 3447A–DFLSH–2/04
Detailed Bit-level Read Timing – RapidS Serial Interface Mode 3
Continuous Array Read (Opcode: E8H)
Main Memory Page Read (Opc ode: D2H)
SI 11XXX
CS
SO
SCK 12 63 64 65 66 67
HIGH IMPEDANCE D7D6D5D2D1D0D7D6D5
BIT 0
OF
PAGE n+1
BIT 8,447
OF
PAGE n
LSB MSB
tSU
tVDATA OUT
SI
11010 XXX
CS
SO
SCK
12345 61 62 63 64 65 66 67
XX
HIGH IMPEDANCE
D7D6D5
DATA OUT
COMMAND OPCODE
MSB
tSU
tV
D4
68
25
AT45CS1282 [Preliminary]
3447A–DFLSH–2/04
Detailed Bit-level Read Timing – RapidS Serial Interface Mo de 3 (Continued)
Buffer Read (Opcode: D4H or D6H)
Status Register Read (Opcode: D7H)
Manufacturer and Device ID Read (Opcode: 9FH)
SI
11010 XXX
CS
SO
SCK
12345 45 46 47 48 49 50 51
XX
HIGH IMPEDANCE
D7D6D5
DATA OUT
COMMAND OPCODE
MSB
t
SU
t
V
D4
52
SI
11010111
CS
SO
SCK
12345 7891011 12 17 18
HIGH IMPEDANCE
D7D6D5
STATUS REGISTER OUTPUT
COMMAND OPCODE
MSB
t
SU
t
V
6
D4D0D7
LSB MSB D6
t
V
DON’T CARE FOR
FREQ. OVER 25 MHz
SI
10011111
CS
SO
SCK
12345 7891011 12 17 18
HIGH IMPEDANCE
000
PRODUCT ID OUTPUT
COMMAND OPCODE
MSB
tSU
tV
6
110
LSB MSB 0
26 AT45CS1282 [Preliminary] 3447A–DFLSH–2/04
Detailed 8-bit Read Timing – Rapid8 Mode 0
Continuous Array Read (Opcode: E8H)
Main Memory Page Read (Opc ode: D2H)
I/O7-I/O0
(INPUT)
CMD ADDR XXX
CS
I/O7-I/O0
(OUTPUT)
CLK
12 22 23 24 25 26 27
HIGH IMPEDANCE
DATA DATA DATA DATA DATA DATA DATA DATA DATA
DATA OUT
BYTE 0
OF
PAGE n+1
BYTE 1055
OF
PAGE n
t
SU
t
V
I/O7-I/O0
(INPUT)
CMD ADDR ADDR ADDR ADDR
XXX
CS
I/O7-I/O0
(OUTPUT)
CLK 12345 20 21 22 23 24 25 26 27
XX
HIGH IMPEDANCE DATA DATA DATA
DATA OUT
COMMAND OPCODE
t
SU
tV
DATA
27
AT45CS1282 [Preliminary]
3447A–DFLSH–2/04
Detailed 8-bit Timing – Rapid8 Mode 0 (Continued)
Buffer Read (Opcode: 54H or 56H)
Status Register Read (Opcode: D7H)
I/O7-I/O0
(INPUT)
CMD XXADDR
CS
I/O7-I/O0
(OUTPUT)
CLK 12345 8
HIGH IMPEDANCE
COMMAND OPCODE
tSU
tVDATA OUT
DATA DATA DATA
MSB
76
ADDR XX
I/O7-I/O0
(INPUT)
CMD
CS
I/O7-I/O0
(OUTPUT)
CLK 123
HIGH IMPEDANCE
tSU
XX DATA
tV
DATA DATA
STATUS
REGISTER OUTPUT
28 AT45CS1282 [Preliminary] 3447A–DFLSH–2/04
Detailed 8-bit Read Timing – Rapid8 Mode 3
Continuous Array Read (Opcode: E8H)
Main Memory Page Read (Opc ode: D2H)
I/O7-I/O0
(INPUT)
CMD ADDR XXX
CS
I/O7-I/O0
(OUTPUT)
CLK
12 23 24 25 26 27
HIGH IMPEDANCE
DATA DATA DATA DATA DATA DATA DATA DATA DATA
BYTE 0
OF
PAGE n+1
BYTE 1055
OF
PAGE n
tSU
tVDATA OUT
I/07-I/O0
(INPUT)
CMD ADDR ADDR ADDR ADDR
XXX
CS
I/07-I/O0
(OUTPUT)
CLK 12345 21 22 23 24 25 26 27
XX
HIGH IMPEDANCE DATA DATA DATA
DATA OUT
COMMAND OPCODE
t
SU
t
V
DATA
28
29
AT45CS1282 [Preliminary]
3447A–DFLSH–2/04
Detailed 8-bit Read Timing – Rapid8 Mode 3 (Continued)
Buffer Read (Opcode: 54H or 56H)
Status Register Read (Opcode: D7H)
I/O7-I/O0
(INPUT) CMD XXADDR ADDR
CS
I/O7-I/O0
(OUTPUT)
CLK 123456879
HIGH IMPEDANCE DATA DATA DATA
DATA OUT
tSU
tV
10
XX
I/O7-I/O0
(INPUT) CMD
CS
I/O7-I/O0
(OUTPUT)
CLK 123
HIGH
IMPEDANCE XX DATA
STATUS REGISTER
OUTPUT
tSU
tV
DATA
30 AT45CS1282 [Preliminary] 3447A–DFLSH–2/04
Note: 1. RapidS Serial Interf ac e .
Order ing Information
fSCK
(MHz)
ICC (mA)
Or de r ing Code P a ckage Operation RangeActive Standby
50(1) 20(1) 0.05 AT45CS1282-TC 40T Commercial
(0°C to 70°C)
50(1) 20(1) 0.05 AT45CS1282-CC 44C2 Commercial
(0°C to 70°C)
Package Type
40T 40-lead, (10 x 20 mm) Plastic Thin Small Outline Package, Type I (TSOP)
44C2 44-ball, (8 x 12 mm) Plastic Chip-size Ball Grid Array Package (CBGA)
31
AT45CS1282 [Preliminary]
3447A–DFLSH–2/04
Pa ckaging Information
40T – TSOP
2325 Orchard Parkway
San Jose, CA 95131
TITLE DRAWING NO.
R
REV.
40T, 40-lead (10 x 20 mm Package) Plastic Thin Small Outline
Package, Type I (TSOP) B
40T
10/18/01
PIN 1
D1 D
Pin 1 Identifier
b
e
EA
A1
A2
0º ~ 8º c
L
GAGE PLANE
SEATING PLANE
L1
COMMON DIMENSIONS
(Unit of Measure = mm)
SYMBOL MIN NOM MAX NOTE
Notes: 1. This package conforms to JEDEC reference MO-142, Variation CD.
2. Dimensions D1 and E do not include mold protrusion. Allowable
protrusion on E is 0.15 mm per side and on D1 is 0.25 mm per side.
3. Lead coplanarity is 0.10 mm maximum.
A – – 1.20
A1 0.05 – 0.15
A2 0.95 1.00 1.05
D 19.80 20.00 20.20
D1 18.30 18.40 18.50 Note 2
E 9.90 10.00 10.10 Note 2
L 0.50 0.60 0.70
L1 0.25 BASIC
b 0.17 0.22 0.27
c 0.10 – 0.21
e 0.50 BASIC
32 AT45CS1282 [Preliminary] 3447A–DFLSH–2/04
44C2 – CBGA
2325 Orchard Parkway
San Jose, CA 95131
TITLE DRAWING NO.
R
REV.
44C2, 44-ball (5 x 9 Array), 8 x 12 x 1.2 mm Body, 0.4 mm Ball
Plastic Chip-scale Ball Grid Array Package (CBGA) A
44C2
06/10/03
Side View
T op View
Bottom View
A
B
C
D
E
F
G
H
J
1
2
3
4
5
2.00 REF
2.00 REF
Marked A1
Identifier
D
E
D1
E1
e
e
Øb
A
A1
0.12
Seating Plane
C
C
A1 Ball Corner
COMMON DIMENSIONS
(Unit of Measure = mm)
SYMBOL MIN NOM MAX NOTE
A – – 1.20
A1 0.25 – –
D 7.90 8.00 8.10
D1 4.00 TYP
E 11.90 12.00 12.10
E1 8.00 TYP
e 1.00 TYP
Ø
b 0.40 TYP
Printed on recycled paper.
3447A–DFLSH–2/04 /xM
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