M12L32162A-5.5TG - Elite Semiconductor Memory Technology, Inc.

ESMT

M12L32162A

Elite Semiconductor Memory Technology Inc. Publication Date : Mar. 2009

Revision : 1.2 1/29

SDRAM 1M x 16Bit x 2Banks

Synchronous DRAM

FEATURES

z JEDEC standard 3.3V power supply

z LVTTL compatible with multiplexed address

z Dual banks operation

z MRS cycle with address key programs

- CAS Latency (2 & 3 )

- Burst Length (1, 2, 4, 8 & full page)

- Burst Type (Sequential & Interleave)

z All inputs are sampled at the positive going edge of the

system clock

z Burst Read Single-bit Write operation

z DQM for masking

z Auto & self refresh

z 64ms refresh period (4K cycle)

GENERAL DESCRIPTION

The M12L32162A is 33,554,432 bits synchronous high

data rate Dynamic RAM organized as 2 x 1,048,576 words

by 16 bits, fabricated with high performance CMOS

technology. Synchronous design allows precise cycle

control with the use of system clock I/O transactions are

possible on every clock cycle. Range of operating

frequencies, programmable burst length and programmable

latencies allow the same device to be useful for a variety of

high bandwidth, high performance memory system

applications.

ORDERING INFORMATION

Product ID Max Freq. Package Comments

M12L32162A-5.5TG 183MHz 54Pin TSOP(II) Pb-free

M12L32162A-6TG 166MHz 54Pin TSOP(II) Pb-free

M12L32162A-7TG 143MHz 54Pin TSOP(II) Pb-free

M12L32162A-5.5BG 183MHz 54 Ball BGA Pb-free

M12L32162A-6BG 166MHz 54 Ball BGA Pb-free

M12L32162A-7BG 143MHz 54 Ball BGA Pb-free

PIN CONFIGURATION (TOP VIEW)

54 PIN TSOP(II) 54 Ball BGA(8mmx8mm)

1

2

3

4

5

6

7

8

9

10

11

12

13

14

15

16

17

18

19

20

21

22

23

24

25

26

27

V

DD

DQ0

V

DDQ

DQ1

DQ2

V

SSQ

DQ3

DQ4

V

DDQ

DQ5

DQ6

V

SSQ

DQ7

V

DD

LDQM

WE

CAS

RAS

CS

NC

BA

A

10

/AP

A

0

A

1

A

2

A

3

V

DD

54

53

52

51

50

49

48

47

46

45

44

43

42

41

40

39

38

37

36

35

34

33

32

31

30

29

28

V

SS

DQ15

V

SSQ

DQ14

DQ13

V

DDQ

DQ12

DQ11

V

SSQ

DQ10

DQ9

V

DDQ

DQ8

V

SS

NC

UDQM

CLK

CKE

NC

A

11

A

9

A

8

A

7

A

6

A

5

A

4

V

SS

VSS

DQ14

DQ12

DQ8

UDQM

DQ15

DQ13

DQ11

DQ9

NC

CLK

A11

A7

NC

A8

VSSQ

CKE

A9

A6

123456789

A

B

C

D

E

F

G

H

J

DQ0

DQ2

DQ4

DQ6

LDQM

RAS

NC

A1

VDD

DQ1

DQ3

DQ5

DQ7

WE

CS

A10

VDDQ

VSSQ

VDDQ

VSSQ

VDD

CAS

BA

A0

DQ10

A5

VSS A4 A2 VDDA9

VDD Q

VSSQ

VDD Q

VSS

ESMT

M12L32162A

Elite Semiconductor Memory Technology Inc. Publication Date : Mar. 2009

Revision : 1.2 2/29

FUNCTIONAL BLOCK DIAGRAM

Bank Select Data Input Register

Column Decoder

Latency & Burst Length

Programming Register

1M x 16

Timing Register

CLK CKE CS RAS CAS WE L(U)DQM

LDQM

LWCBR

DQi

LDQM

LWE

LRAS LCBR LWE LCAS

CLK

ADD

LCKE

PIN FUNCTION DESCRIPTION

Pin Name Input Function

CLK System Clock Active on the positive going edge to sample all inputs.

CS Chip Select Disables or enables device operation by masking or enabling all inputs except

CLK, CKE and L(U)DQM.

CKE Clock Enable Masks system clock to freeze operation from the next clock cycle.

CKE should be enabled at least one cycle prior to new command.

Disable input buffers for power down in standby.

A0 ~ A11 Address Row / column addresses are multiplexed on the same pins.

Row address : RA0 ~ RA11, column address : CA0 ~ CA7

BA Bank Select Address Selects bank to be activated during row address latch time.

Selects bank for read/write during column address latch time.

RAS Row Address Strobe Latches row addresses on the positive going edge of the CLK with RAS low.

Enables row access & precharge.

CAS Column Address S trobe Latches column addresses on the positive going edge of the CLK with

CAS low.

Enables column access.

WE Write Enable Enables write operation and row precharge.

Latches data in starting from CAS , WE active.

L(U)DQM Data Input / Output Mask Makes data output Hi-Z, tSHZ after the clock and masks the output.

Blocks data input when L(U)DQM active.

ESMT

M12L32162A

Elite Semiconductor Memory Technology Inc. Publication Date : Mar. 2009

Revision : 1.2 3/29

DQ0 ~ 15 Data Input / Output Data inputs/outputs are multiplexed on the same pins.

VDD/VSS Power Supply/Ground Power and ground for the input buffers and the core logic.

VDDQ/VSSQ Data Output Power/Ground Isolated power supply and ground for the output buffers to provide improved

noise immunity.

N.C/RFU No Connection/

Reserved for Future Use This pin is recommended to be left No Connection on the device.

ABSOLUTE MAXIMUM RATINGS

Parameter Symbol Value Unit

Voltage on any pin relative to VSS VIN,VOUT -1.0 ~ 4.6 V

Voltage on VDD supply relative to VSS VDD,VDDQ -1.0 ~ 4.6 V

Storage temperature TSTG -55 ~ + 150 C°

Power dissipation PD 0.7 W

Short circuit current IOS 50 mA

Note: Permanent device damage may occur if ABSOLUTE MAXIMUM RATINGS are exceeded.

Functional operation should be restricted to recommended operating condition.

Exposure to higher than recommended voltage for extended periods of time could affect device reliability.

DC OPERATING CONDITIONS

Recommended operating conditions (Voltage referenced to VSS = 0V, TA=0 to 70 C° )

Parameter Symbol Min Typ Max Unit Note

Supply voltage VDD,VDDQ 3.0 3.3 3.6 V

Input logic high voltage VIH 2.0 3.0 VDD+0.3 V 1

Input logic low voltage VIL -0.3 0 0.8 V 2

Output logic high voltage VOH 2.4 - - V IOH =-2mA

Output logic low voltage VOL - - 0.4 V IOL = 2mA

Input leakage current IIL -5 - 5 uA 3

Output leakage current IOL -5 - 5 uA 4

Note : 1.VIH (max) = 4.6V AC for pulse width ≤ 10ns acceptable.

2.VIL (min) = -1.5V AC for pulse width ≤ 10ns acceptable.

3.Any input 0V ≤ VIN ≤ VDD, all other pins are not under test = 0V.

4.Dout is disabled, 0V ≤ VOUT ≤ V

DD.

CAPACITANCE (VDD = 3.3V, TA = 25 C° , f = 1MHz)

Pin Symbol Min Max Unit

CLOCK CCLK 2.5 4.0 pF

RAS , CAS , WE , CS , CKE, LDQM,

UDQM CIN 2.5 5.0 pF

ADDRESS CADD 2.5 5.0 pF

DQ0 ~DQ15 COUT 4.0 6.5 pF

ESMT

M12L32162A

Elite Semiconductor Memory Technology Inc. Publication Date : Mar. 2009

Revision : 1.2 4/29

DC CHARACTERISTICS

(Recommended operating condition unless otherwise noted, TA = 0 to 70 C° VIH(min)/VIL(max)=2.0V/0.8V)

Version

Parameter Symbol Test Condition CAS

Latency -5.5 -6 -7 Unit Note

Operating Current

(One Bank Active) ICC1 Burst Length = 1

tRC ≥ tRC (min), tCC ≥ tCC (min), IOL= 0mA 150 140 100 mA 1

ICC2P CKE ≤VIL(max), tCC =15ns 2

Precharge Standby

Current in power-down

mode ICC2PS CKE ≤VIL(max), CLK

≤

VIL(max), tCC =

∞

2 mA

ICC2N CKE ≥VIH(min), CS ≥VIH(min), tCC =15ns

Input signals are changed one time during 30ns

25 mA

Precharge Standby

Current in non

power-down mode

ICC2NS

CKE ≥VIH(min), CLK

≤

VIL(max), tCC =

∞

Input signals are stable 15 mA

ICC3P CKE ≤VIL(max), tCC =15ns 10

Active Standby Current

in power-down mode ICC3PS CKE ≤ VIL(max), CLK

≤

VIL(max), tCC =

∞

10 mA

ICC3N CKE ≥VIH(min), CS ≥ VIH(min), tCC=15ns

Input signals are changed one time during 2clks

All other pins ≥ V

DD-0.2V or

≤

0.2V

25 mA

Active Standby Current

in non power-down

mode

(One Bank Active)

ICC3NS CKE ≥VIH (min), CLK

≤

VIL(max), tCC=

∞

Input signals are stable 15 mA

3 150 140 120 1

Operating Current

(Burst Mode) ICC4

IOL= 0mA, Page Burst

All Band Activated, tCCD = tCCD (min)

2 150 140 120

mA

Refresh Current ICC5 tRC ≥tRC(min) 150 140 120

mA 2

Self Refresh Current ICC6 CKE ≤0.2V 1 mA

Note: 1.Measured with outputs open. Addresses are changed only one time during tCC(min).

2.Refresh period is 64ms. Addresses are changed only one time during tCC(min).

ESMT

M12L32162A

Elite Semiconductor Memory Technology Inc. Publication Date : Mar. 2009

Revision : 1.2 5/29

AC OPERATING TEST CONDITIONS (VDD=3.3V ±0.3V,TA= 0 to 70 C°)

Parameter Value Unit

Input levels (Vih/Vil) 2.4 / 0.4 V

Input timing measurement reference level 1.4 V

Input rise and fall time tr / tf = 1 / 1 ns

Output timing measurement reference level 1.4 V

Output load condition See Fig.2

OPERATING AC PARAMETER

(AC operating conditions unless otherwise noted)

Version

Parameter Symbol -5.5 -6 -7 Unit Note

Row active to row active delay tRRD(min) 11 12 14 ns 1

RAS to CAS delay tRCD(min) 16.5 18 20 ns 1

Row precharge time tRP(min) 16.5 18 20 ns 1

tRAS(min) 33 36 42 ns 1

Row active time tRAS(max) 100 us

Row cycle time tRC(min) 60 60 63 ns 1

Last data in to new col. Address delay tCDL(min) 1 CLK 2

Last data in to row precharge tRDL(min) 2 CLK 2

Last data in to burst stop tBDL(min) 1 CLK 2

Col. Address to col. Address delay tCCD(min) 1 CLK 3

Refresh period (4,096 rows) tREF(max) 64 ms 5

CAS latency=3 2

Number of valid output data CAS latency=2 1 ea 4

Note: 1. The minimum number of clock cycles is determined by dividing the minimum time required with clock cycle time and

then rounding off to the next higher integer.

2. Minimum delay is required to complete write.

3. All parts allow every cycle column address change.

4. In case of row precharge interrupt, auto precharge and read burst stop.

The earliest a precharge command can be issued after a Read command without the loss of data is CL+BL-2 clocks.

5. A maximum of eight consecutive AUTO REFRESH commands (with tRFCmin) can be posted to any given SDRAM, and

the maximum absolute interval between any AUTO REFRESH command and the next AUTO REFRESH command is

8x15.6 μs.)

3.3V

Output

(Fig.2) AC Output Load Circuit

30 pF

Vtt =1.4V

VOH(DC) = 2.4V, IOH = -2mA

VOL(DC) = 0.4V, IOL = 2mA

30 pF

Output

(Fig.1) DC Output Load circuit

Z0=50 Ω

870 Ω

1200 Ω

50 Ω

ESMT

M12L32162A

Elite Semiconductor Memory Technology Inc. Publication Date : Mar. 2009

Revision : 1.2 6/29

AC CHARACTERISTICS (AC operating conditions unless otherwise noted)

-5.5 -6 -7

Parameter Symbol Min Max Min Max Min Max Unit Note

CAS Latency =3 5.5 6 7

CLK cycle time CAS Latency =2 tCC 10 1000 10 1000 10 1000 ns 1

CAS Latency =3 6 5.5 6

CLK to valid

output delay CAS Latency =2 t

SAC 6 5.5 6

ns 1

Output data hold time tOH 2 2 2.5 ns 2

CLK high pulse width tCH 2 2 2.5 ns 3

CLK low pulse width tCL 2 2 2.5 ns 3

Input setup time tSS 2 2 2 ns 3

Input hold time tSH 2 2 2 ns 3

CLK to output in Low-Z tSLZ 0 0 0 ns 2

CAS Latency =3 6 5.5 6

CLK to output in

Hi-Z CAS latency =2

t

SHZ

6 5.5 6

ns

*All AC parameters are measured from half to half.

Note: 1.Parameters depend on programmed CAS latency.

2.If clock rising time is longer than 1ns,(tr/2-0.5)ns should be added to the parameter.

3.Assumed input rise and fall time (tr & tf)=1ns.

If tr & tf is longer than 1ns, transient time compensation should be considered, i.e., [(tr+ tf)/2-1]ns should be added to the

parameter.

-5.5

Parameter Symbol Min Max Unit Note

CAS Latency =3 5.5

CLK to valid

output delay CAS Latency =2 tSAC 5.5

ns 4

Output data hold time tOH 2 ns 4

CAS Latency =3 5.5

CLK to output in

Hi-Z CAS Latency =2

tSHZ

5.5

ns 4

Note: 4. Special condition (Output Load ≤ 10 ohm+10 pF)

ESMT

M12L32162A

Elite Semiconductor Memory Technology Inc. Publication Date : Mar. 2009

Revision : 1.2 7/29

MODE REGISTER FIELD TABLE TO PROGRAM MODES

Register Programmed with MRS

Address BA A11~A10/AP A9 A8 A7 A6 A5 A4 A3 A2 A1 A0

Function RFU RFU W.B.L TM CAS Latency BT Burst Length

Test Mode CAS Latency Burst Type Burst Length

A8 A7 Type A6 A5 A4 Latency A3 Type A2 A1 A0 BT = 0 BT = 1

0 0 Mode Register Set 0 0 0 Reserved 0 Sequential 0 0 0 1 1

0 1 Reserved 0 0 1 Reserved 1 Interleave 0 0 1 2 2

1 0 Reserved 0 1 0 2 0 1 0 4 4

1 1 Reserved 0 1 1 3

0 1 1 8 8

Write Burst Length 1 0 0 Reserved 1 0 0 Reserved Reserved

A9 Length 1 0 1 Reserved 1 0 1 Reserved Reserved

0 Burst 1 1 0 Reserved 1 1 0 Reserved Reserved

1 Single Bit 1 1 1 Reserved

1 1 1 Full Page Reserved

Full Page Length : 256

Note : 1. RFU(Reserved for future use) should stay “0” during MRS cycle.

2. If A9 is high during MRS cycle, “Burst Read Single Bit Write” function will be enabled.

3. The full column burst (256 bit) is available only at sequential mode of burst type.

ESMT

M12L32162A

Elite Semiconductor Memory Technology Inc. Publication Date : Mar. 2009

Revision : 1.2 8/29

Burst Length and Sequence

(Burst of Two)

Starting Address

(column address A0 binary)

Sequential Addressing

Sequence (decimal)

Interleave Addressing

Sequence (decimal)

0 0,1 0,1

1 1,0 1,0

(Burst of Four)

Starting Address

(column address A1-A0, binary)

Sequential Addressing

Sequence (decimal)

Interleave Addressing

Sequence (decimal)

00 0,1,2,3 0,1,2,3

01 1,2,3,0 1,0,3,2

10 2,3,0,1 2,3,0,1

11 3,0,1,2 3,2,1,0

(Burst of Eight)

Starting Address

(column address A2-A0, binary)

Sequential Addressing

Sequence (decimal)

Interleave Addressing

Sequence (decimal)

000 0,1,2,3,4,5,6,7 0,1,2,3,4,5,6,7

001 1,2,3,4,5,6,7,0 1,0,3,2,5,4,7,6

010 2,3,4,5,6,7,0,1 2,3,0,1,6,7,4,5

011 3,4,5,6,7,0,1,2 3,2,1,0,7,6,5,4

100 4,5,6,7,0,1,2,3 4,5,6,7,0,1,2,3

101 5,6,7,0,1,2,3,4 5,4,7,6,1,0,3,2

110 6,7,0,1,2,3,4,5 6,7,4,5,2,3,0,1

111 7,0,1,2,3,4,5,6 7,6,5,4,3,2,1,0

Full page burst is an extension of the above tables of Sequential Addressing, with the length being 256 for 2Mx16 divice.

POWER UP SEQUENCE

1.Apply power and start clock, attempt to maintain CKE= “H”, L(U)DQM = “H” and the other pin are NOP condition at the inputs.

2.Maintain stable power, stable clock and NOP input condition for a minimum of 200us.

3.Issue precharge commands for all banks of the devices.

4.Issue 2 or more auto-refresh commands.

5.Issue mode register set command to initialize the mode register.

Cf.)Sequence of 4 & 5 is regardless of the order.

The device is now ready for normal operation.

ESMT

M12L32162A

Elite Semiconductor Memory Technology Inc. Publication Date : Mar. 2009

Revision : 1.2 9/29

SIMPLIFIED TRUTH TABLE

COMMAND CKEn-1 CKEn CS RAS CAS WE DQM BA A10/AP A11

A9~A0 Note

Register Mode Register Set H X L L L L X OP CODE 1,2

Auto Refresh H 3

Entry H L L L L H X X 3

L H H H 3

Refresh Self Refresh Exit L H H X X X X X

3

Bank Active & Row Addr. H X L L H H X V Row Address

Auto Precharge Disable L 4

Read &

Column Address Auto Precharge Enable

H X L H L H X V

H

Column

Address

(A0~A7) 4,5

Auto Precharge Disable L 4

Write & Column

Address Auto Precharge Enable

H X L H L L X V

H

Column

Address

(A0~A7) 4,5

Burst Stop H X L H H L X X 6

Bank Selection V L 4

Precharge Both Banks H X L L H L X

X H X 4

H X X X

Entry H L L V V V X

Clock Suspend or

Active Power Down Exit L H X X X X X

X

H X X X

Entry H L L H H H X

H X X X

Precharge Power Down Mode

Exit L H L V V V X

X

DQM H X V X 7

H H X X X

No Operation Command H X L H H H

X X

(V= Valid, X= Don’t Care, H= Logic High , L = Logic Low)

Note:

1.OP Code: Operation Code

A0~ A11, BA: Program keys.(@MRS)

2.MRS can be issued only at both banks precharge state.

A new command can be issued after 2 clock cycle of MRS.

3.Auto refresh functions are as same as CBR refresh of DRAM.

The automatical precharge without row precharge command is meant by “Auto”.

Auto / self refresh can be issued only at both banks idle state.

4.BA: Bank select address.

If “Low”: at read, write, row active and precharge, bank A is selected.

If “High”: at read, write, row active and precharge, bank B is selected.

If A10/AP is “High” at row precharge, BA ignored and both banks are selected.

5.During burst read or write with auto precharge, new read/write command can not be issued.

Another bank read /write command can be issued after the end of burst.

New row active of the associated bank can be issued at tRP after the end of burst.

6.Burst stop command is valid at every burst length.

7.DQM sampled at positive going edge of a CLK masks the data-in at the very CLK (Write DQM latency is 0), but makes

Hi-Z state the data-out of 2 CLK cycles after. (Read DQM latency is 2)

ESMT

M12L32162A

Elite Semiconductor Memory Technology Inc. Publication Date : Mar. 2009

Revision : 1.2 10/29

Single Bit Read-Write-Read Cycle (Same Page) @CAS Latency=3, Burst Length=1

: D o n ' t C a r e

0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19

CLOCK

CKE

CS

RAS

CAS

ADDR

WE

DQ

DQM

A10/AP

tCH

tCL

tCC

Row Active

BA

*Note1

HIGH

tRCD

tSS

tSH

tSS

tSH

tSS

tSH

tSS

tSH

Ra Ca Cb Cc Rb

BS

BSBS

BS

BSBS

Ra

Qa Db Qc

Rb

Read Write Read

Precharge

Row Active

tRC

tRAS

tRP

tCCD

tRAC

*Note2 *Note2,3 *Note4 *Note2

*Note2,3

*Note 3 *Note 3

*Note2,3

tSH

tSLZ

tSAC

tOH

tSH

tSHtSS

*Note4*Note 3

ESMT

M12L32162A

Elite Semiconductor Memory Technology Inc. Publication Date : Mar. 2009

Revision : 1.2 11/29

*Note: 1. All inputs expect CKE & DQM can be don’t care when CS is high at the CLK high going edge.

2. Bank active & read/write are controlled by BA.

BA Active & Read/Write

0 Bank A

1 Bank B

3.Enable and disable auto precharge function are controlled by A10/AP in read/write command.

A10/AP BA Operation

0 Disable auto precharge, leave bank A active at end of burst. 0

1 Disable auto precharge, leave bank B active at end of burst.

0 Enable auto precharge, precharge bank A at end of burst. 1

1 Enable auto precharge, precharge bank B at end of burst.

4.A10/AP and BA control bank precharge when precharge command is asserted.

A10/AP BA precharge

0 0 Bank A

0 1 Bank B

1 X Both Banks

ESMT

M12L32162A

Elite Semiconductor Memory Technology Inc. Publication Date : Mar. 2009

Revision : 1.2 12/29

Power Up Sequence

0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19

CLOCK

CKE

ADDR

DQ

DQM

A10/AP

tRP

Key RAa

RAa

Precharge

All Banks

Auto Refresh Auto Refresh Mode Register Set

(A-Bank)

Row Active

: Don't care

tRC tRC

High level is necessary

BA

High-Z

CS

RAS

CAS

WE

Key

ESMT

M12L32162A

Elite Semiconductor Memory Technology Inc. Publication Date : Mar. 2009

Revision : 1.2 13/29

Read & Write Cycle at Same Bank @Burst Length = 4

t

RCD

t

RC

0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19

CLOCK

CKE

CS

RAS

CAS

ADDR

DQM

BA

CL=2

CL=3

Ra Rb Cb0

t

OH

t

SAC

t

SHZ

t

SHZ

t

RDL

Read

(A-Bank)

Row Active Precharge

(A-Bank)

Precharge

(A-Bank) (A-Bank)

Write

(A-Bank)

Row Active

(A-Bank)

*Note3

*Note4

:Don'tcare

*Note1

Qa0 Qa1 Qa2 Qa3 Db0 Db3

Db1 Db2

Qa0 Qa1 Qa2 Qa3 Db0 Db3

Db1 Db2

t

RAC

t

RAC

t

RDL

Ca0

A10/AP

Ra Rb

HIGH

*Note2

WE

t

OH

t

SAC

QC

*Note: 1.Minimum row cycle times is required to complete internal DRAM operation.

2.Row precharge can interrupt burst on any cycle. [CAS Latency-1] number of valid output data is available after Row

precharge. Last valid output will be Hi-Z(tSHZ) after the clock.

3.Access time from Row active command. tcc*(tRCD +CAS latency-1)+tSAC

4.Ouput will be Hi-Z after the end of burst.(1,2,4,8 bit burst)

Burst can’t end in Full Page Mode.

ESMT

M12L32162A

Elite Semiconductor Memory Technology Inc. Publication Date : Mar. 2009

Revision : 1.2 14/29

Page Read & Write Cycle at Same Bank @ Burst Length=4

*Note :1.To write data before burst read ends, DQM should be asserted three cycle prior to write command to avoid bus

contention.

2.Row precharge will interrupt writing. Last data input, tRDL before Row precharge, will be written.

3.DQM should mask invalid input data on precharge command cycle when asserting precharge before end of burst.

Input data after Row precharge cycle will be masked internally.

CLOCK

CKE

CS

RAS

CAS

BA

ADDR

A10/AP

CL=2

CL=3

WE

DQM

HIGH

tRCD

*Note2

Ra Ca0 Cb0 Cc0 Cd0

Ra

Qa0 Qa1 Qb0 Qb1 Qb2 Dc0 Dc1 Dd0 Dd1

Qa0 Qa1 Qb0 Qb1 Dc0 Dc1 Dd0 Dd2

tCDL

*Note1

Row Active

(A-Bank)

Read

(A-Bank)

Read

(A-Bank)

Write

(A-Bank)

Write

(A-Bank)

Precharge

(A-Bank)

: Don't care

DQ

0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19

tRDL

*Note3

ESMT

M12L32162A

Elite Semiconductor Memory Technology Inc. Publication Date : Mar. 2009

Revision : 1.2 15/29

Page Read Cycle at Different Bank @ Burst Length=4

*Note: 1. CS can be don’t cared when RAS , CAS and WE are high at the clock high going dege.

2.To interrupt a burst read by row precharge, both the read and the precharge banks must be the same.

CLOCK

CKE

CS

RAS

CAS

BA

ADDR

A10/AP

CL=2

CL=3

WE

DQM

HIGH

*Note2

RAa CAa RBb

RAa

Read

(A-Bank)

Row Active

(B-Bank)

(A-Bank)

Read

(A-Bank)

Read

(B-Bank)

Read

(A-Bank)

Read

(B-Bank)

Precharge

(A-Bank)

: Don't care

DQ

CBb CAc CBd CAe

QAa0

*Note1

RBb

0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19

QAa1 QAa2 QAa3 QBb0 QBb1 QBb2 QBb3 QAc0 QAc1 QBd0 QBd1 QAe0 QAe1

QAa0 QAa1 QAa2 QAa3 QBb0 QBb1 QBb2 QBb3 QAc0

QAc1 QBd0 QBd1 QAe0 QAe1

ESMT

M12L32162A

Elite Semiconductor Memory Technology Inc. Publication Date : Mar. 2009

Revision : 1.2 16/29

Page Write Cycle at Different Bank @Burst Length = 4

*Note: 1.To interrupt burst write by Row precharge, DQM should be asserted to mask invalid input data.

2.To interrupt burst write by row precharge, both the write and the precharge banks must be the same.

CLOCK

CKE

CS

RAS

CAS

BA

ADDR

A10/AP

WE

DQM

HIGH

Row Active

(A-Bank) Row Active

(B-Bank)

Write

(A-Bank)

Precharge

(Both Banks)

: Don't care

DQ

Write

(A-Bank) Write

(B-Bank)

Write

(B-Bank)

DAa0 DAa1 DAa2 DAa3 DBb0 DBb1 DBb2 DBb3 DAc0 DAc1 DBd0 DBd1

RAa RBb

RAa CAa RBb CBb CAc CBd

*Note2

tCDL tRDL

*Note1

0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19

ESMT

M12L32162A

Elite Semiconductor Memory Technology Inc. Publication Date : Mar. 2009

Revision : 1.2 17/29

Read & Write Cycle at Different Bank @ Burst Length = 4

*Note: 1.tCDL should be met to complete write.

ESMT

M12L32162A

Elite Semiconductor Memory Technology Inc. Publication Date : Mar. 2009

Revision : 1.2 18/29

Read & Write Cycle with auto Precharge @ Burst Length =4

*Note: 1.tCDL Should be controlled to meet minimum tRAS before internal precharge start

(In the case of Burst Length=1 & 2 and BRSW mode)

0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19

CLOCK

CKE

CAS

ADDR

WE

DQ

DQM

A10/AP

BA

CL=2

CL=3

Row Active

( A - Bank )

Row Active

( B - Bank )

Read with

Auto Precharge

( A - Bank )

Auto Precharge

Start Point

(B-Bank)

: D o n ' t C a r e

Qa1 Qa2 Qa3 Db1 Db2 Db3

Db0Qa0

Ra

Cb

Ra CaRb

Rb

Qa1 Qa2 Qa3 Db1 Db2 Db3

Db0

Qa0

W rite with

Auto Precharge

(B-Bank)

HIGH

Auto Precharge

Start Point

( A - Bank)

CS

RAS

ESMT

M12L32162A

Elite Semiconductor Memory Technology Inc. Publication Date : Mar. 2009

Revision : 1.2 19/29

Clock Suspension & DQM Operation Cycle @CAS Latency=2, Burst Length=4

*Note:1.DQM is needed to prevent bus contention.

CLOCK

CKE

ADDR

DQ

DQM

A10/AP

Ra Ca Cb Cc

Ra

Qa0 Qa1 Qa2 Qa3

tSHZ

Qb1

Qb0

tSHZ

Dc0 Dc2

*Note1

Row Active Read Clock

Suspension Read

Read DQM Write

Write

DQM

Clock

Suspension

Write

DQM

:Don't Care

BA

CS

RAS

CAS

WE

0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19

ESMT

M12L32162A

Elite Semiconductor Memory Technology Inc. Publication Date : Mar. 2009

Revision : 1.2 20/29

Read Interrupted by Precharge Command & Read Burst Stop Cycle @Burst Length =Full page

*Note: 1.Burst can’t end in full page mode, so auto precharge can’t issue.

2.About the valid DQs after burst stop, it is same as the case of RAS interrupt.

Both cases are illustrated above timing diagram. See the label 1,2 on them.

But at burst write, burst stop and RAS interrupt should be compared carefully.

Refer the timing diagram of “Full page write burst stop cycle”.

3.Burst stop is valid at every burst length.

CLOCK

CKE

ADDR

DQ

DQM

A10/AP

BA

RAa CAa CAb

RAa

QAa0 QAa1 QAb1

QAb0 QAb2

*Note1

Row Active

(A-Bank)

Read

(A-Bank)

Burst Stop Read

(A-Bank)

:Don't Care

HIGH

CL=2

CL=3

QAa2 QAa3 QAa4 QAb3 QAb4 QAb5

QAa0 QAa1 QAb1

QAb0 QAb2

QAa2 QAa3 QAa4 QAb3 QAb4 QAb5

11

22

Precharge

(A-Bank)

0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19

CS

RAS

CAS

WE

*Note2

ESMT

M12L32162A

Elite Semiconductor Memory Technology Inc. Publication Date : Mar. 2009

Revision : 1.2 21/29

Write Interrupted by Precharge Command & Write Burst stop Cycle @ Burst Length =Full page

*Note: 1. Burst can’t end in full page mode, so auto precharge can’t issue.

2.Data-in at the cycle of interrupted by precharge can not be written into the corresponding memory cell. It is defined by

AC parameter of tRDL.

DQM at write interrupted by precharge command is needed to prevent invalid write.

Input data after Row precharge cycle will be masked internally.

3.Burst stop is valid at every burst length.

CLOCK

CKE

ADDR

DQ

DQM

A10/AP

RAa CAa CAb

RAa

DAa0 DAa1 DAb1DAb0 DAb2

Row Active

(A-Bank)

Write

(A-Bank)

Burst Stop Write

(A-Bank)

:Don't Care

HIGH

DAa2 DAa3 DAa4 DAb3 DAb4 DAb5

Precharge

(A-Bank)

tBDL tRDL

*Note2

CS

RAS

CAS

WE

BA

0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19

ESMT

M12L32162A

Elite Semiconductor Memory Technology Inc. Publication Date : Mar. 2009

Revision : 1.2 22/29

Burst Read Single bit Write Cycle @Burst Length=2

*Note:1.BRSW modes is enabled by setting A9 “High” at MRS(Mode Register Set).

At the BRSW Mode, the burst length at write is fixed to “1” regardless of programmed burst length.

2.When BRSW write command with auto precharge is executed, keep it in mind that tRAS should not be violated.

Auto precharge is executed at the next cycle of burst-end, so in the case of BRSW write command, the precharge

command will be issued after two clock cycles.

CLOCK

CKE

ADDR

CL=2

DQM

A10/AP

BA

RAa RAc

RAa

QAb0

Row Active

(A-Bank)

Write

(A-Bank)

:Don't Care

HIGH

QAb1

Precharge

(A-Bank)

CAa RBb CAb CBc CAd

RAc

DBc0

DQ

DAa0 QAb0 DBc0

QAb1

CL=3

Row Active

(B-Bank)

Row Active

(A-Bank)

Write with

Auto Precharge

(B-Bank)

Read

(A-Bank)

DAa0 QAd0 QAd1

QAd0 QAd1

*Note1

CS

RAS

CAS

WE

RBb

*Note2

Read with

Auto Precharge

(A-Bank)

ESMT

M12L32162A

Elite Semiconductor Memory Technology Inc. Publication Date : Mar. 2009

Revision : 1.2 23/29

Active/Precharge Power Down Mode @CAS Latency=2, Burst Length=4

*Note :1.Both banks should be in idle state prior to entering precharge power down mode.

2.CKE should be set high at least 1CLK+tss prior to Row active command.

3.Can not violate minimum refresh specification. (64ms)

CLOCK

CKE

ADDR

DQ

DQM

A10/AP

Active

Power-down

Exit

Precharge

: Don't care

*Note3

*Note2

*Note1

tSS

Ra

Qa0 Qa1 Qa2

tSHZ

Precharge

Power-Down

Entry Precharge

Power-Down

Exit

Row Active

Active

Power-down

Entry

Read

0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19

Ca

BA

RAS

CAS

CS

WE

tSS tSS

ESMT

M12L32162A

Elite Semiconductor Memory Technology Inc. Publication Date : Mar. 2009

Revision : 1.2 24/29

Self Refresh Entry & Exit Cycle

*Note: TO ENTER SELF REFRESH MODE

1. CS , RAS & CAS with CKE should be low at the same clock cycle.

2. After 1 clock cycle, all the inputs including the system clock can be don’t care except for CKE.

3. The device remains in self refresh mode as long as CKE stays “Low”.

cf.) Once the device enters self refresh mode, minimum tRAS is required before exit from self refresh.

TO EXIT SELF REFRESH MODE

4. System clock restart and be stable before returning CKE high.

5. CS Starts from high.

6. Minimum tRC is required after CKE going high to complete self refresh exit.

7. 4K cycles of burst auto refresh is required immediately before self refresh entry and immediately after self refresh

exit.

CLOCK

CKE

ADDR

DQ

DQM

A10/AP

Self Refresh Entry Auto Refresh

: Don't care

Self Refresh Exit

Hi-Z Hi-Z

WE

BA

CAS

RAS

CS

*Note2

*Note1

*Note4 tRCmin

*Note6

*Note5

*Note7

0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19

tSS

*Note3

ESMT

M12L32162A

Elite Semiconductor Memory Technology Inc. Publication Date : Mar. 2009

Revision : 1.2 25/29

Mode Register Set Cycle Auto Refresh Cycle

*Both banks precharge should be completed before Mode Register Set cycle and auto refresh cycle.

MODE REGISTER SET CYCLE

*Note: 1. CS , RAS , CAS & WE activation at the same clock cycle with address key will set internal mode register.

2.Minimum 2 clock cycles should be met before new RAS activation.

3.Please refer to Mode Register Set table.

CLOCK

CKE

ADDR Key

:Don't Care

HIGH

CS

RAS

CAS

HIGH

*Note3

Ra

*Note1

DQ Hi-Z

DQM

1 2 3 4 5 6 0 1 2 3 4 5 6 7 8 9 10

Hi-Z

*Note2 tRC

MRS New Command Auto Refresh New Command

WE

0

ESMT

M12L32162A

Elite Semiconductor Memory Technology Inc. Publication Date : Mar. 2009

Revision : 1.2 26/29

PACKING DIMENSIONS

54-LEAD TSOP(II) SDRAM (400mil) (1:3)

Symbol Dimension in mm Dimension in inch

Min Norm Max Min Norm Max

A

1.20 0.047

A1 0.05 0.10 0.15 0.002 0.004 0.006

A2 0.95 1.00 1.05 0.037 0.039 0.041

b 0.25

0.45 0.010 0.018

b1 0.25 0.35 0.40 0.010 0.014 0.016

c 0.12

0.21 0.005 0.008

c1 0.10 0.127 0.16 0.004 0.005 0.006

D 22.22 BSC 0.875 BSC

E 11.76 BSC 0.463 BSC

E1 10.16 BSC 0.400 BSC

L 0.40 0.50 0.60 0.016 0.020 0.024

L1 0.80 REF 0.031 REF

e 0.80 BSC 0.031 BSC

Θ 0° 10° 0° 10°

O

L

DETAIL "A"

SECTION B-B

B

0.10

-C-

D

E

E1

e

PLANE

SEATING

1

L

127

28

54 A2

A

-H-

b

DETAIL A

-C-

IDENTIFIER

-C-

SEE

b

c

1

0.665 REF

0.21 REF

A1

PIN1

ESMT

M12L32162A

Elite Semiconductor Memory Technology Inc. Publication Date : Mar. 2009

Revision : 1.2 27/29

PACKING DIMENSIONS

54-BALL SDRAM ( 8x8 mm )

Symbol Dimension in mm Dimension in inch

Min Norm Max Min Norm Max

A

1.00

0.039

A1 0.20 0.25 0.30 0.008 0.010 0.012

A2 0.61 0.66 0.71 0.024 0.026 0.028

Φb 0.30 0.35 0.40 0.012 0.014 0.016

D 7.90 8.00 8.10 0.311 0.315 0.319

E 7.90 8.00 8.10 0.311 0.315 0.319

D1

6.40

0.252

E1

6.40

0.252

e

0.80

0.031

Controlling dimension : Millimeter.

ESMT

M12L32162A

Elite Semiconductor Memory Technology Inc. Publication Date : Mar. 2009

Revision : 1.2 28/29

Revision History

Revision Date Description

0.1 2006.08.11 Original

0.2 2007.03.20 Add BGA package

0.3 2007.04.27

Rename BGA pin name (BA1 to NC; BA0 to BA)

Modify DC Characteristics

0.4 2007.09.28 add speed –5 sepc.

1.0 2007.10.08 Delete “Preliminary”

1.1 2008.08.19

1. Move Revision History to the last

2. Add -6 spec

1.2 2009.03.27

1.Add the specification of tREF

2.Modify the description about self refresh operation

3.Add speed grade -5.5 and delete speed grade -5

4.Modify the specification of tRC (min) for speed grade -6

5.Modify the test condition of IIL

6.Correct typo error

ESMT

M12L32162A

Elite Semiconductor Memory Technology Inc. Publication Date : Mar. 2009

Revision : 1.2 29/29

Important Notice

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any means without the prior permission of ESMT.

The contents contained in this document are believed to be accurate at the

time of publication. ESMT assumes no responsibility for any error in this

document, and reserves the right to change the products or specification in

this document without notice.

The information contained herein is presented only as a guide or examples

for the application of our products. No responsibility is assumed by ESMT for

any infringement of patents, copyrights, or other intellectual property rights of

third parties which may result from its use. No license, either express ,

implied or otherwise, is granted under any patents, copyrights or other

intellectual property rights of ESMT or others.

Any semiconductor devices may have inherently a certain rate of failure. To

minimize risks associated with customer's application, adequate design and

operating safeguards against injury, damage, or loss from such failure,

should be provided by the customer when making application designs.

ESMT's products are not authorized for use in critical applications such as,

but not limited to, life support devices or system, where failure or abnormal

operation may directly affect human lives or cause physical injury or property

damage. If products described here are to be used for such kinds of

application, purchaser must do its own quality assurance testing appropriate

to such applications.