FAN1851AM - Fairchild Semiconductor

www.fairchildsemi.com

REV. 2.0.1 6/17/05

Features

• Improved performance over industry equivalents

– Tight fault current range (Typ ±100µA)

– Temperature compensated fault current characteristics

– No external trimming required

• Direct interface to SCR

• Supply voltage derived from AC line—26V shunt

• Adjustable sensitivity

• Grounded neutral fault de tection

• Meets UL943 standards

• 450µA quiescent current

• Ideal for 120V or 220V systems

• Package options: 8L DIP and 8L SOIC

Description

The FAN1851A is a controller for AC outlet ground fault

interrupters. These devices detect hazardous grounding con-

ditions (example: a pool of water or an electrical equipment

connected to opposite phases of the AC line) in consumer

and industrial env iron ments. The ou tput of the IC triggers an

external SCR, which in turn opens a relay circuit breaker to

prevent a harmful or lethal shock.

Full advantage of the U.S. UL943 timin g s pecification is

taken to ensure maximum im munity to false triggering due

to line noise. A special feature in the circuitry rapidly resets

the integrating timing capacitor in the event that noise pulses

introduce unwanted charging currents. Also, a flip-flop is

included that ensures firing of even a slow circuit breaker

relay on either of the two half-cycles of the line voltage

when external full wave rectification is u sed .

The application circuit can be configured to detect both

normal faults (hot wire to ground) and grounded neutral

faults.

Block Diagram

+VS

Timing

Capacitor

Sensitivity

Set Resistor

ITH

Sense Amplifier

Output

ITH for IF > 0

3ITH for IF = 0

Latch

D3 I2

Ground

Non-Inverting Input

10V

Inverting Input

SCR Trigger

+VS

FAN1851A

Ground Fault Interrupter

FAN1851A PRODUCT SPECIFICATION

2REV. 2.0.1 6/17/05

Functional Description

The voltage at the supply pin is clamped to +26V by the

internal shunt regulator D3. This shunt regulator also

generates an artificial ground voltage for the noninverting

input of A1 (shown as a +10V source). A1, Q1, and Q2

together act as a current mirror for fault current signals

(which are derived from an external transformer). When a

fault signal is present, the mirrored current charges the

external timing capacitor until its voltage exceeds th e latch

trigger threshold (typically 17.5V). When this threshold is

exceeded, the latch engages and Q3 turns off, allowing I2 to

drive the SCR connected to the "SCR Trigger" pin.

Extra Circuitry in the feedback path of A1 works with the

switched current source I1 to remove any charge on CT

induced by noise in the transformer. If no fault current is

present, then I1 discharges CT with a current equal to 3 ITH,

where ITH is the value of current set by the external RSET

resistor. If fault signals are present at the input of A1 (which

is held at virtual ground, +10V), one of the two current

mirrors in the feedback path of A1 (Q4 and Q5) will become

active, depending on which half-cycle the fault occurs.

This action will raise the voltage at VS, switching I1 to a

value equal to ITH, and reducing the discharge rate of CT to

better allow fault currents to charge it.

Notice that ITH discharges CT during both half-cycles of the

line, while IF only char ges CT during the half-cycle in which

IF exits the "- Input" pin (since Q1 will only carry fault cur-

rent in one direction). Thus, during one half-cycle, IF-ITH

charge s CT, while during the oth er half-cyc le ITH discharges

it.

Pin Assignments

SCR Trigger

– Input

+ Input

Ground

+VS

RSET

Amp Out

Definition of Terms

Normal Fault:

An unintentional electrical path, RB, between the load termi-

nal of the hot line and the ground, as shown by the dashed

lines in Figure1 .

Figure 1. Normal Fault

Grounded Neutral Fault:

An unintentional electrical path between the load terminal of

the neutral line and the ground, as shown by the dashed lines

in Figure 2.

Figure 2. Grounded Neutral Fault

Hot

GFI

Neutral

Line

Hot

RLOAD RB

Neutral

Hot

GFI

Neutral

Line

Hot

RLOAD

RIN

Neutral

PRODUCT SPECIFICATION FAN1851A

REV. 2.0.1 6/17/05 3

Normal Fault Plus Grounded Neutral Fault:

The combination of the normal fault and the grounded

neut ral fault, as shown by t he da shed lines in Figure 3.

Figure 3. Normal Fault Plus Grounded Neutral Fault

Absolute Maximum Ratings

Thermal Characteristics

Parameter Conditions Min Max Units

Supply Current 19 mA

Power Dissipation 570 mW

Operating Temperature -40 70 °C

Lead Soldering Temperature, 60 seconds 300 °C

Parameter Conditions Min Max Units

Maximum Junction Temperature 125 °C

Maximum PDTA < 50°C 468 mW

Thermal Resistance, θJA DIP 85 °C/W

SOIC 150

Hot

GFI

Neutral

Line

Hot

LOAD

Neutral

FAN1851A PRODUCT SPECIFICATION

4REV. 2.0.1 6/17/05

DC Electrical Characteristics

(TA = +25°C, ISHUNT = 5 mA)

Note:

1. This external applied current is in addition to the internal “output drive current” source.

AC Electrical Characteristics

(TA = +25°C, ISHUNT = 5 mA)

Notes:

1. Average of ten trials.

2. Required UL System sensitivity tolerance is 4mA to 6mA.

Parameters Test Conditions Min Typ Max Units

Power Supply Shunt Regulator

Voltage

Pin 8, Average Value 22 26 30 V

Latch Trigger Voltage Pin 7 15 17.5 20 V

Sensitivity Set Voltage Pin 8 to Pin 6 6 7 8.2 V

Output Drive Current Pin 1 With Fault 0.5 1 2.4 mA

Output Saturation Voltage Pin 1 Without Fault 100 240 mV

Output Saturation Resistance Pin 1 Without Fault 100 Ω

Output External Current Sinking

Capability1

Pin 1 Without Fault, VPIN1 Held

to 0.3V

25 mA

Noise Integration Sink Current

Ratio

Pin 7, Ratio of Discharge Currents

Between No Fault and Fault

Conditions

2.0 2.8 3.6 µA/µA

Parameters Conditions Min Typ Max Units

Normal Fault Current Sensitivity2See Figure 9 4.75 5 5.25 mA

Normal Fault Trip Time1500Ω Fault, see Figure 10 18 mS

Normal Fault With Grounded 500Ω Normal Fault, 18 mS

Neutral Fault Trip Time12Ω Neutral, see Figure 10 (Note 1)

PRODUCT SPECIFICATION FAN1851A

REV. 2.0.1 6/17/05 5

Typical Performance Characteristics (TA = +25°C)

Figure 4. Average Trip Time vs. Fault Current Figure 5. Normal Fault Current Threshold vs. RSET

Figure 6. Output Drive Current vs. Output Voltage Figure 7. Pin 1 Saturation Voltage vs.

External Load Current, IL

0.01 0.1 1

1000

100

Trip Time (Seconds)

Fault Current (mA)

Circuit of

Figure 10

UL943

Normal

Fault

10 100K 1M 10M

100

RSET (Ω)

Fault Current on Line [mA(rms)]

IF (rms)* x (0.91)

Sense Transformer 1000:1

RSET =

1400

1200

1000

800

600

400

200

Output Voltage @ VPIN1(V)

Output Drive Current @ Pin 1 (μA)

35302520151050

5 mA

31V

1 mA

VPIN1

0.1 1 10 100

0.1

0.01

External Load Current (mA)

Pin 1 Saturation Voltage (V)

5 mA 31V

1 mA

FAN1851A PRODUCT SPECIFICATION

6REV. 2.0.1 6/17/05

Application Information

A typical ground fault int errupter circuit is shown in

Figure 10. It is des igned to opera te on 120 VAC line voltag e

with 5mA normal fault sens itivity.

A full-wave rectifier bridge an d a 15kΩ/2W resistor are used

to supply the DC power required by the IC. A 1 µF capacitor

at the "+VS" pin is used to filter the ripple of the supply volt-

age and is also connected across the SC R to allow firing of

the SCR on either h alf-cycle. When a f ault causes the SCR to

trigger, the circuit breaker is energized and line voltage is

removed from the load.

At this time no fault current flows and the CT discharge cur-

rent increases from ITH to 3ITH (see Block Diagram). This

quickly resets both the timing capacitor and the output latch.

The circuit breaker can be reset and the line voltage again

supplied to the load, assu ming the fault has been removed.

A 1000:1 sense transformer is used to detect the normal

fault. The fault current, which is basically the difference in

current between the hot and neutral l ines, is s tepped down b y

1000 and fed into the input pin of the operational amplif ier

through a 10µF capacitor. The 0.0033µF capacitor between

the "- Input" pin and the "+ Input" pin and the 200pF capaci-

tor between "+ In put" an d "Ground " pins are add ed to obt ain

better noise immunity. The normal fault sensitivity is deter-

mined by the timing capacitor discharging current, ITH. ITH

can be calculated by:

(1)

At the decision point, the average fault current just equals

the threshold current, ITH.

(2)

Where IF(rms) is the rms input fault current to th e ope ra-

tional amplifier and the factor of 2 is due to the fact that IF

charges the timing capacitor only during one half-cycle,

while ITH discharges the capacitor continuously. The factor

0.91 converts the rms value to an average value. Combining

equations (1) and (2) we have:

(3)

For example, to obtain 5mA(rms) sensitivity for the circuit

in Figure 7 we have:

(4)

RSET

-------------

÷=

rms

()

------------------- 0 .9

×=

SET

IFrms()0.9

--------------------------------

----

RSET

5 mA 0.91×

1000

------------------------------

------------------------------ 1.5 M Ω==

The correct value for RSET can also be determined from the

characteristic curve that plots equation (3). Note that th is is

an approximate calcu lation; the exact value of RSET depends

on the specific sense transformer used and FAN1851A toler-

ances. Inasmuch as UL943 specifies a sensitivity “window”

of 4mA to 6mA, a provision should be made to adjust RSET

with a potentiometer.

Independent of setting sensitivity, the desired integration

time can be obtained through proper selection of the timing

capacitor , CT. Due to the large number of variables involved,

proper selection of CT is best done empirically. The follow-

ing design example should only be used as a guideline.

Assume the goal is to meet UL943 timing requirements.

Also assume that worst case timing occurs during GFI

start-up (S1 closure) with both a heavy normal fault and a

2Ω grounded neutral fault present. This situation is shown in

Figure 8.

Figure 8. Example

UL943 specifies ≤ 25ms average trip time under these con di-

tions. Calculation of CT based upon char ging currents due t o

normal fault only is as follows :

1. Start with a ≤ 25ms specification. Subtract 3ms GFI

turn-on time (15kΩ and 1µF). Subtract 8ms potential

loss of one half -cycle due to fault current sense of

half-cycles only.

2. Subtract 4ms time required to open a sluggish circuit

breaker.

3. Thi s gives a total ≤ 10ms maximum integration time

that could be allowed.

4. To generate 8ms value of integration time that accom-

modates component tolerances and other variables:

(5)

Line

Neutral

Hot

GFI

Hot

Neutral

500

500 (0.2)I

(0.8)I

0.4

--------

---

PRODUCT SPECIFICATION FAN1851A

REV. 2.0.1 6/17/05 7

where:

T = integration time

V = threshold voltage

I = average fault current into CT

(6)

therefore:

(7)

120 VAC rms()

-------------------------------------

⎝⎠

⎛⎞

RG RN+

----------------------

⎝⎠

⎛⎞

heavy fault

current generated

(swamps ITH)

portion of fault

current shunted

around GFI

1 turn

1000 turns

-------------------------

⎝⎠

⎛⎞

---

⎝⎠

⎛⎞

0.91()×××

current

division of

input sense

transformer

charging

on half-

cycles

only

rms to

average

conversion

120

500

---------

⎝⎠

⎛⎞ 0.4

1.6 0.4+

---------------------

⎝⎠

⎛⎞

×1

1000

------------

⎝⎠

⎛⎞

×1

---

⎝⎠

⎛⎞

×0.91()×

17.5

------------------------------------------------------------------------------------------------------------------0.00

×=

CT0.01 µF=

In practice, the actual value of CT will have to be modified

to include the effects of the neutral loop upon the net charg-

ing current. T he ef fect of ne utral loop induced currents is dif-

ficult to quantify, but typically they sum with normal fault

currents, thus allowing a larger value of CT. For UL943

requirements, 0.015µF has been found to be the best com-

promise between timing and noise.

For those GFI standards not requiring grounded neutral

detection, a still larger value capacity can be used and better

noise immunity obtained . The lar ger cap acitor can be accom-

modated because RN and RG are not present, allowing the

full fault current, I, to enter the GFI.

In Figure 10, grounded neutral detection is accomplished by

feeding th e neutral co il with 12 0Hz ener gy contin uously an d

allowing some of the energy to couple into the sense trans-

former during conditions of neutral fault .

Transformers may be obtained from Magnetic Metals, Inc.,

(http://www.magmet.com).

FAN1851A PRODUCT SPECIFICATION

8REV. 2.0.1 6/17/05

Application Circuits

Figure 9. Normal Fault Sensitivity Test Circuit

Figure 10. 120 Hz Neutral Transformer Application

FAN1851A

Timing

Cap

-In

+In

SCR

Trigger

Op Amp

Output

SET

GND

0.047 μF

100K

SHUNT

0.002

300 mV

1.5M

31V

800 Hz

FAN1851A

Timing

Cap

–In

+In

SCR

Trigger

Op Amp

Output

+VS

RSET

GND

RSET*

Line

Sense

Coil

1.0 μF Tant

200 pF

10 μF

Tant

0.01

0.015

0.01/400V

Gnd/Neutral

Coil

200:1

High μ Coil

MOV

Hot

Neutral

Load

0.01/400V

15K/2W

SCR

*Adjust RSET for desired sensitivity.

1000:1

0.0033

Circuit

Breaker

FAN1851A PRODUCT SPECIFICATION

9REV. 2.0.1 6/17/05

Mechanical Dimensions

8-Lead Plastic DIP Package

Dimensions in Millimeters

6.40 ±0.20

3.30 ±0.30

0.130 ±0.012

3.40 ±0.20

0.134 ±0.008

#4 #5

0.252 ±0.008

9.20 ±0.20

0.79

2.54

0.100

0.031

()

0.46 ±0.10

0.018 ±0.004

0.060 ±0.004

1.524 ±0.10

0.362 ±0.008

9.60

0.378 MAX

5.08

0.200

0.33

0.013

7.62

0~15°

0.300

MAX

MIN

0.25

+0.10

–0.05

0.010

+0.004

–0.002

FAN1851A PRODUCT SPECIFICATION

10 REV. 2.0.1 6/17/05

Mechanical Dimensions (continued)

8-Lead Plastic SOIC Package

– C –

ccc C

LEAD COPLANARITY

SEATING

PLANE

h x 45°

A .053 .069 1.35 1.75

Symbol Inches

Min. Max. Min. Max.

Millimeters Notes

A1 .004 .010 0.10 0.25

.020 0.51

B .013 0.33

C .008 .010 0.20 0.25

E .150 .158 3.81 4.01

.228 .244 5.79 6.20

.010 .020 0.25 0.50

.050 BSC 1.27 BSC

L .016 .050 0.40 1.27

0°8°0°8°

N8 8

ccc .004 0.10——

D .189 .197 4.80 5.00

Notes:

Dimensioning and tolerancing per ANSI Y14.5M-1982.

"D" and "E" do not include mold flash. Mold flash or

protrusions shall not exceed .010 inch (0.25mm).

"L" is the length of terminal for soldering to a substrate.

Terminal numbers are shown for reference only.

"C" dimension does not include solder finish thickness.

Symbol "N" is the maximum number of terminals.

FAN1851A PRODUCT SPECIFICATION

LIFE SUPPORT POLICY

FAIRCHILD’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES

OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD SEMICONDUCTOR

CORPORATION. As used herein:

1. Life support devices or systems are devices or systems

which, (a) are intended for surgical implant into the body,

or (b) support or sustain life, and (c) whose failure to

perform when properly used in accordance with

instructions for use provided in the labeling, can be

reasonably expected to result in a significant injury of the

user.

2. A critical component in any component of a life support

device or system whose failure to perform can be

reasonably expected to cause the failure of the life support

device or system, or to affect its safety or effectiveness.

www.fairchildsemi.com

REV. 2.0.1 6/17/05

DISCLAIMER

FAIRCHILD SEMICONDUCTOR RESERVES THE RIGHT TO MAKE CHANGES WITHOUT FURTHER NOTICE TO

ANY PRODUCTS HEREIN TO IMPROVE RELIABILITY, FUNCTION OR DESIGN. FAIRCHILD DOES NOT ASSUME

ANY LIABILITY ARISING OUT OF THE APPLICATION OR USE OF ANY PRODUCT OR CIRCUIT DESCRIBED HEREIN;

NEITHER DOES IT CONVEY ANY LICENSE UNDER ITS PATENT RIGHTS, NOR THE RIGHTS OF OTHERS.

Ordering Information

Part Number Package Pb-Free Operating Temperature Range Packing Method

FAN1851AN 8-lead Plastic DIP Yes -40°C to +70°C Rail

FAN1851AMX 8-lead Plastic SOIC Yes -40°C to +70°C Tape and Reel