1
Data sheet acquired from Harris Semiconductor
SCHS205C
Features
• Typical Propagation Delay: 6ns at VCC = 5V,
CL = 15pF, TA = 25oC
• High-to-Low Voltage Level Converter for up to Vl= 16V
• Fanout (Over Temperature Range)
- Standard Outputs. . . . . . . . . . . . . . . 10 LSTTL Loads
- Bus Driver Outputs . . . . . . . . . . . . . 15 LSTTL Loads
• Wide Operating T emperature Range . . .–55oC to 125oC
• Balanced Propagation Delay and Transition Times
• Significant Power Reduction Compared to LSTTL
Logic ICs
• HC Types
- 2V to 6V Operation
- High Noise Immunity: NIL = 30%, NIH = 30%of VCC at
VCC = 5V
Description
The ’HC4049 and ’HC4050 are fabricated with high-speed
silicon gate technology. They have a modified input
protection structure that enables these parts to be used as
logic level translators which convert high-level logic to a low-
level logic while operating off the low-level logic supply. For
example, 15-V input pulse levels can be down-converted to
0-V to 5-V logic levels. The modified input protection
structure protects the input from negative electrostatic
discharge. These parts also can be used as simple buffers
or inverters without level translation. The ’HC4049 and
’HC4050 are enhanced versions of equivalent CMOS types.
Pinout
CD54HC4049, CD54HC4050
(CERDIP)
CD74HC4049, CD74HC4050
(PDIP, SOIC, SOP, TSSOP)
TOP VIEW
Ordering Information
PART NUMBER TEMP. RANGE
(oC) PACKAGE
CD54HC4049F3A –55 to 125 16 Ld CERDIP
CD74HC4049E –55 to 125 16 Ld PDIP
CD74HC4049M –55 to 125 16 Ld SOIC
CD74HC4049NSR –55 to 125 16 Ld SOP
CD54HC4050F3A –55 to 125 16 Ld CERDIP
CD74HC4050E –55 to 125 16 Ld PDIP
CD74HC4050M –55 to 125 16 Ld SOIC
CD74HC4050NSR –55 to 125 16 Ld SOP
CD74HC4050PW –55 to 125 16 Ld TSSOP
NOTES:
1. When ordering, use the entire part number. Add the suffix 96 to
the M suffix or the R suffix to the PW package to obtain the
variant in the tape and reel.
2. Wafer and die is available which meets all electrical
specifications. Please contact your local TI sales office or
customer service for ordering information.
14
15
16
9
13
12
11
10
1
2
3
4
5
7
6
8
VCC
1Y
1A
2Y
2A
3Y
GND
3A
NC
6A
NC
5Y
5A
4Y
4A
6Y
4049 4050 4050 4049
VCC
1Y
1A
2Y
2A
3Y
GND
3A
NC
6A
NC
5Y
5A
4Y
4A
6Y
February 1998 - Revised March 2002
CAUTION: These devices are sensitive to electrostatic discharge. Users should follow proper IC Handling Procedures.
Copyright © 2002,Texas Instruments Incorporated
CD54/74HC4049,
CD54/74HC4050
High-Speed CMOS Logic
Hex Buffers, Inverting and Non-Inverting
[ /Title
(CD74H
C4049,
CD74H
C4050)
/
Sub-
j
ect
(High
Speed
CMOS
Logic
Hex
2
Functional Diagram
1A
1Y
2Y
3A
3Y
GND
1
2
3
4
5
6
16
14
13
12
NC
5A
4Y
5Y
6A
NC
11
9
710
4A
2A
VCC
8
15 6Y
4050 4049 4049 4050
1Y
2Y
3Y
6Y
NC
5Y
Logic Diagrams
HC4049 HC4050
A Y AY
CD54/74HC4049, CD54/74HC4050
3
Absolute Maximum Ratings Thermal Information
DC Supply Voltage, VCC . . . . . . . . . . . . . . . . . . . . . . . . –0.5V to 7V
DC Input Diode Current, IIK
For VI < –0.5V or VI > VCC + 0.5V . . . . . . . . . . . . . . . . . . . . .±20mA
DC Output Diode Current, IOK
For VO < –0.5V or VO > VCC + 0.5V. . . . . . . . . . . . . . . . . . . .±20mA
DC Output Source or Sink Current per Output Pin, IO
For VO > –0.5V or VO < VCC + 0.5V. . . . . . . . . . . . . . . . . . . .±25mA
DC VCC or Ground Current, ICC or IGND . . . . . . . . . . . . . . . . . .±50mA
Operating Conditions
Temperature Range (TA) . . . . . . . . . . . . . . . . . . . . .–55oC to 125oC
Supply Voltage Range, VCC
HC Types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2V to 6V
HCT Types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4.5V to 5.5V
DC Input or Output Voltage, VI, VO . . . . . . . . . . . . . . . . . 0V to VCC
Input Rise and Fall Time
2V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1000ns (Max)
4.5V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 500ns (Max)
6V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 400ns (Max)
Package Thermal Impedance, θJA (see Note 3):
PDIP Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .67oC/W
SOIC Package. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .73oC/W
SOP Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64oC/W
TSSOP Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108oC/W
Maximum Junction Temperature (Hermetic Pac kage or Die) . . . 175oC
Maximum Junction Temperature (Plastic Package) . . . . . . . . 150oC
Maximum Storage Temperature Range . . . . . . . . . –65oC to 150oC
Maximum Lead Temperature (Soldering 10s). . . . . . . . . . . . . 300oC
(SOIC - Lead Tips Only)
CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation
of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
NOTE:
3. The package thermal impedance is calculated in accordance with JESD 51-7.
VCC
Vl+7V
+16V
VOLTAGE
RELATIONSHIPS
MAXIMUM LIMITS
DC Electrical Specifications
PARAMETER SYMBOL
TEST
CONDITIONS VCC
(V)
25oC –40oC TO 85oC–55oC TO
125oC
UNITSVI(V) IO(mA) MIN TYP MAX MIN MAX MIN MAX
HC TYPES
High Level Input
Voltage VIH - - 2 1.5 - - 1.5 - 1.5 - V
4.5 3.15 - - 3.15 - 3.15 - V
6 4.2 - - 4.2 - 4.2 - V
Low Level Input
Voltage VIL - - 2 - - 0.5 - 0.5 - 0.5 V
4.5 - - 1.35 - 1.35 - 1.35 V
6 - - 1.8 - 1.8 - 1.8 V
High Level Output
Voltage
CMOS Loads
VOH VIH or VIL –0.02 2 1.9 - - 1.9 - 1.9 - V
–0.02 4.5 4.4 - - 4.4 - 4.4 - V
–0.02 6 5.9 - - 5.9 - 5.9 - V
High Level Output
Voltage
TTL Loads
–4 4.5 3.98 - - 3.84 - 3.7 - V
–5.2 6 5.48 - - 5.34 - 5.2 - V
Low Level Output
Voltage
CMOS Loads
VOL VIH or VIL 0.02 2 - - 0.1 - 0.1 - 0.1 V
0.02 4.5 - - 0.1 - 0.1 - 0.1 V
0.02 6 - - 0.1 - 0.1 - 0.1 V
Low Level Output
Voltage
TTL Loads
4 4.5 - - 0.26 - 0.33 - 0.4 V
5.2 6 - - 0.26 - 0.33 - 0.4 V
Input Leakage
Current IIVCC or
GND -6--±0.1 - ±1-±1µA
15 - 6 - - ±0.5 - ±5-±5
Quiescent Device
Current ICC VCC or
GND 0 6 - - 2 - 20 - 40 µA
NOTE: For dual-supply systems theoretical worst case (VI = 2.4V, VCC = 5.5V) specification is 1.8mA.
CD54/74HC4049, CD54/74HC4050
4
Switching Specifications Input tr, tf = 6ns
PARAMETER SYMBOL TEST
CONDITIONS VCC (V)
25oC–40oC TO
85oC–55oC TO
125oC
UNITSMIN TYP MAX MIN MAX MIN MAX
HC TYPES
Propagation Delay,
nA to nY HC4049
nA to nY HC4050
tPLH, tPHL CL= 50pF 2 - - 85 - 105 - 130 ns
4.5 - - 17 - 21 - 26 ns
6 - - 14 - 18 - 22 ns
CL= 15pF 5 - 6 - - - - - ns
Transition Times (Figure 1) tTLH, tTHL CL= 50pF 2 - - 75 - 95 - 110 ns
4.5 - - 15 - 19 - 22 ns
6 - - 13 - 16 - 19 ns
Input Capacitance CI- - - - 10 - 10 - 10 pF
Power Dissipation Capacitance
(Notes 4, 5) CPD -5-35-----pF
NOTES:
4. CPD is used to determine the dynamic power consumption, per gate.
5. PD = VCC2 fi(CPD + CL) where fi = Input Frequency, CL = Output Load Capacitance, VCC = Supply Voltage.
Test Circuit and Waveform
FIGURE 1. HC AND HCU TRANSITION TIMES AND PROPAGATION DELAY TIMES, COMBINATION LOGIC
tPHL tPLH
tTHL tTLH
90%
50%
10%
50%
10%
INVERTING
OUTPUT
INPUT
GND
VCC
tr = 6ns tf = 6ns
90%
CD54/74HC4049, CD54/74HC4050
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