M1S25664DSH8C1G / M1S12864DSH4C1G M1N25664DSH8C1G (GREEN) 256MB and 128MB PC2700 Unbuffered DDR SO-DIMM 200 pin Unbuffered DDR SO-DIMM Based on DDR333 256M bit C Die device Features * 200-Pin Small Outline Dual In-Line Memory Module (SO-DIMM) * Address and control signals are fully synchronous to positive * Unbuffered DDR SO-DIMM based on DDR 256Mbit die C device, clock edge organized as 16Mx16 using Nanya's 110nm technology * Programmable Operation: * Performance: - DIMM CAS Latency: 2/2.5(6K) - Burst Type: Sequential or Interleave PC2700 Speed Sort 6K DIMM CAS Latency 2.5 fCK Clock Frequency tCK Clock Cycle fDQ DQ Burst Frequency - Burst Length: 2, 4, 8 Unit - Operation: Burst Read and Write 166 MHz 6 ns 333 MHz * Auto Refresh (CBR) and Self Refresh Modes * Automatic and controlled precharge commands * 7.8 s Max. Average Periodic Refresh Interval * Serial Presence Detect EEPROM * Intended for 166 MHz applications * Gold contacts * Inputs and outputs are SSTL-2 compatible * SDRAMs are packaged in TSOP packages * VDD = VDDQ = 2.5V 0.2V (DDR333 devices) * SDRAMs have 4 internal banks for concurrent operation * Differential clock inputs * Data is read or written on both clock edges * DRAM DLL aligns DQ and DQS transitions with clock transitions Description M1S25664DSH8C1G, M1S12864DSH4C1G and M1N25664DSH8C1G are unbuffered 200-Pin Double Data Rate (DDR) Synchronous DRAM Small Outline Dual In-Line Memory Modules (SO-DIMM). M1S12864DSH4C1G is 128MB module, organized as a single rank using four 16Mx16 TSOP devices. M1S25664DSH8C1G and M1N25664DSH8C1G are 256MB modules, organized as dual ranks using eight 16Mx16 TSOP devices. Depending on the speed grade, these SO-DIMMs are intended for use in applications operating up to 166 MHz clock speeds and achieves high-speed data transfer rates of up to 333 MHz. Prior to any access operation, the device CAS latency and burst type/ length/operation type must be programmed into the SO-DIMM by address inputs and I/O inputs BA0 and BA1 using the mode register set cycle. The DDR SO-DIMM uses a serial EEPROM and through the use of a standard IIC protocol the serial presence-detect implementation (SPD) can be accessed. The first 128 bytes of the SPD data are programmed with the module characteristics as defined by JEDEC. REV 1.0 July 19, 2005 1 (c) NANYA TECHNOLOGY CORPORATION NANYA reserves the right to change products and specifications without notice. M1S25664DSH8C1G / M1S12864DSH4C1G M1N25664DSH8C1G (GREEN) Unbuffered DDR SO-DIMM Ordering Information Part Number Organization M1S25664DSH8C1G-6K 32Mx64 M1S12864DSH4C1G-6K 16Mx64 Speed DDR333 PC2700 2.5-3-3 M1N25664DSH8C1G-6K 166MHz (6ns @ CL = 2.5) 32Mx64 Power Leads 2.5V Gold Note Green For the closest sales office or information, please visit: www.elixir-memory.com Nanya Technology Corporation Hwa Ya Technology Park 669 Fu Hsing 3rd Rd., Kueishan, Taoyuan, 333, Taiwan, R.O.C. Tel: +886-3-328-1688 REV 1.0 July 19, 2005 2 (c) NANYA TECHNOLOGY CORPORATION NANYA reserves the right to change products and specifications without notice. M1S25664DSH8C1G / M1S12864DSH4C1G M1N25664DSH8C1G (GREEN) Unbuffered DDR SO-DIMM Pin Description CK0, CK1, CK2, Differential Clock Inputs. DQ0-DQ63 Data input/output CKE0, CKE1 Clock Enable DQS0-DQS7 Bidirectional data strobes RAS Row Address Strobe DM0-DM7 Input Data Mask CAS Column Address Strobe VDD Power CK0, CK1, CK2 WE Write Enable VDDQ Supply voltage for DQs S0, S1 Chip Selects VSS Ground A0-A9, A11, A12 Address Inputs NC No Connect A10/AP Address Input/Auto-precharge SCL Serial Presence Detect Clock Input BA0, BA1 SDRAM Bank Address Inputs SDA Serial Presence Detect Data input/output VREF Ref. Voltage for SSTL_2 inputs SA0-2 Serial Presence Detect Address Inputs VDDID VDD Identification flag. VDDSPD Serial EEPROM positive power supply Pinout Pin Front Pin Front Pin Back Pin Front Pin Back Pin Front Pin Back 1 VREF Pin Back 2 VREF 51 VSS 52 VSS 101 A9 102 A8 151 DQ42 152 DQ46 3 VSS 4 VSS 53 DQ19 54 DQ23 103 VSS 104 VSS 153 DQ43 154 DQ47 5 DQ0 6 DQ4 55 DQ24 56 DQ28 105 A7 106 A6 155 VDD 156 VDD 7 DQ1 8 DQ5 57 VDD 58 VDD 107 A5 108 A4 157 VDD 158 CK1 9 VDD 10 VDD 59 DQ25 60 DQ29 109 A3 110 A2 159 VSS 160 CK1 11 DQS0 12 DM0 61 DQS3 62 DM3 111 A1 112 A0 161 VSS 162 VSS 13 DQ2 14 DQ6 63 VSS 64 VSS 113 VDD 114 VDD 163 DQ48 164 DQ52 15 VSS 16 VSS 65 DQ26 66 DQ30 115 A10/AP 116 BA1 165 DQ49 166 DQ53 17 DQ3 18 DQ7 67 DQ27 68 DQ31 117 BA0 118 RAS 167 VDD 168 VDD 19 DQ8 20 DQ12 69 VDD 70 VDD 119 WE 120 CAS 169 DQS6 170 DM6 21 VDD 22 VDD 71 NC 72 NC 121 S0 122 S1 171 DQ50 172 DQ54 23 DQ9 24 DQ13 73 NC 74 NC 123 DU 124 DU 173 VSS 174 VSS 25 DQS1 26 DM1 75 VSS 76 VSS 125 VSS 126 VSS 175 DQ51 176 DQ55 27 VSS 28 VSS 77 DQS8 78 NC 127 DQ32 128 DQ36 177 DQ56 178 DQ60 29 DQ10 30 DQ14 79 NC 80 NC 129 DQ33 130 DQ37 179 VDD 180 VDD 31 DQ11 32 DQ15 81 VDD 82 VDD 131 VDD 132 VDD 181 DQ57 182 DQ61 33 VDD 34 VDD 83 NC 84 NC 133 DQS4 134 DM4 183 DQS7 184 DM7 35 CK0 36 VDD 85 DU 86 DU 135 DQ34 136 DQ38 185 VSS 186 VSS 37 CK0 38 VSS 87 VSS 88 VSS 137 VSS 138 VSS 187 DQ58 188 DQ62 39 VSS 40 VSS 89 CK2 90 VSS 139 DQ35 140 DQ39 189 DQ59 190 DQ63 41 DQ16 42 DQ20 91 CK2 92 VDD 141 DQ40 142 DQ44 191 VDD 192 VDD 43 DQ17 44 DQ21 93 VDD 94 VDD 143 VDD 144 VDD 193 SDA 194 SA0 45 VDD 46 VDD 95 CKE1 96 CKE0 145 DQ41 146 DQ45 195 SCL 196 SA1 47 DQS2 48 DM2 97 DU 98 DU 147 DQS5 148 DM5 197 VDDSPD 198 SA2 49 DQ18 50 DQ22 99 A12 100 A11 149 VSS 150 VSS 199 VDDID 200 DU Note: All pin assignments are consistent for all 8-byte unbuffered versions. REV 1.0 July 19, 2005 3 (c) NANYA TECHNOLOGY CORPORATION NANYA reserves the right to change products and specifications without notice. M1S25664DSH8C1G / M1S12864DSH4C1G M1N25664DSH8C1G (GREEN) Unbuffered DDR SO-DIMM Input/Output Functional Description Symbol CK0, CK1, CK2, CK0, CK1, CK2 CKE0, CKE1 Type (SSTL) (SSTL) Polarity Cross point Active High Function The system clock inputs. All address and command lines are sampled on the cross point of the rising edge of CK and falling edge of CK. A Delay Locked Loop (DLL) circuit is driven from the clock inputs and output timing for read operations is synchronized to the input clock. Activates the DDR SDRAM CK signal when high and deactivates the CK signal when low. By deactivating the clocks, CKE low initiates the Power Down mode or the Self Refresh mode. Enables the associated DDR SDRAM command decoder when low and disables the (SSTL) Active Low command decoder when high. When the command decoder is disabled, new commands are RAS, CAS, WE (SSTL) Active Low When sampled at the positive rising edge of the clock, RAS, CAS, WE define the operation to VREF Supply S0, S1 ignored but previous operations continue. Physical Bank 0 is selected by S0; Bank 1 is selected by S1. VDDQ Supply BA0, BA1 (SSTL) be executed by the SDRAM. Reference voltage for SSTL-2 inputs Isolated power supply for the DDR SDRAM output buffers to provide improved noise immunity - Selects which SDRAM bank is to be active. During a Bank Activate command cycle, these lines define the row address when sampled at the rising clock edge. During a Read or Write command cycle, these lines defines the column address when A0 - A9 A10/AP A11 - A13 sampled at the rising clock edge. In addition to the column address, AP is used to invoke (SSTL) - auto-precharge operation at the end of the Burst Read or Write cycle. If AP is high, auto-precharge is selected and BA0/BA1 defines the bank to be precharged. If AP is low, auto-precharge is disabled. During a Precharge command cycle, AP is used in conjunction with BA0/BA1 to control which bank(s) to precharge. If AP is high all 4 banks will be precharged regardless of the state of BA0/BA1. If AP is low, then BA0/BA1 are used to define which bank to pre-charge. DQ0 - DQ63 (SSTL) - DQS0 - DQS8 (SSTL) Active High CB0 - CB7 (SSTL) - DM0 - DM8 Input Active High VDD, VSS Supply SA0 - SA2 - SDA - SCL - VDDSPD REV 1.0 July 19, 2005 Supply Data and Check Bit input/output pins operate in the same manner as on conventional DRAMs. Data strobes: Output with read data, input with write data. Edge aligned with read data, centered on write data. Used to capture write data. DQS8 is used for ECC modules (CB0-CB7) and is not used on x64 modules. Data Check Bit Input/Output pins. Used on ECC modules and is not used on x64 modules. The data write masks, associated with one data byte. In Write mode, DM operates as a byte mask by allowing input data to be written if it is low but blocks the write operation if it is high. In Read mode, DM lines have no effect. DM8 is associated with check bits CB0-CB7, and is not used on x64 modules. Power and ground for the DDR SDRAM input buffers and core logic Address inputs. Connected to either VDD or VSS on the system board to configure the Serial Presence Detect EEPROM address. This bi-directional pin is used to transfer data into or out of the SPD EEPROM. A resistor must be connected from the SDA bus line to VDD to act as a pull-up. This signal is used to clock data into and out of the SPD EEPROM. A resistor may be connected from the SCL bus time to VDD to act as a pull-up. Serial EEPROM positive power supply. 4 (c) NANYA TECHNOLOGY CORPORATION NANYA reserves the right to change products and specifications without notice. M1S25664DSH8C1G / M1S12864DSH4C1G M1N25664DSH8C1G (GREEN) Unbuffered DDR SO-DIMM Functional Block Diagram 256MB, 2 Ranks, 8 devices, 16Mx16 DDR SDRAMs S1 S0 DQS0 DM0 DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 LDQS DQS1 DM1 DQ8 DQ9 DQ10 DQ11 DQ12 DQ13 DQ14 DQ15 UDQS CS LDM I/O 0 I/O 1 I/O 2 I/O 3 I/O 4 I/O 5 I/O 6 I/O 7 DQS2 DM2 DQ16 DQ17 DQ18 DQ19 DQ20 DQ21 DQ22 DQ23 LDQS DQS3 DM3 DQ24 DQ25 DQ26 DQ27 DQ28 DQ29 DQ30 DQ31 UDQS D0 UDQS D4 UDM I/O 8 I/O 9 I/O 10 I/O 11 I/O 12 I/O 13 I/O 14 I/O 15 CS LDM I/O 0 I/O 1 I/O 2 I/O 3 I/O 4 I/O 5 I/O 6 I/O 7 LDQS CS LDM I/O 0 I/O 1 I/O 2 I/O 3 I/O 4 I/O 5 I/O 6 I/O 7 D1 UDM I/O 8 I/O 9 I/O 10 I/O 11 I/O 12 I/O 13 I/O 14 I/O 15 UDQS D5 UDM I/O 8 I/O 9 I/O 10 I/O 11 I/O 12 I/O 13 I/O 14 I/O 15 BA0-BA1 : SDRAMs D0-D7 RAS RAS : SDRAMs D0-D7 CAS CAS : SDRAMs D0-D7 CKE0 CKE : SDRAMs D0-D3 CKE1 CKE : SDRAMs D4-D7 WE WE : SDRAMs D0-D7 July 19, 2005 LDQS DQS5 DM5 DQ40 DQ41 DQ42 DQ43 DQ44 DQ45 DQ46 DQ47 UDQS CS LDQS LDM I/O 0 I/O 1 I/O 2 I/O 3 I/O 4 I/O 5 I/O 6 I/O 7 D2 UDQS UDM I/O 8 I/O 9 I/O 10 I/O 11 I/O 12 I/O 13 I/O 14 I/O 15 DQS6 DM6 DQ48 DQ49 DQ50 DQ51 DQ52 DQ53 DQ54 DQ55 LDQS DQS7 DM7 DQ56 DQ57 DQ58 DQ59 DQ60 DQ61 DQ62 DQ63 UDQS CS LDQS D3 UDQS CK0 CK0 CK2 A1 A2 SA0 SA1 SA2 SDA D7 UDM I/O 8 I/O 9 I/O 10 I/O 11 I/O 12 I/O 13 I/O 14 I/O 15 CK1 A0 CS LDM I/O 0 I/O 1 I/O 2 I/O 3 I/O 4 I/O 5 I/O 6 I/O 7 UDM I/O 8 I/O 9 I/O 10 I/O 11 I/O 12 I/O 13 I/O 14 I/O 15 Serial PD SCL WP D6 UDM I/O 8 I/O 9 I/O 10 I/O 11 I/O 12 I/O 13 I/O 14 I/O 15 LDM I/O 0 I/O 1 I/O 2 I/O 3 I/O 4 I/O 5 I/O 6 I/O 7 SPD D0-D7 D0-D7 D0-D7 CS LDM I/O 0 I/O 1 I/O 2 I/O 3 I/O 4 I/O 5 I/O 6 I/O 7 CK1 DQ wiring may differ from that described in this drawing. DQ/DQS/DM/CKE/S relationships are maintained as shown. DQ/DQS/DM/DQS resistors are 22+/- 5% Ohms. VDDID strap connections (for memory device VDD, VDDQ): STRAP OUT (OPEN): VDD = VDDQ STRAP IN (VSS): VDD is not equal to VDDQ. REV 1.0 DQS4 DM4 DQ32 DQ33 DQ34 DQ35 DQ36 DQ37 DQ38 DQ39 VDDSPD VDD/VDDQ VREF VSS VDDID A0-A12 : SDRAMs D0-D7 A0-A12 Notes : 1. 2. 3. 4. CS LDM I/O 0 I/O 1 I/O 2 I/O 3 I/O 4 I/O 5 I/O 6 I/O 7 UDM I/O 8 I/O 9 I/O 10 I/O 11 I/O 12 I/O 13 I/O 14 I/O 15 BA0-BA1 LDQS CK2 4 loads 4 loads 0 loads 5 (c) NANYA TECHNOLOGY CORPORATION NANYA reserves the right to change products and specifications without notice. M1S25664DSH8C1G / M1S12864DSH4C1G M1N25664DSH8C1G (GREEN) Unbuffered DDR SO-DIMM Functional Block Diagram 128MB, 1 Rank, 4 devices, 16Mx16 DDR SDRAMs S0 DQS0 DM0 DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 LDQS DQS1 DM1 DQ8 DQ9 DQ10 DQ11 DQ12 DQ13 DQ14 DQ15 UDQS CS LDM I/O 0 I/O 1 I/O 2 I/O 3 I/O 4 I/O 5 I/O 6 I/O 7 D0 UDM I/O 8 I/O 9 I/O 10 I/O 11 I/O 12 I/O 13 I/O 14 I/O 15 DQS2 DM2 DQ16 DQ17 DQ18 DQ19 DQ20 DQ21 DQ22 DQ23 LDQS DQS3 DM3 DQ24 DQ25 DQ26 DQ27 DQ28 DQ29 DQ30 DQ31 UDQS CS LDM I/O 0 I/O 1 I/O 2 I/O 3 I/O 4 I/O 5 I/O 6 I/O 7 D1 UDM I/O 8 I/O 9 I/O 10 I/O 11 I/O 12 I/O 13 I/O 14 I/O 15 BA0-BA1 BA0-BA1 : SDRAMs D0-D3 RAS RAS : SDRAMs D0-D3 CAS CAS : SDRAMs D0-D3 CKE0 CKE : SDRAMs D0-D3 CKE1 N.C. WE Notes : 1. 2. 3. 4. WE : SDRAMs D0-D3 July 19, 2005 DQS5 DM5 DQ40 DQ41 DQ42 DQ43 DQ44 DQ45 DQ46 DQ47 UDQS CS LDM I/O 0 I/O 1 I/O 2 I/O 3 I/O 4 I/O 5 I/O 6 I/O 7 D2 UDM I/O 8 I/O 9 I/O 10 I/O 11 I/O 12 I/O 13 I/O 14 I/O 15 DQS6 DM6 DQ48 DQ49 DQ50 DQ51 DQ52 DQ53 DQ54 DQ55 LDQS DQS7 DM7 DQ56 DQ57 DQ58 DQ59 DQ60 DQ61 DQ62 DQ63 UDQS CS LDM I/O 0 I/O 1 I/O 2 I/O 3 I/O 4 I/O 5 I/O 6 I/O 7 D3 UDM I/O 8 I/O 9 I/O 10 I/O 11 I/O 12 I/O 13 I/O 14 I/O 15 SPD D0-D3 D0-D3 D0-D3 CK0 CK0 CK1 CK1 Serial PD SCL WP DQ wiring may differ from that described in this drawing. DQ/DQS/DM/CKE/S relationships are maintained as shown. DQ/DQS/DM/DQS resistors are 22+/- 5% Ohms. VDDID strap connections (for memory device VDD, VDDQ): STRAP OUT (OPEN): VDD = VDDQ STRAP IN (VSS): VDD is not equal to VDDQ. REV 1.0 LDQS VDDSPD VDD/VDDQ VREF VSS VDDID A0-A12 : SDRAMs D0-D3 A0-A12 DQS4 DM4 DQ32 DQ33 DQ34 DQ35 DQ36 DQ37 DQ38 DQ39 CK2 A0 A1 A2 SA0 SA1 SA2 SDA CK2 2 loads 2 loads 0 loads 6 (c) NANYA TECHNOLOGY CORPORATION NANYA reserves the right to change products and specifications without notice. M1S25664DSH8C1G / M1S12864DSH4C1G M1N25664DSH8C1G (GREEN) Unbuffered DDR SO-DIMM Serial Presence Detect SPD Description Byte 0 Description Number of Serial PD Bytes Written during Production Byte 26 Description Maximum Data Access Time from Clock at CL=1 1 Total Number of Bytes in Serial PD device 27 Minimum Row Precharge Time (tRP) 2 Fundamental Memory Type 28 Minimum Row Active to Row Active delay (tRRD) 3 Number of Row Addresses on Assembly 29 Minimum RAS to CAS delay (tRCD) 4 Number of Column Addresses on Assembly 30 Minimum RAS Pulse Width (tRAS) 5 Number of DIMM Rank 31 Module Bank Density 6 Data Width of Assembly 32 Address and Command Setup Time Before Clock 7 Data Width of Assembly (cont') 33 Address and Command Hold Time After Clock 8 Voltage Interface Level of this Assembly 34 Data Input Setup Time Before Clock 35 Data Input Hold Time After Clock 9 10 DDR SDRAM Device Cycle Time CL=2.5 DDR SDRAM Device Access Time from Clock 36-40 CL=2.5 Reserved 11 DIMM Configuration Type 41 12 Refresh Rate/Type 42 13 Primary DDR SDRAM Width 43 Max Cycle Time (tCK max) 14 Error Checking DDR SDRAM Device Width 44 Maximum DQS-DQ Skew Time (tDQSQ) 45 Maximum Read Data Hold Skew Factor (tQHS) 15 16 17 18 DDR SDRAM Device Attr: Min CLK Delay, Random Col Access DDR SDRAM Device Attributes: Burst Length 46-61 Supported DDR SDRAM Device Attributes: Number of Device Banks DDR SDRAM Device Attributes: CAS Latencies Supported Minimum Active/Auto-refresh Time (tRC) Auto-refresh to Active/Auto-refresh Command Period (tRFC) Reserved 62 SPD Revision 63 Checksum Data 19 DDR SDRAM Device Attributes: CS Latency 64-71 20 DDR SDRAM Device Attributes: WE Latency 72 Manufacturer's JEDEC ID Code 21 DDR SDRAM Device Attributes: 73-90 Module Part number 22 DDR SDRAM Device Attributes: General 91-92 Module Revision Code Module Manufacturing Location Module Manufacturing Data 23 yy= Binary coded decimal year code, 0-99(Decimal), Minimum Clock Cycle 93-94 CL=2.5 00-63(Hex) ww= Binary coded decimal year code, 01-52(Decimal), 01-34(Hex) 24 25 Maximum Data Access Time from Clock at 95-98 Module Serial Number 99-127 Reserved CL=2 Minimum Clock Cycle Time at CL=1 REV 1.0 July 19, 2005 7 (c) NANYA TECHNOLOGY CORPORATION NANYA reserves the right to change products and specifications without notice. M1S25664DSH8C1G / M1S12864DSH4C1G M1N25664DSH8C1G (GREEN) Unbuffered DDR SO-DIMM SPD Values for M1S25664DSH8C1G / M1N25664DSH8C1G M1S25664DSH8C1G M1N25664DSH8C1G Byte Value Hex Value Hex 0 128 80 128 80 1 256 08 256 08 2 SDRAM DDR 07 SDRAM DDR 07 3 13 0D 13 0D 4 9 09 9 09 5 2 02 2 02 6 x64 40 x64 40 7 x64 00 x64 00 8 SSTL 2.5V 04 SSTL 2.5V 04 9 6.0ns 60 6.0ns 60 10 0.70ns 70 0.70ns 70 00 11 Non-Parity 00 Non-Parity 12 SR/1x(7.8us) 82 SR/1x(7.8us) 82 13 x16 10 x16 10 14 N/A 00 N/A 00 15 1 Clock 01 1 Clock 01 16 2,4,8 0E 2,4,8 0E 17 4 04 4 04 18 2/2.5 0C 2/2.5 0C 19 0 01 0 01 20 1 02 1 02 21 Differential Clock 20 Differential Clock 20 22 0.2V Tolerance C0 0.2V Tolerance C0 23 7.5ns 75 7.5ns 75 24 0.75ns 75 0.75ns 75 25 N/A 00 N/A 00 26 N/A 00 N/A 00 27 18ns 48 18ns 48 28 12ns 30 12ns 30 29 18ns 48 18ns 48 30 42ns 2A 42ns 2A 31 128MB 20 128MB 20 32 0.75ns 75 0.75ns 75 33 0.75ns 75 0.75ns 75 34 0.45ns 45 0.45ns 45 35 0.45ns 45 0.45ns 45 36-40 Undefined 00 Undefined 00 41 60ns 3C 60ns 3C 42 72ns 48 72ns 48 43 12ns 30 12ns 30 44 0.45ns 2D 0.45ns 2D 45 0.55ns 55 0.55ns 55 46-61 Undefined 00 Undefined 00 62 Initial 00 1.0 10 63 Checksum ED Checksum FE 64-71 NANYA 7F7F7F0B00000000 NANYA 7F7F7F0B00000000 72 Assembly -- Assembly -- 73-90 Module PN -- Module PN -- 91-92 Revision -- Revision -- 93-94 Year/Week Code -- Year/Week Code -- 95-98 Serial Number -- Serial Number -- 99-127 Reserved -- Reserved -- REV 1.0 July 19, 2005 8 (c) NANYA TECHNOLOGY CORPORATION NANYA reserves the right to change products and specifications without notice. M1S25664DSH8C1G / M1S12864DSH4C1G M1N25664DSH8C1G (GREEN) Unbuffered DDR SO-DIMM SPD Values for M1S12864DSH4C1G M1S12864DSH4C1G Byte Value Hex 0 128 80 1 256 08 2 SDRAM DDR 07 3 13 0D 4 9 09 5 1 01 6 x64 40 7 x64 00 8 SSTL 2.5V 04 9 6.0ns 60 10 0.70ns 70 00 11 Non-Parity 12 SR/1x(7.8us) 82 13 x16 10 14 N/A 00 15 1 Clock 01 16 2,4,8 0E 17 4 04 18 2/2.5 0C 19 0 01 20 1 02 21 Differential Clock 20 22 0.2V Tolerance C0 23 7.5ns 75 24 0.75ns 75 25 N/A 00 26 N/A 00 27 18ns 48 28 12ns 30 29 18ns 48 30 42ns 2A 31 128MB 20 32 0.75ns 75 33 0.75ns 75 34 0.45ns 45 35 0.45ns 45 36-40 Undefined 00 41 60ns 3C 42 72ns 48 43 12ns 30 44 0.45ns 2D 45 0.55ns 55 46-61 Undefined 00 62 Initial 00 63 Checksum EC 64-71 NANYA 7F7F7F0B00000000 72 Assembly -- 73-90 Module PN -- 91-92 Revision -- 93-94 Year/Week Code -- 95-98 Serial Number -- 99-127 Reserved -- REV 1.0 July 19, 2005 9 (c) NANYA TECHNOLOGY CORPORATION NANYA reserves the right to change products and specifications without notice. M1S25664DSH8C1G / M1S12864DSH4C1G M1N25664DSH8C1G (GREEN) Unbuffered DDR SO-DIMM Absolute Maximum Ratings Symbol VIN, VOUT Parameter Voltage on I/O pins relative to VSS Rating Units -0.5 to VDDQ +0.5 V VIN Voltage on Input relative to VSS -0.5 to +3.6 V VDD Voltage on VDD supply relative to VSS -0.5 to +3.6 V VDDQ Voltage on VDDQ supply relative to VSS -0.5 to +3.6 V 0 to +70 C -55 to +150 C TA TSTG Operating Temperature (Ambient) Storage Temperature (Plastic) PD Power Dissipation (per device component) 1 W IOUT Short Circuit Output Current 50 mA Note: Stresses greater than those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This is stress rating only, and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability. DC Electrical Characteristics and Operating Conditions TA= 0C ~ 70C; VDDQ= VDD= 2.5V0.2V(PC2700) Symbol Parameter VDD Supply Voltage VDDQ I/O Supply Voltage VSS, VSSQ Min Max Units Notes PC2700 2.3 2.7 V 1 PC2700 2.3 2.7 V 1 0 0 V Supply Voltage, I/O Supply Voltage VREF I/O Reference Voltage 0.49 x VDDQ 0.51 x VDDQ V 1, 2 VTT I/O Termination Voltage (System) VREF - 0.04 VREF + 0.04 V 1, 3 VIH (DC) Input High (Logic1) Voltage VREF + 0.15 VDDQ + 0.3 V 1 VIL (DC) Input Low (Logic0) Voltage -0.3 VREF - 0.15 V 1 VIN (DC) Input Voltage Level, CK and CK Inputs -0.3 VDDQ + 0.3 V 1 VID (DC) Input Differential Voltage, CK and CK Inputs 0.30 VDDQ + 0.6 V 1, 4 -10 10 A 1 -10 10 A 1 -16.8 - mA 1 16.8 - mA 1 Input Leakage Current II Any input 0V VIN VDD; All other pins not under test = 0V IOZ IOH IOL Output Leakage Current DQs are disabled; 0V Vout VDDQ Output High Current (VOUT = VDDQ -0.373V, min VREF, min VTT) Output Low Current (VOUT = 0.373, max VREF, max VTT) Note: 1. Inputs are not recognized as valid until VREF stabilizes. 2. VREF is expected to be equal to 0.5 VDDQ of the transmitting device, and to track variations in the DC level of the same. Peak-to-peak noise on VREF may not exceed 2% of the DC value. 3. VTT is not applied directly to the DIMM. VTT is a system supply for signal termination resistors, is expected to be set equal to VREF, and must track variations in the DC level of VREF. 4. VID is the magnitude of the difference between the input level on CK and the input level on CK. REV 1.0 July 19, 2005 10 (c) NANYA TECHNOLOGY CORPORATION NANYA reserves the right to change products and specifications without notice. M1S25664DSH8C1G / M1S12864DSH4C1G M1N25664DSH8C1G (GREEN) Unbuffered DDR SO-DIMM AC Characteristics Notes 1-5 apply to the following Tables; Electrical Characteristics and DC Operating Conditions, AC Operating Conditions, Operating, Standby, and Refresh Currents, and Electrical Characteristics and AC Timing.) 1. All voltages referenced to VSS. 2. Tests for AC timing, IDD, and electrical, AC and DC characteristics, may be conducted at nominal reference/supply voltage levels, but the related specifications and device operation are guaranteed for the full voltage range specified. 3. Outputs measured with equivalent load. Refer to the AC Output Load Circuit below. 4. AC timing and IDD tests may use a VIL to VIH swing of up to 1.5V in the test environment, but input timing is still referenced to VREF (or to the crossing point for CK, CK), and parameter specifications are guaranteed for the specified AC input levels under normal use conditions. The minimum slew rate for the input signals is 1V/ns in the range between VIL (AC) and VIH (AC) unless otherwise specified. 5. The AC and DC input level specifications are as defined in the SSTL_2 Standard (i.e. the receiver effectively switches as a result of the signal crossing the AC input level, and remains in that state as long as the signal does not ring back above (below) the DC input LOW (HIGH) level. AC Output Load Circuits VTT 50 ohms Output Timing Reference Point VOUT 30 pF AC Operating Conditions TA = 0 C ~ 70 C; VDDQ= VDD= 2.5V 0.2V (PC2700) Symbol Parameter/Condition VIH (AC) Input High (Logic 1) Voltage. Min Max VREF + 0.31 VIL (AC) Input Low (Logic 0) Voltage. VID (AC) Input Differential Voltage, CK and CK Inputs VIX (AC) Input Differential Pair Cross Point Voltage, CK and CK Inputs Unit Notes V 1, 2 VREF - 0.31 V 1, 2 0.62 VDDQ + 0.6 V 1, 2, 3 (0.5* VDDQ) - 0.2 (0.5* VDDQ) + 0.2 V 1, 2, 4 Note: 1. Input slew rate = 1V/ ns. 2. Inputs are not recognized as valid until VREF stabilizes. 3. VID is the magnitude of the difference between the input level on CK and the input level on CK. 4. The value of VIX is expected to equal 0.5*VDDQ of the transmitting device and must track variations in the DC level of the same. REV 1.0 July 19, 2005 11 (c) NANYA TECHNOLOGY CORPORATION NANYA reserves the right to change products and specifications without notice. M1S25664DSH8C1G / M1S12864DSH4C1G M1N25664DSH8C1G (GREEN) Unbuffered DDR SO-DIMM Operating, Standby, and Refresh Currents TA = 0 C ~ 70 C; VDDQ= VDD= 2.5V 0.2V (PC2700) Symbol IDD0 IDD1 IDD2P IDD2N IDD3P IDD3N IDD4R IDD4W Parameter/Condition clock cycle; address and control inputs changing once per clock cycle Operating Current: one bank; active/read/precharge; Burst = 2; tRC = tRC (MIN); CL=2.5; tCK = tCK (MIN); IOUT = 0mA; address and control inputs changing once per clock cycle Precharge Power-Down Standby Current: all banks idle; power-down mode; CKE VIL (MAX); tCK = tCK (MIN) Idle Standby Current: CS VIH (MIN); all banks idle; CKE VIH (MIN); tCK = tCK (MIN); address and control inputs changing once per clock cycle Active Power-Down Standby Current: one bank active; power-down mode; CKE VIL (MAX); tCK = tCK (MIN) Active Standby Current: one bank; active/precharge; CS VIH (MIN); CKE VIH (MIN); tRC = tRAS (MAX); tCK = tCK (MIN); DQ, DM, and DQS inputs changing twice per clock cycle; address and control inputs changing once per clock cycle Operating Current: one bank; Burst = 2; reads; continuous burst; address and control inputs changing once per clock cycle; DQ and DQS outputs changing twice per clock cycle; CL = 2.5; tCK = tCK (MIN); IOUT = 0mA Operating Current: one bank; Burst = 2; writes; continuous burst; address and control inputs changing once per clock cycle; DQ and DQS inputs changing twice per clock cycle; CL=2.5; tCK = tCK (MIN) IDD5 Auto-Refresh Current: tRC = tRFC (MIN) IDD6 Self-Refresh Current: CKE 0.2V IDD7 Notes Operating Current: one bank; active/precharge; tRC = tRC (MIN); tCK = tCK (MIN); DQ, DM, and DQS inputs changing twice per 1,2 1,2 1,2 1,2 1,2 1,2 1,2 1,2 1,2,3 1,2 Operating Current: four bank; four bank interleaving with BL = 4, address and control inputs randomly changing; 50% of data changing at every transfer; tRC = tRC (min); IOUT = 0mA. 1,2 1. IDD specifications are tested after the device is properly initialized. 2. Input slew rate = 1V/ ns. 3. Current at 7.8 s is time averaged value of IDD5 at tRFC (MIN) and IDD2P over 7.8 s. All IDD current values are calculated from device level. M1N25664DSH8C1G M1S25664DSH8C1G M1S12864DSH4C1G PC2700 PC2700 PC2700 (6K) (6K) (6K) IDD0 428 428 272 mA IDD1 444 444 288 mA IDD2P 32 32 16 mA IDD2N 200 200 100 mA IDD3P 80 80 40 mA IDD3N 312 312 156 mA IDD4R 504 504 348 mA IDD4W 548 548 392 mA IDD5 628 628 472 mA IDD6 16 16 8 mA IDD7 984 984 828 mA Symbol Unit * M1N25664DSH8C1G IDD was calculated from component IDD. It may different from the actual measurement. REV 1.0 July 19, 2005 12 (c) NANYA TECHNOLOGY CORPORATION NANYA reserves the right to change products and specifications without notice. M1S25664DSH8C1G / M1S12864DSH4C1G M1N25664DSH8C1G (GREEN) Unbuffered DDR SO-DIMM AC Timing Specifications for DDR SDRAM Devices Used on Module TA = 0 C ~ 70 C; VDDQ= VDD= 2.5V 0.2V (PC2100/PC2700) (Part 1 of 2) Symbol tAC Parameter 6K 75B PC2700 PC2100 Min. Max. Min. Max. Unit Notes DQ output access time from CK/CK -0.7 +0.7 -0.75 +0.75 ns 1-4 DQS output access time from CK/CK -0.7 +0.7 -0.75 +0.75 ns 1-4 tCH CK high-level width 0.45 0.55 0.45 0.55 tCK 1-4 tCL CK low-level width 0.45 0.55 0.45 0.55 tCK 1-4 tCK Clock cycle time CL=3 - - - - tCK Clock cycle time CL=2.5 6 12 7.5 12 ns 1-4 tCK Clock cycle time CL=2 7.5 12 10 12 ns 1-4 tDH DQ and DM input hold time 0.45 0.5 ns tDS DQ and DM input setup time 0.45 0.5 ns tDIPW DQ and DM input pulse width (each input) 1.75 1.75 ns 1-4 tHZ Data-out high-impedance time from CK/CK -0.7 +0.7 -0.75 +0.75 ns 1-4, 5 tLZ Data-out low-impedance time from CK/CK -0.7 +0.7 -0.75 +0.75 ns 1-4, 5 0.5 ns 1-4 tCK 1-4 tCK 1-4 0.75 ns 1-4 1.25 tCK 1-4 tDQSCK tDQSQ tHP DQS-DQ skew (DQS & associated DQ signals) tCH or tCH or defined by clk high (tCH) or clk low (tCL) time tCL tCL tHP - tHP - tQHS tQHS tQH Data output hold time from DQS tQHS Data hold Skew Factor tDQSS Write command to 1st DQS latching transition tDQSL, DQS input low (high) pulse width tDQSH (write cycle) tDSS tDSH tMRD tWPRES 0.45 Minimum half clk period for any given cycle; 0.55 0.75 1.25 0.75 1-4, 15, 16 1-4, 15, 16 0.35 0.35 tCK 1-4 0.2 0.2 tCK 1-4 0.2 0.2 tCK 1-4 Mode register set command cycle time 2 2 tCK 1-4 Write preamble setup time 0 0 ns 1-4, 7 DQS falling edge to CK setup time (write cycle) DQS falling edge hold time from CK (write cycle) tWPST Write postamble 0.40 tCK 1-4, 6 tWPRE Write preamble 0.25 0.25 tCK 1-4 0.75 0.9 ns 0.75 0.9 ns 0.8 1.0 ns tIH tIS tIH Address and control input hold time (fast slew rate) Address and control input setup time (fast slew rate) Address and control input hold time (slow slew rate) REV 1.0 July 19, 2005 0.60 0.40 0.60 2-4, 9, 11, 12 2-4, 9, 11, 12 2-4, 10, 11, 12, 14 13 (c) NANYA TECHNOLOGY CORPORATION NANYA reserves the right to change products and specifications without notice. M1S25664DSH8C1G / M1S12864DSH4C1G M1N25664DSH8C1G (GREEN) Unbuffered DDR SO-DIMM AC Timing Specifications for DDR SDRAM Devices Used on Module TA = 0 C ~ 70 C; VDDQ= VDD= 2.5V 0.2V (PC2100/PC2700) (Part 2 of 2) Symbol Parameter 6K 75B PC2700 PC2100 Min. tIS tIPW Address and control input setup time (slow slew rate) Max. Min. 10-12, 14 ns 2-4, 12 1.1 tCK 1-4 0.40 0.60 tCK 1-4 45ns 120us tRP RE Read preamble 0.9 1.1 0.9 tRP ST Read postamble 0.40 0.60 tRAS Active to Precharge command 42ns 120us tRC Active to Active/Auto-refresh command period period ns Max. 1.0 2.2 Auto-refresh to Active/Auto-refresh command Notes 2-4, 0.8 Input pulse width tRFC Unit 2.2 1-4 60 65 ns 1-4 72 75 ns 1-4 tRCD Active to Read or Write delay 18 20 ns 1-4 tRAP Active to Read Command with Auto-precharge 18 20 ns 1-4 tRP Precharge command period 18 20 ns 1-4 tRRD Active bank A to Active bank B command 12 15 ns 1-4 tWR Write recovery time 1-4 Auto-precharge write recovery + precharge time 15 (tWR/ tCK ) + (tRP / tCK ) ns tDAL 15 (tWR/ tCK ) + (tRP / tCK ) tCK 1-4, 13 tWTR Internal write to read command delay 1 1 tCK 1-4 tPDEX Power down exit time 6 7.5 ns 1-4 tXSNR Exit self-refresh to non-read command 75 75 ns 1-4 tXSRD Exit self-refresh to read command 200 200 tCK 1-4 tREFI Average Periodic Refresh Interval s 1-4, 8 REV 1.0 July 19, 2005 7.8 7.8 14 (c) NANYA TECHNOLOGY CORPORATION NANYA reserves the right to change products and specifications without notice. M1S25664DSH8C1G / M1S12864DSH4C1G M1N25664DSH8C1G (GREEN) Unbuffered DDR SO-DIMM AC Timing Specification Notes 1. Input slew rate = 1V/ns. 2. The CK/CK input reference level (for timing reference to CK/CK) is the point at which CK and CK cross: the input reference level for signals other than CK/CK is VREF. 3. Inputs are not recognized as valid until VREF stabilizes. 4. The Output timing reference level, as measured at the timing reference point indicated in AC Characteristics (Note 3) is VTT. 5. tHZ and tLZ transitions occur in the same access time windows as valid data transitions. These parameters are not referred to a specific voltage level, but specify when the device is no longer driving (HZ), or begins driving (LZ). 6. The maximum limit for this parameter is not a device limit. The device operates with a greater value for this parameter, but system performance (bus turnaround) degrades accordingly. 7. The specific requirement is that DQS be valid (high, low, or some point on a valid transition) on or before this CK edge. A valid transition is defined as monotonic and meeting the input slew rate specifications of the device. When no writes were previously in progress on the bus, DQS will be transitioning from Hi-Z to logic LOW. If a previous write was in progress, DQS could be HIGH, LOW, or transitioning from high to low at this time, depending on tDQSS. 8. A maximum of eight Auto refresh commands can be posted to any given DDR SDRAM device. 9. For command/address input slew rate >= 1.0 V/ns. Slew rate is measured between VOH (AC) and VOL (AC). 10. For command/address input slew rate >= 0.5 V/ns and < 1.0 V/ns. Slew rate is measured between VOH (AC) and VOL (AC). 11. CK/CK slew rates are >= 1.0 V/ns. 12. These parameters guarantee device timing, but they are not necessarily tested on each device, and they may be guaranteed by design or tester characterization. 13. For each of the terms in parentheses, if not already an integer, round to the next highest integer. tCK is equal to the actual system clock cycle time. For example, for PC2100 at CL= 2.5, tDAL = (15ns/7.5ns) +(20ns/7.0ns) = 2 + 3 = 5. 14. An input setup and hold time derating table is used to increase tIS and tIH in the case where the input slew rate is below 0.5 V/ns. Input Slew Rate 1. 2. Delta (tIS) Delta (tIH) Unit Note 0.5 V/ns 0 0 ps 1, 2 0.4 V/ns +50 0 ps 1, 2 0.3 V/ns +100 0 ps 1, 2 Input slew rate is based on the lesser of the slew rates determined by either VIH (AC) to VIL (AC) or VIH (DC) to VIL (DC), similarly for rising transitions. These derating parameters may be guaranteed by design or tester characterization and are not necessarily tested on each device. 15. An input setup and hold time derating table is used to increase tDS and tDH in the case where the I/O slew rate is below 0.5 V/ns. 1. 2. Input Slew Rate Delta (tDS) Delta (tDH) Unit 0.5 V/ns 0 0 ps 1, 2 0.4 V/ns +75 +75 ps 1, 2 0.3 V/ns +150 +150 ps 1, 2 Note I/O slew rate is based on the lesser of the slew rates determined by either VIH (AC) to VIL (AC) or VIH (DC) to VIL (DC), similarly for rising transitions. These derating parameters may be guaranteed by design or tester characterization and are not necessarily tested on each device. 16. An I/O Delta Rise, Fall Derating table is used to increase tDS and tDH in the case where DQ, DM, and DQS slew rates differ. 1. 2. 3. 4. Delta Rise and Fall Rate Delta (tDS) Delta (tDH) Unit Note 0.0 ns/V 0 0 ps 1-4 0.25 ns/V +50 +50 ps 1-4 0.5 ns/V +100 +100 ps 1-4 Input slew rate is based on the lesser of the slew rates determined by either VIH (AC) to VIL (AC) or VIH (DC) to VIL (DC), similarly for rising transitions. Input slew rate is based on the larger of AC to AC delta rise, fall rate and DC to DC delta rise, fall rate. The delta rise, fall rate is calculated as: [1/(slew rate 1)] - [1/(slew rate 2)] For example: slew rate 1 = 0.5 V/ns; slew rate 2 = 0.4 V/ns. Delta rise, fall = (1/0.5) - (1/0.4) [ns/V] = -0.5 ns/V Using the table above, this would result in an increase in tDS and tDH of 100 ps. These derating parameters may be guaranteed by design or tester characterization and are not necessarily tested on each device. REV 1.0 July 19, 2005 15 (c) NANYA TECHNOLOGY CORPORATION NANYA reserves the right to change products and specifications without notice. M1S25664DSH8C1G / M1S12864DSH4C1G M1N25664DSH8C1G (GREEN) Unbuffered DDR SO-DIMM Package Dimensions 256MB, 8 TSOP devices FRONT 67.60 (2X) 1.80 1 2.15 39 41 11.40 31.75 20.00 6.00 4.00 63.60 199 Detail A Detail B 4.20 47.40 2.45 1.80 BACK SIDE 3.80 MAX 2 40 42 200 1.00+/- 0.10 Detail B 0.45 0.60 1.00+/- 0.1 2.55 4.00+/-0.10 0.25 MAX Detail A Note: All dimensions are typical with tolerances of +/- 0.15 unless otherwise stated. Units: Millimeters (Inches) REV 1.0 July 19, 2005 16 (c) NANYA TECHNOLOGY CORPORATION NANYA reserves the right to change products and specifications without notice. M1S25664DSH8C1G / M1S12864DSH4C1G M1N25664DSH8C1G (GREEN) Unbuffered DDR SO-DIMM Package Dimensions 128MB, 4 TSOP devices FRONT 67.60 (2X) 1.80 1 2.15 39 41 11.40 31.75 20.00 6.00 4.00 63.60 199 Detail A Detail B 4.20 47.40 1.80 2.45 BACK SIDE 3.00 MAX 2 40 42 200 1.00+/- 0.10 Detail A 0.45 0.60 1.00+/- 0.1 2.55 4.00+/-0.10 0.25 MAX Detail B Note: All dimensions are typical with tolerances of +/- 0.15 unless otherwise stated. Units: Millimeters (Inches) REV 1.0 July 19, 2005 17 (c) NANYA TECHNOLOGY CORPORATION NANYA reserves the right to change products and specifications without notice. M1S25664DSH8C1G / M1S12864DSH4C1G M1N25664DSH8C1G (GREEN) Unbuffered DDR SO-DIMM Revision Log Rev Date Modification 0.1 April 8, 2004 Release 0.2 April 16, 2004 Speed grade update 0.3 June 1, 2005 Add green part number 1.0 July 19, 2005 Official Release for Super Elixir Nanya Technology Corporation Hwa Ya Technology Park 669 Fu Hsing 3rd Rd., Kueishan, Taoyuan, 333, Taiwan, R.O.C. Tel: +886-3-328-1688 Please visit our home page for more information: www.elixir-memory.com Nanya reserves the right to make changes or deletions without any notice to any of its products. Nanya makes no guarantee, warranty or representation regarding the suitability of its products for any particular purpose. Nanya assumes no liability arising out of the application or use of its products. All parameters can and do vary in its application and must be validated for each customer application by the customer's technician. By purchasing Nanya products, Nanya does not convey any license under its patent rights not the rights of others. Nanya products are not designed or intended or authorized for use in systems intended for the military or surgical implants or any other applications where life is involved or where injury or death may occur or the loss/corruption of data or the loss of system reliability or mission critical applications. Should the buyer purchase or use Nanya products in such unintended or unauthorized application, the Buyer and user shall indemnify and hold Nanya and its officers, employees, subsidiaries, affiliates and distributors harmless against all claims, costs, damages, all fees and expenses directly or indirectly arising from any claim of loss, injury or death associated with unintended or unauthorized use even if such claims alleges Nanya was negligent regarding design or manufacture of the part. Nanya and the Nanya logo are trademarks of the Nanya Technology Corporation. Printed in Taiwan (c)2004 REV 1.0 July 19, 2005 18 (c) NANYA TECHNOLOGY CORPORATION NANYA reserves the right to change products and specifications without notice.