This document is a general product description and is subject to change without notice. Hynix Semiconductor does not assume any

responsibility for use of ci rcuits described. No patent l ic enses are implied.

Rev 1.1 / Sep. 2008 1

This Hynix’s Fully Buffered DIMM is a high-bandwidth & large capacity channel solution that has a narrow

host interface. Hynix’s FB-DIMM features novel architecture including the Advanced Memory Buffer that

• 240 pin Fully Buffered ECC dual In-Line DDR2 SDRAM Module

• JEDEC standard Double Data Rate2 Synchronous DRAMs (DDR2 SDRAMs) with 1.8V +/- 0.1V Power Supply

•4 Bank architecture

• OCD (Off-Chip Driver Impedance Adjustment)

•RoHS compliant

• Full Module Heat Spreader

Rev 1.1 / Sep. 2008 2

240pin Fully Buffered DDR2 SDRAM DIMMs

ORDERING INFORMATION

Note:

**: ‘P’ of Part Number;12th digit, stands for lead free products.

SPEED GRADE & KEY PARAMETERS

ADDRESS TABLE

1GB 128Mx72 18 2

1GB 128M x 72 2 64Mbx8 18 14(A0~A13)/2(BA0~BA1)/10(A0~A9) 8K / 64ms

11(A0~A9,A11) 8K / 64ms

Rev 1.1 / Sep. 2008 3

240pin Fully Buffered DDR2 SDRAM DIMMs

Pin Name type Polarity Function Description Count

SDA Input / Output - SPD Data Input / Outp ut 1

SA[2:0] Input - SPD Address inputs, also used to select the DIMM number in the AMB 3

The DNU/M_Test pin provides an external connec tion on R/Cs A-D for

testing the margin of Vref which is produced by a voltage divider on the

module. It is not intended to be used in normal system operation and

Rev 1.1 / Sep. 2008 4

240pin Fully Buffered DDR2 SDRAM DIMMs

1VDD41PN13

2 VDD 42 VSS 82 PS4 122 VDD 162 VSS 202 SS4

3 VDD 43 VSS 83 PS4 123 VDD 163 VSS 203 SS4

4 VSS 44 RFU* 84 VSS 124 VSS 164 RFU* 204 VSS

Rev 1.1 / Sep. 2008 5

240pin Fully Buffered DDR2 SDRAM DIMMs

VDD

Rev 1.1 / Sep. 2008 6

240pin Fully Buffered DDR2 SDRAM DIMMs

Rev 1.1 / Sep. 2008 7

240pin Fully Buffered DDR2 SDRAM DIMMs

/DQS0

DQS /CS DM

DQS /CS DM

DQS /CS DM

DQS /CS DM

DQS6

/DQS7

/DQS8

SA0 SA1 SA2

SCL SDA

A0 A1 A2

Rev 1.1 / Sep. 2008 8

240pin Fully Buffered DDR2 SDRAM DIMMs

DDR2 Interface Signals 175

Rev 1.1 / Sep. 2008 9

240pin Fully Buffered DDR2 SDRAM DIMMs

240pin Fully Buffered DDR2 SDRAM DIMMs

240pin Fully Buffered DDR2 SDRAM DIMMs

240pin Fully Buffered DDR2 SDRAM DIMMs

ABSOLUTE MAXIMUM RATINGS

Parameter Symbol Rating Units Notes

Leakage Cu rrent (Link) IL -5 - +5 uA 3

240pin Fully Buffered DDR2 SDRAM DIMMs

Note:

Environmental Parameters

1. The designer must meet the case temperature specifications for individual module components.

240pin Fully Buffered DDR2 SDRAM DIMMs

Command and address lines stable. DRAM clock active.

Channel Standby A ver age powe r over 42 fr ames where the channel enters and exits

Dram clocks active, ODE and CKE driven low.

240pin Fully Buffered DDR2 SDRAM DIMMs

Note:

at 60% with De-emphasis at -3dB when enabled. Address and Data field s ar e pseudo-random, which provides a 50%

Assuming 1 activate command and 1 read/write command per BL=4 transferBL=4.10 lanes southbound and 14 lanes

240pin Fully Buffered DDR2 SDRAM DIMMs

Idle Current, DRAM Power Down (Conditions TBD)

240pin Fully Buffered DDR2 SDRAM DIMMs

Note 1: All dimensions are typical millimeter scale unless otherwise stated.

240pin Fully Buffered DDR2 SDRAM DIMMs

128Mx72, 1GB Module (2 ranks of x8 based DDR2 SDRAMs)

240pin Fully Buffered DDR2 SDRAM DIMMs

256Mx72, 2GB Module (2 ranks of x4 based DDR2 SDRAMs)