960 Altera Corporation
AN 94: Understanding MAX 7000 Timing
t
LPA
Low-power adder. The delay associated with macrocells in
low-power operation. In low-power mode,
t
LPA
must be added
to the logic array delay (
t
LAD
), the register control delay (
t
LAC
,
t
IC
,
t
ACL
, or
t
EN
), and the shared expander delay (
t
SEXP
) paths.
External
Timing
Parameters
External timing parameters represent actual pin-to-pin timing
characteristics. Each external timing parameter consists of a combination
of internal timing parameters. The data sheet for each device gives the
values of the external timing parameters. These external timing
parameters are worst-case values, derived from extensive performance
measurements and ensured by testing. All external timing parameters are
shown in bold type. The following list defines external timing parameters
for MAX 7000 devices.
t
PD1
Dedicated input pin to non-registered output delay. The time
required for a signal on any dedicated input pin to propagate
through the combinatorial logic in a macrocell and appear at an
external device output pin.
t
PD2
I/O pin input to non-registered output delay. The time required
for a signal on any I/O pin input to propagate through the
combinatorial logic in a macrocell and appear at an external
device output pin.
t
PZX
Tri-state to active output delay. The time required for an input
transition to change an external output from a tri-state (high-
impedance) logic level to a valid high or low logic level.
t
PXZ
Active output to tri-state delay. The time required for an input
transition to change an external output from a valid high or low
logic level to a tri-state (high-impedance) logic level.
t
CLR
Time to clear register delay. The time required for a low signal to
appear at the external output, measured from the input
transition.
t
SU
Global clock setup time. The time that data must be present at
the input pin before the global (synchronous) clock signal is
asserted at the clock pin.
t
H
Global clock hold time. The time that data must be present at
the input pin after the global clock signal is asserted at the clock
pin.
t
FSU
Fast-input clock setup time. When the fast-input path is used,
t
FSU
is the time that data must be present at the input pin before
the global (synchronous) clock signal is asserted at the clock pin.