Page 1
EP5348UI 400mA PowerSoC
Step-Down DC-DC Switching Converter with Integrated Inductor
DESCRIPTION
The EP5348UI delivers the optimal trade-off between
footprint and efficiency. It is a perfect alternative to
replace less efficient LDOs in space constrained
applications that require improved efficiency.
The EP5348UI is a 400mA PowerSoC which
integrates MOSFET switches, control, compensation,
and the magnetics in a micro-QFN Package. This
highly integrated DC-DC solution offers up to 46-
points better efficiency than the comparable LDO. A
significant reduction in power loss and improved
thermals are achieved. It enables extended battery
life and helps Meet Energy Star requirements.
Integrated magnetics enables a tiny solution
footprint, low output ripple, and high reliability, while
maintaining high efficiency. The complete solution
size is similar to an LDO and much smaller than a
comparable DC-DC.
All Enpirion products are RoHS compliant and lead-
free manufacturing environment compatible.
FEATURES
• Integrated Inductor Technology
• 400mA continuous output current
• 2.0mm x 1.75mm x 0.9mm uQFN package
• Small Solution Footprint
• Efficiency, up to 90%
• VOUT Range 0.6V to VIN – VDROP_OUT
• Short circuit and over current protection
• UVLO and thermal protection
• IC level reliability in a PowerSoC solution
APPLICATIONS
• Applications where poor LDO efficiency creates:
o Thermal challenges
o Battery Life challenges
o Failure to meet Energy Star requirements
• Space-constrained applications
• Portable media players and USB peripherals
EP5348
10µF
0603
VOUT
PVIN
AGND
VIN
ENABLE
AVIN
PGND
COUT
VOUT
RA
RB
VFB
2.2µF
0603
CIN
CAVIN
0.1µF
CA
Figure 1: Simplified Applications Circuit
Figure 2: Highest Efficiency in Smallest Solution Size
15
25
35
45
55
65
75
85
95
0.0 0.1 0.2 0.3
Efficiency (%)
Load Current (A)
EP5348UI
LDO
Δ = 46-points
VIN = 5.0V
VOUT = 1.2V
DataSheeT
– enpirion® power solutions
05721 January 9, 2019 Rev E
Datasheet | Intel® Enpirion® Power Solutions: EP5348UI
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ORDERING INFORMATION
Part Number Package Markings TJ Rating Package Description
EP5348UI ATXX -40 to +125 16-pin (2.5mm x 2.25mm x 1.1mm) uQFN
EVB-EP5348UI-E QFN Evaluation Board
Packing and Marking Information: https://www.intel.com/content/www/us/en/products/programmable.html
PIN FUNCTIONS
Figure 3: EP5348UI Pin Out Diagram (Top View)
NOTE A: NC pins are not to be electrically connected to each other or to any external signal, ground, or voltage. However,
they must be soldered to the PCB. Failure to follow this guideline may result in part malfunction or damage.
NOTE B: Black ‘dot’ on top left is pin 1 indicator on top of the device package.
PVIN
AVIN
ENABLE
NC
NC
VOUT
VOUT
NC(SW)
NC(SW)
EP5348UI
3
1
4
2
5
14 13
6 7
10
9
11
8
12
NC(SW)
PGND
NC
VFB
AGND
05721 January 9, 2019 Rev E
Datasheet | Intel® Enpirion® Power Solutions: EP5348UI
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PIN DESCRIPTIONS
PIN NAME TYPE FUNCTION
1,15,
14 NC(SW) Analog
NO CONNECT – These pins are internally connected to the common
switching node of the internal MOSFETs. NC (SW) pins are not to be
electrically connected to any external signal, ground, or voltage. However,
they must be soldered to the PCB. Failure to follow this guideline may
result in part malfunction or damage to the device.
2 PGND Ground Power ground. Connect this pin to the ground electrode of the Input and
output filter capacitors.
3, 8, 9 NC Analog
NO CONNECT: These pins may already be connected inside the device.
Therefore, they cannot be electrically connected to each other or to any
external signal, voltage, or ground. They must however be soldered to the
PCB. Failure to follow this guideline may result in device damage.
4 VFB Analog Feedback pin for external voltage divider network.
5 AGND Analog Analog ground. This is the quiet ground for the internal control circuitry,
and the ground return for external feedback voltage divider
6, 7 VOUT Power Regulated Output Voltage. Refer to application section for proper layout
and decoupling.
10 ENABLE Analog Output Enable. Enable = logic high; Disable = logic low
11 AVIN Power Input power supply for the controller circuitry. Connect to VIN at a quiet
point.
12 PVIN Power Input Voltage for the MOSFET switches.
ABSOLUTE MAXIMUM RATINGS
CAUTION: Absolute Maximum ratings are stress ratings only. Functional operation beyond the recommended operating
conditions is not implied. Stress beyond the absolute maximum ratings may impair device life. Exposure to absolute
maximum rated conditions for extended periods may affect device reliability.
Absolute Maximum Pin Ratings
PARAMETER SYMBOL MIN MAX UNITS
Supply Voltage PVIN, AVIN, VOUT -0.3 6.0 V
Voltages on: ENABLE -0.3 VIN+ 0.3 V
Voltages on: VFB -0.3 2.7 V
Absolute Maximum Thermal Ratings
PARAMETER CONDITION MIN MAX UNITS
Maximum Operating Junction
Temperature TJ-ABS +150 °C
Storage Temperature Range TSTG -65 +150 °C
Reflow Peak Body Temperature (10 Sec) MSL3 JEDEC J-STD-020A +260 °C
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Datasheet | Intel® Enpirion® Power Solutions: EP5348UI
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Absolute Maximum ESD Ratings
PARAMETER CONDITION MIN MAX UNITS
HBM (Human Body Model) ±2000 V
CDM (Charged Device Model) ±500 V
RECOMMENDED OPERATING CONDITIONS
PARAMETER SYMBOL MIN MAX UNITS
Input Voltage Range VIN 2.4 5.5 V
Output Voltage Range VOUT 0.6 VIN – VDO (1) V
Operating Ambient Temperature TA -40 +85 °C
Operating Junction Temperature TJ -40 +125 °C
THERMAL CHARACTERISTICS
PARAMETER SYMBOL TYPICAL UNITS
Thermal Shutdown TSD 155 °C
Thermal Shutdown Hysteresis TSDHYS 15 °C
Thermal Resistance: Junction to Ambient (0 LFM) (2) θJA 105 °C/W
(1) VDO (dropout voltage) is defined as (ILOAD x Droput Resistance). Please refer to Electrical Characteristics Table.
(2) Based on 2 oz. external copper layers and proper thermal design in line with EIA/JEDEC JESD51-7 standard for
high effective thermal conductivity boards.
ELECTRICAL CHARACTERISTICS
NOTE: TA = -40°C to +85°C unless otherwise noted. Typical values are at TA = 25°C, VIN = 3.6V.
CIN = 2.2µF 0603 MLCC, COUT = 10µF 0603.
PARAMETER SYMBOL TEST CONDITIONS MIN TYP MAX UNITS
Operating Input Voltage
Range VIN 2.5 5.5 V
Under Voltage Lock-out
– VIN Rising VUVLO_R 2.3 V
Under Voltage Lock-out
– VIN Falling VUVLO_F 2.2 V
Shut-down Current ISD Enable = Low 3 µA
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Datasheet | Intel® Enpirion® Power Solutions: EP5348UI
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PARAMETER SYMBOL TEST CONDITIONS MIN TYP MAX UNITS
VFB Voltage Initial
Accuracy VFB
TA = 25°C, VIN = 3.6V;
ILOAD = 100mA ;
0.8V ≤ VOUT ≤ 3.3V
0.588 0.600 0.612 V
Drop Out Resistance RDO Input to Output Resistance in
100% duty cycle operation. 350 500 mΩ
Line Regulation ∆VOUT_LINE 2.5V ≤ VIN ≤ 5.5V 0.03 %/V
Load Regulation ∆VOUT_LOAD 0A ≤ ILOAD ≤ 400mA 0.48 %/A
Temperature Variation ∆VOUT_TEMPL -40°C ≤ TA ≤ +85°C 24 ppm/°C
Feedback Pin Input
Current (3) IFB <300 nA
Output Current Range IOUT 0 400 mA
OCP Threshold ILIM 2.5V ≤ VIN ≤ 5.5V
0.6V ≤ VOUT ≤ 3.3V 1.4 A
Output Dropout
Resistance (3)
Voltage (1) (3)
RDO
VDO_FL
Input to Output Resistance
VINMIN - VOUT at Full load
520
208
780
312
mΩ
mV
Operating Output
Voltage Range VOUT VDO = IOUT * RDO 0.6 VIN-VDO V
Enable Pin Logic Low VENLO 0.3 V
Enable Pin Logic High VENHI 1.4 V
Enable Pin Current (3) IENABLE <200 nA
Operating Frequency FOSC 9 MHz
VOUT Rise Time TRISE From 0 to full output voltage 1.17 1.8 2.43 mSec
(3) Parameter guaranteed by design and characterization.
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Datasheet | Intel® Enpirion® Power Solutions: EP5348UI
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TYPICAL PERFORMANCE CURVES
Efficiency vs. Load Current: VIN = 3.3V, VOUT (from top to
bottom) = 2.5, 1.8, 1.2V
Efficiency vs. Load Current: VIN = 5.0V, VOUT (from top to
bottom) = 3.3, 2.5, 1.8, 1.2V
20
30
40
50
60
70
80
90
0.0 0.1 0.2 0.3 0.4
Efficiency (%)
Load Current (A)
VIN = 3.3V
VOUT=2.5
VOUT=1.8
VOUT=1.2
Top to Bottom:
20
30
40
50
60
70
80
90
0.0 0.1 0.2 0.3 0.4
Efficiency (%)
Load Current (A)
VIN = 5.0V
VOUT=3.3V
VOUT=2.5V
VOUT=1.8V
VOUT=1.2V
Top to Bottom:
05721 January 9, 2019 Rev E
Datasheet | Intel® Enpirion® Power Solutions: EP5348UI
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TYPICAL PERFORMANCE CHARACTERISTICS
Output Ripple: VIN = 3.3V, VOUT = 1.0V, Iout = 400mA
CIN = 2.2
µ
F/0603, COUT = 10
µ
F/0603 + 2.2uF/0603
Output Ripple: VIN = 3.3V, VOUT = 1.0V, Iout = 400mA
CIN = 2.2
µ
F/0603, COUT = 10
µ
F/0603 + 2.2uF/0603
Output Ripple: VIN = 5V, VOUT = 1.0V, Iout = 400mA
CIN = 2.2
µ
F/0603, COUT = 10
µ
F/0603 + 2.2uF/0603
Output Ripple: VIN = 5V, VOUT = 1.0V, Iout = 400mA
CIN = 2.2
µ
F/0603, COUT = 10
µ
F/0603 + 2.2uF/0603
20 MHz BW limit 500 MHz BW
500 MHz BW
20 MHz BW limit
05721 January 9, 2019 Rev E
Datasheet | Intel® Enpirion® Power Solutions: EP5348UI
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TYPICAL PERFORMANCE CHARACTERISTICS (CONTINUED)
Load Transient: VIN = 3.3V, VOUT = 1.0V
Ch.1: VOUT, Ch.2: ILOAD 0
↔
400mA
CIN = 2.2
µ
F/0603, COUT = 10
µ
F/0603 + 2.2uF/0603
Load Transient: VIN = 5V, VOUT = 1.0V
Ch.1: VOUT, Ch.2: ILOAD 0
↔
400mA
CIN = 2.2
µ
F/0603, COUT = 10
µ
F/0603 + 2.2uF/0603
Power Up/Down at No Load: VIN/VOUT = 5.0V/1.2V,
Cout
≈
10µF, Ch.1: ENABLE, Ch. 2: VOUT, Ch.4: IOUT
Power Up/Down into 3
Ω
load: VIN/VOUT = 5.5V/3.3V,
Cout
≈
10µF, Ch.1: ENABLE, Ch. 2: VOUT, Ch.4: IOUT
05721 January 9, 2019 Rev E
Datasheet | Intel® Enpirion® Power Solutions: EP5348UI
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FUNCTIONAL DESCRIPTION
Functional Overview
The EP5348UI requires only 2 small MLCC capacitors and a few small-signal components for a complete DC-
DC converter solution. The device integrates MOSFET switches, PWM controller, Gate-drive, part of the loop
compensation, and inductor into a tiny 2.0mm x 1.75mm x 0.9mm micro-QFN package. Advanced package
design, along with the high level of integration, provides very low output ripple and noise. The EP5348UI uses
voltage mode control for high noise immunity and load matching to advanced ≤90nm loads. An external
resistor divider is used to program output setting over the 0.6V to VIN-VDROPOUT as specified in the Electrical
Characteristics Table. The EP5348UI provides the industry’s highest power density of any 400mA DC-DC
converter solution.
The key enabler of this revolutionary integration is Intel Enpirion’s proprietary power MOSFET technology.
The advanced MOSFET switches are implemented in deep-submicron CMOS to supply very low switching loss
at high switching frequencies and to allow a high level of integration. The semiconductor process allows
seamless integration of all switching, control, and compensation circuitry.
The proprietary magnetics design provides high-density/high-value magnetics in a very small footprint. Intel
Enpirion magnetics are carefully matched to the control and compensation circuitry yielding an optimal
solution with assured performance over the entire operating range.
Protection features include under-voltage lock-out (UVLO), over-current protection (OCP), short circuit
protection, and thermal overload protection.
Integrated Inductor
The EP5348UI utilizes a proprietary low loss integrated inductor. The integration of the inductor greatly
simplifies the power supply design process. The inherent shielding and compact construction of the integrated
inductor reduces the noise that can couple into the traces of the printed circuit board. Further, the package
layout is optimized to reduce the electrical path length for the high di/dT currents that are always present in
DC-DC converters. The integrated inductor provides the optimal solution to the complexity, output ripple, and
noise that plague low power DC-DC converter design.
Control Matched to sub 90nm Loads
The EP5348UI utilizes a type III compensation network. Voltage mode control is inherently impedance
matched to the sub 90nm process technology that is used in today’s advanced ICs. Voltage mode control also
provides a high degree of noise immunity at light load currents so that low ripple and high accuracy are
maintained over the entire load range. The very high switching frequency allows for a very wide control loop
bandwidth and hence excellent transient performance.
Soft Start
Internal soft start circuits limit the rate of output voltage rise when the device starts up from a power down
condition, or when the “ENABLE” pin is asserted “high”. Digital control circuitry controls the VOUT rise time to
ensure a smooth turn-on ramp.
The EP5348UI has a fixed VOUT turn-on time. Therefore, the ramp rate will vary with the output voltage setting.
Output voltage rise time is given in the Electrical Characteristics Table.
05721 January 9, 2019 Rev E
Datasheet | Intel® Enpirion® Power Solutions: EP5348UI
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Excess bulk capacitance on the output of the device can cause an over-current condition at startup. The
maximum total capacitance on the output, including the output filter capacitor, and bulk and decoupling
capacitance at the load, is given as:
COUT_TOTAL_MAX = 9.333 x 10-4 / VOUT
The nominal value for the output filter capacitor is 10uF. See the applications section for more details.
Over Current/Short Circuit Protection
The current limit function is achieved by sensing the current flowing through a sense P-MOSFET which is
compared to a reference current. When this level is exceeded the P-FET is turned off and the N-FET is turned
on, pulling VOUT low. This condition is maintained for approximately 0.5mS and then a normal soft start is
initiated. If the over current condition still persists, this cycle will repeat.
Under Voltage Lockout
During initial power up an under voltage lockout circuit will hold-off the switching circuitry until the input
voltage reaches a sufficient level to ensure proper operation. If the voltage drops below the UVLO threshold,
the lockout circuitry will disable the switching. Hysteresis is included to prevent chattering between states.
Enable
The ENABLE pin provides a means to shut down the converter or enable normal operation. A logic low will
disable the converter and cause it to shut down. A logic high will enable the converter into normal operation.
NOTE: The ENABLE pin must not be left floating.
Thermal Shutdown
When excessive power is dissipated in the chip, the junction temperature rises. Once the junction temperature
exceeds the thermal shutdown threshold, the thermal shutdown circuit turns off the converter output voltage
thus allowing the device to cool. When the junction temperature decreases by 15C°, the device will go through
the normal startup process.
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Datasheet | Intel® Enpirion® Power Solutions: EP5348UI
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APPLICATION INFORMATION
Output Voltage Programming
EP5348
10µF
0603
VOUT
PVIN
AGND
V
IN
ENABLE
AVIN
PGND
C
OUT
V
OUT
R
A
R
B
VFB
2.2µF
0603
C
IN
C
AVIN
0.1µF
C
A
Figure 4. EP5348UI Application Circuit
The EP5348UI uses a simple resistor divider to program the output voltage.
Referring to Figure 3, use 200 kΩ, 1% or better for the upper resistor (RA). The value of the bottom resistor (RB)
in kΩ is given as:
nominal6.0
)(
*VVFB
VFBV
RVFB
R
OUT
A
B
=
−
=
A 5pF MLCC capacitor CA is also required in parallel with RA for compensation.
Input Filter Capacitor
CIN_MIN = 2.2µF 0603 case size or larger.
The input capacitor must use a X5R or X7R or equivalent dielectric formulation. Y5V or equivalent dielectric
formulations lose capacitance with frequency, bias, and with temperature, and are not suitable for switch-
mode DC-DC converter input filter applications.
Output Filter Capacitor
COUT_MIN = 10uF 0603 + 2.2uF 0603 MLCC when 4.5V ≤ VIN ≤ 5.5V, AND IOUT > 300mA.
COUT_MIN = 10uF 0603 MLCC for all other use cases. However, ripple performance can always be improved by
adding a second 2.2uF or 1uF output capacitor for any operating condition.
VOUT has to be sensed at the last output filter capacitor next to the EP5348UI. Any additional bulk capacitance
for load decoupling and byass has to be far enough from the VOUT sensing point so that it does not interfere
with the control loop operation. Excess total capacitance on the output (Output Filter + Bulk) can cause an
over-current condition at startup. Please see the Soft Start section under Functional Overview for the
maximum allowable bulk capacitance on the output rail.
The output capacitor must use a X5R or X7R or equivalent dielectric formulation. Y5V or equivalent dielectric
formulations lose capacitance with frequency, bias, and temperature and are not suitable for switch-mode DC-
DC converter output filter applications.
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Datasheet | Intel® Enpirion® Power Solutions: EP5348UI
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LDO Replacement
The Intel Enpirion EP5348UI is a suitable replacement for inefficient LDOs and can be used to augment the
LDOs in a PMU with minimum footprint impact. This integrated DCDC solution offers significantly better
efficiency, and significant reduction in power loss. The resulting improved thermals and extended battery life
helps meet Energy Star requirements. The total solution size is 25% smaller than a comparable LDO and half
the footprint of a comparable DC-DC.
As the table below shows, EP5348UI provides the optimal trade-off between footprint and efficiency when
compared to a traditional LDO:
Power-Up/Down Sequencing
During power-up, ENABLE should not be asserted before PVIN, and PVIN should not be asserted
before AVIN. The PVIN should never be powered when AVIN is off. During power down, the AVIN
should not be powered down before the PVIN. Tying PVIN and AVIN or all three pins (AVIN, PVIN,
ENABLE) together during power up or power down meets these requirements.
Pre-Bias Start-up
The EP5348UI does not support startup into a pre-biased condition. Be sure the output capacitors are not
charged or the output of the EP5348UI is not pre-biased when the EP5348UI is first enabled.
VIN
(V)
VOUT
(V)
LOAD
(mA)
EFF
DCDC
EFF
LDO
PLOSS
DCDC
(mW)
PLOSS
LDO
(mW)
Power Saved
(mW)
5.0 1.2 400 70.4% 24.0% 202 1520 1318
5.0 1.8 400 76.4% 36.0% 222 1280 1058
5.0 2.5 400 81.6% 50.0% 225 1000 775
5.0 3.3 400 87.7% 66.0% 185 680 495
3.3 1.2 400 77.1% 36.4% 143 840 697
3.3 1.8 400 83.3% 54.5% 144 600 456
3.3 2.5 400 88.2% 75.8% 134 320 186
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Datasheet | Intel® Enpirion® Power Solutions: EP5348UI
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LAYOUT RECOMMENDATIONS
Figure 4: Top PCB Layer Critical Components and
Copper for Minimum Footprint
Figure 5: Bottom PCB Layer Critical Components (RA, RB,
CA) & Copper for Minimum Footprint
Figures 4 and 5 show critical PCB top and bottom layer components and traces for a minimum-footpint
recommended EP5348 layout with ENABLE tied to VIN. Alternate ENABLE configurations need to be connected
and routed according to specific customer application. This layout consists of four layers. For the other 2
layers and the exact dimensions, please see the Gerber files at https://www.intel.com/enpirion. The
recommendations given below are general guidelines. Customers may need to adjust these according to their
own layout and manufacturing rules.
Recommendation 1: Input and output filter capacitors should be placed on the same side of the PCB, and as
close to the EP5348UI package as possible. They should be connected to the device with very short and wide
traces. Do not use thermal reliefs or spokes when connecting the capacitor pads to the respective nodes. The
+V and GND traces between the capacitors and the EP5348UI should be as close to each other as possible so
that the gap between the two nodes is minimized, even under the capacitors.
Recommendation 2: The system ground plane should be the first layer immediately below the surface layer.
This ground plane should be continuous and un-interrupted below the converter and the input/output
capacitors. Please see the Gerber files at https://www.intel.com/enpirion.
Recommendation 3: Multiple small vias should be used to connect ground terminal of the input capacitor and
output capacitors to the system ground plane. It is preferred to put these vias along the edge of the GND
copper closest to the +V copper. These vias connect the input/output filter capacitors to the GND plane, and
help reduce parasitic inductances in the input and output current loops. See Figure 4. If the two vias cannot be
put under CIN or COUT, then put two vias right after the capacitors next the VIN and VOUT vias.
Recommendation 4: As Figure 5 shows, RA, RB, and CA have been placed on the back side to minimize the
footprint. These components also need to be close to the VFB pin (see Figures 3, 4 and 5). The VFB pin is a
high-impedance, sensitive node. Keep any trace connected to this node as short and thin as possible.
Whenever possible, connect RB directly to the AGND pin instead of going through the GND plane. In the layout
shown above, RB goes to the via next to AGND pin using a dedicated trace on layer 3 not shown here. Please
see the Gerber files at https://www.intel.com/enpirion.
05721 January 9, 2019 Rev E
Datasheet | Intel® Enpirion® Power Solutions: EP5348UI
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Recommendation 5: AVIN is the power supply for the small-signal control circuits. It should be connected to
the input voltage at a quiet point. In Figure 4 this connection is made at the vias just before CIN. There is an
additional decoupling capacitor CAVIN for AVIN which is connected between the device pin and the GND plane.
Recommendation 6: The via to the right of pin 2 underneath the device helps to minimize the parasitic
inductances in the input and output loop ground connections.
Recommendation 7: The top layer 1 metal under the device must not be more than shown in Figure 4. As with
any switch-mode DC/DC converter, try not to run sensitive signal or control lines underneath the converter
package on other layers.
Recommendation 8: The VOUT sense point should be just after the last output filter capacitor. Keep the sense
trace short in order to avoid noise coupling into the node.
RECOMMENDED PCB FOOTPRINT
Figure 6: EP5348UI PCB Footprint (Top View)
Dimensions in mm
05721 January 9, 2019 Rev E
Datasheet | Intel® Enpirion® Power Solutions: EP5348UI
WHERE TO GET MORE INFORMATION
For more information about Intel® and Enpirion® PowerSoCs, visit:
https://www.intel.com/enpirion
© 2017 Intel Corporation. All rights reserved. Intel, the Intel logo, Altera, ARRIA, CYCLONE, ENPIRION, MAX, MEGACORE, NIOS, QUARTUS, and STRATIX words and logos are trademarks of Intel
Corporation or its subsidiaries in the U.S. and/or other countries. Other marks and brands may be claimed as the property of others. Intel reserves the right to make changes to any products and
services at any time without notice. Intel assumes no responsibility or liability arising out of the application or use of any information, product, or service described herein except as expressly agreed to
in writing by Intel. Intel customers are advised to obtain the latest version of device specifications before relying on any published information and before placing orders for products or services.
* Other marks and brands may be claimed as the property of others.
Page 16
REVISION HISTORY
Rev Date Change(s)
E Dec, 2018 Changed datasheet into Intel format.
05721 January 9, 2019 Rev E
