Publication Number 21445 Revision EAmendment 8Issue Date November 11, 2009
Am29F040B
Am29F040 B Cover S heet
Data Sheet
The following document contains information on Spansion memory products.
Continuity of Specifications
There is no change to this data sheet as a result of offering the device as a Spansion product. Any changes that have been
made are the result of normal data sheet improvement and are noted in the document revision summary.
For More Information
Please contact your local sales office for additional information about Spansion memory solutions.
2 Am29F040B 21445_E8 November 11, 2009
Data Sheet
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DATA SHEET
This Data Sheet states AMD’s current technical specifications regarding the Products described herein. This Data
Sheet may be revised by subsequent versions or modifications due to changes in technical specifications.
Publication# 21445 Rev: EAmendment: 8
Issue Date: November 11, 2009
Am29F040B
4 Megabit (512 K x 8-Bit)
CMOS 5.0 Volt-only, Uniform Sector Flash Memory
DISTINCTIVE CHARACTERISTICS
• 5.0 V ± 10% for read and write operations
— Minimizes system level power requirements
• Manufactured on 0.32 µm process technology
— Compatible with 0.5 µm Am29F040 device
• High performance
— Access times as fast as 55 ns
• Low power consumption
— 20 mA typical active read current
— 30 mA typical program/erase current
— 1 µA typical standby current (standard access
time to active mode)
• Flexible sector architecture
— 8 uniform sectors of 64 Kbytes each
— Any combination of sectors can be erased
— Supports full chip erase
— Sector protection:
A hardware method of locking sectors to prevent
any program or erase operations within that sector
• Embedded Algorithms
— Embedded Erase algorithm automatically
preprograms and erases the entire chip or any
combination of designated sectors
— Embedded Program algorithm automatically
writes and verifies bytes at specified addresses
• Minimum 1,000,000 program/erase cycles per
sector guaranteed
• 20-year data retention at 125°C
— Reliable operation for the life of the system
• Package options
— 32-pin PLCC or TSOP
• Compatible with JEDEC standards
— Pinout and software compatible with
single-power-supply Flash standard
— Superior inadvertent write protection
• Data# Polling and toggle bits
— Provides a software method of detecting
program or erase cycle completion
• Erase Suspend/Erase Resume
— Suspends a sector erase operation to read data
from, or program data to, a non-erasing sector,
then resumes the erase operation
2 Am29F040B 21445E8 November 11, 2009
DATA SHEET
GENERAL DESCRIPTION
The Am29F040B is a 4 Mbit, 5.0 volt-only Flash mem-
ory organized as 524,288 Kbytes of 8 bits each. The
512 Kbytes of data are divided into eight sectors of 64
Kbytes each for flexible erase capability. The 8 bits of
data appear on DQ0–DQ7. The Am29F040B is offered
in 32-pin PLCC or TSOP packages. This device is de-
signed to be programmed in-system with the standard
system 5.0 volt VCC supply. A 12.0 volt VPP is not re-
quired for write or erase operations. The device can also
be programmed in standard EPROM programmers.
This device is manufactured using AMD’s 0.32 µm pro-
cess technology, and offers all the features and
benefits of the Am29F040, which was manufactured
using 0.5 µm process technology. In addtion, the
Am29F040B has a second toggle bit, DQ2, and also of-
fers the ability to program in the Erase Suspend mode.
The standard Am29F040B offers access times of 55,
70 and 90 ns, allowing high-speed microprocessors to
operate without wait states. To eliminate bus contention
the device has separate chip enable (CE#), write en-
able (WE#) and output enable (OE#) controls.
The device requires only a single 5.0 volt power sup-
ply for both read and write functions. Internally
generated and regulated voltages are provided for the
program and erase operations.
The device is entirely command set compatible with the
JEDEC single-power-supply Flash standard. Com-
mands are written to the command register using
standard microprocessor write timings. Register con-
tents serve as input to an internal state-machine that
controls the erase and programming circuitry. Write cy-
cles also internally latch addresses and data needed
for the programming and erase operations. Reading
data out of the device is similar to reading from other
Flash or EPROM devices.
Device programming occurs by executing the program
command sequence. This initiates the Embedded
Program algorithm—an internal algorithm that auto-
matically times the program pulse widths and verifies
proper cell margin.
Device erasure occurs by executing the erase com-
mand sequence. This initiates the Embedded Erase
algorithm—an internal algorithm that automatically
preprograms the array (if it is not already programmed)
before executing the erase operation. During erase, the
device automatically times the erase pulse widths and
verifies proper cell margin.
The host system can detect whether a program or
erase operation is complete by reading the DQ7 (Data#
Polling) and DQ6 (toggle) status bits. After a program
or erase cycle has been completed, the device is ready
to read array data or accept another command.
The sector erase architecture allows memory sectors
to be erased and reprogrammed without affecting the
data contents of other sectors. The device is fully
erased when shipped from the factory.
Hardware data protection measures include a low
VCC detector that automatically inhibits write opera-
tions during power transitions. The hardware sector
protection feature disables both program and erase
operations in any combination of the sectors of mem-
ory. This can be achieved via programming equipment.
The Erase Suspend feature enables the user to put
erase on hold for any period of time to read data from,
or program data to, any sector that is not selected for
erasure. True background erase can thus be achieved.
The system can place the device into the standby mode.
Power consumption is greatly reduced in this mode.
AMD’s Flash technology combines years of Flash
memory manufacturing experience to produce the
highest levels of quality, reliability and cost effective-
ness. The device electrically erases all bits within a
sector simultaneously via Fowler-Nordheim tunneling.
The data is programmed using hot electron injection.
November 11, 2009 21445E8 Am29F040B 3
DATA SHEET
TABLE OF CONTENTS
Product Selector Guide . . . . . . . . . . . . . . . . . . . . . 4
Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
Connection Diagrams . . . . . . . . . . . . . . . . . . . . . . 5
Pin Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . 5
Logic Symbol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
Ordering Information . . . . . . . . . . . . . . . . . . . . . . . 6
Device Bus Operations . . . . . . . . . . . . . . . . . . . . . 7
Table 1. Am29F040B Device Bus Operations ...................................7
Requirements for Reading Array Data ..................................... 7
Writing Commands/Command Sequences .............................. 7
Program and Erase Operation Status ...................................... 7
Standby Mode .......................................................................... 7
Output Disable Mode................................................................ 8
Table 2. Sector Addresses Table ......................................................8
Autoselect Mode....................................................................... 9
Table 3. Am29F040B Autoselect Codes (High Voltage Method) .......9
Sector Protection/Unprotection................................................. 9
Hardware Data Protection ........................................................ 9
Low VCC Write Inhibit ........................................................................ 9
Write Pulse “Glitch” Protection.......................................................... 9
Logical Inhibit .................................................................................... 9
Power-Up Write Inhibit ...................................................................... 9
Command Definitions . . . . . . . . . . . . . . . . . . . . . 10
Reading Array Data ................................................................ 10
Reset Command..................................................................... 10
Autoselect Command Sequence ............................................ 10
Byte Program Command Sequence....................................... 10
Figure 1. Program Operation ......................................................... 11
Chip Erase Command Sequence ........................................... 11
Sector Erase Command Sequence ........................................ 11
Erase Suspend/Erase Resume Commands........................... 12
Figure 2. Erase Operation.............................................................. 12
Command Definitions ............................................................. 13
Table 4. Am29F040B Command Definitions....................................13
Write Operation Status . . . . . . . . . . . . . . . . . . . . 14
DQ7: Data# Polling................................................................. 14
Figure 3. Data# Polling Algorithm .................................................. 14
DQ6: Toggle Bit I .................................................................... 15
DQ2: Toggle Bit II ................................................................... 15
Reading Toggle Bits DQ6/DQ2............................................... 15
DQ5: Exceeded Timing Limits ................................................ 15
DQ3: Sector Erase Timer ....................................................... 16
Figure 4. Toggle Bit Algorithm....................................................... 16
Table 5. Write Operation Status...................................................... 17
Absolute Maximum Ratings. . . . . . . . . . . . . . . . . 18
Figure 5. Maximum Negative Overshoot Waveform ..................... 18
Figure 6. Maximum Positive Overshoot Waveform....................... 18
Operating Ranges . . . . . . . . . . . . . . . . . . . . . . . . . 18
DC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . 19
TTL/NMOS Compatible .......................................................... 19
CMOS Compatible.................................................................. 19
Test Conditions. . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Figure 7. Test Setup..................................................................... 20
Table 6. Test Specifications ........................................................... 20
Key to Switching Waveforms. . . . . . . . . . . . . . . . 20
AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . 21
Read Only Operations ............................................................ 21
Figure 8. Read Operation Timings ................................................ 22
Erase and Program Operations .............................................. 23
Figure 9. Program Operation Timings........................................... 24
Figure 10. Chip/Sector Erase Operation Timings ......................... 24
Figure 11. Data# Polling Timings (During Embedded Algorithms) 25
Figure 12. Toggle Bit Timings (During Embedded Algorithms)..... 25
Figure 13. DQ2 vs. DQ6................................................................ 26
AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . 27
Erase and Program Operations .............................................. 27
Alternate CE# Controlled Writes .................................................... 27
Figure 14. Alternate CE# Controlled Write Operation Timings ..... 28
Erase and Programming Performance . . . . . . . . 29
Latchup Characteristics . . . . . . . . . . . . . . . . . . . . 29
TSOP Pin Capacitance . . . . . . . . . . . . . . . . . . . . 29
PLCC Pin Capacitance . . . . . . . . . . . . . . . . . . . . . 30
Data Retention. . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
PL 032—32-Pin Plastic Leaded Chip Carrier ......................... 31
TS 032—32-Pin Standard Thin Small Package...................... 32
Revision Summary . . . . . . . . . . . . . . . . . . . . . . . . 33
4 Am29F040B 21445E8 November 11, 2009
DATA SHEET
PRODUCT SELECTOR GUIDE
Note: See the “AC Characteristics” section for more information.
BLOCK DIAGRAM
Family Part Number Am29F040B
Speed Option
VCC = 5.0 V ± 5% -55
VCC = 5.0 V ± 10% -70 -90
Max access time, ns (tACC)55 70 90
Max CE# access time, ns (tCE)55 70 90
Max OE# access time, ns (tOE)25 30 35
Erase Voltage
Generator
Y- G a t i n g
Cell MatrixX-Decoder
Y-Decoder
Address Latch
Chip Enable
Output Enable
Logic
PGM Voltage
Generator
Timer
VCC Detector
State
Control
Command
Register
WE#
CE#
OE#
A0–A18
STB
STB
DQ0–DQ7
VCC
VSS
Data Latch
Input/Output
Buffers
November 11, 2009 21445E8 Am29F040B 5
DATA SHEET
CONNECTION DIAGRAMS
PIN CONFIGURATION
A0–A18 = Address Inputs
DQ0–DQ7 = Data Input/Output
CE# = Chip Enable
WE# = Write Enable
OE# = Output Enable
VSS = Device Ground
VCC =+5.0 V single power supply
(see Product Selector Guide for
device speed ratings and voltage
supply tolerances)
LOGIC SYMBOL
5
6
7
8
9
10
11
12
13
17 18 19 20161514
29
28
27
26
25
24
23
22
21
1313023432
A7
A6
A5
A4
A3
A2
A1
A0
DQ0
DQ1
DQ2
VSS
DQ3
DQ4
DQ5
DQ6
A14
A13
A8
A9
A11
OE#
A10
CE#
DQ7
A12
A15
A16
A18
VCC
WE#
A17
PLCC
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
A11
A9
A8
A13
A14
A17
WE#
V
CC
A18
A16
A15
A12
A7
A6
A5
A4
OE#
A10
CE#
DQ7
DQ6
DQ5
DQ4
DQ3
V
SS
DQ2
DQ1
DQ0
A0
A1
A2
A3
32-Pin Standard TSOP
19
8
DQ0–DQ7
A0–A18
CE#
OE#
WE#
6 Am29F040B 21445E8 November 11, 2009
DATA SHEET
ORDERING INFORMATION
Standard Products
AMD standard products are available in several packages and operating ranges. The order number (Valid Combi-
nation) is formed by a combination of the following:
Valid Combinations
Valid Combinations list configurations planned to be supported in volume for this device. Consult the local AMD sales office to
confirm availability of specific valid combinations and to check on newly released combinations.
Am29F040B -55 E F
TEMPERATURE RANGE
I = Industrial (-40°C to +85°C)
E = Extended (–55°C to +125°C)
F = Industrial (-40°C to +85°C) for Pb-free Package
K = Extended (-55°C to +125°C) for Pb-free Package
PACKAGE TYPE
J = 32-Pin Rectangular Plastic Leaded Chip Carrier (PL 032)
E = 32-Pin Thin Small Outline Package (TSOP) Standard Pinout (TS 032)
SPEED OPTION
See Product Selector Guide and Valid Combinations
DEVICE NUMBER/DESCRIPTION
Am29F040B
4 Megabit (512 K x 8-Bit) CMOS 5.0 Volt-only Sector Erase Flash Memory
5.0 V Read, Program, and Erase
Valid Combinations VCC Voltage
AM29F040B-55 JI, JE, JF, JK
EI, EE, EF, EK
5.0 V ± 5%
AM29F040B-70
5.0 V ± 10%
AM29F040B-90 JI, JE,JF, JK
EI, EE, EF, EK
November 11, 2009 21445E8 Am29F040B 7
DATA SHEET
DEVICE BUS OPERATIONS
This section describes the requirements and use of the
device bus operations, which are initiated through the
internal command register. The command register it-
self does not occupy any addressable memory
location. The register is composed of latches that store
the commands, along with the address and data infor-
mation needed to execute the command. The contents
of the register serve as inputs to the internal state ma-
chine. The state machine outputs dictate the function of
the device. The appropriate device bus operations
table lists the inputs and control levels required, and the
resulting output. The following subsections describe
each of these operations in further detail.
Table 1. Am29F040B Device Bus Operations
Legend:
L = Logic Low = VIL, H = Logic High = VIH, VID = 12.0 ± 0.5 V, X = Don’t Care, DIN = Data In, DOUT = Data Out, AIN = Address In
Note: See the “Sector Protection/Unprotection” section. for more information.
Requirements for Reading Array Data
To read array data from the outputs, the system must
drive the CE# and OE# pins to VIL. CE# is the power
control and selects the device. OE# is the output con-
trol and gates array data to the output pins. WE# should
remain at VIH.
The internal state machine is set for reading array data
upon device power-up, or after a hardware reset. This
ensures that no spurious alteration of the memory con-
tent occurs during the power transition. No command is
necessary in this mode to obtain array data. Standard
microprocessor read cycles that assert valid addresses
on the device address inputs produce valid data on the
device data outputs. The device remains enabled for
read access until the command register contents are
altered.
See “Reading Array Data” for more information. Refer
to the AC Read Operations table for timing specifica-
tions and to the Read Operations Timings diagram for
the timing waveforms. ICC1 in the DC Characteristics
table represents the active current specification for
reading array data.
Writing Commands/Command Sequences
To write a command or command sequence (which in-
cludes programming data to the device and erasing
sectors of memory), the system must drive WE# and
CE# to VIL, and OE# to VIH.
An erase operation can erase one sector, multiple sec-
tors, or the entire device. The Sector Address Tables
indicate the address space that each sector occupies.
A “sector address” consists of the address bits required
to uniquely select a sector. See the “Command Defini-
tions” section for details on erasing a sector or the
entire chip, or suspending/resuming the erase
operation.
After the system writes the autoselect command se-
quence, the device enters the autoselect mode. The
system can then read autoselect codes from the inter-
nal register (which is separate from the memory array)
on DQ7–DQ0. Standard read cycle timings apply in this
mode. Refer to the “Autoselect Mode” and “Autoselect
Command Sequence” sections for more information.
ICC2 in the DC Characteristics table represents the ac-
tive current specification for the write mode. The “AC
Characteristics” section contains timing specification
tables and timing diagrams for write operations.
Program and Erase Operation Status
During an erase or program operation, the system may
check the status of the operation by reading the status
bits on DQ7–DQ0. Standard read cycle timings and ICC
read specifications apply. Refer to “Write Operation
Status” for more information, and to each AC Charac-
teristics section for timing diagrams.
Standby Mode
When the system is not reading or writing to the device,
it can place the device in the standby mode. In this
mode, current consumption is greatly reduced, and the
Operation CE# OE# WE# A0–A20 DQ0–DQ7
Read L L H AIN DOUT
Write L H L AIN DIN
CMOS Standby VCC ± 0.5 V X X X High-Z
TTL Standby H X X X High-Z
Output Disable L H H X High-Z
8 Am29F040B 21445E8 November 11, 2009
DATA SHEET
outputs are placed in the high impedance state, inde-
pendent of the OE# input.
The device enters the CMOS standby mode when the
CE# pin is held at VCC ± 0.5 V. (Note that this is a more
restricted voltage range than VIH.) The device enters
the TTL standby mode when CE# is held at VIH. The
device requires the standard access time (tCE) before it
is ready to read data.
If the device is deselected during erasure or program-
ming, the device draws active current until the
operation is completed.
ICC3 in the DC Characteristics tables represents the
standby current specification.
Output Disable Mode
When the OE# input is at VIH, output from the device is
disabled. The output pins are placed in the high imped-
ance state.
Table 2. Sector Addresses Table
Note: All sectors are 64 Kbytes in size.
Sector A18 A17 A16 Address Range
SA0 000 00000h–0FFFFh
SA1 001 10000h–1FFFFh
SA2 010 20000h–2FFFFh
SA3 011 30000h–3FFFFh
SA4 100 40000h–4FFFFh
SA5 101 50000h–5FFFFh
SA6 110 60000h–6FFFFh
SA7 111 70000h–7FFFFh
November 11, 2009 21445E8 Am29F040B 9
DATA SHEET
Autoselect Mode
The autoselect mode provides manufacturer and de-
vice identification, and sector protection verification,
through identifier codes output on DQ7–DQ0. This
mode is primarily intended for programming equipment
to automatically match a device to be programmed with
its corresponding programming algorithm. However,
the autoselect codes can also be accessed in-system
through the command register.
When using programming equipment, the autoselect
mode requires VID (11.5 V to 12.5 V) on address pin
A9. Address pins A6, A1, and A0 must be as shown in
Autoselect Codes (High Voltage Method) table. In addi-
tion, when verifying sector protection, the sector
address must appear on the appropriate highest order
address bits. Refer to the corresponding Sector Ad-
dress Tables. The Command Definitions table shows
the remaining address bits that are don’t care. When all
necessary bits have been set as required, the program-
ming equipment may then read the corresponding
identifier code on DQ7–DQ0.
To access the autoselect codes in-system, the host
system can issue the autoselect command via the
command register, as shown in the Command Defini-
tions table. This method does not require VID. See
“Command Definitions” for details on using the autose-
lect mode.
Table 3. Am29F040B Autoselect Codes (High Voltage Method)
Sector Protection/Unprotection
The hardware sector protection feature disables both
program and erase operations in any sector. The hard-
ware sector unprotection feature re-enables both
program and erase operations in previously protected
sectors.
Sector protection/unprotection must be implemented
using programming equipment. The procedure re-
quires a high voltage (VID) on address pin A9 and the
control pins. Details on this method are provided in a
supplement, publication number 19957. Contact an
AMD representative to obtain a copy of the appropriate
document.
The device is shipped with all sectors unprotected.
AMD offers the option of programming and protecting
sectors at its factory prior to shipping the device
through AMD’s ExpressFlash™ Service. Contact an
AMD representative for details.
It is possible to determine whether a sector is protected
or unprotected. See “Autoselect Mode” for details.
Hardware Data Protection
The command sequence requirement of unlock cycles
for programming or erasing provides data protection
against inadvertent writes (refer to the Command Defi-
nitions table). In addition, the following hardware data
protection measures prevent accidental erasure or pro-
gramming, which might otherwise be caused by
spurious system level signals during VCC power-up and
power-down transitions, or from system noise.
Low VCC Write Inhibit
When VCC is less than VLKO, the device does not ac-
cept any write cycles. This protects data during VCC
power-up and power-down. The command register and
all internal program/erase circuits are disabled, and the
device resets. Subsequent writes are ignored until VCC
is greater than VLKO. The system must provide the
proper signals to the control pins to prevent uninten-
tional writes when VCC is greater than VLKO.
Write Pulse “Glitch” Protection
Noise pulses of less than 5 ns (typical) on OE#, CE# or
WE# do not initiate a write cycle.
Logical Inhibit
Write cycles are inhibited by holding any one of OE# =
VIL, CE# = VIH or WE# = VIH. To initiate a write cycle,
CE# and WE# must be a logical zero while OE# is a
logical one.
Power-Up Write Inhibit
If WE# = CE# = VIL and OE# = VIH during power up, the
device does not accept commands on the rising edge
of WE#. The internal state machine is automatically
reset to reading array data on power-up.
Description A18–A16 A15–A10 A9 A8–A7 A6 A5–A2 A1 A0
Identifier Code on
DQ7-DQ0
Manufacturer ID: AMD X X VID X VIL X VIL VIL 01h
Device ID: Am29F040B X X VID X VIL X VIL VIH A4h
Sector Protection
Verification
Sector
Address X VID X VIL X VIH VIL
01h (protected)
00h (unprotected)
10 Am29F040B 21445E8 November 11, 2009
DATA SHEET
COMMAND DEFINITIONS
Writing specific address and data commands or se-
quences into the command register initiates device
operations. The Command Definitions table defines the
valid register command sequences. Writing incorrect
address and data values or writing them in the im-
proper sequence resets the device to reading array
data.
All addresses are latched on the falling edge of WE# or
CE#, whichever happens later. All data is latched on
the rising edge of WE# or CE#, whichever happens
first. Refer to the appropriate timing diagrams in the
“AC Characteristics” section.
Reading Array Data
The device is automatically set to reading array data
after device power-up. No commands are required to
retrieve data. The device is also ready to read array
data after completing an Embedded Program or Em-
bedded Erase algorithm.
After the device accepts an Erase Suspend command,
the device enters the Erase Suspend mode. The sys-
tem can read array data using the standard read
timings, except that if it reads at an address within
erase-suspended sectors, the device outputs status
data. After completing a programming operation in the
Erase Suspend mode, the system may once again
read array data with the same exception. See “Erase
Suspend/Erase Resume Commands” for more infor-
mation on this mode.
The system must issue the reset command to re-en-
able the device for reading array data if DQ5 goes high,
or while in the autoselect mode. See the “Reset Com-
mand” section, next.
See also “Requirements for Reading Array Data” in the
“Device Bus Operations” section for more information.
The Read Operations table provides the read parame-
ters, and Read Operation Timings diagram shows the
timing diagram.
Reset Command
Writing the reset command to the device resets the de-
vice to reading array data. Address bits are don’t care
for this command.
The reset command may be written between the se-
quence cycles in an erase command sequence before
erasing begins. This resets the device to reading array
data. Once erasure begins, however, the device ig-
nores reset commands until the operation is complete.
The reset command may be written between the se-
quence cycles in a program command sequence
before programming begins. This resets the device to
reading array data (also applies to programming in
Erase Suspend mode). Once programming begins,
however, the device ignores reset commands until the
operation is complete.
The reset command may be written between the se-
quence cycles in an autoselect command sequence.
Once in the autoselect mode, the reset command must
be written to return to reading array data (also applies
to autoselect during Erase Suspend).
If DQ5 goes high during a program or erase operation,
writing the reset command returns the device to read-
ing array data (also applies during Erase Suspend).
Autoselect Command Sequence
The autoselect command sequence allows the host
system to access the manufacturer and devices codes,
and determine whether or not a sector is protected.
The Command Definitions table shows the address
and data requirements. This method is an alternative to
that shown in the Autoselect Codes (High Voltage
Method) table, which is intended for PROM program-
mers and requires VID on address bit A9.
The autoselect command sequence is initiated by writ-
ing two unlock cycles, followed by the autoselect
command. The device then enters the autoselect
mode, and the system may read at any address any
number of times, without initiating another command
sequence.
A read cycle at address XX00h or retrieves the manu-
facturer code. A read cycle at address XX01h returns
the device code. A read cycle containing a sector ad-
dress (SA) and the address 02h in returns 01h if that
sector is protected, or 00h if it is unprotected. Refer to
the Sector Address tables for valid sector addresses.
The system must write the reset command to exit the
autoselect mode and return to reading array data.
Byte Program Command Sequence
Programming is a four-bus-cycle operation. The pro-
gram command sequence is initiated by writing two
unlock write cycles, followed by the program set-up
command. The program address and data are written
next, which in turn initiate the Embedded Program al-
gorithm. The system is not required to provide further
controls or timings. The device automatically provides
internally generated program pulses and verify the pro-
grammed cell margin. The Command Definitions take
shows the address and data requirements for the byte
program command sequence.
When the Embedded Program algorithm is complete,
the device then returns to reading array data and ad-
dresses are no longer latched. The system can
determine the status of the program operation by using
DQ7 or DQ6. See “Write Operation Status” for informa-
tion on these status bits.
November 11, 2009 21445E8 Am29F040B 11
DATA SHEET
Any commands written to the device during the Em-
bedded Program Algorithm are ignored.
Programming is allowed in any sequence and across
sector boundaries. A bit cannot be programmed
from a “0” back to a “1”. Attempting to do so may halt
the operation and set DQ5 to “1”, or cause the Data#
Polling algorithm to indicate the operation was suc-
cessful. However, a succeeding read shows that the
data is still “0”. Only erase operations can convert a “0”
to a “1”.
Note: See the appropriate Command Definitions table for
program command sequence.
Figure 1. Program Operation
Chip Erase Command Sequence
Chip erase is a six-bus-cycle operation. The chip erase
command sequence is initiated by writing two unlock
cycles, followed by a set-up command. Two additional
unlock write cycles are then followed by the chip erase
command, which in turn invokes the Embedded Erase
algorithm. The device does not require the system to
preprogram prior to erase. The Embedded Erase algo-
rithm automatically preprograms and verifies the entire
memory for an all zero data pattern prior to electrical
erase. The system is not required to provide any con-
trols or timings during these operations. The Command
Definitions table shows the address and data require-
ments for the chip erase command sequence.
Any commands written to the chip during the Embed-
ded Erase algorithm are ignored.
The system can determine the status of the erase op-
eration by using DQ7, DQ6, or DQ2. See “Write
Operation Status” for information on these status bits.
When the Embedded Erase algorithm is complete, the
device returns to reading array data and addresses are
no longer latched.
Figure 2 illustrates the algorithm for the erase opera-
tion. See the Erase and Program Operations tables in
“AC Characteristics” for parameters, and to the Chip/
Sector Erase Operation Timings for timing waveforms.
Sector Erase Command Sequence
Sector erase is a six bus cycle operation. The sector
erase command sequence is initiated by writing two un-
lock cycles, followed by a set-up command. Two
additional unlock write cycles are then followed by the
address of the sector to be erased, and the sector
erase command. The Command Definitions table
shows the address and data requirements for the sec-
tor erase command sequence.
The device does not require the system to preprogram
the memory prior to erase. The Embedded Erase algo-
rithm automatically programs and verifies the sector for
an all zero data pattern prior to electrical erase. The
system is not required to provide any controls or tim-
ings during these operations.
After the command sequence is written, a sector erase
time-out of 50 µs begins. During the time-out period,
additional sector addresses and sector erase com-
mands may be written. Loading the sector erase buffer
may be done in any sequence, and the number of sec-
tors may be from one sector to all sectors. The time
between these additional cycles must be less than 50
µs, otherwise the last address and command might not
be accepted, and erasure may begin. It is recom-
mended that processor interrupts be disabled during
this time to ensure all commands are accepted. The in-
terrupts can be re-enabled after the last Sector Erase
command is written. If the time between additional sec-
tor erase commands can be assumed to be less than
50 µs, the system need not monitor DQ3. Any com-
mand other than Sector Erase or Erase Suspend
during the time-out period resets the device to
reading array data. The system must rewrite the com-
mand sequence and any additional sector addresses
and commands.
The system can monitor DQ3 to determine if the sector
erase timer has timed out. (See the “DQ3: Sector Erase
START
Write Program
Command Sequence
Data Poll
from System
Verify Data? No
Yes
Last Address?
No
Yes
Programming
Completed
Increment Address
Embedded
Program
algorithm
in progress
12 Am29F040B 21445E8 November 11, 2009
DATA SHEET
Timer” section.) The time-out begins from the rising
edge of the final WE# pulse in the command sequence.
Once the sector erase operation has begun, only the
Erase Suspend command is valid. All other commands
are ignored.
When the Embedded Erase algorithm is complete, the
device returns to reading array data and addresses are
no longer latched. The system can determine the sta-
tus of the erase operation by using DQ7, DQ6, or DQ2.
Refer to “Write Operation Status” for information on
these status bits.
Figure 2 illustrates the algorithm for the erase opera-
tion. Refer to the Erase/Program Operations tables in
the “AC Characteristics” section for parameters, and to
the Sector Erase Operations Timing diagram for timing
waveforms.
Erase Suspend/Erase Resume Commands
The Erase Suspend command allows the system to in-
terrupt a sector erase operation and then read data
from, or program data to, any sector not selected for
erasure. This command is valid only during the sector
erase operation, including the 50 µs time-out period
during the sector erase command sequence. The
Erase Suspend command is ignored if written during
the chip erase operation or Embedded Program algo-
rithm. Writing the Erase Suspend command during the
Sector Erase time-out immediately terminates the
time-out period and suspends the erase operation. Ad-
dresses are “don’t-cares” when writing the Erase
Suspend command.
When the Erase Suspend command is written during a
sector erase operation, the device requires a maximum
of 20 µs to suspend the erase operation. However,
when the Erase Suspend command is written during
the sector erase time-out, the device immediately ter-
minates the time-out period and suspends the erase
operation.
After the erase operation has been suspended, the
system can read array data from or program data to
any sector not selected for erasure. (The device “erase
suspends” all sectors selected for erasure.) Normal
read and write timings and command definitions apply.
Reading at any address within erase-suspended sec-
tors produces status data on DQ7–DQ0. The system
can use DQ7, or DQ6 and DQ2 together, to determine
if a sector is actively erasing or is erase-suspended.
See “Write Operation Status” for information on these
status bits.
After an erase-suspended program operation is com-
plete, the system can once again read array data within
non-suspended sectors. The system can determine
the status of the program operation using the DQ7 or
DQ6 status bits, just as in the standard program oper-
ation. See “Write Operation Status” for more
information.
The system may also write the autoselect command
sequence when the device is in the Erase Suspend
mode. The device allows reading autoselect codes
even at addresses within erasing sectors, since the
codes are not stored in the memory array. When the
device exits the autoselect mode, the device reverts to
the Erase Suspend mode, and is ready for another
valid operation. See “Autoselect Command Sequence”
for more information.
The system must write the Erase Resume command
(address bits are “don’t care”) to exit the erase suspend
mode and continue the sector erase operation. Further
writes of the Resume command are ignored. Another
Erase Suspend command can be written after the de-
vice has resumed erasing.
Notes:
1. See the appropriate Command Definitions table for erase
command sequence.
2. See “DQ3: Sector Erase Timer” for more information.
Figure 2. Erase Operation
START
Write Erase
Command Sequence
Data Poll
from System
Data = FFh?
No
Yes
Erasure Completed
Embedded
Erase
algorithm
in progress
November 11, 2009 21445E8 Am29F040B 13
DATA SHEET
Command Definitions
Table 4. Am29F040B Command Definitions
Legend:
X = Don’t care
RA = Address of the memory location to be read.
RD = Data read from location RA during read operation.
PA = Address of the memory location to be programmed.
Addresses latch on the falling edge of the WE# or CE# pulse,
whichever happens later.
PD = Data to be programmed at location PA. Data latches on the
rising edge of WE# or CE# pulse, whichever happens first.
SA = Address of the sector to be verified (in autoselect mode) or
erased. Address bits A18–A16 select a unique sector.
Notes:
1. See Table 1 for description of bus operations.
2. All values are in hexadecimal.
3. Except when reading array or autoselect data, all bus cycles
are write operations.
4. Address bits A18–A11 are don’t cares for unlock and
command cycles, unless SA or PA required.
5. No unlock or command cycles required when reading array data.
6. The Reset command is required to return to reading array
data when device is in the autoselect mode, or if DQ5 goes
high (while the device is providing status data).
7. The fourth cycle of the autoselect command sequence is a
read cycle.
8. The data is 00h for an unprotected sector and 01h for a
protected sector.See “Autoselect Command Sequence” for
more information.
9. The system may read and program in non-erasing sectors, or
enter the autoselect mode, when in the Erase Suspend
mode. The Erase Suspend command is valid only during a
sector erase operation.
10. The Erase Resume command is valid only during the Erase
Suspend mode.
Command
Sequence
(Note 1)
Cycles
Bus Cycles (Notes 2–4)
First Second Third Fourth Fifth Sixth
Addr Data Addr Data Addr Data Addr Data Addr Data Addr Data
Read (Note 5) 1 RA RD
Reset (Note 6) 1 XXX F0
Autoselect
(Note 7)
Manufacturer ID 4 555 AA 2AA 55 555 90 X00 01
Device ID 4 555 AA 2AA 55 555 90 X01 A4
Sector Protect Verify
(Note 8) 4 555 AA 2AA 55 555 90 SA
X02
00
01
Program 4 555 AA 2AA 55 555 A0 PA PD
Chip Erase 6 555 AA 2AA 55 555 80 555 AA 2AA 55 555 10
Sector Erase 6 555 AA 2AA 55 555 80 555 AA 2AA 55 SA 30
Erase Suspend (Note 9) 1 XXX B0
Erase Resume (Note 10) 1 XXX 30
14 Am29F040B 21445E8 November 11, 2009
DATA SHEET
WRITE OPERATION STATUS
The device provides several bits to determine the sta-
tus of a write operation: DQ2, DQ3, DQ5, DQ6, and
DQ7. Table 5 and the following subsections describe
the functions of these bits. DQ7 and DQ6 each offer a
method for determining whether a program or erase
operation is complete or in progress. These three bits
are discussed first.
DQ7: Data# Polling
The Data# Polling bit, DQ7, indicates to the host sys-
tem whether an Embedded Algorithm is in progress or
completed, or whether the device is in Erase Suspend.
Data# Polling is valid after the rising edge of the final
WE# pulse in the program or erase command
sequence.
During the Embedded Program algorithm, the device
outputs on DQ7 the complement of the datum pro-
grammed to DQ7. This DQ7 status also applies to
programming during Erase Suspend. When the Em-
bedded Program algorithm is complete, the device
outputs the datum programmed to DQ7. The system
must provide the program address to read valid status
information on DQ7. If a program address falls within a
protected sector, Data# Polling on DQ7 is active for ap-
proximately 2 µs, then the device returns to reading
array data.
During the Embedded Erase algorithm, Data# Polling
produces a “0” on DQ7. When the Embedded Erase al-
gorithm is complete, or if the device enters the Erase
Suspend mode, Data# Polling produces a “1” on DQ7.
This is analogous to the complement/true datum output
described for the Embedded Program algorithm: the
erase function changes all the bits in a sector to “1”;
prior to this, the device outputs the “complement,” or
“0.” The system must provide an address within any of
the sectors selected for erasure to read valid status in-
formation on DQ7.
After an erase command sequence is written, if all sec-
tors selected for erasing are protected, Data# Polling
on DQ7 is active for approximately 100 µs, then the de-
vice returns to reading array data. If not all selected
sectors are protected, the Embedded Erase algorithm
erases the unprotected sectors, and ignores the se-
lected sectors that are protected.
When the system detects DQ7 has changed from the
complement to true data, it can read valid data at
DQ7–DQ0 on the following read cycles. This is be-
cause DQ7 may change asynchronously with
DQ0–DQ6 while Output Enable (OE#) is asserted low.
The Data# Polling Timings (During Embedded Algo-
rithms) figure in the “AC Characteristics” section
illustrates this.
Table 5 shows the outputs for Data# Polling on DQ7.
Figure 3 shows the Data# Polling algorithm.
DQ7 = Data? Yes
No
No
DQ5 = 1?
No
Yes
Yes
FAIL PASS
Read DQ7–DQ0
Addr = VA
Read DQ7–DQ0
Addr = VA
DQ7 = Data?
START
Notes:
1. VA = Valid address for programming. During a sector
erase operation, a valid address is an address within any
sector selected for erasure. During chip erase, a valid
address is any non-protected sector address.
2. DQ7 should be rechecked even if DQ5 = “1” because
DQ7 may change simultaneously with DQ5.
Figure 3. Data# Polling Algorithm
November 11, 2009 21445E8 Am29F040B 15
DATA SHEET
DQ6: Toggle Bit I
Toggle Bit I on DQ6 indicates whether an Embedded
Program or Erase algorithm is in progress or complete,
or whether the device has entered the Erase Suspend
mode. Toggle Bit I may be read at any address, and is
valid after the rising edge of the final WE# pulse in the
command sequence (prior to the program or erase op-
eration), and during the sector erase time-out.
During an Embedded Program or Erase algorithm op-
eration, successive read cycles to any address cause
DQ6 to toggle. (The system may use either OE# or
CE# to control the read cycles.) When the operation is
complete, DQ6 stops toggling.
After an erase command sequence is written, if all sec-
tors selected for erasing are protected, DQ6 toggles for
approximately 100 µs, then returns to reading array
data. If not all selected sectors are protected, the Em-
bedded Erase algorithm erases the unprotected
sectors, and ignores the selected sectors that are
protected.
The system can use DQ6 and DQ2 together to deter-
mine whether a sector is actively erasing or is erase-
suspended. When the device is actively erasing (that is,
the Embedded Erase algorithm is in progress), DQ6
toggles. When the device enters the Erase Suspend
mode, DQ6 stops toggling. However, the system must
also use DQ2 to determine which sectors are erasing
or erase-suspended. Alternatively, the system can use
DQ7 (see the subsection on “DQ7: Data# Polling”).
If a program address falls within a protected sector,
DQ6 toggles for approximately 2 µs after the program
command sequence is written, then returns to reading
array data.
DQ6 also toggles during the erase-suspend-program
mode, and stops toggling once the Embedded Pro-
gram algorithm is complete.
The Write Operation Status table shows the outputs for
Toggle Bit I on DQ6. Refer to Figure 4 for the toggle bit
algorithm, and to the Toggle Bit Timings figure in the
“AC Characteristics” section for the timing diagram.
The DQ2 vs. DQ6 figure shows the differences be-
tween DQ2 and DQ6 in graphical form. See also the
subsection on “DQ2: Toggle Bit II”.
DQ2: Toggle Bit II
The “Toggle Bit II” on DQ2, when used with DQ6, indi-
cates whether a particular sector is actively erasing
(that is, the Embedded Erase algorithm is in progress),
or whether that sector is erase-suspended. Toggle Bit
II is valid after the rising edge of the final WE# pulse in
the command sequence.
DQ2 toggles when the system reads at addresses
within those sectors that have been selected for era-
sure. (The system may use either OE# or CE# to
control the read cycles.) But DQ2 cannot distinguish
whether the sector is actively erasing or is erase-sus-
pended. DQ6, by comparison, indicates whether the
device is actively erasing, or is in Erase Suspend, but
cannot distinguish which sectors are selected for era-
sure. Thus, both status bits are required for sector and
mode information. Refer to Table 5 to compare outputs
for DQ2 and DQ6.
Figure 4 shows the toggle bit algorithm in flowchart
form, and the section “DQ2: Toggle Bit II” explains the
algorithm. See also the “DQ6: Toggle Bit I” subsection.
Refer to the Toggle Bit Timings figure for the toggle bit
timing diagram. The DQ2 vs. DQ6 figure shows the dif-
ferences between DQ2 and DQ6 in graphical form.
Reading Toggle Bits DQ6/DQ2
Refer to Figure 4 for the following discussion. When-
ever the system initially begins reading toggle bit
status, it must read DQ7–DQ0 at least twice in a row to
determine whether a toggle bit is toggling. Typically, a
system would note and store the value of the toggle bit
after the first read. After the second read, the system
would compare the new value of the toggle bit with the
first. If the toggle bit is not toggling, the device has com-
pleted the program or erase operation. The system can
read array data on DQ7–DQ0 on the following read
cycle.
However, if after the initial two read cycles, the system
determines that the toggle bit is still toggling, the sys-
tem also should note whether the value of DQ5 is high
(see the section on DQ5). If it is, the system should
then determine again whether the toggle bit is toggling,
since the toggle bit may have stopped toggling just as
DQ5 went high. If the toggle bit is no longer toggling,
the device has successfully completed the program or
erase operation. If it is still toggling, the device did not
complete the operation successfully, and the system
must write the reset command to return to reading
array data.
The remaining scenario is that the system initially de-
termines that the toggle bit is toggling and DQ5 has not
gone high. The system may continue to monitor the
toggle bit and DQ5 through successive read cycles, de-
termining the status as described in the previous
paragraph. Alternatively, it may choose to perform
other system tasks. In this case, the system must start
at the beginning of the algorithm when it returns to de-
termine the status of the operation (top of Figure 4).
DQ5: Exceeded Timing Limits
DQ5 indicates whether the program or erase time has
exceeded a specified internal pulse count limit. Under
these conditions DQ5 produces a “1.” This is a failure
condition that indicates the program or erase cycle was
not successfully completed.
16 Am29F040B 21445E8 November 11, 2009
DATA SHEET
The DQ5 failure condition may appear if the system
tries to program a “1” to a location that is previously pro-
grammed to “0.” Only an erase operation can change
a “0” back to a “1.” Under this condition, the device
halts the operation, and when the operation has ex-
ceeded the timing limits, DQ5 produces a “1.”
Under both these conditions, the system must issue the
reset command to return the device to reading array
data.
DQ3: Sector Erase Timer
After writing a sector erase command sequence, the
system may read DQ3 to determine whether or not an
erase operation has begun. (The sector erase timer
does not apply to the chip erase command.) If addi-
tional sectors are selected for erasure, the entire time-
out also applies after each additional sector erase com-
mand. When the time-out is complete, DQ3 switches
from “0” to “1.” The system may ignore DQ3 if the sys-
tem can guarantee that the time between additional
sector erase commands is always less than 50 µs. See
also the “Sector Erase Command Sequence” section.
After the sector erase command sequence is written,
the system should read the status on DQ7 (Data# Poll-
ing) or DQ6 (Toggle Bit I) to ensure the device has
accepted the command sequence, and then read DQ3.
If DQ3 is “1”, the internally controlled erase cycle has
begun; all further commands (other than Erase Sus-
pend) are ignored until the erase operation is complete.
If DQ3 is “0”, the device accepts additional sector erase
commands. To ensure the command has been ac-
cepted, the system software should check the status of
DQ3 prior to and following each subsequent sector
erase command. If DQ3 is high on the second status
check, the last command might not have been ac-
cepted. Ta bl e 5 shows the outputs for DQ3.
START
No
Yes
Yes
DQ5 = 1?
No
Yes
Toggle Bit
= Toggle?
No
Program/Erase
Operation Not
Complete, Write
Reset Command
Program/Erase
Operation Complete
Read DQ7–DQ0
Toggle Bit
= Toggle?
Read DQ7–DQ0
Twice
Read DQ7–DQ0
Notes:
1. Read toggle bit twice to determine whether or not it is
toggling. See text.
2. Recheck toggle bit because it may stop toggling as DQ5
changes to “1”. See text.
Figure 4. Toggle Bit Algorithm
(Notes 1,
2)
(Note 1)
November 11, 2009 21445E8 Am29F040B 17
DATA SHEET
Table 5. Write Operation Status
Notes:
1. DQ7 and DQ2 require a valid address when reading status information. Refer to the appropriate subsection for further details.
2. DQ5 switches to ‘1’ when an Embedded Program or Embedded Erase operation has exceeded the maximum timing limits.
See “DQ5: Exceeded Timing Limits” for more information.
Operation
DQ7
(Note 1) DQ6
DQ5
(Note 2) DQ3
DQ2
(Note 1)
Standard
Mode
Embedded Program Algorithm DQ7# To g g l e 0 N/A No toggle
Embedded Erase Algorithm 0To g g l e 0 1 Toggle
Erase
Suspend
Mode
Reading within Erase
Suspended Sector 1No toggle 0 N/A Toggle
Reading within Non-Erase
Suspended Sector Data Data Data Data Data
Erase-Suspend-Program DQ7# To g g le 0 N/A N/A
18 Am29F040B 21445E8 November 11, 2009
DATA SHEET
ABSOLUTE MAXIMUM RATINGS
Storage Temperature
Plastic Packages . . . . . . . . . . . . . . . –65°C to +125°C
Ambient Temperature
with Power Applied. . . . . . . . . . . . . . –55°C to +125°C
Voltage with Respect to Ground
VCC (Note 1) . . . . . . . . . . . . . . . . . –2.0 V to 7.0 V
A9, OE# (Note 2) . . . . . . . . . . . . . –2.0 V to 12.5 V
All other pins (Note 1) . . . . . . . . . . –2.0 V to 7.0 V
Output Short Circuit Current (Note 3) . . . . . . 200 mA
Notes:
1. Minimum DC voltage on input or I/O pins is –0.5 V. During
voltage transitions, inputs may undershoot VSS to –2.0 V
for periods of up to 20 ns. See Figure 5. Maximum DC
voltage on input and I/O pins is VCC + 0.5 V. During
voltage transitions, input and I/O pins may overshoot to
VCC + 2.0 V for periods up to 20 ns. See Figure 6.
2. Minimum DC input voltage on A9 pin is –0.5 V. During
voltage transitions, A9 and OE# may undershoot VSS to
–2.0 V for periods of up to 20 ns. See Figure 5. Maximum
DC input voltage on A9 and OE# is 12.5 V which may
overshoot to 13.5 V for periods up to 20 ns.
3. No more than one output shorted to ground at a time.
Duration of the short circuit should not be greater than
one second.
Stresses above those listed under “Absolute Maximum
Ratings” may cause permanent damage to the device. This is
a stress rating only; functional operation of the device at
these or any other conditions above those indicated in the op-
erational sections of this specification is not implied. Expo-
sure of the device to absolute maximum rating conditions for
extended periods may affect device reliability.
OPERATING RANGES
Industrial (I) Devices
Ambient Temperature (TA) . . . . . . . . . –40°C to +85°C
Extended (E) Devices
Ambient Temperature (TA) . . . . . . . . –55°C to +125°C
VCC Supply Voltages
VCC for ± 5% devices . . . . . . . . . . .+4.75 V to +5.25 V
VCC for ± 10% devices . . . . . . . . . . . +4.5 V to +5.5 V
Operating ranges define those limits between which the
functionality of the device is guaranteed.
20 ns
20 ns
+0.8 V
–0.5 V
20 ns
–2.0 V
Figure 5. Maximum Negative
Overshoot Waveform
20 ns
20 ns
VCC
+2.0 V
VCC
+0.5 V
20 ns
2.0 V
Figure 6. Maximum Positive
Overshoot Waveform
November 11, 2009 21445E8 Am29F040B 19
DATA SHEET
DC CHARACTERISTICS
TTL/NMOS Compatible
CMOS Compatible
Notes for DC Characteristics (both tables):
1. The ICC current listed includes both the DC operating current and the frequency dependent component (at 6 MHz).
The frequency component typically is less than 2 mA/MHz, with OE# at VIH.
2. Maximum ICC specifications are tested with VCC = VCCmax.
3. ICC active while Embedded Algorithm (program or erase) is in progress.
4. Not 100% tested.
5. For CMOS mode only, ICC3 = 20 µA max at extended temperatures (> +85°C).
Parameter
Symbol Parameter Description Test Description Min Typ Max Unit
ILI Input Load Current VIN = VSS to VCC, VCC = VCC Max ±1.0 µA
ILIT A9 Input Load Current VCC = VCC Max, A9 = 12.5 V 50 µA
ILO Output Leakage Current VOUT = VSS to VCC, VCC = VCC Max ±1.0 µA
ICC1 VCC Active Read Current (Notes 1, 2)CE# = VIL, OE# = VIH 20 30 mA
ICC2
VCC Active Write (Program/Erase)
Current (Notes 2, 3, 4)CE# = VIL, OE# = VIH 30 40 mA
ICC3 VCC Standby Current (Note 2) CE# = VIH 0.4 1.0 mA
VIL Input Low Level –0.5 0.8 V
VIH Input High Level 2.0 VCC + 0.5 V
VID
Voltage for Autoselect
and Sector Protect VCC = 5.25 V 10.5 12.5 V
VOL Output Low Voltage IOL = 12 mA, VCC = VCC Min 0.45 V
VOH Output High Voltage IOH = –2.5 mA, VCC = VCC Min 2.4 V
VLKO Low VCC Lock-Out Voltage 3.2 4.2 V
Parameter
Symbol Parameter Description Test Description Min Typ Max Unit
ILI Input Load Current VIN = VSS to VCC, VCC = VCC Max ±1.0 µA
ILIT A9 Input Load Current VCC = VCC Max, A9 = 12.5 V 50 µA
ILO Output Leakage Current VOUT = VSS to VCC, VCC = VCC Max ±1.0 µA
ICC1
VCC Active Read Current
(Notes 1, 2)CE# = VIL, OE# = VIH 20 30 mA
ICC2
VCC Active Program/Erase Current
(Notes 2, 3, 4)CE# = VIL, OE# = VIH 30 40 mA
ICC3 VCC Standby Current (Notes 2, 5)CE# = VCC ± 0.5 V 1 5 µA
VIL Input Low Level –0.5 0.8 V
VIH Input High Level 0.7 x VCC VCC + 0.3 V
VID
Voltage for Autoselect and Sector
Protect VCC = 5.25 V 10.5 12.5 V
VOL Output Low Voltage IOL = 12.0 mA, VCC = VCC Min 0.45 V
VOH1 Output High Voltage IOH = –2.5 mA, VCC = VCC Min 0.85 VCC V
VOH2 IOH = –100 μA, VCC = VCC Min VCC –0.4 V
VLKO Low VCC Lock-out Voltage 3.2 4.2 V
20 Am29F040B 21445E8 November 11, 2009
DATA SHEET
TEST CONDITIONS
Table 6. Test Specifications
KEY TO SWITCHING WAVEFORMS
2.7 kΩ
CL6.2 kΩ
5.0 V
Device
Under
Test
Figure 7. Test Setup
Note: Diodes are IN3064 or equivalent
Test Condition -55 All others Unit
Output Load 1 TTL gate
Output Load Capacitance, CL
(including jig capacitance) 30 100 pF
Input Rise and Fall Times 520 ns
Input Pulse Levels 0.0–3.0 0.45–2.4 V
Input timing measurement
reference levels 1.5 0.8, 2.0 V
Output timing measurement
reference levels 1.5 0.8, 2.0 V
WAVEFORM INPUTS OUTPUTS
Steady
Changing from H to L
Changing from L to H
Don’t Care, Any Change Permitted Changing, State Unknown
Does Not Apply Center Line is High Impedance State (High Z)
November 11, 2009 21445E8 Am29F040B 21
DATA SHEET
AC CHARACTERISTICS
Read Only Operations
Notes:
1. See Figure 7 and Ta bl e 6 for test conditions.
2. Output driver disable time.
3. Not 100% tested.
Parameter Symbols
Description Test Setup
Speed Options (Note
1)
UnitJEDEC Std -55 -70 -90
tAVAV tRC Read Cycle Time (Note 3) Min 55 70 90 ns
tAVQV tACC Address to Output Delay CE# = VIL,
OE# = VIL
Max 55 70 90 ns
tELQV tCE Chip Enable to Output Delay OE# = VIL Max 55 70 90 ns
tGLQV tOE Output Enable to Output Delay Max 30 30 35 ns
tOEH
Output Enable Hold Time
(Note 3)
Read Min 0 0 0 ns
Toggle and
Data# Polling Min 10 10 10 ns
tEHQZ tDF
Chip Enable to Output High Z
(Notes 2, 3)Max 18 20 20 ns
tGHQZ tDF
Output Enable to Output High Z
(Notes 2, 3)18 20 20 ns
tAXQX tOH
Output Hold Time from Addresses, CE# or
OE#, Whichever Occurs First Min 0 0 0 ns
22 Am29F040B 21445E8 November 11, 2009
DATA SHEET
tCE
Outputs
WE#
Addresses
CE#
OE#
HIGH Z
Output Valid
HIGH Z
Addresses Stable
tRC
tACC
tOEH
tOE
0 V
tDF
tOH
Figure 8. Read Operation Timings
November 11, 2009 21445E8 Am29F040B 23
DATA SHEET
AC CHARACTERISTICS
Erase and Program Operations
Notes:
1. Not 100% tested.
2. See the “Erase and Programming Performance” section for more information.
Parameter Symbols
Description
Speed Options
UnitJEDEC Std -55 -70 -90
tAVAV tWC Write Cycle Time (Note 1) Min 55 70 90 ns
tAVWL tAS Address Setup Time Min 0ns
tWLAX tAH Address Hold Time Min 40 45 45 ns
tDVWH tDS Data Setup Time Min 25 30 45 ns
tWHDX tDH Data Hold Time Min 0ns
tOES Output Enable Setup Time Min 0ns
tGHWL tGHWL
Read Recover Time Before Write
(OE# high to WE# low) Min 0ns
tELWL tCS CE# Setup Time Min 0ns
tWHEH tCH CE# Hold Time Min 0ns
tWLWH tWP Write Pulse Width Min 30 35 45 ns
tWHWL tWPH Write Pulse Width High Min 20 ns
tWHWH1 tWHWH1
Byte Programming Operation
(Note 2) Ty p 7µs
tWHWH2 tWHWH2
Sector Erase Operation
(Note 2))Ty p 1sec
tVCS VCC Set Up Time (Note 1))Min 50 µs
24 Am29F040B 21445E8 November 11, 2009
DATA SHEET
AC CHARACTERISTICS
OE#
WE#
CE#
VCC
Data
Addresses
tDS
tAH
tDH
tWP
PD
tWHWH1
tWC tAS
tWPH
tVCS
555h PA PA
Read Status Data (last two cycles)
A0h
tCS
Status DOUT
Program Command Sequence (last two cycles)
tCH
PA
Note: PA = program address, PD = program data, DOUT is the true data at the program address.
Figure 9. Program Operation Timings
OE#
CE#
Addresses
V
CC
WE#
Data
2AAh SA
t
AH
t
WP
t
WC
t
AS
t
WPH
555h for chip erase
10 for Chip Erase
30h
t
DS
t
VCS
t
CS
t
DH
55h
t
CH
In
Progress Complete
t
WHWH2
VA
VA
Erase Command Sequence (last two cycles) Read Status Data
Note:
SA = Sector Address. VA = Valid Address for reading status data.
Figure 10. Chip/Sector Erase Operation Timings
November 11, 2009 21445E8 Am29F040B 25
DATA SHEET
AC CHARACTERISTICS
WE#
CE#
OE#
High Z
tOE
High Z
DQ7
DQ0–DQ6
Complement Tr u e
Addresses VA
tOEH
tCE
tCH
tOH
tDF
VA VA
Status Data
Complement
Status Data Tr u e
Valid Data
Valid Data
tACC
tRC
Note: VA = Valid address. Illustration shows first status cycle after command sequence, last status read cycle, and array data
read cycle .
Figure 11. Data# Polling Timings (During Embedded Algorithms)
WE#
CE#
OE#
High Z
t
OE
DQ6/DQ2
Addresses VA
t
OEH
t
CE
t
CH
t
OH
t
DF
VA VA
t
ACC
t
RC
Valid DataValid StatusValid Status
(first read) (second read) (stops toggling)
Valid Status
VA
Note:
VA = Valid address; not required for DQ6. Illustration shows first two status cycle after command sequence, last status read cycle,
and array data read cycle.
Figure 12. Toggle Bit Timings (During Embedded Algorithms)
26 Am29F040B 21445E8 November 11, 2009
DATA SHEET
AC CHARACTERISTICS
Note: Both DQ6 and DQ2 toggle with OE# or CE#. See the text on DQ6 and DQ2 in the section “Write Operation Status” for more
information.
Figure 13. DQ2 vs. DQ6
Enter
Erase
Erase
Erase
Enter Erase
Suspend Program
Erase Suspend
Read Erase Suspend
Read
Erase
WE#
DQ6
DQ2
DQ2 and DQ6 toggle with OE# and CE#
Erase
Complete
Erase
Suspend
Suspend
Program
Resume
Embedded
Erasing
November 11, 2009 21445E8 Am29F040B 27
DATA SHEET
AC CHARACTERISTICS
Erase and Program Operations
Alternate CE# Controlled Writes
Notes:
1. Not 100% tested.
2. See the “Erase and Programming Performance” section for more information.
Parameter Symbols
Description
Speed Options
UnitJEDEC Std -55 -70 -90
tAVAV tWC Write Cycle Time (Note 1))Min 55 70 90 ns
tAVEL tAS Address Setup Time Min 0ns
tELAX tAH Address Hold Time Min 40 45 45 ns
tDVEH tDS Data Setup Time Min 25 30 45 ns
tEHDX tDH Data Hold Time Min 0ns
tGHEL tGHEL Read Recover Time Before Write Min 0ns
tWLEL tWS CE# Setup Time Min 0ns
tEHWH tWH CE# Hold Time Min 0ns
tELEH tCP Write Pulse Width Min 30 35 45 ns
tEHEL tCPH Write Pulse Width High Min 20 20 20 ns
tWHWH1 tWHWH1
Byte Programming Operation
(Note 2))Ty p 7µs
tWHWH2 tWHWH2
Sector Erase Operation
(Note 2))Ty p 1sec
28 Am29F040B 21445E8 November 11, 2009
DATA SHEET
AC CHARACTERISTICS
t
GHEL
t
WS
OE#
CE#
WE#
t
DS
Data
t
AH
Addresses
t
DH
t
CP
DQ7# D
OUT
t
WC
t
AS
t
CPH
PA
Data# Polling
A0 for program
55 for erase
t
RH
t
WHWH1 or 2
t
WH
PD for program
30 for sector erase
10 for chip erase
555 for program
2AA for erase
PA for program
SA for sector erase
555 for chip erase
t
BUSY
Notes:
1. PA = Program Address, PD = Program Data, SA = Sector Address, DQ7# = Complement of Data Input, DOUT = Array Data.
2. Figure indicates the last two bus cycles of the command sequence.
Figure 14. Alternate CE# Controlled Write Operation Timings
November 11, 2009 21445E8 Am29F040B 29
DATA SHEET
ERASE AND PROGRAMMING PERFORMANCE
Notes:
1. Typical program and erase times assume the following conditions: 25°C, 5.0 V VCC, 1,000,000 cycles. Additionally,
programming typicals assume checkerboard pattern.
2. Under worst case conditions of 90°C, VCC = 4.5 V (4.75 V for -55), 1,000,000 cycles.
3. The typical chip programming time is considerably less than the maximum chip programming time listed, since most bytes
program faster than the maximum byte program time listed. If the maximum byte program time given is exceeded, only then
does the device set DQ5 = 1. See the section on DQ5 for further information.
4. In the pre-programming step of the Embedded Erase algorithm, all bytes are programmed to 00h before erasure.
5. System-level overhead is the time required to execute the four-bus-cycle command sequence for programming. See Table 4
for further information on command definitions.
6. The device has a guaranteed minimum erase and program cycle endurance of 1,000,000 cycles.
LATCHUP CHARACTERISTICS
Includes all pins except VCC. Test conditions: VCC = 5.0 V, one pin at a time.
TSOP PIN CAPACITANCE
Notes:
1. Sampled, not 100% tested.
2. Test conditions TA = 25°C, f = 1.0 MHz.
Parameter
Typ
(Note 1)
Max
(Note 2) Unit Comments
Sector Erase Time 1 8 sec
Excludes 00h programming prior to erasure (Note 4)
Chip Erase Time 864 sec
Byte Programming Time 7300 µs
Excludes system-level overhead (Note 5)
Chip Programming Time (Note 3) 3.6 10.8 sec
Min Max
Input Voltage with respect to VSS on all I/O pins –1.0 V VCC + 1.0 V
VCC Current –100 mA +100 mA
Parameter Symbol Parameter Description Test Setup Typ Max Unit
CIN Input Capacitance VIN = 0 67.5 pF
COUT Output Capacitance VOUT = 0 8.5 12 pF
CIN2 Control Pin Capacitance VIN = 0 7.5 9pF
30 Am29F040B 21445E8 November 11, 2009
DATA SHEET
PLCC PIN CAPACITANCE
Notes:
1. Sampled, not 100% tested.
2. Test conditions TA = 25°C, f = 1.0 MHz.
DATA RETENTION
Parameter Symbol Parameter Description Test Setup Typ Max Unit
CIN Input Capacitance VIN = 0 4 6 pF
COUT Output Capacitance VOUT = 0 812 pF
CIN2 Control Pin Capacitance VPP = 0 812 pF
Parameter Test Conditions Min Unit
Minimum Pattern Data Retention Time
150°C10 Ye a r s
125°C20 Ye a r s
November 11, 2009 21445E8 Am29F040B 31
DATA SHEET
PHYSICAL DIMENSIONS
PL 032—32-Pin Plastic Leaded Chip Carrier
Dwg rev AH; 10/99
32 Am29F040B 21445E8 November 11, 2009
DATA SHEET
PHYSICAL DIMENSIONS (continued)
TS 032—32-Pin Standard Thin Small Package
Dwg rev AA; 10/99
November 11, 2009 21445E8 Am29F040B 33
DATA SHEET
REVISION SUMMARY
Revision A (May 1997)
Initial release.
Revision B (January 1998)
Global
Formatted for consistency with other 5.0 volt-only data
sheets.
Revision B+1 (January 1998)
AC Characteristics, Erase and Program Operations
Added Note references to tWHWH1. Corrected the pa-
rameter symbol for VCC Set-up Time to tVCS; the
specification is 50 µs minimum. Deleted the last row in
table.
Revision B+2 (April 1998)
Distinctive Characteristics
Changed minimum 100K write/erase cycles guaran-
teed to 1,000,000.
Ordering Information
Added extended temperature availability to the -55 and
-70 speed options.
AC Characteristics
Erase and Program Operations; Erase and Program
Operations Alternate CE# Controlled Writes: Corrected
the notes reference for tWHWH1 and tWHWH2.
These parameters are 100% tested. Corrected the note
reference for tVCS. This parameter is not 100% tested.
Erase and Programming Performance
Changed minimum 100K program and erase cycles
guaranteed to 1,000,000.
Revision C (January 1999)
Global
Updated for CS39S process technology.
Distinctive Characteristics
Added 20-year data retention bullet.
DC Characteristics—TTL/NMOS Compatible
VOH: Changed the parameter description to “Output
High Voltage” from Output High Level”.
DC Characteristics—TTL/NMOS Compatible and
CMOS Compatible
ICC1, ICC2, ICC3: Added Note 2 “Maximum ICC specifi-
cations are tested with VCC = VCCmax”.
ICC3: Deleted VCC = VCCMax.
Revision C+1 (February 1999)
Command Definitions
Command Definitions table: Deleted “XX” from the
fourth cycle data column of the Sector Protect Verify
command.
Revision C+2 (May 17, 1999)
Test Specifications Table
Corrected the input and output measurement entries in
the “All others” column.
Revision D (November 15, 1999)
AC Characteristics—Figure 9. Program Operations
Timing and Figure 10. Chip/Sector Erase
Operations
Deleted tGHWL and changed OE# waveform to start at
high.
Physical Dimensions
Replaced figures with more detailed illustrations.
Revision E0 (November 29, 2000)
Added table of contents.
Ordering Information
Deleted burn-in option.
Revision E1 (October 4, 2004)
Added PB-Free option to Standard Ordering Matrix.
Updated Valid Combinations
Revision E2 (July 18, 2005)
Ordering Information
In valid combinations list, added the following: Pb-free
options JD, JF, JK to set of -55 and -70 speed options;
Pb-free options PD, PF, PK, JD, JF, JK to the set of -90,
-120, and -150 speed options.
Revision E3 (January 31, 2006)
Global
Removed 150 speed option from document.
Removed 32-pin Reverse TSOP diagrams and all ref-
erences from Ordering Information.
Revision E4 (May 18, 2006)
Added migration and obsolescence information.
Revision E5 (November 1, 2006)
Deleted migration and obsolescence text.
Revision E6 (March 3, 2009)
Global
Added obsolescence information.
34 Am29F040B 21445E8 November 11, 2009
DATA SHEET
Revision E7 (August 3, 2009)
Global
Removed obsolescence information.
Revision E8 (November 11, 2009)
Global
Removed 120 ns speed option.
Removed all commercial temperature range options.
Removed PDIP package option.
Colophon
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limitation, ordinary industrial use, general office use, personal use, and household use, but are not designed, developed and manufactured as
contemplated (1) for any use that includes fatal risks or dangers that, unless extremely high safety is secured, could have a serious effect to the
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